Method for controlling electrical and / or electronic components of a vehicle module and such a vehicle module with automatic module addressing via daisy chain

Abstract

Procedure for assigning logical bus node addresses to the bus nodes ((BK1) to [BK n ]) of a data bus system with a serial, bidirectional, differential two-wire communication bus (DB) - wherein the data bus system has a bus master (ECU) with an address input (Adr i0 ) exhibits and - where the data bus system is n bus nodes ((BK1) to [BK n ]) with n as a positive integer and - where each of the n bus nodes ((BK2) to [BK n ]) via a data line section ((DB1) to [DB n ]) or a serial, bidirectional, differential two-wire communication bus (DB) is connected to the bus master (ECU) for data transmission and - where a line is connected to an address input (adr i0 ) of the bus master (ECU) starting through all bus nodes ((BK1) to [BK n ]) is routed through in such a way that it passes through the individual bus nodes ((BK1) to [BK n]) in n line sections [L1 to L n ] is subdivided and - where each of the bus nodes is referred to below, for clarity, as the j-th bus node (BK). j ) denoted by 1≤j≤ n, one of these j-th bus nodes (BK) j ) associated address input [Adr ij ] and one of these j-th bus junctions (BK) j ) associated address output [Adr oj ] exhibits and - where each of the bus hubs (BK) j ), if it is not the nth bus stop [BK n] is, with 1≤j≤ n-1 with its address input [Adr ij ] with the address output (Adr o ( j+1 )) of a subsequent bus junction [BK j+1 ] with 1≤j≤ n-1 through a bus junction following the next one [BK j+1] associated line section [L j+1 ] is connected and - where each of the bus hubs (BK) j ) with 2≤j≤ n with its address output [Adr oj ] with the address input [Adri( j-1)] of a preceding bus junction [BK j-1 ] with 2≤j≤ n through a bus junction (BK) j ) associated line section [L j ] is connected and - where the first bus node (BK1) with its address output (Adr o1 ) with the address input (Adr i0 ) of the bus master (ECU) is connected by a line section [L1] belonging to the bus node (BK1) and - where the respective bus node address of each bus node (BK1 to BK) n ) can be valid or invalid with the steps - Invalidate all or at least part of the respective bus node addresses of bus nodes ((BK1) to [BK n ]) and relocating at least this part of the bus junctions ((BK1) to [BK n ]) into an addressing state; - While the addressing state is active: Setting the level of the address input (Adr i0) of the bus master (ECU) to a second logical value when the level of this address input (Adr i0 ) this bus master (ECU) not through the address output (Adr o1 ) of the first bus junction (BK1) of the bus junctions ((BK1) to [BK n ]) is overwritten; - While the addressing state exists in each bus node (BK) j ) the bus junction ((BK2) to [BK n ]) excluding the first bus node (BK1): Overriding the level at the address input [Adri (j-1) ] of the respective bus hub (BK j ) preceding bus junction [BK j-1 ] through this respective bus junction (BK) j ) with a first logical level when the bus node address of this respective bus node (BK) j ) is invalid and the level at the address input [Adr ij ] of this respective bus junction (BK) j ) has a first logical value and setting the level of the address input [Adr ij] this bus junction (BK) j ) to a second logical value when the level of this address input [Adr ij ] this bus junction (BK) j ) not through the address output [Adr o(j+1) ] one of the respective bus hubs (BK) j ) following bus junction [BK j+1] the bus junction ((BK3) to [BK n ]) is overwritten; - While the addressing state exists in the first bus node (BK1): Overwrite the level at the address input (Adr i0 ) of the bus master (ECU) through the first bus node (BK1) with a first logical level if the bus node address of the first bus node (BK1) is invalid and the level at the address input (Adr o1 ) this first bus node (BK1) has a first logical value and setting the level of the address input (Adr i1 ) this first bus node (BK1) to a second logical value when the level of this address input (Adr i1) this first bus node (BK1) not through the address output (Adr o2 ) of the bus node (BK2) following the first bus node (BK1) the bus nodes ((BK2) to [BK n ]) is overwritten; - While the addressing state exists: Signaling of a bus node address to all bus nodes ((BK1) to [BK n ]) by the bus master (ECU) and acceptance of the signaled bus node address as a valid bus node address by that bus node (BK) j ) the bus junction ((BK1) to [BK n ]), whose bus node address is invalid and whose address input [Adr ij ] has a second logical value and this signaling is repeated by the bus master (ECU) until the address input (Adr i0 ) of the bus master (ECU) has a second logical value; - Moving the bus nodes ((BK1) to [BK n]) into a second operating state different from the addressing state, when the address input (Adr i0 ) of the bus master (ECU) has a second logical value.

Description

[0001] The invention relates to a device for controlling electrical and / or electronic components of a motor vehicle module, in particular an interior light and / or exterior light such as a rear light module of a motor vehicle. Furthermore, the invention relates to a motor vehicle module with multiple electrical and / or electronic components, in particular an interior light and / or exterior light such as a rear light module of a motor vehicle.

[0002] The electrical and electronic components of automotive modules, such as the various lighting modules, are becoming increasingly complex. Especially in the area of ​​lighting, there has recently been an increasing trend toward using dynamic functions such as the "wiping turn signal" or the so-called "coming home" application. This takes advantage of the fact that the individual exterior and interior lighting functions of a vehicle are each implemented by multiple LEDs or OLEDs. Dynamic effects can now be realized in a comparatively simple hardware manner by controlling the numerous light sources that such a vehicle lighting module has in different ways.

[0003] The multitude of components of a vehicle module—for example, the multitude of LEDs or OLEDs assigned to the individual lighting functions of a rear light module, for example—are advantageously connected to a control unit of the module via a communication bus or are in communication with the control unit via the communication bus. Typically, the control unit also includes a voltage converter for supplying power, in particular, to LED drivers of a lighting module.

[0004] In terms of transmission speed and robustness, differential two-wire communication bus systems have proven their worth. The information signals are transmitted between the control unit and the participants as a voltage difference between the two bus lines, thereby achieving greater signal reliability, higher transmission speed, and lower susceptibility to interference. Such two-wire bus lines are generally known.

[0005] The problem is that the hardware complexity for such two-wire bus systems and their participants is considerable. A particular disadvantage in terms of cost is the fact that the participants must have relatively precise clock generators that operate synchronously with each other. Furthermore, the light modules must be able to determine their physical position during installation and connection in the vehicle factory and convert this into a logical address. This allows similar light modules to be used without pre-programming a bus node address for these light modules, which massively reduces the potential for errors and logistics in production.

[0006] From NN: “High-Brightness LED Matrix Manager for Automotive Headlight Systems”, February 1, 2016 (2016-02-01), pages 1-53, XP055348745, Dallas, Texas (found on the Internet: URL:http: / / www.ti.com / lit / ds / symlink / tps92661-ql.pdf on 2017-02-23) a vehicle headlight control is known whose bus has two lines to which no differential signals are applied.

[0007] In MONAL GIRADKAR ET AL: “Design and Implementation of Adaptive Front Light System of Vehicle Using FPGA Based LIN Controller”, EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET), 2011 4TH INTERNATIONAL CONFERENCE ON, IEEE, November 18, 2011 (2011-11-18), pages 258-261, XP032087461, DOI: 10.1109 / ICETET.2011.67; ISBN: 978-1-4577-1847-2, a bit timing logic for a CAN bus is described.

[0008] A device for controlling an adaptive automotive headlight with an FPGA-based LIN controller is described in GUO JINYAN ET AL: “The design and realization of CAN bit timing logic”, MICROELECTRONICS AND ELECTRONIS (PRIMEASIA), 2010 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN, IEEE, PISCATAWAY, NJ, USA, September 22, 2010 (2010-09-22), pages 333-337, XP031777603, ISBN: 978-1-4244-6735-8.

[0009] Finally, ZENG WEIYING ET AL: "In-Vehicle Networks Outlook: Achievements and Challenges," IEEE COMMUNICATIONS SURVEYS & TUTORIALS, Vol. 18, No. 3, February 27, 2016 (2016-02-27), pp. 1552–1571, XP011620858, DOI: 10.1109 / COMST.2016.2521642; [accessed 2016-08-19] provides an overview of in-vehicle communication systems.

[0010] DE 10 2016 125 290 A1 and DE 10 2017 100 718 A1 disclose devices and methods for addressing and operating an LED chain using a JTAG protocol. One problem is that the clock signal must be transmitted together with the data using a multi-level signal. However, there is a market need to be able to rely on existing protocols. In this case, the bus nodes must be synchronized with sufficient precision to avoid transmission of the clock signal as described in the technical teachings of DE 10 2016 125 290 A1 and DE 10 2017 100 718 A1. In the CAN protocol, for example, this is solved using complex timing synchronization, which, however, generally leads to overly complex bus nodes.

[0011] The document DE 10 2016 100 847 B3 shows a method for initializing a single-wire data bus between a bus master and multiple bus nodes. The method of document DE 10 2016 100 847 B3 comprises determining a new bus node address by the bus master, followed by storing this bus node address in a bus node address register (of a bus node) by the bus master. The bus master and the respective bus node of DE 10 2016 100 847 B3 are connected to one another by one or more single-wire data bus sections. According to the technical teaching of DE 10 2016 100 847 B3, a method or a device according to DE 10 2016 100 847 B3 makes no statement as to whether a bus node address is valid or not.

[0012] The publication DE 10 2008 003 082 A1 describes a control unit and a method for controlling personal protection equipment, as well as a sensor for outputting an accident-relevant signal. According to the technical teaching of DE 10 2008 003 082 A1, a digital data signal relevant for controlling the personal protection equipment is output via an interface. The interface of DE 10 2008 003 082 A1 has a plurality of current sources for influencing signal edges of the digital data signal.

[0013] The document DE 10 2016 214 416 A1 deals with a method for assigning addresses by a master unit to a number of slave units.

[0014] The two publications DE 10 2008 003 082 A1 and DE 10 2016 214 416 A1 also do not bring us any closer to a solution to the problem.

[0015] The object of the invention is to provide a device for controlling electrical and / or electronic components of a motor vehicle module and such a motor vehicle module which is reduced in terms of hardware complexity.

[0016] The claims determine the claimed scope. The description clarifies the claims and places them in an overall context.

[0017] Abbreviations are marked in the text with square brackets "[]" in contrast to the reference symbols and are listed in the attached list of abbreviations. Reference symbols that appear in any of the figures are marked in the text with round brackets "()" in contrast to the abbreviations and are listed in the attached list of reference symbols. The designations are always listed with the respective reference symbols, even if these are used elsewhere in the description than in the figure description.

[0018] The indices j and n each correspond to a positive integer.

[0019] To achieve this object, the invention proposes a device for controlling electrical and / or electronic components of a motor vehicle module, in particular an interior light and / or exterior light such as a rear light module of a motor vehicle, wherein the device is provided • with a differential two-wire communication bus, • several components connected to the two-wire communication bus and • a control unit that receives control commands for the components from outside and converts these control commands into bit streams to be sent to the components via the two-wire communication bus and receives bit streams generated by the components, • each component comprising an asynchronous digital serial interface, a microcontroller and a clock for generating a sampling signal for sampling bit streams sent over the two-wire communication bus and • wherein at least the bit streams sent by the control unit have synchronization information for synchronizing the clock generators of the components to the clock with which the control unit sends the bits of the bit streams via the two-wire communication bus and • wherein each component is configured to determine and then use a logical bus node address correlated with its physical position by means of one or more auto-addressing methods.

[0020] Furthermore, to achieve the object according to the invention, a motor vehicle module with several electrical and / or electronic components, in particular an interior light and / or exterior light such as a rear light module of a motor vehicle, wherein the motor vehicle module is provided with • a differential two-wire communication bus, • where the components are connected to the two-wire communication bus and • a control unit that receives control commands for the components from outside and converts these control commands into bit streams to be sent to the components via the two-wire communication bus and receives bit streams generated by the components, • each component comprising an asynchronous digital serial interface, a microcontroller and a clock for generating a sampling signal for sampling bit streams sent over the two-wire communication bus and • wherein at least the bit streams sent by the control unit have synchronization information for synchronizing the clock generators of the components to the clock with which the control unit sends the bits of the bit streams via the two-wire communication bus and • wherein the components change from a normal state to an addressing state before starting normal operation and carry out a process for determining bus node addresses which depend on the physical position of the bus nodes in the chain of bus nodes and then leave the addressing state again.

[0021] The proposed approach combines the advantages of a differential two-wire communication bus with auto-addressing capability with the advantages of using asynchronous, digital, serial interfaces, via which the individual participants or components are connected to the two-wire communication bus. The use of so-called Universal Asynchronous Receiver Transmitters (UARTs) requires that the bit stream received via such a digital serial interface contain synchronization information for the clock generator of the bus participant (the respective bus node). However, such synchronization information (e.g., synchronization bits) can now also be easily integrated via a differential two-wire communication bus, for example, in the header of a data frame representing the bit stream.Thus, the protocol of the differential two-wire communication bus used according to the invention comprises elements such as those known from single-wire buses, whose participants have standardized and cost-effective UARTs.

[0022] The invention is particularly suitable for use in digital interfaces for robust and high-speed data transmission via a two-wire cable connection between circuit boards equipped with LEDs, for example, for a rear light and interior light within a lamp, with a data rate of up to 500 kbit / s. Symmetrical transmission is used via a differential high-speed two-wire bus system for the purpose of transmitting a simple serial protocol, thus reducing the digital hardware complexity. Figure 1

[0023] The Fig. Figure 1 shows an example of a taillight module (BLM) of a motor vehicle. The taillight module (BLM) has a bus master (ECU) and a serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, and differential two-wire communication bus (DB) consists of a first single-wire bus (DB a ) and a second single-wire bus (DB bThe TXD and RXD lines of the bus master (ECU) lead to a level converter (TR) to convert the signal level for operating the two-wire communication bus DB. The bus master (ECU) receives various control commands from outside, for example for the functions of tail light, indicator, rear fog light, dynamic effects, etc., and / or information via a digital bus. The bus master (ECU) converts these commands into bit streams, which include, among other things, bits of a synchronization field of the corresponding data frame (bit stream packet (BP)). The level converter and bus master (ECU) are also considered a unit below and referred to jointly as the bus master (ECU).

[0024] Various components or participants are connected to the communication bus (DB) as bus nodes BK1 to BK6. For example, the first and second bus nodes (BK1 and BK2) are responsible for implementing the turn signal, the third bus node (BK3) for the tail light, the fourth and sixth bus nodes (BK4 and BK6) for the brake light function, and the fifth bus node (BK5) for the reversing light. Each of these participants or components has a multitude of LEDs (LED1 to LED6) controlled by respective LED drivers.

[0025] Each bus node is also equipped with a digital interface (IF1 to IF6) in the form of a UART. Furthermore, each bus node has a microcontroller ([µC 1]to [µC6]) and also a clock generator ([CLKG1] to [CLKG6]) in order to be able to read messages on the differential two-wire communication bus (DB) synchronously with the transmission of the bits of the bit streams or to be able to place such bit streams on the two-wire communication bus (DB) synchronously for reading by other participants or the bus master (ECU).

[0026] Furthermore, the hardware for controlling the components of a vehicle module according to the invention is simplified by using fixed sampling points at the component or two-wire communication bus device level instead of dynamically adjusting the sampling points. The latter is considerably more complex. The clock is generated for each device by reading the synchronization information from the bit streams, which is advantageously sent at the beginning of a bit stream.

[0027] Fig. Figure 2 shows a two-wire communication bus (DB), such as is known from the prior art. The serial, bidirectional, differential two-wire communication bus (DB) consists of a first single-wire bus (DB a ) and a second single-wire bus (DB b ).

[0028] The serial, bidirectional, differential two-wire communication bus (DB) connects the bus master (ECU) with several bus nodes ((BK1) to [BK n ]). Figure 3

[0029] The bus master (ECU) has a first driver [TR a ] with which he developed the first single-wire bus (DB a ) into a first state (Z1) or a second state (Z2) or a third state (Z3).

[0030] A first driver can preferably assume two of three permitted states as a CAN driver: In a first state, it sets a first logic level (Z1) on the first single-wire bus (DB a). In a second state, it applies a third logic level (Z3) to the first single-wire bus (DB a ). The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n' ]) as the first current sink for the first addressing currents of the first addressing current sources ((Iq1) to [Iq n ]) of the bus nodes ((BK1) to [BK n ]) and their first quiescent currents. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the second driver [TR b ] of the relevant bus node ((BK1) to [BK n ]) assumes the second state (Z2). As a result, the signal is differentially impressed with a first differential level (z1). Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the third state (Z3) when the second driver [TR b] of the relevant bus node ((BK1) to [BK n ]) assumes the third state (Z3). This differentially imprints the signal with a third differential level (z3).

[0031] The first driver can also preferably assume two of two permitted states as an RS485 driver: In a first state, it sets a first logic level (Z1) on the first single-wire bus (DB a ). In a second state, it applies a second logic level (Z2) to the first single-wire bus (DB a ). The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n ]) as the first current sink for the first addressing currents of the first addressing current sources ((Iq1) to [Iq n ]) of the bus nodes ((BK1) to [BK n ]) and their first quiescent currents. Preferably, the first driver of a bus node ((BK1) to [BK n]) or the bus master (ECU) indicates the first state (Z1) when the second driver [TR b ] of the relevant bus node ((BK1) to [BK n ]) assumes the second state (Z2). As a result, the signal is differentially impressed with a first differential level (z1). Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the second driver [TR b ] of the relevant bus node ((BK1) to [BK n ]) assumes the first state (Z1). This differentially imprints the signal with a second differential level (z2).

[0032] In addition, the first driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DB a ) by a first driver of another bus node ((BK1) to [BK n ]) or the bus master (ECU).

[0033] A second driver can preferably assume two of three permitted states as a CAN driver: In a first state, it applies a second logic level (Z2) to the second single-wire bus (DB b ). In a second state, it applies a third logic level (Z3) to the second single-wire bus (DB b ). The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n ]) as a second current sink for the second addressing currents of the second addressing current sources ((Iq'1) to [Iq' n ]) of the bus nodes ((BK1) to [BK n ]) and their second quiescent currents. Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the first driver [TR a ] of the relevant bus node ((BK1) to [BK n]) assumes the first state (Z1). As a result, the signal is differentially impressed with a first differential level (z1). Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the third state (Z3) when the first driver [TR a ] of the relevant bus node ((BK1) to (BK n ]) assumes the third state (Z3). This differentially imprints the signal with a third differential level (z3).

[0034] The second driver can also be used as an RS485 driver in two of two permitted states: In a first state, it applies a second logic level (Z2) to the first single-wire bus (DB a ). In a second state, it applies a first logic level (Z1) to the second single-wire bus (DB b ). The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n]) as a second current sink for the second addressing currents of the second addressing current sources ((Iq'1) to [Iq' n ]) of the bus nodes ((BK1) to [BK n ]) and their second quiescent currents. Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the first driver [TR a ] of the relevant bus node ((BK1) to [BK n ]) assumes the first state (Z1). As a result, the signal is differentially impressed with a first differential level (z1). Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the first driver [TR a ] of the relevant bus node ((BK1) to [BK n]) assumes the second state (Z2). As a result, the signal is differentially impressed with a second differential level (z2). In addition, the second driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DB a ) by a second driver of another bus node ((BK1) to [BK n ]) or the bus master (ECU). Figure 2

[0035] Each of the bus nodes ((BK1) to [BK n]) and the bus master (ECU) preferably have a receiver (Rec). The respective receiver (Rec) extracts the data (DATA) contained in the bit stream packets (BP) on the serial, bidirectional, differential two-wire communication bus (DB) and outputs these, preferably together with error information, via an output (out) of the receiver (Rec). The receiver (Rec) typically checks whether check information (CHKD) within data information (DATA) of a bit stream packet (BP) indicates error-free reception by the receiver (Rec). If a bit stream packet (BP) was not received error-free by the receiver (Rec), the receiver (Rec) preferably signals this. The actual useful circuits at the receiver output (out) are shown here in the Fig. 2 not shown for clarity. These process the information (out) received by the receiver (Rec) and control the drivers [TR a , TR b] for the respective transmission process of a bus node ((BK1) to [BK n ]) or the bus master (ECU).

[0036] The data bus system has a common supply voltage line (V bat ) and typically a common reference potential [GND], which is Fig. 2 is not shown.

[0037] Please note that the Fig. 2 despite the serial arrangement of the bus nodes ((BK1) to [BK n ]) has a star structure of the data bus. The representation of the Fig. 2 breaks off at the third bus node (BK3) for better clarity.

[0038] In one embodiment, a device for controlling electrical and / or electronic bus nodes ((BK1) to [BK n]), in particular within a motor vehicle module, an interior light and / or exterior light such as a rear light module of a motor vehicle, which comprises a serial, bidirectional, differential two-wire communication bus (DB) with n bus nodes (BK1 to [BK n ]). Where n is a positive integer greater than 1. Furthermore, the proposed device has a bus master (ECU). The serial, bidirectional, differential communication bus (DB) consists of a first single-wire bus (DB a )and a second single-wire bus (DB b ). Each bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) has a differential serial interface [IF j ] to the serial, bidirectional, differential communication bus (DB). Each bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) preferably has a clock generator [CLKG j ], a scanning device [AT j], an address recognition unit [ADR j ] and a bus node address register [BKADR j ] The serial, bidirectional, differential communication bus (DB) is designed such that it can preferably be in at least a first logical state (high, Z1) and a second logical state (low, Z2) and possibly a third logical state (idle, Z3).

[0039] First, levels of the High-Speed ​​CAN protocol [HS-CAN] can be used. This will be explained first.

[0040] For this purpose, the serial, bidirectional, differential communication bus (DB) in the transmitters (TX a , TX b ) the respective bus node (BK j ) preferably via a high-impedance voltage divider per transmitter (TX a , TX b ) preferably to a preferably vanishing differential voltage difference between the first single-wire bus (DB a) and the second single-wire bus (DB b ) are clamped according to the third logical state (Idle, Z3). Each of the transmitters (TX a , TX b ) preferably comprises a switch with which the first single-wire bus (DB a )of the serial, bidirectional, differential communication bus (DB) by the first driver [TR a ] is brought to the first logical state (High, Z1) and the second single-wire bus (DB b ) of the serial, bidirectional, differential communication bus (DB) by the second driver [TR b ] can be brought into a second logical state (Low, Z2). This is in Fig. 3 below. If the switches of the drivers [TR a , TR b ] is switched off (IDLE), the serial, bidirectional, differential communication bus (DB) returns to the third logical state (Idle, Z3).

[0041] Second, levels of the RS484 protocol can be used. This will be explained in the second section.

[0042] For this purpose, the serial, bidirectional, differential communication bus (DB) in the transmitters (TX a , TX b ) the respective bus node (BK j ) preferably via a high-impedance voltage divider per transmitter (TX a , TX b ) are preferably clamped to a differential voltage difference corresponding to the third logical state (Idle, Z3). Each of the transmitters (TX a , TX b) preferably comprises a half-bridge each, with which the serial, bidirectional, differential communication bus (DB) can be brought to the first logical state (high, Z1) and to a second logical state (low, Z2) by mutually inverse control. If the half-bridges are switched off (IDLE), the serial, bidirectional, differential communication bus (DB) returns to the third logical state (idle, Z3). Figure 3

[0043] The serial interface (IF j ) of at least one bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) is connected to the serial, bidirectional, differential communication bus (DB) in order to send and / or receive data via this serial, bidirectional, differential communication bus (DB). It typically comprises each bus node (BK j ) the already mentioned transmitters (TX a , TX b) and a receiver (Rec). The clock and data extraction within the bus nodes ((BK1) to [BK n ]) from the bit packets (BP) is not shown in the drawings for the sake of simplicity, as it can be taken from the state of the art. The bus master (ECU) receives external control commands for the n bus nodes ((BK1) to [BK n ]) and transmits these control commands via the serial, bidirectional, differential communication bus (DB) to the bus nodes ((BK1) to [BK n ]) to be sent. The bus master (ECU) transmits the bits of the bit streams to be sent by the bus master (ECU) via the serial, bidirectional, differential communication bus (DB) in response to a clock pulse (CLK) within the bus master (ECU). The bus master (ECU) receives in the opposite direction from the bus nodes ((BK1) to [BK n ]) generated bit streams over the serial, bidirectional, differential communication bus (DB). Clock generator [CLKG j] within each bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) generate within each bus node (BK j ) of these bus nodes ((BK1) to [BK n ]) a respective sampling signal [CLKA j ]. The scanning device [AT j ] of this respective bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) then samples in dependence on the sampling signal [CLKA j ] of this bus node (BK j ) the bit streams sent over the serial, bidirectional, differential communication bus (DB). These can be bit streams from the bus master (ECU) to the bus nodes ((BK1) to [BK n ]) as well as bit streams of the other bus nodes ((BK1) to [BK n ]) to the bus master (ECU) or to other bus nodes ((BK1) to [BK n ]). The relevant bus node (BK j) extracts in this way from the signals on the serial, bidirectional, differential communication bus (DB) a local bit stream within this bus node (BK j ), from the output of the receiver (Rec) by sampling the output signal of the receiver (Rec) or a signal derived from it. The bus master (ECU) sends the bit streams to be transmitted as sequences of bits in bit stream packets (frames, BP). The bus nodes also prefer to send their bit streams as sequences of bits in bit stream packets (frames, BP), which preferably correspond in structure to those of the bus master (ECU). For simplicity, only the bit stream packets (frames, BP) of the bus master (ECU) are discussed here. For the bit stream packets (BP) of the bus nodes ((BK1) to [BK n ]) the same applies.

[0044] As explained previously, this structure means that the serial, bidirectional, differential two-wire communication bus (DB), if neither the bus master (ECU) nor one of the n bus nodes ((BK1) to [BK n ]) transmits data over the serial, bidirectional, differential two-wire communication bus (DB), the first logical state (Z1) (dashed in Fig. 3) or the third logical state (Z3) - which is preferred.

[0045] The proposed preferred structure of the bit stream packets (BP) sent by the bus master (ECU) is described using Fig. 3. The V diff The signal is intended to represent the differential level on the serial, bidirectional, differential communication bus (DB), i.e. the voltage difference between the first single-wire bus (DB a ) and the second single-wire bus (DB b ).

[0046] The diagram labeled HS-CAN describes the corresponding levels when CAN drivers [TR a , TR b ] be used.

[0047] The diagram labeled RS485 shows the corresponding levels when RS485 driver [TR a , TR b ] be used.

[0048] The Drivers [TR a , TR b ] provide three voltage levels in the HS-CAN scheme, but only two differential voltage levels.

[0049] The Drivers [TR a , TR b ] provide two voltage levels and only two differential voltage levels in the RS485 scheme.

[0050] It is proposed here that at least some of the bit stream packets (BP) sent by the bus master (ECU) contain the following contents: 1. a start signal (START) in the form of i bits with i as an integer positive with i-1≤m / 3 of the m bits of the respective bit stream packet (BP) with a second logical differential state (z2) on the serial, bidirectional, differential two-wire communication bus (DB), 2. a synchronization information (SYNC) for synchronizing the sampling signal [CLKA j ] the clock generator [CLKG j ] the bus node (BK j ) with the clock (CLK) of the bus master (ECU), 3. Data information (DATA) in the form of k bits with k

[0051] The address recognition units ([Adr1] to [Adr n ]) of the bus nodes ((BK1) to [BK n ​]) and possibly also the bus master (ECU) evaluate the address information (ADRD) of the bit stream packets (BP). The address recognition units ([Adr1] to [Adr n ]) of the bus nodes ((BK1) to [BK n ]) only allow the use of the contained useful information (INFO) if the content of the address information (ADRD) matches the content of the bus node address register [BKADR j ] of the bus node (BK j ) corresponds. Preferably, the bus nodes (BK j ) of the n bus nodes ((BK1) to [BK n ]) means for carrying out an auto-addressing procedure for a two-wire data bus in order to set the bus node address register [BAKDR j ] with a logical bus node address that corresponds to the physical position of this bus node (BK j ) of the n bus nodes ((BK1) to [BK n]) within the serial, bidirectional, differential two-wire communication bus (DB). This is an essential step that is not solved in the state of the art.

[0052] In a refinement of the procedure, each bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) a microcontroller [µC j ], which performs some of the previously mentioned tasks, such as the address recognition unit [ADR j ] of the respective bus node (BK j ) and / or the scanning device [AT j ] of the respective bus node (BK j ) by software program. It is now proposed that preferably at least one additional bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) at least one light source [LED j ] and at least one energy supply [EV j ] The at least one energy supply means [EV j] of at least one bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) is then responsible for the energy supply of at least one light source [LED j ] of at least one bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) is provided.

[0053] As before, the clock generator [CLKG j ] of each bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) a sampling signal [CLKA j ] within the respective bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]). The scanning device [AT j ] of a preferred bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) samples again depending on the sampling signal [CLKA j ] of this bus node [BK j] bit streams sent over the serial, bidirectional, differential two-wire communication bus (DB) to generate a local bit stream within this bus node (BK j ). The bit stream packets (BP) preferably consist of a temporal sequence of m individual bits of the same temporal length t B with m as an integer positive, whose time length t B by no more than a factor of + / - (0.4 / m)*ts and / or better + / - (0.2 / m)*t B and / or better + / - (0.1 / m)*t B and / or better + / - (0.05 / m)*t B within a bit stream packet (BP). At least some of the bit stream packets (BP) sent by the bus master (ECU) preferably have the following contents (see Fig. 3): 1. A start signal (START) in the form of i bits with i as an integer positive with i-1≤m / 3 with a second differential logic state (z2) on the serial, bidirectional, differential two-wire communication bus (DB); 2. A synchronization information (SYNC) consisting of k-bits with k as a positive integer, in particular with k j ) the clock generator [CLKG j ] the bus node (BK j ) to the phase of the clock (CLK) of the bus master (ECU) and to the frequency synchronization of the sampling signal [CLKA j ] the clock generator [CLKG j ] the bus node (BK j ) to the frequency of the clock (CLK) of the bus master (ECU); 3. Data information (DATA) from the remaining bits of the mik bits of the m bits of the respective bit stream packet (BP), whereby the data information (DATA) includes address information (ADRD) and payload information (INFO) and check information (CHKD).​

[0054] At least part of the useful information (INFO) includes lighting information (ILD) for controlling the energy supply of the lamps [LED j ] of the bus node (BK j ) by the energy supply [EV j ] of the bus node (BK j ) depending on this lighting information. For this purpose, a lighting register is typically used within the energy supply [EV j ] with a value depending on the received illumination information (ILD), which determines the radiation properties such as color, color temperature and brightness of the connected lamps [LED j ] In order for this data to be transmitted by the relevant bus node (BK j ), the logical content of the address information (ADRD) must match the content of the bus node address register [BKADR j ] of the bus node (BK j) match. If this is not the case, the data information (DATA) is ignored. The same applies if the integrity check of the received data information (DATA) using the check data (CHKD) also received reveals that the reception was faulty. The respective address recognition unit [ADR j ] of the respective bus node (BK j ) evaluates the address information (ADRD) of a received bit stream packet (BP) and only then allows the contained payload information (INFO) to be used by the rest of the bus node devices of the bus node (BK j ) if the content of the received address information (ADRD) matches the content of the bus node address register [BKADR j ] of the bus node (BK j ) corresponds and is error-free. In contrast to the state of the art, bus nodes ((BK1) to [BK n]) means to perform an auto-addressing procedure for a serial, bidirectional and differential communication bus (DB). As a result of such an auto-addressing procedure, the bus node address register [BAKDR j ] these bus nodes ((BK1) to [BK n ]) is filled with a logical bus node address that corresponds to the physical position of this bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) within the serial, bidirectional, differential two-wire communication bus (DB).

[0055] The previously described tests can still be used. In a first variant of the device, the bus master (ECU) and / or bus node ((BK1) to [BK n ]) is equipped with means to detect a malfunctioning clock generator [CLKG j ] of one or more bus nodes (BK j ) close.

[0056] The following describes various example auto-addressing methods and other variants that can be used as examples: Asymmetric auto-addressing with bus shunt resistors that are not subject to addressing current. Figure 4

[0057] It is now typically desired that the bus nodes ((BK1) to [BK n ]) independently determine their physical position within the data bus system in the serial, bidirectional, differential two-wire communication bus (DB) and receive a bus node address based on this, so that the logical address corresponds to the physical address. This has the advantage that for similarly constructed bus nodes ((BK1) to [BK n]) only one type of bus node needs to be maintained in production, which prevents potential errors and improves logistics. To implement such auto-addressing, one might consider incorporating auto-addressing. This is possible in Fig. 4. As an example, the first single-wire bus (DB a ) a first bus shunt resistor (R2) per bus node ((BK1) to [BK n ]). A second differential amplifier (D2) is used to measure the first current through the first single-wire bus (DB a )by means of the first shunt resistor (R2). The output of the second differential amplifier (D2), which is used to measure the first current through the first single-wire bus (DB a ) is connected to a third comparator (D3) which compares the output value of the second differential amplifier (D2) with a first reference value (Ref). This corresponds in its effect to a comparison of the first current in the first single-wire bus (DBa ) through the first bus shunt resistor (R2) with a first reference current [I ref ]. The data bus system with its bus nodes ((BK1) to [BK n ]) can now be set into an addressing state and a normal state by the bus master (ECU) using a special bus signal. During the addressing state, an auto-addressing process is carried out. If the data bus system is in the addressing state, the bus nodes ((BK1) to [BK n ]), which can perform the auto-addressing procedure in a corresponding addressing state of the bus nodes. The first addressing current source (Iq j ) (with 1≤j≤n) of the respective bus node (BK j ) is switched off in the normal state or fulfils another function such as supplying energy to a light source [LED j ]. The first addressing current source (Iq j ) (with 1≤j≤n) of the respective bus node (BK j) is switched off in the addressing state if the respective bus node (BK j ) detects by means of said first means (R2, D2, D3) a first current through its first bus shunt resistor (R2) which is above a threshold value corresponding to the first reference current [I Ref ] In the example of Fig. 4 feeds the respective first addressing current source (Iq j ) of a bus node (BK j ) send their first addressing current from the bus master (ECU) before the respective first bus shunt resistor (R2) of the respective bus node (BK j ) into the first single-wire bus (DB a ) if the bus node (BK j ) by means of the previously described first means (R2, D2, D3) determines that only a first current below this threshold flows through its first bus shunt resistor (R2) towards the bus master (ECU). This has the disadvantage that a self-test of the bus node (BK j) is not possible at this feed point of the first addressing current. In addition, the first driver [TR a ] of the bus master (ECU). Therefore, the first addressing current of the first addressing current sources ((Iq1) to [Iq n ]) to an n-th part of the maximum current value that the first driver [TR a ] can still absorb. This limits the resistance value of the first bus shunt resistor (R2) downwards, since otherwise the level of the voltage drop across the first bus shunt resistor (R2) of a bus node (BK j ) is too small for detection by the first means (R2, D2, D3) of this bus node (BK j ). This leads to increased sensitivity to electromagnetic radiation, which is what we are supposed to avoid. In addition, the asymmetry between the first single-wire bus (DB a ) the Fig. 4 and the second single-wire bus (DB b ) the Fig. 4 to the coupling of common-mode interference into the differential signal on the serial, bidirectional, differential two-wire communication bus (DB), which should also be avoided. If a bus node (BK j ) in the addressing state, after a certain, predetermined waiting time after entering the addressing state, determines that its first addressing current source (Iq j ) is not yet switched off, it is the last bus node not yet provided with a valid bus node address (BK j ). It then adopts a bus node address, typically offered by the bus master (ECU), as its new valid bus node address. Since it then has a valid bus node address, it then switches its addressing current source (Iq j ) and then waits for the end of the addressing state of the data bus system without its addressing current source (Iq j) before the end of the addressing state of the data bus system. The bus node [BK j-1 ], which as the next bus node in the next initialization run then determines that its addressing current source (Iq j ) is not switched off, then takes over the next bus node address to be assigned offered by the bus master (ECU) as its valid bus node address and so on. This continues until all bus nodes ((BK1) to [BK n ]) of the data bus system have thus received a valid bus node address. The bus master then typically moves the data bus system and its bus nodes ((BK1) to [BK n ]) returns to the normal state, retaining the valid bus node addresses. This recommended retention of valid bus node addresses during the transition from the addressing state to the normal state applies preferentially to the entire document. Symmetrical auto-addressing with bus shunt resistors that are not subject to addressing current. Figure 5

[0058] One problem that arises with auto-addressing is, as mentioned, that of symmetry. Since the serial, bidirectional, differential two-wire communication bus (DB) is a differential bus, the two single-wire buses (DB a and DB b ) should be constructed as symmetrically as possible to avoid any potential for common-mode interference. The data bus system should therefore have bus nodes (BK j) for the serial, bidirectional, differential two-wire communication bus (DB), which consists of a first single-wire bus (DB1) and a second single-wire bus (DB2), a first bus shunt resistor (R2) inserted into the first single-wire bus (DB1) and a second bus shunt resistor (R2') inserted into the second single-wire bus (DB2). A corresponding proposal based on Fig. 4 is in Fig. 5. The two bus shunt resistors (R2, R2') per bus node (BK j ) the bus nodes ((BK1) to [BK n ]) are preferably monolithically integrated and matched and with a relative resistance value deviation within the respective bus node (BK j ) of less than 10% and / or better less than 5% and / or better less than 2% and / or better less than 1% and / or better less than 0.5%.

[0059] Each bus node (BK j ) the bus nodes ((BK1) to [BK n]) is now in addition to the first means (R2, D2, D3) for detecting the first current through the first bus shunt resistor (R2) in the first single-wire bus (DB a ) with second means (R2', D2', D3') for detecting the second current through the second bus shunt resistor (R2') in the second single-wire bus (DB b ) equipped.

[0060] As an example, the second single-wire bus (DB b ) a second bus shunt resistor (R2') per bus node ((BK1) to [BK n ]). A further second differential amplifier (D2') is used to measure the second current through the second single-wire bus (DB b ) by means of the second shunt resistor (R2') of the relevant bus node (BK j ). The output of the further second differential amplifier (D2'), which is used to measure the second current through the second single-wire bus (DB b) is connected to a further third comparator (D3'), which compares the output value of the further second differential amplifier (D2') with a further reference value (Ref'), which is typically equal to the first-mentioned reference value (Ref). This corresponds in its effect to a comparison of the second current in the second single-wire bus (DB b ) through the second bus shunt resistor (R2') with a second reference current [I' ref ], which is typically equal to the aforementioned first reference current [I ref ] is selected. The second addressing current source (Iq' j ) (with 1≤j≤n) of the respective bus node (BK j ) is switched off when the respective bus node (BK j ) detects by means of said second means (R2', D2', D3') a first current through its second bus shunt resistor (R2') which is above a threshold value corresponding to the first reference current [I Ref ] In the example of Fig. 5 feeds the respective second addressing current source (Iq' j ) of a bus node (BK j ) the second addressing current seen from the bus master (ECU) also before the respective second bus shunt resistor (R2') of the respective bus node (BK j ) into the second single-wire bus (DB b ) if the bus node (BK j ) by means of the previously described second means (R2', D2', D3') determines that only a second current below this threshold flows through its second bus shunt resistor (R2') towards the bus master (ECU). As before, this has the disadvantage that a self-test of the bus node (BK j ) is not possible. In addition, the second driver [TR b ] of the bus master (ECU). Therefore, the second addressing current of the second addressing current sources ((Iq'1) to [Iq' n]) to an n-th part of the maximum current value that the second driver [TR b ] can still absorb. This limits the resistance value of the second bus shunt resistor (R2') downwards, since otherwise the level of the voltage drop across the second bus shunt resistor (R2') of a bus node (BK j ) would be too small for detection by the second means (R2', D2', D3'). This leads to increased sensitivity to electromagnetic radiation, which should be avoided. The symmetry between the first single-wire bus (DB a ) the Fig. 5 and the second single-wire bus (DB b ) the Fig. 5, however, already leads to a reduced coupling of common-mode noise into the differential signal on the serial, bidirectional, differential two-wire communication bus (DB), which is an advantage.

[0061] Both addressing current sources (Iq j 'Iq'j ) of a bus node (BK j ) is switched off when the bus node (BK j ) by means of the previously described first means (R2, D2, D3) determines that a first current above the threshold value flows through its first bus shunt resistor (R2) in the direction of the bus master (ECU) or by means of the previously described second means (R2', D2', D3') determines that only a second current above this threshold value flows through its second bus shunt resistor (R2') in the direction of the bus master (ECU). Symmetrical auto-addressing with bus shunt resistors through which the addressing current flows. Figure 6

[0062] Fig. 6 now shows another proposal based on the Fig. 5. Essential difference to Fig. 5 is now that the respective first addressing current sources ((Iq1) to [Iq n]) seen from the bus master (ECU), the first addressing current behind the first bus shunt resistors (R2) in the addressing phase in which the respective bus node (BK j ) is in an addressing state, if the respective bus node (BK j ) by means of the first means (R2, D2, D3) determines a current value of the first current through the first bus shunt resistor (R2) which is smaller than a predetermined first reference current value [I ref ] The third comparator (D3) is now preferably a third differential amplifier (D3). In contrast to the proposal of the Fig. 5, the first addressing current of the respective first addressing current source (Iq j ) of the respective bus node (BK j ) is now adjusted until the first current through the first bus shunt resistor (R2) corresponds to the specified first reference current [I ref ] . Analogously, in deviation from Fig. 5 the respective second addressing current sources ((Iq'1) to [Iq' n ]) seen from the bus master (ECU), the respective second addressing current also behind the corresponding second bus shunt resistors (R2') in the addressing phase in which the respective bus node (BK j ) is in an addressing state, if the respective bus node (BK j ) by means of the second means (R2', D2', D3') determines a current value of the second current through the second bus shunt resistor (R2) which is less than a predetermined second reference current value [I' ref ], which is preferably equal to the first reference current value [I ref ] The further third comparator (D3') is now preferably a further third differential amplifier (D3'). In contrast to the proposal of the Fig. 5, the second addressing current of the respective second addressing current source (Iq' j ) of the respective bus node (BK j) is now also adjusted until the second current through the second bus shunt resistor (R2') corresponds to the specified second reference current [I' ref ] corresponds.

[0063] Of course it is possible in the configuration of the Fig. 6 the addressing current sources ((lq1) to [Iq n ], (Iq'1) to [Iq' n ]) to switch instead of regulating.

[0064] The proposed bus hub (BK j ) is thus connected to a first addressing current source (Iq j ) to determine the bus position of the bus node (BK j ) in the serial, bidirectional, differential two-wire communication bus (DB), which inputs a first addressing stream into the first single-wire bus (DB a ) of the serial, bidirectional, differential two-wire communication bus (DB) in such a way that the first total current (i j) through the first bus shunt resistor (R2) of the bus node (BK j ) a predetermined or calculated or otherwise determined first total current [I ref ] corresponds. Preferably, the first addressing current flows through the first bus shunt resistor (R2). Preferably, the respective bus node (BK j ) now with a second addressing current source (Iq' j ) to determine the bus position of the bus node (BK j ) in the serial, bidirectional, differential two-wire communication bus (DB), which inject a second addressing stream into the second single-wire bus (DB b ) of the serial, bidirectional, differential two-wire communication bus (DB) in a controlled manner, so that the second total current (i j ) through the second bus shunt resistor (R2') of the bus node (BK j ) a predetermined or calculated or otherwise determined second total current [I' ref] . The second addressing current now flows through the second bus shunt resistor (R2'). For symmetry, it is helpful if the two addressing current sources (Iq j 'Iq' j ) are designed to match. All measuring and controlling components of the control loop should also be designed for these two addressing current sources (Iq j 'Iq' j ) must be executed in a matching manner to achieve full symmetry. Figures 7 to 9

[0065] The Fig. 7 to 9 represent the proposed advantageous features of the control. The control is illustrated using the example of the control of the first addressing current sources ((Iq1) to [Iq n ]), but also applies to the second addressing current sources ([Iq'1] to [Iq' n ]) in an analogous manner. The control characteristic for the first addressing current source (Iq j ) of a bus node (Bk j) is preferably generated by a first filter (F) that generates a first control signal [rw j ] of the relevant bus node (BK j ) is generated, with which the first addressing current source (Iq j ) of the relevant bus node (BK j ). The control characteristic for the second addressing current source (Iq' j ) of a bus node (Bk j ) is preferably generated by a second filter or a second controller (F'), which generates a second control signal (rw' j ) of the relevant bus node (BK j ) is generated, with which the second addressing current source (Iq' j ) of the relevant bus node (BK j ) is controlled. Figure 7

[0066] Fig. Figure 7 shows, by way of example, the course of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3) in an exemplary data bus system with n=3 bus nodes (BK1 to BK3). It also shows the first addressing current (I 1_intern ) of the first addressing current source (Iq1) of the first bus node (BK1), the first addressing current (I 2_intern ) of the first addressing current source (Iq2) of the second bus node (BK2) and the first addressing current (I 3_intern ) of the first addressing current source (Iq3) of the third bus node (BK3). Here, the time constants for the up-regulation of the first addressing current of the first addressing current sources and the down-regulation of the first addressing current of the first addressing current sources are approximately the same. An overshoot occurs. It is clearly visible that the first addressing current (I 1_intern) of the first addressing current source (Iq1) of the first bus node (BK1) and the first addressing current (I 2_intern ) of the first addressing current source (Iq2) of the second bus node (BK2) are regulated down by the regulators of these first auto-addressing bus nodes, while the first addressing current (I 3_intern ) of the first addressing current source (Iq3) of the third bus node (BK3) to the reference value [I ref ] is regulated. The settling time is determined by a first time constant [t1] for increasing the first addressing current of the first addressing current sources (Iq1 to Iq3). Figure 8

[0067] Fig. Figure 8 shows the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3). It also shows the current (I 1_intern) of the first addressing current source (Iq1) of the first bus node (BK1), the current (I 2_intern ) of the first addressing current source (Iq2) of the second bus node (BK2) and the current (I 3_intern ) of the first addressing current source (Iq3) of the third bus node (BL3). Here, the first time constants [t1] for the upregulation of the first addressing current of the first addressing current sources are approximately ten times as long as the second time constants [τ2] for the downregulation of the first addressing current of the first addressing current sources. Only a minimal overshoot occurs. Figure 9

[0068] Fig. Figure 9 shows the curves of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3). Here, the first time constants [τ1] for the upregulation of the first addressing current of the first addressing current sources are approximately 100 times as long as the second time constants [τ2] for the downregulation of the first addressing current of the first addressing current sources. No overshoot occurs.

[0069] Preferably, the bus node (BK j ) first means (R2, D2) for detecting the current through the first bus shunt resistor (R2) and / or second means (R2', D2') for detecting the current through the second bus shunt resistor (R2').

[0070] If the data bus system is designed in such a way that the first and second addressing current of the two addressing current sources (Iq j 'Iq' j) are always fed from the bus master (ECU) behind the bus shunt resistors (R2, R2'), the current detected by the first bus shunt resistor (R2) and / or the second bus shunt resistor (R2') can be used for a self-test. With full symmetry, for example, both voltage drops across both bus shunt resistors (R2, R2') should preferably be equal. A cold solder joint, for example, can be easily detected this way. Figure 10

[0071] For error detection, it is advantageous to connect the bus node (BK j ) with a first detection device (DET) which detects the internal signals (ds1, ds3) of the bus node (BK j ) for plausibility. The internal signals are preferably control signals within the bus node (BK j). In the case of bus symmetry, for example, the symmetry of these signals can be checked. However, tests per channel are also possible. Reference is made to German patent application DE 10 2017 122 365B3, which was not yet published at the time of filing this document.

[0072] Fig. 10 shows the principle of such a detection. Fig. 10 shows the control loop of a bus node (BK j ). Here, j stands for a position in the bus chain of the bus nodes ((BK1) to [BK n ]) in the form of a positive, integer, natural number. It is a j-th bus node (BK j ), which is able to • Firstly, to detect a swap of its bus inputs with its bus outputs and • Secondly, in this case as an exemplary countermeasure ◯ the injection point for the first addressing current of its regulated first addressing current source (Iq j) in front of or behind its first bus shunt resistor (R2) so that auto-addressing is possible depending on the wiring and ◯ the feed point for the second addressing current of its regulated second addressing current source (Iq' j ) in front of or behind its second bus shunt resistor (R2') so that auto-addressing is possible depending on the wiring.

[0073] In the Fig. 10 only shows, by way of example, the repositioning of the feed point of the first addressing current of the first addressing current source (Iq j ) of the considered bus node (BK j ) is demonstrated. For the repositioning of the feed point of the second addressing current of the second addressing current source (Iq' j ) of the considered bus node (BK j ) the same applies.

[0074] The Fig. 10 exemplary j-th auto-addressing bus nodes (BK j) has for the repositioning of the feed point of the first addressing current of the first addressing current source (Iq j ) of the considered bus node (BK j ) a first detection device (DET) which is able to detect a swap of the bus input of the j-th bus node (BK j ) for the first single-wire bus (DB a ) with the bus output of the j-th bus node (BK j ) for the first single-wire bus (DB a ). For this purpose, the exemplary first detection device (DET) checks internal signals of the j-th bus node (BK j ) for plausibility. Let the internal signals of the j-th bus node (BK j ) to a swap of the bus input of the j-th bus node (BK j ) for the first single-wire bus (DB a )with the bus output of the j-th bus node (BK j ) for the first single-wire bus (DB a)safely, the first detection device (DET) can potentially take various exemplary measures: a. Signaling the error to a user; b. Signalling the error to the bus master (ECU) by means of a response to a diagnostic request (broadcast message) or by means of an interrupt line; c. Use of a predetermined error address as a valid bus node address; d. Reconfiguration of the internal topology to neutralize the fault; e. Reparameterization of internal sub-devices such as current sources to neutralize the fault; Further measures are conceivable.

[0075] In the example of Fig. 10, a reconfiguration of the internal topology is planned to neutralize the error. In the Fig. 10, for example, the first detection device (DET) changes the feed point for the first addressing current of the regulated first addressing current source (Iq j ) of the j-th bus node (BK j ), for example by means of a first analog demultiplexer (X3) and reverses the polarity of the inputs or the output of the second differential amplifier (D2) by means of the polarity signal (pol). Figure 11

[0076] For a better overview, the analog device for the second single-wire bus (DB b ) is not shown, as it is constructed analogously. Fig. 11 simplified examples of the j-th auto-addressing bus node (BK j ) has for the repositioning of the feed point of the second addressing current of the second addressing current source (Iq' j ) of the considered bus node (BK j) a second detection device (DET') which is able to detect a swap of the bus input of the j-th bus node (BK j ) for the second single-wire bus (DB b ) with the bus output of the j-th bus node (BK j ) for the second single-wire bus (DB b ). For this purpose, the exemplary second detection device (DET') checks further internal signals of the j-th bus node (BK j ) for plausibility. Let the internal signals of the j-th bus node (BK j ) to a swap of the bus input of the j-th bus node (BK j ) for the second single-wire bus (DB b ) with the bus output of the j-th bus node (BK j ) for the second single-wire bus (DB b ) close safely, the second detection device (DET') can potentially take various exemplary measures: a. Signaling the error to a user; b. Signalling the error to the bus master (ECU) by means of a response to a diagnostic request (broadcast message) or by means of an interrupt line; c. Use of an error address as bus node address; d. Reconfiguration of the internal topology to neutralize the fault; e. Reparameterization of internal sub-devices such as current sources to neutralize the fault; Further measures are conceivable.

[0077] Here, too, a reconfiguration of the internal topology can be provided to neutralize the fault. The second detection device (DET') can, for example, also be the feed point for the second addressing current of the regulated second addressing current source (Iq' j ) of the j-th bus node (BK j) for example by means of a second analog demultiplexer (X3') and swap the polarity of the inputs or the output of the further second differential amplifier (D2') by means of a second polarity signal (pol').

[0078] As an alternative to the previous example of Fig. 10 and Fig. 11, a re-parameterization of internal sub-devices such as current sources for neutralizing the fault is possible if instead of a first addressing current source (Iq j ) of the j-th bus node (BK j ) and a first multiplexer (X3) a first addressing current source [lq j1 ] of the j-th bus node (BK j ) and, for example, another first addressing current source [lq j2 ] of the j-th bus node (BK j ), of which the first addressing current source [lq j1 ] of the j-th bus node (BK j) feeds its first addressing current before the first bus shunt resistor (R2) and the further first addressing current source [lq j2 ] of the j-th bus node (BK j ) feeds its further first addressing current behind the first bus shunt resistor (R2). In this case, the first detection device (DET) would detect the first addressing current of one of the two first addressing current sources ([Iq j1 ], [lq j2 ]) to zero, so that the equivalent effect as with the combination of a first addressing current source (Iq j ) of the j-th bus node (BK j ) is achieved with switching by a first demultiplexer (X3).

[0079] For the second single-wire bus (DB b ) would then be used instead of a second addressing current source (Iq' j ) of the j-th bus node (BK j ) and a further second multiplexer (X3') a second addressing current source [Iq'j1] of the j-th bus node (BKj ) and, for example, another second addressing current source [Iq' j2 ] of the j-th bus node (BK j ), of which the second addressing current source [Iq'j1] of the j-th bus node (BK j ) feeds its second addressing current before the second bus shunt resistor (R2') and the further second addressing current source [Iq' j2 ] of the j-th bus node (BK j ) feeds its further second addressing current behind the second bus shunt resistor (R2'). In this case, the second detection device (DET') would detect the second addressing current of one of the two second addressing current sources ([Iq'j1], [Iq' j2 ]) to zero, so that the equivalent effect as when combining a second addressing current source (Iq' j ) of the j-th bus node (BK j ) with switching by a further second demultiplexer (X3').

[0080] For example, the first detection device (DET) can detect that the first control value of the first control signal (rw j ) of the j-th bus node (BK j ) the first addressing current of the first addressing current source (Iq j ) is maximized. This can be achieved, for example, with a suitable design by comparing the first control value of the first control signal (rw j ) with a tenth threshold value (Ref10). If the derivative of the first addressing current of the first auto-addressing current source (Iq j ) after the first control value of the first control signal (rw j ) is positive, this means that the first control value of the first control signal (rw j) is above the tenth threshold value (Ref10). Furthermore, the first detection device (DET) can simultaneously compare the output (ds2) of the second differential amplifier (D2) with an eleventh threshold value (Ref11). If the value of the output (ds2) of the second differential amplifier (D2) is below the eleventh threshold value (Ref11), the first detection device (DET) can conclude that there is a negative voltage drop across the first bus shunt resistor (R2) or that there is a voltage drop across the first bus shunt resistor (R2) close to zero. This condition is illegal because the first auto-addressing current source (Iq j ) does indeed provide a positive first addressing current, which, if correctly mounted, should flow through the first bus shunt resistor (R2), but this obviously does not happen.

[0081] For example, the second detection device (DET') can also detect that the second control value of the second control signal (rw' j ) of the j-th bus node (BK j ) the second addressing current of the second addressing current source (Iq' j ) is maximized. This can be achieved, for example, with a suitable design by comparing the second control value of the second control signal (rw' j ) with a further tenth threshold value (Ref10'), which is preferably equal to the tenth threshold value (Ref10). If the derivative of the second addressing current of the second auto-addressing current source (Iq' j ) according to the second control value of the second control signal (rw' j ) is positive, this means that the second control value of the second control signal (rw' j) is above the further tenth threshold value (Ref10'), which is preferably equal to the tenth threshold value (Ref10). Furthermore, the second detection device (DET') can simultaneously compare the further output (ds2') of the further second differential amplifier (D2') with a further eleventh threshold value (Ref11'). The further eleventh threshold value (Ref11') is preferably equal to the eleventh threshold value (Ref11). If the value of the further output (ds2') of the further second differential amplifier (D2') is below the further eleventh threshold value (Ref11), the second detection device (DET') can conclude a negative voltage drop across the second bus shunt resistor (R2') or a voltage drop across the second bus shunt resistor (R2') close to zero. This state is illegal because the second auto-addressing current source (Iq' j) does indeed provide a positive second addressing current, which, if correctly mounted, should flow through the second bus shunt resistor (R2'), but this obviously does not happen.

[0082] Preferably, the first detection device (DET) and the second detection device (DET') form a unit.

[0083] A switching of the bus direction, as described above, preferably only occurs when both detection devices (DET, DET') detect a swap of the bus connections.

[0084] The detection devices (DET, DET') can signal a detected error, for example, via a respective error signal (er, er') to a bus node internal computer or a suitable controller.

[0085] The test results can be transmitted through the bus node (BK j ) or a sub-device (DET, DET') of the bus node (BK j) to initiate and take predetermined measures when one or more of the detection devices (DET, DET') detect implausible internal signals within the bus node (BK j ). For example, the bus node (BK j ) assume a swap of input and output. To compensate for this, it is advantageous if the bus node (BK j ) has a first sub-device (X3) which defines the feed point of the first addressing current of the first addressing current source (Iq j ) and / or if the bus node (BK j ) has a second sub-device (X3') which defines the feed point of the second addressing current of the second addressing current source (Iq' j ). Preference is given to changes for controlling the first single-wire bus (DB a) and the first bus shunt resistor (R2) synchronously with the analog changes for controlling the second single-wire bus (DB b ) and the second bus shunt resistor (R2'). Instead of switching the feed point of the addressing current sources (iq j and IQ' j ) by means of said demultiplexers (X3, X3') it is also possible to use two different first addressing current sources instead of a single first addressing current source (Iq j ) is conceivable, which transforms the switching by means of the demultiplexer (X3) into a switching between these two first addressing current sources. Such a bus node (BK j ) has instead of a first addressing current source (Iq j) a first addressing current source and a further first addressing current source, wherein the first addressing current source feeds its first addressing current into a node connected to the first terminal of the first bus shunt resistor (R2) when it feeds current, and wherein the further first addressing current source feeds its first addressing current into a node connected to the second terminal of the first bus shunt resistor (R2) when it feeds current. The two first addressing current sources preferably feed their addressing currents such that the resulting total addressing current flows through the first bus shunt resistor (R2), which ensures the self-test capability. The bus node (BK j) further comprises, in comparison to the prior art, a second addressing current source and a further second addressing current source instead of a second addressing current source, wherein the second addressing current source feeds its addressing current into a node connected to the first terminal of the second bus shunt resistor (R2') when it feeds in current, and wherein the further second addressing current source feeds its addressing current into a node connected to the second terminal of the second bus shunt resistor (R2') when it feeds in current. These two second addressing current sources also preferably feed their addressing currents in such a way that the addressing current flows through the second bus shunt resistor (R2') in order to ensure self-test capability.

[0086] If several bus nodes are connected to a data bus, it must be ensured that dangerous overcurrent situations do not occur due to overshoots of the total bus current. Therefore, it has proven advantageous if the first addressing current source (Iq j ) increases the first addressing current with a first time constant [τ1] and decreases it with a second time constant [τ2] which is smaller than the first time constant [τ1] and / or when the second addressing current source (Iq' j) increases the second addressing current with a third time constant [τ3] and decreases it with a fourth time constant [τ4], which is smaller than the third time constant [τ3]. Preferably, the third time constant [τ3] and the first time constant [τ1] are chosen to have the same amount in order to dynamically ensure bus symmetry. For the same reason, the fourth time constant [τ4] and the second time constant [τ2] are chosen to have the same amount in order to dynamically ensure bus symmetry. Reference should be made here again to the Fig. 7 to 9. REDUCTION OF BUS RESISTANCE IN NORMAL OPERATION Figure 12

[0087] It is here on Fig. 12. It has now been proven that the bus shunt resistors (R2, R2') affect the properties of the single-wire buses (DB a , DB b) and thus the serial, bidirectional, differential two-wire communication bus (DB). Therefore, it was recognized that it is useful to use a first bus shunt bypass switch (S4) for each bus node (BK j ) the corresponding first bus shunt resistor (R2) of the bus node (BK j ) in normal operation, i.e. in the normal state of the bus node (BK j ), and to open this first bus shunt bypass switch (S4) only in the addressing state, thus allowing the first bus shunt resistor (R2) to become effective only in the addressing state. In order not to disturb the bus symmetry, it is therefore also advisable to use a second bus shunt bypass switch (S4') for each bus node (BK j ) the corresponding second bus shunt resistor (R2') of the bus node (BK j ) in normal operation, i.e. in the normal state of the bus node (BK j), and to open this second bus shunt bypass switch (S4') only in the addressing state and thus to allow the second bus shunt resistor (R2') to become effective only in the addressing state.

[0088] In the previously described bus node (BK j ) is therefore a bus node (BK j ), which is capable of carrying out a procedure for assigning bus addresses to bus nodes of a serial, bidirectional, differential two-wire communication bus (DB). The procedure for assigning bus addresses to bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n ]) of a serial, bidirectional, differential two-wire communication bus (DB) by means of first bus shunt resistors (R2) and by means of second bus shunt resistors (R2') in the individual bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n]) in an allocation period in which the bus nodes ((BK1) to [BK n ]) are in an addressing state, which distinguishes this method significantly from the state of the art. After the method for assigning bus addresses to the bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n ]) of the serial, bidirectional, differential two-wire communication bus (DB) in the allocation period is followed by an operating period in which the bus nodes are operated normally, i.e., are in a normal state. The bus node (BK j ) is thus preferably distinguished from the prior art by such a first bus shunt resistor (R2) and such a second bus shunt resistor (R2'). Preferably, the bus node (BK j ) are each provided with a first bus shunt bridging switch (S4), which is switched on before a bus address is assigned to the bus node (BK j) is open during the allocation period and is closed after a bus address has been assigned to the bus node during the allocation period and is closed during the operating period. Similarly, for reasons of symmetry, the bus node (BK j ) preferably a second bus shunt bridging switch (S4') is provided, which before a bus address is assigned to the bus node (BK j ) is open during the allocation period and which, after a bus address has been allocated to the bus node (BK j ) is closed during the allocation period and is closed during the operating period. These bus shunt bypass switches (S4, S4') significantly reduce the bus resistance and reduce sensitivity to electromagnetic interference. They thus improve EMC performance.

[0089] Differential symmetrical common-mode and differential-mode based auto-addressing Instead of a first addressing current of a first addressing current source (Iq j ) of a bus node (BKj ) and a second addressing current of a second addressing current source (Iq' j ) of a bus node (BK j ) can also be a common mode current source [GLlq j ] of a bus node (BK j ) with two outputs, both of which supply the same amount of common-mode current into the first single-wire bus (DB a )and the second single-wire bus (DB b ) of the serial bidirectional differential communication bus (DB) with the same sign. The first output of these two outputs corresponds to the first addressing current source (Iq j ). The second output then corresponds to the second addressing current source (Iq' j ). The first addressing current of the first addressing current source (Iq j ) is then equal in magnitude to the second addressing current of the second addressing current source (Iq' j ). The use of a single common-mode addressing current source [GLlqj ] has the advantage that only one control system is required.

[0090] Instead of a first addressing current of a first addressing current source (Iq j ) of a bus node (BK j ) and a second addressing current of a second addressing current source (Iq' j ) of a bus node (BK j ) can also be a push-pull current source [GGlq j ] of a bus node (BK j ) with two outputs, both of which supply the same amount of push-pull current into the first single-wire bus (DB a )and the second single-wire bus (DB b ) of the serial bidirectional differential communication bus (DB), but now with a different sign. The first output of these two outputs corresponds to the first addressing current source (Iq j ). The second output then corresponds again to the second addressing current source (Iq' j). The first addressing current of the first addressing current source (Iq j ) is then equal in magnitude but not in sign to the second addressing current of the second addressing current source (Iq' j ). The use of a single push-pull addressing current source[GLlq j ] also has the advantage that only one control system is required.

[0091] Mixed solutions using common-mode and differential-mode addressing current sources are conceivable.

[0092] Accordingly, a bus hub (BK j) for a serial, bidirectional, differential two-wire communication bus (DB) with a bus master (ECU), in which the serial, bidirectional, differential two-wire communication bus (DB) comprises a first single-wire bus (DB1) and a second single-wire bus (DB2). A first bus shunt resistor (R2), which is inserted into the first single-wire bus (DB1), and a second bus shunt resistor (R2'), which is inserted into the second single-wire bus (DB2), are part of the bus node (BK j ). The bus node also includes a differential first common-mode addressing current source [GLlq j ] to determine the bus position of the bus node (BK j ) in the serial, bidirectional, differential two-wire communication bus (DB). The differential first common-mode addressing current source [GLlq j ] can supply a first common-mode addressing current component in the manner into the first single-wire bus (DB a) of the serial, bidirectional, differential two-wire communication bus (DB) in a controlled manner so that the first total current (i j ) through the first bus shunt resistor (R2) of the bus node (BK j ) a predetermined or calculated or otherwise determined first total current [I ref ] At the same time, the differential first common-mode addressing current source [GLlq j ] a second common-mode addressing current component of the same magnitude and sign in the manner of again additionally into the second single-wire bus (DB b ) of the serial, bidirectional, differential two-wire communication bus (DB) in a regulated manner with the same sign as the sign of the first push-pull addressing current component, so that the second total current (i' j ) through the second bus shunt resistor (R2') of the bus node (BK j) the specified or calculated or otherwise determined first total current [I ref ] also corresponds. The first common-mode addressing current component of the common-mode addressing current source [GLlq j ] of the bus node (BK j ) flows through the first bus shunt resistor (R2) of the bus node (BK j ) towards the bus master (ECU). The second common-mode addressing current component of the common-mode addressing current source [GLlq j ] of the bus node (BK j ) flows through the second bus shunt resistor (R2') of the bus node (BK j ) towards the bus master (ECU).

[0093] In addition to the common-mode control, push-pull control is also possible. Therefore, a bus node (BK j) for a serial, bidirectional, differential two-wire communication bus (DB) with a bus master (ECU), in which the serial, bidirectional, differential two-wire communication bus (DB) comprises a first single-wire bus (DB1) and a second single-wire bus (DB2), and in which a first bus shunt resistor (R2) is inserted into the first single-wire bus (DB1) and a second bus shunt resistor (R2') is inserted into the second single-wire bus (DB2). The bus node (BK j ) then has a differential first push-pull addressing current source [GGlq j ] to determine the bus position of the bus node (BK j ) in the serial, bidirectional, differential two-wire communication bus (DB), which inject a first push-pull addressing current component into the first one-wire bus (DB a) of the serial, bidirectional, differential two-wire communication bus (DB) in a controlled manner, so that the first total current (i j ) through the first bus shunt resistor (R2) of the bus node (BK j ) a predetermined or calculated or otherwise determined first total current [I ref ] The push-pull addressing current source [GGlq j ] of the bus node (BK j ) feeds the second push-pull addressing current component, which is equal in amount, into the second single-wire bus (DB b ) of the serial, bidirectional, differential two-wire communication bus (DB) is regulated with the opposite sign to the sign of the first push-pull addressing current component, so that the second total current (i' j ) through the second bus shunt resistor (R2') of the bus node (BK j ) the specified or calculated or otherwise determined first total current [Iref ] also corresponds. The first push-pull addressing current component of the push-pull addressing current source [GGlq j ] of the bus node (BK j ) flows through the first bus shunt resistor (R2) of the bus node (BK j ) towards the bus master (ECU). The second push-pull addressing current component of the push-pull addressing current source [GGlq j ] of the bus node (BK j ) flows through the second bus shunt resistor (R2') of the bus node (BK j ) towards the bus master (ECU).

[0094] For control, the bus node (BK j ) preferably via first means (R2, D2) to detect the current through the first bus shunt resistor (R2) and / or via second means (R2', D2') to detect the current through the second bus shunt resistor (R2').

[0095] As previously explained, the ability to measure the voltage drop across the respective bus shunt resistor (R2, R2') can also be used for a self-test. Therefore, a bus node (BK j ) is proposed, in which the detected current through the first bus shunt resistor (R2) is used for a self-test and / or in which the detected current through the second bus shunt resistor (R2') is used for a self-test. In this case, the detected voltage drop across the bus shunt resistor is compared with an expected value. If the detected voltage deviates from the expected value by more than a specified amount, an error exists that can be signaled.

[0096] Preferably, the proposed bus node (BK j ) for this purpose at least one detection device (DET) which detects internal signals (ds1, ds3) of the bus node (BK j ) for plausibility. Preferably, the bus node (BKj ) or a sub-device (DET) of the bus node (BK j ) Measures if the detection device (DET) detects implausible internal signals within the bus node (BK j ). A possible measure can be taken by a first sub-device (X3) of the bus node (BK j ) and a second sub-device (X3') of the bus node (BK j ) in such a way that the feed points of the first common-mode addressing currents of the common-mode addressing current source [GLlq j ] by the first sub-device (X3) of the bus node (BK j ) and the second sub-device (X3') of the bus node (BK j ) be changed if a predetermined error is detected.

[0097] Another possible measure can be implemented by a first sub-device (X3) of the bus node (BK j ) and a second sub-device (X3') of the bus node (BK j) in such a way that the feed points of the first push-pull addressing currents of the push-pull addressing current source [GGlq j ] by the first sub-device (X3) of the bus node (BK j ) and the second sub-device (X3') of the bus node (BK j ) be changed if a predetermined error is detected.

[0098] Here, too, regulation of the addressing currents with specific time constants is desirable and recommended. Therefore, a bus node (BK j ) is proposed, in which the common-mode addressing current source [GLlq j ] increases the common mode addressing current with a first time constant [τ1] and decreases it with a second time constant [τ2] which is smaller than the first time constant [τ1].

[0099] Analogously, a bus node (BK j ) is proposed, in which the push-pull addressing current source [GGlq j] increases the push-pull addressing current with a first time constant [τ1] and decreases it with a second time constant [τ2] which is smaller than the first time constant [τ1]. AUTOADDRESSING USING AN INTERRUPT LINE Figure 13

[0100] Fig. 13 is based on Fig. 2. In addition to the addressing method described above, the bus node (BK j ), which is intended for a data bus system with a serial, bidirectional, differential two-wire communication bus (DB), for a different auto-addressing method (see Fig. 13). The relevant bus node (BK j ) is then again intended to work on a procedure for assigning logical bus node addresses to the bus nodes ((BK1) to [BK n ]) of the data bus system. The corresponding data bus system then has a bus master (ECU) with an address input (Adr i0). The data bus system should again have n bus nodes ((BK1) to [BK n ]) including this bus node (BK j ) even with n as a positive integer. The bus node (BK j ) is transmitted via a data line section ((DB1) to [DB n ]) or the serial, bidirectional, differential two-wire communication bus (DB) consisting of data line sections ((DB1) to [DB n ]) and further bus nodes ((BK2) to [BK n ]) is connected to the bus master (ECU) for data transmission. Within the data bus system, a line [L1 to L n ] from an address input (Adr i0 ) of the bus master (ECU) of the data bus system through all bus nodes ((BK1) to [BK n ]) of the data bus system including this bus node (BK j ) itself is looped through in such a way that it passes through the individual bus nodes ((BK1) to [BK n ]) including this bus node (BK j ) even in n line sections [L1 to Ln ] Each of the bus nodes (BK j ) includes an associated address input [Adr ij ] and a bus node (BK j ) associated address output [Adr oj ]. Each of the bus nodes (BK j ) with 1≤j≤ n-1, if it is not the n-th bus node [BK n ] is intended to be connected to its address input [Adr ij ] with the address output [Adr o(j+1) ] of a subsequent bus node [BK j+1 ] with 1≤j≤ n-1 by a bus node following [BK j+1 ] associated (j+1)-th line section [L j+1 ] from the (j+1)-th bus node [BK j+1 ] to the j-th bus node (BK j ) to be connected. Each of the bus nodes (BK j ), if it is not the first bus node (BK1), its address output [Adr oj ] with the address input [Adr i(j-1) ] of a preceding bus node [BK j-1 ] with 2≤j≤ n by a bus node (BK j) associated j-th line section[L j ] from the j-th bus node (BK j ) to the (j-1)-th bus node [BK j-1 ] The first bus node (BK1) is (j=1) connected to its address output (Adr o1 ) with the address input (Adr i0 ) of the bus master (ECU) by a bus node (BK j ) associated line section [L1]. The bus node address of the bus node (BK j ) in its bus node address register [BKADR j ] can be valid or invalid, as in this entire document. The proposed bus node now provides means and methods to set its bus node address and to make its bus node address valid or invalid. This can, for example, be special data contents (DATA) of bit packets (BP) of the bus master (ECU), with which the bus master (ECU) can control individual or several or all bus nodes ((BK1) to [BK n]) to invalidate the addresses in their bus node address registers. The proposed bus node (BK j ) can assume an addressing state and a second operating state (or normal state) different from the addressing state. The bus node (BK j ) preferably has means for switching between the addressing state and the second operating state depending on commands from the bus master (ECU). The bus node (BK j ) then has means to, when it is in the addressing state and if its bus node address is invalid, in this case, to change the logical state at the address input [Adr i(j-1) ] of a preceding bus node [BK j-1 ] to a first logical value by overwriting or, if it is in the addressing state and if its bus node address is invalid, in this case, to set the logical state at the address input (Adr i0) of a preceding bus master (ECU) to a first logical value by overwriting. The bus node (BK j ) further preferably has means for determining the logical state at its address input [Adr ij ] to a second logical value if this second logical value is not determined by a subsequent bus node [BK j+1 ] is overwritten with a first logical value, and means to adopt a bus node address signalled by the bus master (ECU) as its valid future bus node address if its bus node address is invalid and if it is in the addressing state and if its address input [Adr ij ] has a second logical value, and to mark this future bus node address as "valid" in this case.

[0101] In a refinement of this proposal, the address input [Adr ij ] of the bus node (BK j) in the second operating state as an input of an interrupt signal of a subsequent bus node [BK j-1 ] can be used. In this way, an interrupt line can be used for the auto-addressing of bus nodes of a serial, bidirectional, differential two-wire communication bus (DB). Preferably, the address output [Adr oj ] of the bus node (BK j ) in the second operating state as an output of an interrupt signal of a subsequent bus node [BK j-1 ] and / or the bus node (BK j ) itself. Figure 14

[0102] Fig. 14 describes the basic sequence of the preferred address allocation method described here. After starting the address allocation method (START), the bus master (BM) signals in a first method step (1) by means of a preferred first broadcast command preferably to one bus node or preferably to all or at least part of the set of bus nodes ((BK1) to [BK n ]) that such a procedure for assigning bus node addresses for these bus nodes is started. This preferably results in all these bus nodes ((BK1) to [BK n ]) invalidate or delete any valid bus node addresses present in these bus nodes. If addressing is to be performed using an interrupt line looped through all bus nodes [L1 to L n ] as in Fig. 13, in this preferred version of the proposal this interrupt line [L1 to L n] for the duration of the addressing process this function and is integrated into the said point-to-point connections between the bus nodes ((BK1) to [BK n ]) and the point-to-point connection between the first LED bus node (BK1) and the bus master (BM) is split. In a second process step (2), the bus master (ECU) splits the bus node ((BK1) to [BK n ]) that a bus node address is to be assigned and which logical bus node address this is. The bus node, here arbitrarily the jth bus node (BK j ), whose address input [Adr ij ] has a second logical value, then takes over the bus address offered by the bus master (BM) in this process step and sets its address output [Adr oj ] in such a way that it uses the address input [Adr i(j-1) ] of a preceding bus node [BK j-1] no longer overwrites the first logical value, but a second logical value at the address input [Adr i(j-1) ] of a preceding bus node [BK j-1 ] This second logical value is then given priority by the preceding bus node [BK j-1 ] himself at his address entrance [Adri (j-1) ] is imprinted. In a further third step (3), the bus master (ECU) checks whether the logical value at its address input (Adr i0 ) corresponds to a second logical value or not. If it does not correspond (N), the bus master (ECU) repeats the second process step (2). If it corresponds to this logical value (J), the bus master (ECU) terminates the process by performing a fourth process step (4). If necessary, it first carries out a check for correct assignment. Preferably, the bus master (ECU) sends a message to all bus nodes ((BK1) to [BK n]) that the bus node addresses have been assigned. This causes the bus nodes ((BK1) to [BK n ]) again from the addressing state that was assumed with the first method step (1) into another operating state, preferably the normal operating state or normal state. In particular, the bus nodes ((BK1) to [BK n ]) After performing this fourth step, any looped interrupt line used for the point-to-point connections is used again as an interrupt line. This concludes the proposed method as such (END). Symmetrical auto-addressing method using bus shunt resistors

[0103] Here we describe a procedure for addressing the bus nodes ((BK1) to [BK n ]) of a data bus system using a symmetric method is discussed.

[0104] It is an auto-addressing method for addressing the bus nodes ((BK1) to [BKn ]) of a data bus system based on a serial, bidirectional, differential two-wire communication bus (DB). The data bus system comprises a bus master (ECU), a serial, bidirectional, differential two-wire communication bus (DB) originating from the bus master (ECU), and several addressable bus nodes ((BK1) to [BK n ]) connected to the serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, differential two-wire communication bus (DB) consists of the first single-wire bus (DB a ) and the second single-wire bus (DB b ). Each bus node that has not yet been addressed (BK j ) the bus nodes ((BK1) to [BK n ]) does not have a valid bus node address and therefore feeds a first addressing current into the first single-wire bus (DB a ) and a second addressing current into the second single-wire bus (DB b). All of these addressing streams flow through the serial, bidirectional, differential two-wire communication bus (DB) towards the bus master (ECU). Each bus node (BK) that has not yet been addressed j ) detects the signal transmitted by the first single-wire bus (DB a ) of the serial, bidirectional, differential two-wire communication bus (DB) and the first current flowing through the second single-wire bus (DB b ) of the serial, bidirectional, differential two-wire communication bus (DB). Only the not yet addressed bus node (BK j) which does not detect a first current or only detects a first current which is smaller than a predefinable first threshold value and which at the same time does not detect a second current or only detects a second current which is smaller than a predefinable further first threshold value is identified as a bus node which has not yet been addressed. The bus node identified in this way is assigned an address for the purpose of addressing, whereby it receives a valid bus node address. The aforementioned steps are carried out without the last addressed bus node until all bus nodes which have not yet been addressed have been addressed. Preferably, the first threshold value is equal to the further first threshold value and the value of the first addressing current within a bus node is equal to the value of the second addressing current within this bus node.

[0105] In addition to addressed bus nodes, i.e., those with a valid bus node address, unaddressed bus nodes without a valid bus node address can also be connected to the serial, bidirectional, differential two-wire communication bus (DB). The unaddressed bus node feeds into the first single-wire bus (DB a ) a first quiescent current and into the second single-wire bus (DB b ) a second quiescent current. Each bus node that has not yet been addressed detects the current generated by the first single-wire bus (DB a ) and the first quiescent current flowing through the second single-wire bus (DB b ) flowing second quiescent current. Only the not yet addressed bus nodes with invalid bus node addresses feed the first addressing currents into the first single-wire bus (DB a ) and the second addressing streams into the second single-wire bus (DB b). Only the not yet addressed bus node which, when the addressing currents are fed in by all not yet addressed bus nodes, does not detect any current difference in the first or second current compared to the previous current detection, or only detects a current difference in the first or second current that is smaller than a predefinable second threshold value, is identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for addressing purposes, whereby it receives a valid bus node address. The aforementioned steps are carried out without the last addressed bus node in each case until all not yet addressed bus nodes have been addressed. The second threshold value is preferably equal to the first threshold value or the further first threshold value.

[0106] In a further variant of the method, each addressable bus node feeds into the first single-wire bus (DB a) a first quiescent current, which can be zero, and into the second single-wire bus (DB b ) a second quiescent current, which can be zero. Each unaddressed bus node without a valid bus node address feeds a first quiescent current into the first single-wire bus (DB a ) and a second quiescent current into the second single-wire bus (DB b ). Each bus node not yet addressed detects the signal transmitted by the first single-wire bus (DB a ) due to the quiescent current supply and the first current flowing through the second single-wire bus (DB b) due to the quiescent current injection. This determines which of the not yet addressed bus nodes detects a first current that is above a predeterminable third threshold, and which of the not yet addressed bus nodes detects a second current that is above a predeterminable third threshold. Only those not yet addressed bus nodes that detect a first current that is less than or equal to the third threshold when the quiescent currents are injected feed first addressing currents into the first single-wire bus (DB a ) and only those bus nodes that have not yet been addressed and that detect a second current that is smaller than or equal to the third threshold value when feeding in the quiescent currents, preferentially feed second addressing currents into the second single-wire bus (DB b). It is preferred at this point if only those bus nodes which have not yet been addressed and which, when feeding in the quiescent currents, detect a first current which is less than or equal to the third threshold value, and which, at the same time, when feeding in the quiescent currents, detect a second current which is less than or equal to the further third threshold value, feed first addressing currents into the first single-wire bus (DB a ) and second addressing streams into the second single-wire bus (DB b ) feed in.

[0107] From the group of these not-yet-addressed bus nodes feeding addressing currents, only the bus node that detects no first current or only a first current that is less than a predefinable fourth threshold, and that detects no second current or only a second current that is less than a predefinable further fourth threshold, is identified as a not-yet-addressed bus node. The bus node identified in this way is assigned an address for addressing purposes. The aforementioned steps are carried out without the last addressed bus node in each case until all not-yet-addressed bus nodes have been addressed. Preferably, the third and / or fourth threshold and / or the further third and / or further fourth threshold and the first threshold are the same.

[0108] In a variant of the method, non-addressable bus nodes are connected to the serial, bidirectional, differential two-wire communication bus (DB) in addition to the addressable bus nodes. Such a non-addressable bus node feeds into the first single-wire bus (DB a ) a first quiescent current and into the second single-wire bus (DB b ) a second quiescent current. Each bus node that has not yet been addressed determines the first addressing currents before feeding them into the first single-wire bus (DB a ) in the first single-wire bus (DB a ) due to the quiescent current feed of all non-addressable bus nodes by a first current detection. Each not yet addressed bus node determines before feeding the second addressing currents into the second single-wire bus (DB b ) in the second single-wire bus (DB b) due to the quiescent current feed of all non-addressable bus nodes, a second current detection is used. Subsequently, each addressable bus node feeds into the first single-wire bus (DB a ) a first quiescent current and into the second single-wire bus (DB b ) a second quiescent current. This determines which of the not yet addressed bus nodes has a first current in the first single-wire bus (DB a ) which is above a predeterminable fifth threshold value, and / or a second current in the second single-wire bus (DB b ) is detected which is above a further, predefined fifth threshold value. Only those bus nodes which have not yet been addressed and which, when the first quiescent currents are fed into the first single-wire bus (DB a ) detect a first current that is less than or equal to the fifth threshold, feed first addressing currents into the first single-wire bus (DBa ). Only those bus nodes that have not yet been addressed and which, when the second quiescent currents are fed into the second single-wire bus (DB b ) detect a second current which is less than or equal to the further fifth threshold value, feed second addressing currents into the second single-wire bus (DB b ). However, it is particularly preferred if only those bus nodes that have not yet been addressed and which, when the first quiescent currents are fed into the first single-wire bus (DB a ) detect a first current which is less than or equal to the fifth threshold value, and which, at the same time, when the second quiescent currents are fed into the second single-wire bus (DB b ) detect a second current which is less than or equal to the further fifth threshold value, first addressing currents into the first single-wire bus (DB a) and second addressing streams into the second single-wire bus (DB b ) feed in.

[0109] From the group of these not-yet-addressed bus nodes feeding addressing currents, only the bus node that detects no current difference in the first current compared to the first current detection or only a current difference in the first current that is less than a predeterminable sixth threshold, and that detects no current difference in the second current compared to the first current detection or only a current difference in the second current that is less than a predeterminable further sixth threshold, is identified as a not-yet-addressed bus node. The bus node identified in this way is assigned an address for addressing purposes. The aforementioned steps are carried out without the last addressed bus node in each case until all not-yet-addressed bus nodes have been addressed.The fifth threshold value and / or the sixth threshold value and / or the further fifth threshold value and / or the further sixth threshold value and / or the first threshold value are preferably the same.

[0110] The first current detection preferably takes place in the bus node via the first bus shunt resistors (R2) of the first single-wire bus (DB a ) and the second current detection preferably takes place in the bus node via the second bus shunt resistors (R2') of the second single-wire bus (DB b ). The first bus shunt resistors (R2) assigned to an addressable bus node preferably correspond, at least in terms of value, to the second bus shunt resistors (R2') assigned to the respective addressable bus node. All first bus shunt resistors (R2) are preferably in the first single-wire bus (DB a ) along the first single-wire bus (DB a) in series and all second bus shunt resistors (R2') are preferably in the second single-wire bus (DB b ) along the second single-wire bus (DB b ) connected in series.

[0111] Instead of current detection, voltage detection can also be carried out in the bus nodes.

[0112] The assignment of an address is then typically carried out by transmitting an address to the identified bus node in that the same address is transmitted to all bus nodes that have not yet been addressed before a bus node is identified and only the subsequently identified bus node accepts this address as its bus node address.

[0113] Preferably, the assignment of an address takes place after the first identification of a bus node and / or a verification of the bus node address takes place after the identification of a bus node.

[0114] The verification of the identification of a bus node can be carried out, for example, by identifying the bus node again and / or by identifying the bus node using the other single-wire bus and comparing the second identification with the first identification.

[0115] Verification of a participant's identification can also be achieved by re-identifying the participant using a different auto-addressing method and comparing the second identification with the first identification. Any errors that occur are signaled. ASYMMETRICAL AUTOADDRESSING METHOD VIA BUS SHUNT RESISTORS

[0116] The data bus system comprises a bus master (ECU), a serial, bidirectional, differential two-wire communication bus (DB) originating from the bus master (ECU) and several addressable bus nodes ((BK1) to [BK n]) that are connected to the serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, differential, two-wire communication bus (DB) consists of a first single-wire bus (DB a ) and a second single-wire bus (DB b ). In the first auto-addressing method discussed here, each bus node that has not yet been addressed (BK j ) the bus nodes ((BK1) to [BK n ]) for identifying an addressing current in at least ONE single-wire bus of the single-wire buses (DB a , DB b ). Each bus node that has not yet been addressed feeds the addressing current into at least one single-wire bus, hereinafter referred to as the addressing single-wire bus. However, it is preferred if this addressing current is fed into both single-wire buses (DB a , DB b). All other bus nodes that have not yet been addressed also feed their respective addressing current into the addressing single-wire bus. All addressing currents flow through the serial, bidirectional, differential two-wire communication bus (DB) towards the bus master (ECU). Each bus node that has not yet been addressed (BK j ) detects the current flowing through the addressing single-wire bus of the serial, bidirectional, differential two-wire communication bus (DB). This detection is preferably carried out via the bus shunt resistors (R2, R2') mentioned above. Only the bus node that has not yet been addressed (BK j) that detects no current or only a current that is less than a predefined first threshold is identified as an unaddressed bus node. The bus node thus identified is assigned an address for addressing purposes, which gives it a valid bus node address. This is preferably determined by the bus master (ECU). The previously mentioned steps are repeated without the last addressed bus node, i.e., another initialization run is performed until all unaddressed bus nodes have been addressed.

[0117] It may happen that, in addition to the addressed bus nodes, one or more unaddressed bus nodes are connected to the serial, bidirectional, differential two-wire communication bus (DB), which inject a quiescent current into the addressing single-wire bus. In this case, the previously described procedure must be modified. This modification then requires that each unaddressed bus node detects the quiescent current flowing through the addressing single-wire bus before injecting the addressing currents. Only the unaddressed bus nodes inject the addressing currents into the addressing single-wire bus.Only the unaddressed bus node that, when the addressing currents are fed through all unaddressed bus nodes, detects no current difference compared to the previous current detection, or only detects a current difference that is smaller than a predefined second threshold, is identified as an unaddressed bus node. The bus node thus identified is assigned an address for addressing purposes, thereby obtaining a valid bus node address. The aforementioned steps are performed without the last addressed bus node until all unaddressed bus nodes have been addressed. Preferably, the second threshold is equal to the first threshold.

[0118] Incidentally, it can also happen that each addressable bus node feeds a quiescent current into the addressing single-wire bus, and that each unaddressed bus node feeds a quiescent current into the addressing single-wire bus. The procedure is then modified similarly to the one described above: Each unaddressed bus node again detects the current flowing through the addressing single-wire bus due to the quiescent current feed. A circuit within the bus nodes (BK j) then determines which of the as yet unaddressed bus nodes detects a current that is above a predeterminable third threshold. Only those as yet unaddressed bus nodes that detect a current that is less than or equal to the third threshold when the quiescent currents are fed in feed addressing currents into the addressing single-wire bus. From the group of these as yet unaddressed bus nodes feeding in addressing currents, only the bus node that detects no current or only a current that is less than a predeterminable fourth threshold is identified as an as yet unaddressed bus node. The bus node identified in this way is assigned an address for addressing purposes, whereby it receives a valid bus node address.The aforementioned steps are again performed without the last addressed bus node until all unaddressed bus nodes have been addressed. Here, too, the third and / or fourth threshold is preferably equal to the first threshold.

[0119] Again, it may happen that, in addition to the addressable bus nodes, at least one non-addressable bus node is connected to the serial, bidirectional, differential two-wire communication bus (DB), which feeds a quiescent current into the addressing single-wire bus. Again, the method is appropriately modified: Before feeding the addressing currents, each non-addressable bus node determines the current flowing in the addressing single-wire bus based on the quiescent current feed of all non-addressable bus nodes through a first current detection. Subsequently, each addressable bus node feeds a quiescent current into the addressing single-wire bus. It is then determined which of the non-addressable bus nodes detects a current that is above a predeterminable fifth threshold.Only those not yet addressed bus nodes that detect a current less than or equal to the fifth threshold when the quiescent currents are fed in feed addressing currents into the addressing single-wire bus. From the group of these not yet addressed bus nodes feeding addressing currents, only the bus node that detects no current difference compared to the first current detection or only detects a current difference less than a predefined sixth threshold is identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for addressing purposes, whereby it receives a valid bus node address. The previously mentioned steps are again carried out without the last addressed bus node until all not yet addressed bus nodes have been addressed.Again, preferably the fifth threshold and / or sixth threshold is equal to the first threshold.

[0120] The current detection in the bus nodes is preferably carried out via shunt resistors of the addressing single-wire bus assigned to the addressable bus nodes, wherein in the other single-wire bus, which is not the addressing single-wire bus, further bus shunt resistors assigned to the addressable participants are preferably, but not necessarily, arranged in the participants, which preferably correspond in value to the shunt resistors in the addressing single-wire bus. Most preferably, the bus shunt resistors (R2, R2') in the two single-wire buses (DB a , DB b) with each other. All shunt resistors in the addressing single-wire bus along the addressing single-wire bus are preferably connected in series. All shunt resistors in the other single-wire bus along this other single-wire bus are also preferably connected in series.

[0121] It is possible to perform voltage detection in the bus nodes instead of current detection.

[0122] A variant of the method provides that the assignment of an address is carried out by transmitting an address to the identified bus node or by transmitting the same address to all bus nodes not yet addressed before a bus node is identified and that only the subsequently identified bus node accepts this address as its bus node address.

[0123] A further variant of the proposed method provides that the assignment of an address takes place after the first identification of a bus node or that a verification of the bus node address takes place after the identification of a bus node.

[0124] A further variant of the proposed method provides that the verification of the identification of a bus node is carried out by identifying the bus node again and / or by identifying the bus node by means of the other single-wire bus and comparing the second identification with the first identification.

[0125] A further variant of the proposed method provides for the verification of a participant's identification by re-identifying the participant using a different auto-addressing method and comparing the second identification with the first identification. Preferably, the bus node and / or the bus master then signal an error. Symmetrical auto-addressing method via bus shunt resistors with self-test capability and addressing current control

[0126] Furthermore, a self-testing auto-addressing method for assigning bus node addresses within a data bus system is proposed. The data bus system comprises a serial, bidirectional, differential two-wire communication bus (DB) with a chain of n bus nodes ((BK1), (BK2), (BK3), ..... [BK n-1 ], [BK n]), with n as a positive integer greater than zero, and a bus master (ECU). The serial, bidirectional, differential two-wire communication bus (DB) is connected to the bus master (ECU). Each bus node ((BK2), (BK3), ..... [BK n-1] , [BK n ]) has a preceding bus node ((BK1), (BK2), (BK3), ..... [BK n-1] ) if it is not the first bus node (BK1) and each bus node ((BK2), (BK3), ..... [BK n-1] , [BK n ]) is connected to its preceding bus node ((BK1), (BK2), (BK3), ..... [BK n-1] ) by the serial, bidirectional, differential two-wire communication bus (DB) by means of a connecting section of the serial, bidirectional, differential two-wire communication bus (DB) if it is not the first bus node (BK1). The serial, bidirectional, differential two-wire communication bus (DB) consists of a first single-wire bus (DB a ) and a second single-wire bus (DBb ). The first bus node (BK1) is connected to the bus master (ECU) via the serial, bidirectional, differential two-wire communication bus (DB) by means of a connecting section of the serial, bidirectional, differential two-wire communication bus (DB). Each bus node (BK2), (BK3), ..... [BK n-1] , [BK n ]) sends a first bus node output current ((i2), (i3), ...[i( n-1 )] [i n ]) via the section (DB1) of the first single-wire bus (DB a ), the part of the connection section between this bus node ((BK2), (BK3), ..... [BK n-1] , [BK n ]) and its preceding bus node ((BK1), (BK3), ..... [BK n-1] , [BK n-1] ) is, at its preceding bus nodes ((BK1), (BK2), (BK3), ..... [BK n . 1]), if it is not the first bus node (BK1). Each bus node ((BK2), (BK3), ..... [BK n-1] , [BK n]) sends a second bus node output current ((i'2), (i'3),...[i' (n-1) ], [i' n ]) via the section (DB2) of the second single-wire bus (DB b ), the part of the connection section between this bus node ((BK2), (BK3), ..... [BK n-1] , [BK n ]) and its preceding bus node ((BK1), (BK3), ..... [BK n-1] , [BK n-1 ]) is connected to its preceding bus nodes ((BK1), (BK2), (BK3), ..... [BK n-1 ]) if it is not the first bus node (BK1). The first bus node (BK1) sends a first bus node output current (i1) via the section (DB1) of the first single-wire bus (DB a ), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), to the bus master (ECU). The first bus node (BK1) sends a second bus node output current (i2) via the section (DB2) of the second single-wire bus (DB b), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), to the bus master (ECU). The bus master (ECU) receives a first bus node input current (i1) via the section (DB1) of the first single-wire bus (DB a ), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), from its subsequent first bus nodes (BK1). The bus master (ECU) receives a second bus node input current (i'1) via the section (DB2) of the second single-wire bus (DB b ), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), from its subsequent first bus nodes (BK1). Each bus node ((BK1), (BK2), ..... [BK n-1] ) receives a first bus node input current ((i2), (i3), ...[i( n-1 )], [i n ]) via the section (DB1) of the first single-wire bus (DB a), the part of the connection section between this bus node ((BK2), (BK3), ..... [BK n-1] , [BK n ]) and its preceding bus node ((BK1), (BK3), ..... [BK n-1] , [BK n-1] ), from its subsequent bus nodes ((BK2), (BK3), ..... [BK n-1] , [BK n ]), if it is not the last bus node [BK n] Each bus node [(BK1), (BK2), ..... [BK n-1] ) receives a second bus node input current ((i2), (i3), ...[i( n-1 )] [i n ]) over the section of the second single-wire bus (DB b ), the part of the connection section between this bus node ((BK2), (BK3), ..... [BK n-1] , [BK n ]) and its preceding bus node ((BK1), (BK3), ..... [BK n-1] , [BK n-1] ), from its subsequent bus nodes ((BK2), (BK3), ..... [BK n-1] , [BK n ]), if it is not the last bus node [BK n]This method, in contrast to the previously described method, uses both single-wire buses (DB a and DB b ) for the transmission of the addressing currents. First, a maximum addressing current [I amax] This is followed by the execution of an initialization sequence comprising the following steps for each auto-addressing bus node of the n bus nodes ((BK1), (BK2), ..... [BK n-1] , [BK n ]), which does not yet have a valid bus node address, until all auto-addressing bus nodes of the n bus nodes ((BK1), (BK2), ..... [BK n-1] , [BK n ]) have a valid bus node address: • Signaling of a bus address to be assigned to all auto-addressing bus nodes of the n bus nodes ((BK1), (BK2), ..... ]BK n-1] , [BK n] ); • Perform the following steps for each auto-addressing bus node (BK j) the auto-addressing bus nodes of the n bus nodes ((BK1), (BK2), ..... ]BK n-1] , [BK n ]), hereinafter referred to as the relevant auto-addressing bus node (BK j ) designated: • Reception of the said auto-addressing command from the bus master (ECU) by the relevant auto-addressing bus node (BK j ); • Receipt of the bus address to be assigned from the bus master (ECU) by the relevant auto-addressing bus node (BK j ); • Receipt of a start signal for the allocation of the bus address to be allocated from the bus master (ECU) by the relevant auto-addressing bus node (BK j ) and start of a timer by the relevant auto-addressing bus node (BK j ); • Feeding in the data from the following bus nodes ([BK j+1 ], [BK j+2 ] ... [BK n-1] , [BK n ]) received first bus input current [i( j+1)] via the section (DB1) of the first single-wire bus (DB a ), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the respective auto-addressing bus node (BK j ) and the preceding (j-1)-th bus node [BK j-1] is, as part of the first bus output current [i j] of the relevant auto-addressing bus node (BK j ); • Feeding in the data from the following bus nodes ([BK j+1] , [BK j+2] ...) received second bus input current [i'( j+1 )] via the section (DB2) of the second single-wire bus (DB b ), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the respective auto-addressing bus node (BK j ) and the preceding (j-1)-th bus node [BK j-1] is, as part of the second bus output current (i' j) of the relevant auto-addressing bus node (BK j ); • Detecting the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) by means of first measuring means (R2, D2, D3); • Detecting the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) by means of second measuring means (R2', D2', D3'); • Generation of a first control signal (rw j ) from the detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) by means of first means of regulation (F); • Generation of a second control signal (rw' j ) from the detected second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) by means of second regulating means (F'); • Regulating the first bus node output current (i j ) by the relevant auto-addressing bus node (BK j ), by means of a first regulated auto-addressing current source (Iq j ), whose first addressing current is a portion of the first bus output current (i j ), to a first predetermined total current value [I ref ] depending on the generated first control signal (rw j ), whereby an increase of the first addressing current of the first regulated auto-addressing current source (Iq j ) of the relevant auto-addressing bus node (BK j ) with a first time constant [τ 1] and wherein a reduction of the first addressing current of the first regulated auto-addressing current source (Iq j ) of the relevant auto-addressing bus node (BK j ) with a second time constant [τ 2] and where the second time constant [τ 2]is smaller than the first time constant [τ 1] ; • Regulating the second bus node output current (i' j ) by the relevant auto-addressing bus node (BK j ), by means of a second regulated auto-addressing current source (Iq' j ), whose second addressing current is a portion of the second bus output current (i' j ) to a second predetermined total current value [l' ref] depending on the generated second control signal (rw' j ), wherein an increase in the second addressing current of the second regulated auto-addressing current source (Iq' j ) of the relevant auto-addressing bus node (BK j ) with a third time constant [τ 3] and wherein a reduction of the second addressing current of the second regulated auto-addressing current source (Iq' j ) of the relevant auto-addressing bus node (BK j ) with a fourth time constant [τ4] and where the fourth time constant [τ 4] is smaller than the third time constant [τ3]; ▪ Compare the first control value [r j ] of the first control signal (rw j ) of the relevant auto-addressing bus node (BK j ) with a first threshold value [SW j ] of the relevant auto-addressing bus node (BK j ); ▪ Compare the second control value [r' j ] of the second control signal (rw' j ) of the relevant auto-addressing bus node (BK j ) with a second threshold value [SW' j ] of the relevant auto-addressing bus node (BK j ); ▪ Freezing the regulation of the first addressing current source (Iq j ) of the relevant auto-addressing bus node (BK j ) at a first time t1 after the start of the timer; ▪ Freezing the regulation of the second addressing current source (Iq' j) of the relevant auto-addressing bus node (BK j ) at a second time t2 after the start of the timer; ▪ Acceptance of the bus node address to be assigned from the bus master (ECU) as a valid bus node address of the relevant auto-addressing bus node (BK j ) if a minimum time has passed since the start of the timer and if the comparison of the first control value [r j ] with the first threshold [SW j ] results in the first addressing current of the first addressing current source (Iq j ) of the relevant auto-addressing bus node (BK j ) is above a current threshold and / or if the comparison of the second control value [r' j ] with the second threshold [SW' j ] results in the second addressing current of the second addressing current source (Iq j ) of the relevant auto-addressing bus node (BK j) is above a current threshold and configuration of the relevant auto-addressing bus node (BK j ) as a bus node without auto-addressing capability with the bus node address to be assigned as the valid bus node address of the relevant auto-addressing bus node (BK j ) at a third time t3 after the first time t1 and after the second time t2, whereby this auto-addressing bus node (BK j ) will no longer participate in the following initialization sequences until further notice. • Checking the successful address assignment by the bus master (ECU); • If necessary, deletion of the validity of the last assigned bus node address, whereby the relevant auto-addressing bus nodes (BK j ) behave like auto-addressing bus nodes (BK j ) without a valid bus node address; • Check whether all auto-addressing bus nodes have received a valid bus node address; • Performing another initialization sequence if not all auto-addressing bus nodes have received a valid bus node address.

[0127] This basic method can be supplemented with an additional step after or together with the adoption of the bus node address to be assigned. It then comprises bridging the first bus shunt resistor (R2) by means of a first bus shunt bridging switch (S4) and / or bridging the second bus shunt resistor (R2') by means of a second bus shunt bridging switch (S4') when changing from the addressing state with an invalid bus node address of the respective bus node (BK j ) into the addressing state with a valid bus node address of the respective bus node (BK j ) or when switching to the normal state. This approach has the advantage of reducing bus resistance during operation (normal state after address assignment).

[0128] When transitioning to auto-addressing mode (addressing state), the bridging of the bus shunt resistors (R2, R2') is reversed. The procedure then includes opening the first bus shunt bridging switch (S4) when the bus node address of the relevant auto-addressing bus node (BK j ) is not valid, and / or opening the second bus shunt bypass switch (S4') if the bus node address of the relevant auto-addressing bus node (BK j ) is not valid.

[0129] Incidentally, the third time constant [τ3] is preferably smaller by a factor greater than 10 than the first time constant [τ 1] and as the second time constant [τ 2] The third time constant τ3 preferably depends in a process variant within the respective auto-addressing bus node (BK j ) from the first value of the first bus node output current (ij ) of the relevant auto-addressing bus node (BK j ) and / or from the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) away.

[0130] Preferably, the first time constant [τ 1] within the relevant auto-addressing bus node (BK j ) from the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) and / or the second time constant [τ 2] within the relevant auto-addressing bus node (BK j ) from the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) away.

[0131] The first time constant [τ1] within the respective auto-addressing bus node (BKj) can be determined from the value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) in such a way that the value of the first time constant [τ 1] has a first value below a threshold value and a second value above this threshold value, and / or from the value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) in such a way that the value of the second time constant τ2 has a third value below a threshold and a fourth value above this threshold.

[0132] It is important that the technology disclosed here enables a self-test. It is therefore advantageous if a check of the recorded first value of the first bus node output current (i j ) and / or the detected second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) is checked for plausibility and, if necessary, measures are taken if the recorded first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) and / or the detected second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) or their combination is not plausible.

[0133] Preferably, the feed point of the first addressing stream (i j ) if the detected first value of the first bus node output current (i j) of the relevant auto-addressing bus node (BK j ) is not plausible. Similarly, the feed-in point of the first addressing stream (i j ) and the feed point of the second addressing stream (i' j ) if the detected first value of the first bus node output current (i j ) and / or the detected second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) and / or their combination is not plausible.

[0134] In one variant, an error is preferably signalled via the serial bidirectional differential communication bus (DB) upon request by a bus master (ECU) if the detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) and / or the detected second value of the second bus node output current (i'j ) of the relevant auto-addressing bus node (BK j ) or their combination is not plausible.

[0135] In a variant of the method, the step of detecting the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) by means of first measuring means (R2, D1, D3) as detecting the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) by means of first measuring means (R2, D1, D3) with a first sign, if the detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) is plausible, and detecting the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j) by means of first measuring means (R2, D1, D3) with a second sign which is inverted to the first sign, if the detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) is not plausible.

[0136] In a further variant of the method, which relates to the other single-wire bus, the step of detecting the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) by means of second measuring means (R2', D1', D3') as follows: The step comprises detecting the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) by means of second measuring means (R2', D1', D3') with a first sign, if the detected second value of the second bus node output current (i' j) of the relevant auto-addressing bus node (BK j ) is plausible, and detecting the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) by means of second measuring means (R2', D1', D3') with a second sign which is inverted to the first sign, if the detected second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) is not plausible.

[0137] A further method variant additionally comprises detecting the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) by means of second measuring means (R2', D1', D3') in the following manner: This step comprises first detecting the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j) by means of second measuring means (R2', D1', D3') with a first sign, if the previously detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) is plausible and if the previously recorded second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) is plausible, and detecting the second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) by means of second measuring means (R2', D1', D3') with a second sign which is inverted to the first sign, if the previously detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) is not plausible or if the previously recorded second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BKj ) is not plausible.

[0138] Two values ​​are plausible within the meaning of this disclosure if they are the result of two different tests that, by design, should produce the same result, although not necessarily identical, and are equal to one another. Equality here means a deviation of the absolute value of the norm of the results by less than a predetermined threshold. Two values ​​are not plausible within the meaning of this disclosure if they are the result of two different tests that, by design, should produce the same result, although not necessarily identical, and are not equal to one another.

[0139] Furthermore, this variant comprises performing the step of detecting the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j) by means of first measuring means (R2, D1, D3) in the following manner: The step comprises detecting the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) by means of first measuring means (R2, D1, D3) with a first sign, if the previously detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) is plausible and if the previously recorded second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) is plausible, and detecting the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) by means of first measuring means (R2, D1, D3) with a second sign which is inverted to the first sign, if the previously detected first value of the first bus node output current (i j) of the relevant auto-addressing bus node (BK j ) is not plausible or if the previously recorded second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) is not plausible.

[0140] A variant of the procedure with plausibility checks involves using an error address as a valid bus node address of the relevant auto-addressing bus node (BK j ) if the detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK j ) is not plausible or if the detected second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK j ) is not plausible. AUTOADDRESSING METHOD VIA INTERRUPT LINE

[0141] In addition to these address assignment methods supported by bus shunt resistors (R2, R2'), it is proposed to perform the following auto-addressing procedure via an interrupt line: This is a procedure for assigning logical bus node addresses to the bus nodes ((BK1) to [BK n ]) of a data bus system with a serial, bidirectional, differential two-wire communication bus (DB), in which the data bus system comprises a bus master (ECU) with an address input (Adr io ) and n bus nodes ((BK1) to [BK n ]) (with n as a positive integer). Each of the n bus nodes ((BK2) to [BK n ]) is connected via a data line section (DB1 to DB n) or a serial, bidirectional, differential two-wire communication bus (DB) is connected to the bus master (ECU) for data transmission. A line used here to signal the auto-addressing information, which is typically an interrupt line, is now connected to an address input (Adr io ) of the bus master (ECU) through all bus nodes ((BK1) to [BK n ]) are looped through so that they are routed through the individual bus nodes ((BK1) to [BK n ]) into n line sections ([L1] to [L n ]). Each of the bus nodes, hereinafter referred to as the j-th bus node (BK j ) denoted by 1≤j≤n, now has a bus node (BK j ) corresponding address input [Adr ij ] and a j-th bus node (BK j ) associated address output [Adr oj] are used as inputs and outputs to stimulate the auto-addressing information and to forward it. Each of the bus nodes (BK j ) if it is not the n-th bus node [BK n ] is connected to its address input [Adr ij] (with 1≤j≤n-1) with the address output [Adr o ( j+1 )] of a subsequent bus node [BK j+1 ] with 1≤j≤n-1 by a bus node following [BK j+1 ] associated (j+1)-th line section [L j+1 ] connected. Each of the bus nodes (BK j ) with 2≤j≤ n is connected to its address output [Adr oj ] with the address input (Adr i(j_1) ) of a preceding bus node [BK j-1 ] with 2≤j≤ n by a bus node (BK j ) associated j-th line section [L j ] The first bus node (BK1) is connected to its address output (Adr o1 ) with the address input (Adr i0) of the bus master (ECU) by a line section (L1) belonging to the first bus node (BK1). The respective bus node address of each bus node ((BK1) to [BK n ]) can be valid or invalid. The first step of this procedure is to invalidate all or at least some of the respective bus node addresses of the bus nodes ((BK1) to [BK n ]) and a relocation of at least this part of the bus nodes ((BK1) to [BK n ]) e.g. from a normal state to an addressing state. The first has the purpose of establishing a defined initial state. The second has the purpose of address allocation in all bus nodes ((BK1) to [BK n ]). As long as the bus node is in the addressing state, the line in question is not used for its normal function, for example, as an interrupt request line, but for transporting the auto-addressing function.

[0142] During this addressing state, the first step is to set the level of the address input (Adr io ) of the bus master (ECU) to a second logical value when the level of this address input (Adr io ) of this bus master (ECU) is not controlled by the address output (Adr o1 ) of the first bus node (BK1) of the bus nodes ((BK1) to [BK n ]) is overwritten. It is a characteristic that both the bus master (ECU) with its address input (Adr i0 ), as well as the bus nodes ((BK1) to [BK n-1] ) with their address inputs ((Adr i1 ) to [Addr in ]) through the address outputs ((Adr o1 ) to [Addr on ]) of the following bus nodes ((BK1) to [BK n ]) can be overwritten, since these are designed with lower resistance than the corresponding driver stages in the address inputs ((Adr i1 ) to [Addr in ]) of the bus nodes ((BK1) to [BK n]). Only the last bus node [BK n] is with its address input [Adr in ] is not connected to any other subsequent bus node. Therefore, in this last bus node [BK n] the driver stage within the address input [Adr in ] of the last bus node [BK n] the logical state at the address input [Adr in ]. This allows the last bus node to recognize that it is the last in the series of bus nodes that does not yet have a valid bus node address, and can therefore accept the address offered by the bus master as the new valid bus node address if it does not have a valid bus node address, provided that it does not have a valid bus node address by any means. Since it has thus received a valid bus node address and now has it, this bus node (BK j ) then its address output [Adr oj ], whereby the driver stage of the previous address input [Adr i(j-1)] of the previous bus node [BK j-1 ] no longer through the address output [Adr oj ] of the bus node (BK j ) is overwritten and the preceding bus node [BK j-1 ] can then be recognized as the last bus node without a valid bus node address in the series of bus nodes not yet addressed and thus the preceding bus node [BK j-1 ] can then adopt the newly assigned bus node address offered by the bus master (ECU) in the same way as its valid bus node address.

[0143] Since the preceding bus node [BK j-1 ] receives a valid bus node address in the subsequent initialization run and then has this address, this preceding bus node [BK j-1 ] then its address output [Adr o(j-1) ], whereby the driver stage of the next but one previous address input [Adr i(j-2)] of the next but one previous bus node [BK j-2 ] no longer through the address output [Adr o(j-1) ] of the previous bus node [BK j-1 ] is overwritten and the next preceding bus node [BK j-2 ] can then be recognized as the last bus node without a valid bus node address in the series of bus nodes not yet addressed and thus, during the next but one initialization process, the next but one preceding bus node [BK j-2 ] can then adopt the newly assigned bus node address offered by the bus master (ECU) in the same way as its valid bus node address.

[0144] This continues bus node by bus node. During the existence of the addressing state, therefore, in each bus node (BK j ) the bus nodes ((BK2) to [BK n ]) excluding the first bus node (BK1) overwriting the level at the address input [Adr i(j-1)] of the respective bus node (BK j ) preceding bus node [BK j-1] through this respective bus node (BK j ) with a first logic level if the bus node address of this respective bus node (BK j ) is invalid and the level at the address input [Adr ij ] of this respective bus node (BK j ) has a first logical value and setting the level of the address input [Adr ij] this bus node (BK j ) to a second logical value when the level of this address input [Adr ij] this bus node [BK j ] not through the address output [Adr o(j+1) ] of the respective bus node (BK j ) possibly subsequent bus node [BK j+1 ] the bus nodes ((BK3) to [BK n ]). Likewise, while the addressing state exists in the first bus node (BK1), the level at the address input (Adr io) of the bus master (ECU) by the first bus node (BK1) with a first logic level if the bus node address of the first bus node (BK1) is invalid and the level at the address input (Adr o1 ) of this first bus node (BK1) has a first logical value and setting the level of the address input (Adr i1 ) of this first bus node (BK1) to a second logical value when the level of this address input (Adr i1 ) of this first bus node (BK1) is not transmitted through the address output (Adr o2 ) of the bus node (BK2) following the first bus node (BK1) of the bus nodes ((BK2) to [BK n ]). Furthermore, while the addressing state exists, a bus node address is signaled to all bus nodes ((BK1) to [BK n ]) by the bus master (ECU) and the acceptance of the signalled bus node address as a valid bus node address by that bus node (BK j) the bus nodes ((BK1) to [BK n ]), whose bus node address is invalid and whose address input [Adr ij] has a second logical value and the repetition of this signaling by the bus master (ECU) until the address input (Adr io ) of the bus master (ECU) has a second logical value, i.e., it is not overwritten. This addressing is repeated until the bus master (ECU) is the last in the chain of unaddressed bus nodes. Therefore, the bus nodes ((BK1) to [BK n ]) into a second operating state different from the addressing state - which is typically the normal state when the address input (Adr io ) of the bus master (ECU) has a second logical value.

[0145] As already mentioned, in some cases it is advantageous if the line ([L1] to [L n ]) is used as an interrupt line in the second operating state. AUTO-ADDRESSING METHOD USING BUS SHUNT RESISTORS IN THE SUPPLY VOLTAGE LINE Figure 15

[0146] Finally, an auto-addressing method for assigning bus node addresses within a data bus system with a communication bus, in particular a serial, bidirectional, differential two-wire communication bus (DB), with n bus nodes ((BK1), (BK2), (BK3), ..... [BK n-1 ], [BK n ]), with n as a positive integer greater than zero, and a bus master (ECU) is proposed, in which the bus nodes are connected via a supply voltage line (V bat ) are supplied with electrical energy, the communication bus (DB) is connected to the bus master (ECU), each bus node ((BK1), (BK2), ..... [BK n-1 ], [BK n ]) is connected to the communication bus (DB) and in which within the bus nodes ((BK1) to [BK n ]) each one to the respective bus node (BK j ) of the n bus nodes ((BK1) to [BK n]) assigned measuring resistance [Rm j ] into the supply voltage line (V bat ) is inserted. This case corresponds to the Fig. 15. Thus, the data bus system proposed here has n measuring resistors ((Rm1) to [Rm n ]). The measuring resistors ((Rm1) to [Rm n ]) of the bus nodes ((BK1) to [BK n ]) thus divide the supply voltage line (V bat ) in n supply voltage line sections. Figure 16

[0147] Since, especially in the case of data bus systems for controlling several groups of lamps ((LED1) to [LED n ]) (see also Fig. 16) significant currents via the supply voltage line (V bat ), the measuring resistors ((Rm1) to [Rm n ]) should preferably be chosen with as low a resistance as possible in order to minimize losses. It is therefore conceivable to use instead of dedicated measuring resistors ((Rm1) to [Rm n]) only conductor track constrictions or even just conductor sections of predefined length, width and thickness for all bus nodes with the same material and with a specific track resistance deviating from 0 Ω / m as measuring resistors ((Rm1) to [Rm n ]). These are only examples for the realization of the measuring resistors ((Rm1) to [Rm n ]). Other implementations, such as thick-film technology, etc. are conceivable. Each bus node (BK j ) the bus nodes ((BK1) to [BK n ]) has an addressing current source (Iq j ). As such addressing current sources (Iq j ) power sources can also be used which, in the normal state of the bus node, serve as a power source for a light-emitting diode or other light source [LED j ] can be used. Each bus node (BK j ) the bus nodes ((BK1) to [BK n ]) preferably has resources ((D2), (D3), [Rm j]) to measure the current through the measuring resistor [Rm j ] of this bus node (BK j ) the bus nodes ((BK1) to [BK n ]). The second differential amplifier (D2) of a bus node (BK j ) records the voltage drop across the respective measuring resistor [Rm j 9 of the relevant bus node (BK j ). A third differential amplifier (D3) compares the value of the output signal of the second differential amplifier (D2) with a reference value (Ref) by forming the difference. The third differential amplifier (D3) of the bus node (BK j ) generates, depending on the result of this comparison, together with a controller or filter (F) of the bus node (BK j ) a control signal (rw j ) that is specific to this bus node (BK j ). The value of this control signal (rw j ) depends on the value of the addressing current of the addressing current source (Iq j ) of the relevant bus node (BK j) when the bus node (BK j ) has previously been brought from the normal state to the addressing state by the bus master (ECU). If the bus node is in the normal state, the addressing current source (Iq j ) is switched off if it has no other task in this normal state. For example, it is also possible to switch off a power source which in normal operation is used to supply energy to consumers, such as lamps and / or LEDs [LED j ], is used in the addressing state of the bus node (BK j ) as addressing current source (Iq j ) of the bus node (BK j ). This is in Fig. 16, which, except for the lamps ((LED1) to [LED n ]) not from the Fig. 15. A command from the bus master (ECU) causes the bus node (BK j) into the addressing state, whereby its addressing current source (Iq j ) is switched on. This switching on of its addressing current source (Iq j ) preferably a bus node (BK j ) only if it does not have a valid bus node address, which is typically stored in a bus node address register [BKADR], and is marked as "valid" or "invalid" with a corresponding flag.

[0148] This flag is then typically also used to mark it as "invalid." If its bus node address is invalid, a bus node (BK j ) therefore preferentially participates in an auto-addressing sequence when it is initiated by the bus master (ECU). This also applies to the other auto-addressing methods. The addressing current source (Iq j ) of each bus node (BK j ) the bus nodes ((BK1) to [BK n]) then feeds an addressing current towards the power supply (SUP) into the supply voltage line (V bat ) into the terminal of the measuring resistor [Rm j ] of this bus node (BK j ) along the supply voltage line (V bat ) is furthest away from the power supply (SUP). The bus nodes ((BK1) to [BK j-1 ]) that are located less far from the power supply (SUP) record with their respective measuring devices ((Rm1) to [Rm j-1 ], (D2), (D3)) each measure the additional voltage drop across their respective measuring resistors (Rm1 to Rm j-1 ) and regulate their addressing current sources ((Iq1) to [Iq j-1 ]) or, depending on the implementation of the procedure, switch them off in this addressing state of the bus nodes ((BK1) to [BK n ]). This shutdown can be achieved by a threshold comparison, e.g. of the respective control signal (rw j) of a bus node (BK j ) can be recognized. This allows the respective bus node (BK j ) then determines that it is not the last bus node in the bus node series without a valid bus node address or that it is the last bus node in the bus node series without a valid bus node address. In this latter case, the bus node adopts the bus node address offered by the bus master as its valid bus node address. Thus, this bus node - assuming the jth bus node (BK j ) - now a valid bus node address and switches its addressing current source (Iq j ) for the duration of the addressing procedure. The addressing procedure is, as always in this disclosure, typically terminated by a command from the bus master (ECU), which preferentially addresses all bus nodes ((BK1) to [BK n ]) typically causes the addressing state to end and, for example, enter the normal state.

[0149] The proposed method for addressing via voltage drops along the supply voltage line (V bat ) therefore now provides for the following concrete steps: • Signaling of an addressing state, hereinafter referred to as the Power Line addressing state, to all bus nodes ((BK1) to [BK n ]), whereby they have an addressing state for carrying out an auto-addressing procedure by means of the supply voltage line (V bat ) assume; • If necessary, signaling to at least one bus node or part, preferably to all of the bus nodes ((BK1) to [BK n ]) invalidate their bus node addresses; • Performing an initialization sequence comprising the following steps for each bus node (BK j ) of the n bus nodes ((BK1), (BK2), ..... [BK n-1] , [BK n ]), which does not yet have a valid

[0150] Bus node address has up to all bus nodes of the n bus nodes ((BK1), (BK2), ..... [BK n-1 ], [BK n ]) have a valid bus node address: ◯ Signaling of a bus address to be assigned to all bus nodes of the n bus nodes ((BK1), (BK2), ..... [BK n-1 ], [BK n ]) (Typically, this signaling also includes the command from the bus master (ECU) to the bus nodes to enter or, if necessary, maintain the addressing state.); ◯ Carry out the following steps in parallel for each bus node (BK j ) the bus node of the n bus nodes ((BK1), (BK2), ..... [BK n-1 ], [BK n ]), hereinafter referred to as the relevant bus node (BK j ) that does not have a valid bus node address: ▪ Reception of the said auto-addressing command from the bus master (ECU) by the relevant bus node (BK j ); ▪ Receipt of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BK j ); ▪ Receipt of a start signal for the allocation of the bus address to be allocated from the bus master (ECU) by the relevant bus node (BK j ) and start of a timer at a start time t0=0s by the relevant bus node (BK j ); ▪ Determining the voltage drop across the measuring resistor (Rm j ) of the relevant bus node (BK j ) as base voltage value [V m0 ] using measuring instruments ([Rm j ], (D2), (D3)); ▪ At a fourth time [t4] after the start time [t0]: Switching on the addressing current source (Iq j ) of the relevant bus node (BK j ) and regulation of the voltage drop across the measuring resistor [Rm j ] of the relevant bus node (BK j ) using the addressing current source (Iq j) depending on the voltage drop across the measuring resistor [Rm j ] by means of a control signal (rw j ), which is determined by measuring instruments ((D2), (D3), [Rm j ]) and / or control means (F) of the bus node (BK j ) to a total target voltage value, which is equal to a target voltage value plus the previously measured base voltage value [V m0 ], whereby an increase in the addressing current of the auto-addressing current source (Iq j ) of the relevant bus node (BK j ) with a first time constant [τ 1] and whereby a reduction of the addressing current of the auto-addressing current source (Iq j ) of the relevant bus node (BK j ) with a second time constant [τ 2] (Note that here no statement can be made about the value of the first time constant [τ 1] compared to the second time constant [τ 2] occurs.); ▪ At a fifth time [t5] after the start time [t0] and after the fourth time [t4]: Recording the value of the control signal (rw j ) or a signal derived therefrom and comparing this value with a threshold value and ▪ Use of the bus node address to be assigned as a valid bus node address of the bus node (BK j ) if the magnitude of this value is above the threshold and switching off the addressing current source (Iq j ) at the latest when the bus node (BK) leaves the addressing state j );

[0151] It is advisable to check the successful address assignment by the bus master (ECU) after assigning a bus node address to a bus node (BK j ). If this results in an error, for example if several bus nodes report a bus collision, it is advisable to delete the validity of the last assigned bus node address, whereby the relevant bus nodes (BKj ) again like bus hubs (BK j ) without a valid bus node address. After all bus node addresses have been assigned to all bus nodes ((BK1) to [BK n ]) that should receive a bus node address, it should be checked whether all bus nodes ((BK1) to [BK n ]) that should receive a bus node address have received a valid bus node address. If all bus nodes have received a valid bus node address, the bus master (ECU) signals preferentially to all bus nodes ((BK1) to [BK n ]) that they should leave the addressing state and enter another state, preferably the normal state. In the normal state, the bus nodes ((BK1) to [BK n ]) their addressing current sources ((Iq1) to [Iq n ]) or operate them in the function specified for these addressing current sources ((Iq1) to [Iq n]) in this operating state, here the normal state. Performing an additional initialization sequence is useful if not all bus nodes ((BK1) to [BK n ]) that should receive a bus node address have received a valid bus node address. In principle, it is useful if the second time constant [τ 2] is smaller by a factor of more than 10 than the first time constant [τ 1] At least the first time constant [τ 1] greater than the second time constant [τ 2] It is advantageous if the first time constant [τ 1] within the relevant auto-addressing bus node (BK j ) of the measured value ([Rm j ], (D2), (D3)) recorded value of the voltage drop across the measuring resistor [Rm j ] of the relevant auto-addressing bus node (BK j ) and / or the second time constant [τ 2]within the relevant auto-addressing bus node (BK j ) of the measured value ([Rm j ], (D2), (D3)) recorded value of the voltage drop across the measuring resistor [Rm j ] of the relevant auto-addressing bus node (BK j ). This allows for faster control of the voltage drop across the measuring resistor [Rm j ] of the relevant bus node (BK j ). Figure 17

[0152] In the Fig. 17, second addressing current sources (Iq' j ) of the relevant bus nodes (BK j ) for auto-addressing via the power supply line (V bat ) are used. Second measuring devices (D2', D3') are also used in addition to the first measuring devices ((Rm1) to [Rm n], (D2), (D3)). This redundancy can be used for testing and monitoring purposes, since each auto-addressing run for both branches should lead to the same result. If this is not the case, the offered bus node address is preferably not accepted, but rather, for example, a specially reserved and predetermined error address is assumed. If the bus master (ECU) addresses this error address using its data bus protocol, the bus node at which the error occurred responds to the bus master (ECU), which it should not do if no error had occurred in the bus node. The test can, for example, be carried out in such a way that the difference between the value of the first control signal (rw j ) of a bus node (BK j ) and the value of the second control signal (rw' j ) of this bus node (BK j). If the magnitude of this difference exceeds a predetermined limit, at least one of the circuits is malfunctioning. This can be detected and used to prevent the bus node address offered by the bus master (ECU) from being adopted as a valid bus node address. Instead, the predetermined error address is adopted as the valid bus node address, which can then be verified by the bus master (ECU) addressing this address. Simultaneous use of different auto-addressing methodsFigure 18

[0153] It is advantageous to be able to use several of the auto-addressing methods described here, as each method can confirm the success of correct identification through redundancy. Furthermore, using more than two auto-addressing methods can achieve a fail-operational property. This means that auto-addressing is usually performed successfully, but an error is detected, which can then be signaled. This is potentially particularly important for safety-relevant applications. Fig. Figure 18 shows such a proposed device, which allows the implementation of several auto-addressing methods and thus has increased security. Fig. 18 is a combination of the Fig. 17, Fig. 13, Fig. 6 and Fig. 5. In the bus nodes ((BK1) to [BK n ]) a first multiplexer (X1) of the respective bus node (BK j) and a second multiplexer (X2) of this bus node (BK j ) is used to connect the inputs of the second differential amplifier (D2) of this bus node (BK j ) to the first bus shunt resistor (R2) of this bus node (BK j ) or to the measuring resistor [Rm j ] of this bus node (BK j ) to switch. In the bus nodes ((BK1) to [BK n ]) a further first multiplexer (X1') of the respective bus node (BK j ) and another second multiplexer (X2') of this bus node (BK j ) is used to control the inputs of the second differential amplifier (D2') of this bus node (BK j ) to the second bus shunt resistor (R2') of this bus node (BK j ) or to the measuring resistor (Rm j ) of this bus node (BK j ). Accordingly, the first addressing current source (Iq j ) of this bus node (BK j) either with a reference potential (GND) or with the first single-wire bus (DB a ) by a third demultiplexer (X3) of this bus node (BK j ). The third demultiplexer (X3) of this bus node (BK j ) also determines whether the first addressing current of the first addressing current source (Iq j ) of this bus node (BK j ) before or after the first bus shunt resistor (R2) of this bus node (BK j ) into the first single-wire bus (DB a ). Analogously, the second addressing current source (Iq' j ) of this bus node (BK j ) either with a reference potential (GND) or with the second single-wire bus (DB b ) by a further third demultiplexer (X3') of this bus node (BK j ). The third demultiplexer (X3') of this bus node (BK j) also determines whether the second addressing current of the second addressing current source (Iq' j ) of this bus node (BK j ) before or after the second bus shunt resistor (R2') of this bus node (BK j ) into the second single-wire bus (DB b ) is fed into the grid. Low-impedance normal operationFigure 19

[0154] It is now useful if only in the addressing state of the bus nodes ((BK1) to [BK n ]) the bus shunt resistors (R2, R2') in the first single-wire bus (DB a ) and the second single-wire bus (DB b ) are effective. Therefore, it is advisable, as soon as the addressing state is left, preferably in all bus nodes ((BK1) to [BK n ]) by a first bridging switch (S4) in preferably each bus node (BK j ) the first bus shunt resistor (R2) of this bus node (BK j ) and by a second bridging switch (S4') in this bus node (BK j) the second bus shunt resistor (R2') of this bus node (BK j ) short-circuit. This is in Fig. 19 shown.

[0155] Of course, this procedure would also be applicable for the measuring resistance [Rm j ] of a bus node (BK j ) is conceivable. However, the corresponding switches would generally require too much chip area. Furthermore, the voltage drop across the normal supply voltage line is usually sufficient, so in these cases a dedicated measuring resistor [Rm j ] into the supply voltage line (V bat ) is inserted, but a section of the supply voltage line (V bat ) as measuring resistance [Rm j ] of this bus node (BK j ) can be used. Interchange detection Figure 20

[0156] Fig. 20 now additionally shows in the exemplary bus nodes ((BK1) to [BK n]) a fourth multiplexer (X4) per bus node (BK j ), with which a control within this bus node (BK j ) the two inputs of the second differential amplifier (D2) of this bus node (BK j ) can be swapped. Furthermore, the Fig. 20 additionally in the exemplary bus nodes ((BK1) to [BK n ]) a further fourth multiplexer (X4') per bus node (BK j ), with which the control within this bus node (BK j ) the two inputs of the further second differential amplifier (D2') of this bus node (BK j ) can be swapped. Figure 21

[0157] This can be Fig. 21 will now be explained for the error case shown there: The second bus node (BK2) is installed incorrectly. This can now be easily determined by the control of the second bus node (BK2) in a self-test, which is preferably carried out at the beginning of the initialization procedure. Preferably, for example, the bus master (ECU) signals to the bus nodes ((BK1) to [BK n ]) that they should perform such a self-test. Other start scenarios, e.g. during a power-on phase, are conceivable. For example, the bus node (BK j ) by means of its measuring instruments (R2, R2', D2, D2', D3, D3', Iq j 'Iq' j , X1, X1', X2, X2', X3, X3') determine whether the first addressing current of its first addressing current source (Iq j) flows through its first bus shunt resistor (R2) when it should flow through its first bus shunt resistor (R2), and whether the second addressing current of its second addressing current source (Iq' j ) flows through its second bus shunt resistor (R2') when it should flow through the second bus shunt resistor (R2'). If this is the other way around, the bus node controller can determine this based on the corresponding measurement results and, using a fourth multiplexer (X4) of this bus node (BK j ) and the third multiplexer (X3) of this bus node (BK j ) on the one hand the inputs of the second differential amplifier (D2) of this bus node (BK j ) and on the other hand, the feed point for the first addressing current of the first addressing current source (Iq j ) of this bus node (BK j ) to the other side of the first bus shunt resistor (R2) of this bus node (BK j). In this case, the control of the bus node can be carried out by means of a further fourth multiplexer (X4') of this bus node (BK j ) and the further third multiplexer (X3') of this bus node (BK j ) on the one hand the inputs of the further second differential amplifier (D2') of this bus node (BK j ) and, on the other hand, the feed point for the second addressing current of the second addressing current source (Iq' j ) of this bus node (BK j ) to the other side of the second bus shunt resistor (R2') of this bus node (BK j ). Then the auto-addressing procedure can be carried out again using the bus shunt resistors (R2, R2'). Also possible, but not shown here for clarity, is changing the feed point of the first addressing current source (Iq j ) of this bus node (BK j ) into the supply voltage line (V bat) to the other side of the measuring resistor (Rm j ) using a fifth multiplexer (X5) not shown. However, this is only useful if the first addressing current source (Iq j ) does not have to supply too much current in the normal state. However, this is precisely the case when the first auto-addressing current source (Iq j ) in the normal state of the bus node (BK j ) for example the energy source of light sources (LED j ) of the bus node. In this case, the transistors of the fifth multiplexer (X5) (not shown) would be too large and therefore too expensive. Likewise, switching the feed point of the second addressing current source (Iq' j ) of this bus node (BK j ) into the supply voltage line (V bat ) to the other side of the measuring resistor (Rm j ) using a fifth multiplexer (X5') (not shown). The same considerations apply here.

[0158] It was also not shown that the input of the address input (Adr ij ) of the relevant bus node (BK j ) (here as an example the second bus node (BK2)) with the output of the address output (Adr oj ) of the relevant bus node (BK j ) can be swapped by means of two multiplexers (X6, X7) if such a swap as in Fig. 21 by controlling the bus node (BK j ) e.g. was determined in the manner described above.

[0159] These are exemplary measures to compensate for the insertion of a bus node with a connector swap. List of characters Fig. 1 shows an example of a rear light module (BLM) of a motor vehicle. Fig. 2 shows a two-wire communication bus (DB), as is known, for example, from the prior art. Fig. Figure 3 shows the preferred structure of the bit stream packets (BP) sent by the bus master (ECU). Fig. 4 shows a data bus system in which a first bus shunt resistor (R2) is inserted into the first single-wire bus (DBa) for each bus node ((BK1) to [BK n ]) is inserted. Fig. 5 shows based on Fig. 4 a serial, bidirectional, differential two-wire communication bus (DB) with a first bus shunt resistor (R2) inserted into the first single-wire bus (DB1) and a second bus shunt resistor (R2') inserted into the second single-wire bus (DB2). Fig. 6 corresponds to the Fig. 5 with the difference that the respective first addressing current sources ((Iq1) to [Iq n ]) seen from the bus master (ECU), the first addressing current behind the first bus shunt resistors (R2) in the addressing phase in which the respective bus node (BK j) is in an addressing state. Fig. 7 shows, by way of example, the course of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2) and the output current (i3) of the third bus node (BK3) in an exemplary data bus system with n=3 bus nodes (BK1 to BK3). Fig. 8 shows the course of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2) and the output current (i3) of the third bus node (BK3). Fig. 9 shows the course of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2) and the output current (i3) of the third bus node (BK3). Fig. 10 shows the control loop of a bus node (BK j ) with a first detection device (DET) which detects internal signals (ds1, ds3) of the bus node (BK j ) checks for plausibility. Fig. 11 shows a simplified representation of a j-th auto-addressing bus node (BK j ), which is responsible for repositioning the feed point of the second addressing current of the second addressing current source (Iq' j ) of the considered bus node (BK j ) has a second detection device (DET'). Fig. 12 shows auto-addressing bus nodes (BK1, BK2, BK3) with a second bus shunt bypass switch (S4') per bus node (BKj) to bridge the associated second bus shunt resistor (R2') of the bus node (BKj) in normal operation, i.e. in the normal state of the bus node (BKj), and to open this second bus shunt bypass switch (S4') only in the addressing state. Fig. 13 is based on the Fig. 2 and shows a data bus system with auto-addressing via interrupt line. Fig. 14 describes the basic procedure of the preferred address allocation procedure described here using the interrupt line Fig. 15 shows a serial, bidirectional, differential two-wire communication bus (DB), with n bus nodes ((BK1), (BK2), (BK3), ..... [BK n-1 ], [BK n ]), with n being a positive integer greater than zero, and a bus master (ECU), in which the bus nodes are connected via a supply voltage line (V bat ) are supplied with electrical energy, the communication bus (DB) is connected to the bus master (ECU), each bus node ((BK1), (BK2), ..... [BK n-1 ], [BK n ]) is connected to the communication bus (DB) and in which within the bus nodes ((BK1) to [BK n ]) each one assigned to the respective bus node (BK j ) of the n bus nodes ((BK1) to [BK n ]) assigned measuring resistance (Rm j ) into the supply voltage line (V bat ) is inserted Fig. 16 shows Fig. 15 with lamps (LED1 to LED n ). Fig. 17 is based on Fig. 15, where now also second addressing current sources (Iq' j ) of the relevant bus nodes (BK j ) for auto-addressing via the power supply line (V bat ) be used. Fig. 18 shows a device that allows the implementation of several auto-addressing methods. Fig. 18 is a combination of the Fig. 17, Fig. 13, Fig. 6 and Fig. 5. Fig. 19 corresponds to the Fig. 18 with a bypass switch (S4). Fig. 20 shows in the exemplary bus nodes ((BK1) to [BK n ]) a fourth multiplexer (X4) per bus node (BK j ), with a controller within this bus node (BK j ) and a further fourth multiplexer (X4') per bus node (BK j), with a controller within this bus node (BK j ) with which the control within this bus node (BK j ) the two inputs of the further second differential amplifier (D2') of this bus node (BK j ) can be swapped. Fig. 21 shows Fig. 20 with a twisted bus node (BK2). List of abbreviations ADR1 address recognition unit of the first bus node (BK1); ADR2 address recognition unit of the second bus node (BK2); ADR3 Address recognition unit of the third bus node (BK3); ADR4 Address recognition unit of the fourth bus node (BK4); ADR5 Address recognition unit of the fifth bus node (BK5); ADR6 Address recognition unit of the sixth bus node (BK6); ADR j Address recognition unit of the j-th bus node [BK j ]; ADR n Address recognition unit of the n-th bus node [BK n ]; Addr i(j-1) Address input of the (j-1)-th bus node [BK (j-1) ]; Addr ij Address input of the j-th bus node (BK j ); Addr i(j+1) Address input of the (j+1)-th bus node [BK (j+1) ]; Addr in Address input of the nth bus node [BK n ]; Addr o(j-1) Address output of the (j-1)-th bus node [BK j-1 )]; Addr oj Address output of the j-th bus node (BK j ); Addr o(j+1) Address output of the (j+1)-th bus node [BK (j+1) ]; Addr on Address output of the nth bus node [BK n ]; AT1 scanning device of the first bus node (BK1); AT2 scanning device of the second bus node (BK2); AT3 scanning device of the third bus node (BK3); AT4 scanning device of the fourth bus node (BK4); AT5 scanning device of the fifth bus node (BK5); AT6 scanning device of the sixth bus node (BK6); AT j Sampling device of the j-th bus node [BK j ]; AT n Sampling device of the n-th bus node [BK n ]; au English: “arbitrary units”, relative units; BKADR1 Bus node address register of the first bus node (BK1); BKADR2 Bus node address register of the second bus node (BK2); BKADR3 Bus node address register of the second bus node (BK3); BKADR4 Bus node address register of the second bus node (BK4); BKADR5 Bus node address register of the second bus node (BK5); BKADR6 Bus node address register of the second bus node (BK6); BKADR j Bus node address register of the jth bus node [BK j ]; BKADR n Bus node address register of the nth bus node [BK n ]; BK j-2 (j-2)th bus node; BK j-1(j-1)th bus node; BK j+1 (j+1)th bus node; BK j+2 (j+2)th bus node; BK n-2 (n-2)th bus node; BK n-1 (n-1)th bus node; BK n nth bus node; BLM taillight module; CLKA1 sampling signal within the first bus node (BK1); CLKA2 sampling signal within the second bus node (BK2); CLKA3 sampling signal within the third bus node (BK3); CLKA4 sampling signal within the fourth bus node (BK4); CLKA5 sampling signal within the fifth bus node (BK5); CLKA6 sampling signal within the sixth bus node (BK6); CLKA j Sampling signal within the j-th bus node [BK j ]; CLKA n Sampling signal within the n-th bus node [BK n ]; CLKG1 clock of the first bus node (BK1); CLKG2 clock generator of the second bus node (BK2); CLKG3 clock generator of the third bus node (BK3); CLKG4 Clock generator of the fourth bus node (BK4); CLKG5 Clock generator of the fifth bus node (BK5); CLKG6 Clock generator of the sixth bus node (BK6); CLKG j Clock generator of the j-th bus node [BK j ]; CLKG n Clock generator of the nth bus node [BK n ]; DB j j-th, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the j-th bus node (BK j ) and the (j-1)th bus node [BK j-1 ]. It comprises a corresponding section of the first single-wire bus (DB a ) and the second single-wire bus (DB b ); DB nn-th, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the n-th bus node [BK n] and the (n-1)th bus node [BK n-1 ]. It comprises a corresponding section of the first single-wire bus (DB a ) and the second single-wire bus (DB b ); EV1 Power supply means of the first bus node (BK1), which is intended for the power supply of the first light source (LED1) of the first bus node (BK1). EV2 Power supply means of the second bus node (BK2), which is intended for the power supply of the second light source (LED2) of the second bus node (BK2). EV3 Power supply device of the third bus node (BK3), which is intended to supply power to the third light source (LED3) of the third bus node (BK3). EV4 Power supply means of the fourth bus node (BK4), which is intended to supply power to the fourth lamp [LED4] of the fourth bus node (BK4). EV5 Power supply device of the fifth bus node (BK5), which is intended to supply power to the fifth lamp [LED5] of the fifth bus node (BK5). EV6 Power supply device of the sixth bus node (BK6), which is intended for the power supply of the sixth lamp [LED6] of the sixth bus node (BK6). EV j Power supply of the j-th bus node (BK j ), which is responsible for the energy supply of the j-th lamp [LED j ] of the j-th bus node (BK j ) is provided. EV n Power supply of the n-th bus node [BK n ], which is responsible for the energy supply of the n-th light source [LED n ] of the n-th bus node [BK n] is intended. GGlq jpush-pull current source; GLlq j Common mode addressing current source of the bus node (BK j ); GND second supply voltage line (complementary to V bat ) also called reference potential; HS-CAN high-speed CAN protocol; I amax maximum addressing current; IQ j1 first addressing current source of the j-th bus node (BK j ) when dividing the first addressing current source [Iq j1 ] of the j-th bus node (BK j ) into a first addressing current source feeding in front of the first bus shunt resistor (R2) and another first addressing current source feeding in behind the first bus shunt resistor (R2); IQ j2 further first addressing current source of the j-th bus node (BK j ) when dividing the first addressing current source [Iq j1 ] of the j-th bus node (BK j) into a first addressing current source feeding before the first bus shunt resistor (R2) and a first addressing current source feeding after the first bus shunt resistor (R2); Iq' j1 second addressing current source of the j-th bus node (BK j ) when dividing the second addressing current source [Iq j1 ] of the j-th bus node (BK j ) into a second addressing current source feeding in front of the second bus shunt resistor (R2') and another second addressing current source feeding in behind the second bus shunt resistor (R2'); Iq' j2 further second addressing current source of the j-th bus node (BK j ) when dividing the second addressing current source [Iq j1 ] of the j-th bus node (BK j) into a second addressing current source feeding in front of the second bus shunt resistor (R2') and another second addressing current source feeding in behind the second bus shunt resistor (R2'); I ref first specified total current value within a bus node (BK j ) for the first bus node output current (i j ). The first total current value should preferably be the same for all bus nodes. However, it can also vary from bus node to bus node. I' ref second specified total current value within a bus node (BK j ) for the second bus node output current (i' j ). The second total current value should preferably be the same for all bus nodes. However, it can also vary from bus node to bus node. L1 to L n Line from the line sections L1 to L n ; L4 fourth line section from the fourth bus node [BK4] to the third bus node (BK3); L j-1 (j-1)-th line section from the (j-1)-th bus node [BK j-1 ] to the (j-2)th bus node [BK j-2 ]; L j j-th line section from the j-th bus node (BK j ) to the (j-1)-th bus node [BK j-1 ]; L j+1 (j+1)-th line section from the (j+1)-th bus node [BK j+1] to the j-th bus node (BK j ); L n-1 (n-1)-th line section from the (n-1)-th bus node [BK n-1] to the (n-2)th bus node [BK n-2 ]; L n n-th line section from the n-th bus node [BK n ] to the (n-1)th bus node [BK n-1] ; LED j Lamp of the j-th bus node (BK j ). Light source groups and interconnections are included here. (These can be, for example, series and parallel connections of several LEDs.) LED n Lamp of the nth bus node [BK n ]. This includes light source groups and interconnections. (These can be, for example, series and parallel connections of several LEDs.) µC1 microcontroller of the first bus node (BK1); µC2 microcontroller of the second bus node (BK2); µC3 microcontroller of the third bus node (BK3); µC4 microcontroller of the fourth bus node (BK4); µC5 microcontroller of the fifth bus node (BK5); µC6 microcontroller of the sixth bus node (BK6); µC j Microcontroller of the j-th bus node (BK j ); µC n Microcontroller of the n-th bus node [BK n ]; rw n first control signal of the nth bus node [BK n ]. The first control signal of the nth bus node [BK n] is determined by means, preferably a first filter (F) of the n-th bus node [BKn ], which is connected to the third comparator (D3) of the n-th bus node [BK n] can also form a unit, from the output signal of the third comparator (D3) of the n-th bus node [BK n] formed and serves to control the first auto-addressing current source [Iq n ] of the n-th bus node [BK n ]; rw' n second control signal of the nth bus node [BK n ]. The second control signal of the n-th bus node [BK n] is determined by means, preferably a second filter (F) of the n-th bus node [BK n ], which is connected to the corresponding third comparator (D3') of the n-th bus node [BK n] can also form a unit, from the output signal of the corresponding third comparator (D3') of the n-th bus node [BK n] and is used to control the second auto-addressing current source [Iq' n ] of the n-th bus node [BK n ]; SUP power supply; SW1 first threshold value for comparison with the first control value (r1) of the first bus node (BK1) for deciding whether the address data should be adopted as a valid bus node address; SW'1 second threshold value for comparison with the second control value (r'1) of the first bus node (BK1) for deciding whether the address data should be adopted as a valid bus node address; SW2 first threshold value for comparison with the first control value (r2) of the second bus node (BK2) for deciding whether the address data should be adopted as a valid bus node address; SW'2 second threshold value for comparison with the second control value (r'2) of the second bus node (BK2) for deciding whether the address data should be adopted as a valid bus node address; SW3 first threshold value for comparison with the first control value (r3) of the third bus node (BK3) for deciding whether the address data should be adopted as a valid bus node address; SW'3 second threshold value for comparison with the second control value (r'3) of the third bus node (BK3) for deciding whether the address data should be adopted as a valid bus node address; SW j first threshold value for comparison with the first control value (r j ) of the j-th bus node (BK j ) for deciding whether the address data should be adopted as a valid bus node address; SW' j second threshold value for comparison with the second control value (r' j ) of the j-th bus node (BK j ) for deciding whether the address data should be adopted as a valid bus node address; SW n first threshold value for comparison with the first control value [r n] of the n-th bus node [BK n] for deciding whether the address data should be adopted as a valid bus node address; SW' n second threshold value for comparison with the second control value [r' n ] of the n-th bus node [BK n] for deciding whether the address data should be adopted as a valid bus node address; τ1 first time constant with which the increase of the first addressing current of the first regulated auto-addressing current source (Iq j ) of the relevant bus node (BK j ) takes place; τ2 second time constant with which the reduction of the first addressing current of the first regulated auto-addressing current source (Iq j ) of the relevant auto-addressing bus node (BK j ) takes place τ3 third time constant with which the increase of the second addressing current of the second regulated auto-addressing current source (Iq' j) of the relevant bus node (BK j ) takes place; τ4 fourth time constant with which the reduction of the second addressing current of the second regulated auto-addressing current source (Iq' j ) of the relevant auto-addressing bus node (BK j ) takes place; τ ref device-specific, not further defined temporal reference value; t time; t1 first time point after the start of the timer at which a freezing of the regulation of the first addressing current source (Iq j ) of the relevant auto-addressing bus node (BK j ) takes place; t2 second time point after the start of the timer at which a freezing of the regulation of the second addressing current source (Iq' j ) of the relevant auto-addressing bus node (BK j ) takes place; t3 third time at which, under certain conditions, the acceptance of the bus node address to be assigned by the bus master (ECU) as a valid bus node address of the relevant auto-addressing bus node (BK j ) takes place; TR driver; TR a first driver in the bus master (ECU) or in a bus node ((BK1) to [BK n ]). The driver is preferably implemented as a CAN driver or RS485 driver. A first driver can preferably assume two of three permitted states as a CAN driver: In a first state, it applies a first logic level (Z1) to the first single-wire bus (DB a ). In a second state, it applies a third logic level (Z3) to the first single-wire bus (DB a ). The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n]) as the first current sink for the first addressing currents of the first addressing current sources ((Iq1), (Iq2) to [Iq n ]) of the bus nodes ((BK1) to [BK n ]) and their first quiescent currents. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the second driver [TR b ] of the relevant bus node ((BK1) to [BK n ]) assumes the second state (Z2). As a result, the signal is differentially impressed with a first differential level (z1). Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the third state (Z3) when the second driver [TR b ] of the relevant bus node ((BK1) to [BK n]) assumes the third state (Z3). This differentially imprints the signal with a third differential level (z3). The first driver, also as an RS485 driver, can preferably assume two of two permitted states: In a first state, it applies a first logic level (Z1) to the first single-wire bus (DB a ). In a second state, it applies a second logic level (Z2) to the first single-wire bus (DB a ). The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n ]) as the first current sink for the first addressing currents of the first addressing current sources ((Iq1), (Iq2) to [Iq n ]) of the bus nodes ((BK1) to [BK n ]) and their first quiescent currents. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the second driver [TR b] of the relevant bus node ((BK1) to [BK n ]) assumes the second state (Z2). As a result, the signal is differentially impressed with a first differential level (z1). Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the second driver [TR b ] of the relevant bus node ((BK1) to [BK n ]) assumes the first state (Z1). As a result, the signal is differentially impressed with a second differential level (z2). In addition, the first driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DB a ) by a first driver of another bus node ((BK1) to [BK n ]) or the bus master (ECU). TR b second driver in the bus master (ECU) or in a bus node ((BK1) to [BK n]). The second driver is preferably implemented as a CAN driver or RS485 driver. A second driver can preferably assume two of three permitted states as a CAN driver: In a first state, it applies a second logic level (Z2) to the second single-wire bus (DB b ). In a second state, it applies a third logic level (Z3) to the second single-wire bus (DB b ). The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n ]) as a second current sink for the second addressing currents of the second addressing current sources ((Iq'1) to [Iq' n ]) of the bus nodes ((BK1) to [BK n ]) and their second quiescent currents. Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the first driver [TR a] of the relevant bus node ((BK1) to [BK n]) assumes the first state (Z1). As a result, the signal is differentially impressed with a first differential level (z1). Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the third state (Z3) when the first driver [TR a] of the relevant bus node ((BK1) to [BK n ]) assumes the third state (Z3). This differentially imprints the signal with a third differential level (z3). The second driver, also as an RS485 driver, can preferably assume two of two permitted states: In a first state, it applies a second logic level (Z2) to the first single-wire bus (DB a ). In a second state, it applies a first logic level (Z1) to the second single-wire bus (DB b ). The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n]) as a second current sink for the second addressing currents of the second addressing current sources ((Iq'1) to [Iq' n ]) of the bus nodes ((BK1) to [BK n ]) and their second quiescent currents. Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the first driver [TR a] of the relevant bus node ((BK1) to [BK n ]) assumes the first state (Z1). As a result, the signal is differentially impressed with a first differential level (z1). Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the first driver [TR a] of the relevant bus node ((BK1) to [BK n]) assumes the second state (Z2). As a result, the signal is differentially impressed with a second differential level (z2). In addition, the first driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DB a ) by a first driver of another bus node ((BK1) to [BK n ]) or the bus master (ECU). UART Universal Asynchronous Receiver Transmitter; V m0 base voltage value; X5 Multiplexer for swapping the connections of the measuring resistor [Rm j ] of a bus node (BK j ); X6 first multiplexer for swapping the connections of the address input [Adr ij ] and the address output [Adr oj ] of a bus node (BK j ); X7 second multiplexer for swapping the connections of the address input [Adr ij] and the address output [Adr oj ] of a bus node (BK j ); List of reference symbols ADRD Address information within the data information (DATA) of a bit stream packet (BP); Addr io Address input of the bus master (ECU); Addr i1 Address input of the first bus node (BK1); Addr i2 Address input of the second bus node (BK2); Addr i3 Address input of the third bus node (BK3); Addr o1 Address output of the first bus node (BK1); Addr o2 Address output of the second bus node (BK2); Addr o3 Address output of the third bus node (BK3); BK1 first bus node; BK2 second bus node; BK3 third bus node; BK4 fourth bus node; BK5 fifth bus node; BK6 sixth bus node; BK jj-th bus node, also referred to in this disclosure as the relevant bus node, if statements about an individual bus node of the bus nodes (BK1, BK2, .....BK n-1 , BK n ) are made; BP Bit stream packet (English frame), also called data packet; CHKD: Check information within the data information (DATA) of a bitstream packet (BP). This is preferably a CRC checksum and / or parity bits, etc. CLK clock within the bus master (ECU); CLKA j Sampling signal within the j-th bus node (BK j ); D2 second differential amplifier for measuring the first current through the first single-wire bus (DB a ) by means of the first shunt resistor (R2) or to measure the current through the supply voltage line (V bat ) using the measuring resistor [Rm j ] within the respective bus node (BK j). For clarity, the second differential amplifiers are not provided with indices for the respective bus nodes. D2' second differential amplifier for measuring the second current through the second single-wire bus (DB b ) by means of the second shunt resistor (R2') or to measure the current through the supply voltage line (V bat ) using the measuring resistor [Rm j ] within the respective bus node (BK j ). For clarity, the second differential amplifiers are not provided with indices for the respective bus nodes. D3 third comparator or third differential amplifier for comparing the output of the second differential amplifier (D2), which is used to measure the current through the first single-wire bus (DB a ) by means of the first shunt resistor (R2) or through the supply voltage line by means of the measuring resistor [Rm j], with a threshold value (Ref) within the respective bus node (BK j ). For clarity, the third comparators and differential amplifiers are not marked with indices for the respective bus nodes (BK j ). D3' third comparator or third differential amplifier for comparing the output of the second differential amplifier (D2'), which is used to measure the current through the second single-wire bus (DB b ) by means of the second shunt resistor (R2') or through the supply voltage line by means of the measuring resistor [Rm j ], with a further threshold value (Ref') within the relevant bus node (BK j ). For clarity, the third comparators and differential amplifiers are not marked with indices for the respective bus nodes (BK j ). DATA Data information within a bit stream packet; DB serial, bidirectional, differential two-wire communication bus; DB a first single-wire bus of the serial, bidirectional, differential two-wire communication bus (DB); DB b second single-wire bus of the serial, bidirectional, differential two-wire communication bus (DB); DB1 first, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the first bus node (BK1) and the bus master (ECU). It comprises a corresponding section of the first single-wire bus (DB a ) and the second single-wire bus (DB b ); DB2 second, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the second bus node (BK2) and the first bus node (BK1). It comprises a corresponding section of the first single-wire bus (DB a) and the second single-wire bus (DB b ); DB3 third, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the third bus node (BK3) and the second bus node (BK2). It comprises a corresponding section of the first single-wire bus (DB a ) and the second single-wire bus (DB b ); DET first detection device within a bus node (BK j ); DET' second detection device within a bus node (BK j ); ds2 Output of the second differential amplifier (D2). This is an internal signal within a bus node (BK j ); ds2' Output of the second differential amplifier (D2'). This is an internal signal within a bus node (BK j ); ds3 internal signal within a bus node (BK j ); ds3' further internal signal within a bus node (BK j ); ECU bus master, also referred to as control unit; the first error signal of the first detection device (DET); er' second error signal of the second detection device (DET'); F first filter; F' second filter; i1 first bus node output current which the first bus node (BK1) sends to the bus master (ECU) via the section of the first single-wire bus (DB1) which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the first bus node (BK1) and the bus master (ECU), and which the bus master receives as the first bus master input current; i'1 second bus node output current which the first bus node (BK1) sends to the bus master (ECU) via the section of the second single-wire bus (DB2) which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the first bus node (BK1) and the bus master (ECU) and which the bus master receives as a second bus master input current; i2 first bus node output current which the second bus node (BK2) sends to the first bus node (BK1) via the section of the first single-wire bus (DB1) which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the second bus node (BK2) and the first bus node (BK1) and which the first bus node (BK1) receives as the first bus node input current; i'2 second bus node output current which the second bus node (BK2) sends to the first bus node (BK1) via the section of the second single-wire bus (DB2) which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the second bus node (BK2) and the first bus node (BK1) and which the first bus node (BK1) receives as a second bus node input current; i3 first bus node output current which the third bus node (BK3) sends to the second bus node (BK2) via the section of the first single-wire bus (DB1) which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the third bus node (BK3) and the second bus node (BK2) and which the second bus node (BK2) receives as a first bus node input current; i'3 second bus node output current which the third bus node (BK3) sends to the second bus node (BK2) via the section of the second single-wire bus (DB2) which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the third bus node (BK3) and the second bus node (BK2) and which the second bus node (BK2) receives as a second bus node input current; i j first bus node output current that the j-th bus node (BK j ) over the section of the first single-wire bus (DB1), which is part of the connecting section of the serial, bidirectional, differential two-wire communication bus (DB) between the j-th bus node (BK j ) and the (j-1)th bus node [BK j-1 ] is connected to the (j-1)-th bus node [BK j-1 ] and which the (j-1)-th bus node [BK (j-1) ] as the first bus node input current; i' jsecond bus node output current that the j-th bus node (BK j ) over the section of the second single-wire bus (DB2), which is part of the connecting section of the serial, bidirectional, differential two-wire communication bus (DB) between the j-th bus node (BK j ) and the (j-1)th bus node [BK j-1 ] is connected to the (j-1)-th bus node [BK j-1 ] and which the (j-1)-th bus node [BK (j-n) ] as the second bus node input current; i j+1 first bus node output current that the (j+1)-th bus node [BK j+1 ] over the section of the first single-wire bus (DB1), which is part of the connecting section of the serial, bidirectional, differential two-wire communication bus (DB) between the (j+1)-th bus node [BK j+1 ] and the j-th bus node (BK j ) is connected to the j-th bus node (BK j ) and which the j-th bus node (BK j ) as the first bus node input current; i' j+1 second bus node output current that the (j+1)-th bus node [BK j+1 ] over the section of the second single-wire bus (DB2), which is part of the connecting section of the serial, bidirectional, differential two-wire communication bus (DB) between the (j+1)-th bus node [BK j+1 ] and the j-th bus node (BK j ) is connected to the j-th bus node (BK j ) and which the j-th bus node (BK j ) as a second bus node input current; i n-1 first bus node output current that the (n-1)th bus node [BK n-1 ] over the section of the first single-wire bus (DB1), which is part of the connecting section of the serial, bidirectional, differential two-wire communication bus (DB) between the (n-1)th bus node [BK n-1 ] and the (n-2)th bus node [BK n-2 ] is connected to the (n-2)-th bus node [BK n-2 ] and which the (n-2)-th bus node [BK n-2] as the first bus node input current; i' n-1 second bus node output current that the (n-1)-th bus node [BK n-1 ] over the section of the second single-wire bus (DB2), which is part of the connecting section of the serial, bidirectional, differential two-wire communication bus (DB) between the (n-1)th bus node [BK n-1 ] and the (n-2)th bus node [BK n-2 ] is connected to the (n-2)-th bus node [BK n-2 ] and which the (n-2)-th bus node [BK n-2 ] as the second bus node input current; i n first bus node output current that the n-th bus node [BK n ] over the section of the first single-wire bus (DB1), which is part of the connecting section of the serial, bidirectional, differential two-wire communication bus (DB) between the n-th bus node [BK n ] and the (n-1)th bus node [BK n-1 ] is connected to the (n-1)th bus node [BK n-1] and which the (n-1)-th bus node [BK n-1 ] as the first bus node input current; i' n second bus node output current that the n-th bus node [BK n ] over the section of the second single-wire bus (DB2), which is part of the connecting section of the serial, bidirectional, differential two-wire communication bus (DB) between the n-th bus node [BK n ] and the (n-1)th bus node [BK n-1 ] is connected to the (n-1)th bus node [BK n-1 ] and which the (n-1)-th bus node [BK n-1 ] as the second bus node input current; IF1 differential serial interface of the first bus node (BK1); IF2 differential serial interface of the second bus node (BK2); IF3 differential serial interface of the third bus node (BK3); IF4 differential serial interface of the fourth bus node (BK4); IF5 differential serial interface of the fifth bus node (BK5); IF6 differential serial interface of the sixth bus node (BK6); IF( j-1 ) differential serial interface of the (j-1)-th bus node [BK j-1 ]; IF j differential serial interface of the j-th bus node (BK j ); IF (j+1) differential serial interface of the (j+1)-th bus node [BK j+1 ]; IF (n-1) differential serial interface of the (n-1)th bus node [BK n-1 ]; IF n differential serial interface of the n-th bus node [BK n ]; ILD lighting information for controlling the energy supply of the lamps (LED j ) of the bus node (BK j ) by the energy supply means (EV j ) of the bus node (BK j ) depending on this lighting information; INFO Payload information within the data information (DATA) of a bit stream packet (BP). This is preferably lighting data for the respective bus node (BK j ); Iq1 first addressing current source of the first bus node (BK1); Iq1' second addressing current source of the first bus node (BK1); Iq2 first addressing current source of the second bus node (BK2); Iq2' second addressing current source of the second bus node (BK2); Iq3 first addressing current source of the third bus node (BK3); Iq3' second addressing current source of the third bus node (BK3); IQ j first addressing current source of the j-th bus node (BK j ); IQ j ' second addressing current source of the j-th bus node (BK j ); IQ n first addressing current source of the n-th bus node [BK n ]; IQ n' second addressing current source of the n-th bus node [BK n ]; L1 first line section from the first bus node (BK1) to the bus master (ECU); L2 second line section from the second bus node (BK2) to the first bus node (BK1); L3 third line section from the third bus node (BK3) to the second bus node (BK2); µC microcontroller; LED1: The light source of the first bus node (BK1). This includes light source groups and interconnections. (This can be, for example, series and parallel connections of multiple LEDs.) LED2: Illuminant of the second bus node (BK2). This includes illuminant groups and interconnections. (This can be, for example, series and parallel connections of multiple LEDs.) LED3: Illuminant of the third bus node (BK3). This includes illuminant groups and interconnections. (This can be, for example, series and parallel connections of multiple LEDs.) LED4: Illuminants of the fourth bus node (BK4). This includes illuminant groups and interconnections. (This can be, for example, series and parallel connections of multiple LEDs.) LED5: Illuminant of the fifth bus node (BK5). This includes illuminant groups and interconnections. (This can be, for example, series and parallel connections of multiple LEDs.) LED6: Illuminant of the sixth bus node (BK6). This includes illuminant groups and interconnections (for example, series and parallel connections of multiple LEDs). pol first polarity signal that preferentially controls the multiplexer (X4); pol' second polarity signal, which preferentially controls the further multiplexer (X4'); R2 first shunt resistor for measuring the current through the first single-wire bus (DB a ) within the respective bus node (BK j ). The first shunt resistor is used here as part of the bus node (BK j ). It is located in each of the auto-addressable bus nodes ((BK1) to [BK n ]) are preferably present in each case. For clarity, the first shunt resistors were not provided with indices for the respective bus nodes. R2' second shunt resistor for measuring the current through the second single-wire bus (DB b ) within the respective bus node (BK j ). The second shunt resistor is used here as part of the bus node (BK j ). It is located in each of the auto-addressable bus nodes ((BK1) to [BK n]) are preferably present in each case. For clarity, the second shunt resistors were not provided with indices for the respective bus nodes. Rec receiver. Each bus node ((BK1) to [BK n ]) and the bus master (ECU) preferably have a receiver. A receiver extracts the data (DATA) contained in the bit stream packets (BP) and outputs it, preferably together with error information, via an output (out). The receiver typically checks whether the check information (CHKD) within the data information (DATA) of a bit stream packet (BP) indicates error-free reception. If a bit stream packet (BP) was not received correctly, the receiver signals this. Ref10 tenth threshold; Ref10' further tenth threshold; Ref11 eleventh threshold; Ref11' further eleventh threshold; Rm1 measuring resistor in the supply voltage line for the first bus node (BK1); Rm2 measuring resistor in the supply voltage line for the second bus node (BK2); Rm3 measuring resistor in the supply voltage line for the third bus node (BK3); Rm j Measuring resistor in the supply voltage line for the j-th bus node (BK j ); Rm n Measuring resistor in the supply voltage line for the n-th bus node [BK n ]; rw1 first control signal of the first bus node (BK1). The first control signal of the first bus node (BK1) is formed from the output signal of the third comparator (D3) of the first bus node (BK1) by means, preferably a first filter (F) of the first bus node (BK1), which can also form a unit with the third comparator (D3) of the first bus node (BK1), and serves to control the first auto-addressing current source (Iq1) of the first bus node (BK1); rw'1 second control signal of the first bus node (BK1). The second control signal of the first bus node (BK1) is formed from the output signal of the corresponding third comparator (D3') of the first bus node (BK1) by means, preferably a second filter (F) of the first bus node (BK1), which can also form a unit with the corresponding third comparator (D3') of the first bus node (BK1), and serves to control the second auto-addressing current source (Iq'1) of the first bus node (BK1); rw2 first control signal of the second bus node (BK2). The first control signal of the second bus node (BK2) is formed from the output signal of the second comparator (D3) of the second bus node (BK2) by means, preferably a first filter (F) of the second bus node (BK2), which can also form a unit with the third comparator (D3) of the second bus node (BK2), and serves to control the first auto-addressing current source (Iq2) of the second bus node (BK2); rw'2 second control signal of the second bus node (BK2). The second control signal of the second bus node (BK2) is formed from the output signal of the corresponding third comparator (D3') of the second bus node (BK2) by means, preferably a second filter (F) of the second bus node (BK2), which can also form a unit with the corresponding third comparator (D3') of the second bus node (BK2), and serves to control the second auto-addressing current source (Iq'2) of the second bus node (BK2); rw3 first control signal of the third bus node (BK3). The first control signal of the third bus node (BK3) is formed from the output signal of the third comparator (D3) of the third bus node (BK3) by means, preferably a first filter (F) of the third bus node (BK3), which can also form a unit with the third comparator (D3) of the third bus node (BK3), and serves to control the first auto-addressing current source (Iq3) of the third bus node (BK3); rw'3 second control signal of the third bus node (BK3). The second control signal of the third bus node (BK3) is formed from the output signal of the corresponding third comparator (D3') of the third bus node (BK3) by means, preferably a second filter (F) of the third bus node (BK3), which can also form a unit with the corresponding third comparator (D3') of the third bus node (BK3), and serves to control the second auto-addressing current source (Iq'3) of the third bus node (BK3); rw j first control signal of the j-th bus node (BK j ). The first control signal of the j-th bus node (BK j ) is determined by means, preferably a first filter (F) of the j-th bus node (BK j ), which is connected to the third comparator (D3) of the j-th bus node (BK j ) can also form a unit, from the output signal of the third comparator (D3) of the j-th bus node (BK j) and is used to control the first auto-addressing current source (Iq j ) of the j-th bus node (BK j ); rw' j second control signal of the j-th bus node (BK j ). The second control signal of the j-th bus node (BK j ) is determined by means, preferably a second filter (F) of the j-th bus node (BK j ), which is connected to the corresponding third comparator (D3') of the j-th bus node (BK j ) can also form a unit, from the output signal of the corresponding third comparator (D3') of the j-th bus node (BK j ) and is used to control the second auto-addressing current source (Iq' j ) of the j-th bus node (BK j ); S4 first bypass switch - also called first bus shunt bypass switch - for bridging the first shunt resistor (R2) within a bus node (BK j). The first bypass switch can also be designed as a transistor and / or as a more complex circuit of various electronic and other components if the functionality of a switch arises in the working area; S4' second bypass switch - also called second bus shunt bypass switch - for bridging the second shunt resistor (R2') within a bus node (BK j ). The second bypass switch can also be designed as a transistor and / or as a more complex circuit of various electronic and other components if the functionality of a switch is required in the operating area; START start signal; SYNC synchronization information; t B Length of a single bit within a bit stream packet (BP); TX a Transmitter that drives the first driver [TR a ] includes; TX b Transmitter that drives the second driver [TRb ] includes; V bat supply voltage line; X1 first multiplexer for connecting a first input of the second differential amplifier (D2) for measuring the current through the first single-wire bus (DB a ) with a first terminal of the first shunt resistor (R2) on the bus master (ECU) side or optionally with a second terminal of the measuring resistor [Rm j ] in the supply voltage line within the relevant bus node (BK j ); X1' second multiplexer for connecting a first input of the second comparator (D2') for measuring the current through the second single-wire bus (DB b ) with a first terminal of the second shunt resistor (R2') on the bus master (ECU) side or optionally with a second terminal of the measuring resistor [Rm j ] in the supply voltage line within the relevant bus node (BK j ); X2 first multiplexer for connecting a second input of the second differential amplifier (D2) for measuring the current through the first single-wire bus (DB a ) with a second terminal of the first shunt resistor (R2) on the opposite side of the bus master (ECU) or with a first terminal of the measuring resistor [Rm j ] in the supply voltage line within the relevant bus node (BK j ); X2' second multiplexer for connecting a second input of the second comparator (D2') for measuring the current through the second single-wire bus (DB b ) with a second terminal of the second shunt resistor (R2') on the opposite side of the bus master (ECU) or with a first terminal of the measuring resistor [Rm j ] in the supply voltage line within the relevant bus node (BK j ); X3 first demultiplexer for connecting a terminal of the first addressing current source (Iqj ) of the bus node (BK j ) with a first terminal of the first shunt resistor (R2) or with a second terminal of the first shunt resistor (R2) or with a reference potential within the relevant bus node (BK j ); X3' second demultiplexer for connecting a terminal of the second addressing current source (Iq' j ) of the bus node (BK j ) with a first terminal of the second shunt resistor (R2') or with a second terminal of the second shunt resistor (R2') or with a reference potential within the respective bus node (BK j ); X4 first multiplexer for swapping the inputs of the second differential amplifier (D2) of the bus node (BK j ); X4' second multiplexer for swapping the inputs of the further second differential amplifier (D2') of the bus node (BK j ); Z1 first logical state in which the first single-wire bus (DB a ) or the second single-wire bus (DB b ). This is also referred to as "High" in this disclosure. z1 is the first differential state the serial, bidirectional, differential two-wire communication bus (DB) can be in. This is also referred to as "High" in this disclosure. Z2 second logical state in which the first single-wire bus (DB a ) or the second single-wire bus (DB b ). This is also referred to as Low in this disclosure. z2 Second differential state in which the serial, bidirectional, differential two-wire communication bus (DB) can be. This is also referred to as "Low" in this disclosure. Z3 third logical state in which the first single-wire bus (DB a ) or the second single-wire bus (DB b). This is also referred to as Idle in this disclosure. Preferably, but not necessarily, the corresponding physical level of the first single-wire bus (DB a ) or the second single-wire bus (DB b ) a value around a common mean. z3 third differential state in which the serial, bidirectional, differential two-wire communication bus (DB) can be. This is also referred to as "Idle" in this disclosure. Preferably, but not necessarily, the corresponding differential physical level has a value around zero.

Claims

[1] Procedure for assigning logical bus node addresses to the bus nodes ((BK1) to [BK n ]) of a data bus system with a serial, bidirectional, differential two-wire communication bus (DB) - where the data bus system comprises a bus master (ECU) with an address input (Adr i0 ) and - where the data bus system has n bus nodes ((BK1) to [BK n ]) with n as a positive integer and - where each of the n bus nodes ((BK2) to [BK n ]) via a data line section ((DB1) to [DB n ]) or a serial, bidirectional, differential two-wire communication bus (DB) is connected to the bus master (ECU) for data transmission and - where one line is connected from an address input (Adr i0 ) of the bus master (ECU) through all bus nodes ((BK1) to [BK n ]) is looped through so that it passes through the individual bus nodes ((BK1) to [BK n]) in n line sections [L1 to L n ] and - where each of the bus nodes, hereinafter referred to as the j-th bus node (BK j ) denoted by 1≤j≤ n, a bus node (BK j ) corresponding address input [Adr ij ] and a j-th bus node (BK j ) associated address output [Adr oj ] and - where each of the bus nodes (BK j ) if it is not the n-th bus node [BK n] is, with 1≤j≤ n-1 with its address input [Adr ij ] with the address output (Adr o ( j+1 )) of a subsequent bus node [BK j+1 ] with 1≤j≤ n-1 by a bus node following [BK j+1] associated line section [L j+1 ] and - where each of the bus nodes (BK j ) with 2≤j≤ n with its address output [Adr oj ] with the address input [Adri( j-1)] of a preceding bus node [BK j-1 ] with 2≤j≤ n by a bus node (BK j ) associated line section [L j ] and - where the first bus node (BK1) with its address output (Adr o1 ) with the address input (Adr i0 ) of the bus master (ECU) by a line section [L1] belonging to the bus node (BK1) and - where the respective bus node address of each bus node (BK1 to BK n ) can be valid or not valid with the steps - Invalidating all or at least part of the respective bus node addresses of the bus nodes ((BK1) to [BK n ]) and moving at least this part of the bus nodes ((BK1) to [BK n ]) into an addressing state; - While the addressing state exists: Setting the level of the address input (Adr i0) of the bus master (ECU) to a second logical value when the level of this address input (Adr i0 ) of this bus master (ECU) is not controlled by the address output (Adr o1 ) of the first bus node (BK1) of the bus nodes ((BK1) to [BK n ]) is overwritten; - During the existence of the addressing state in each bus node (BK j ) the bus nodes ((BK2) to [BK n ]) excluding the first bus node (BK1): Overwriting the level at the address input [Adri (j-1) ] of the respective bus node (BK j ) preceding bus node [BK j-1 ] through this respective bus node (BK j ) with a first logic level if the bus node address of this respective bus node (BK j ) is invalid and the level at the address input [Adr ij ] of this respective bus node (BK j ) has a first logical value and setting the level of the address input [Adr ij] of this bus node (BK j ) to a second logical value when the level of this address input [Adr ij ] of this bus node (BK j ) not through the address output [Adr o(j+1) ] of the respective bus node (BK j ) subsequent bus node [BK j+1] the bus node ((BK3) to [BK n ]) is overwritten; - During the existence of the addressing state in the first bus node (BK1): Overwriting the level at the address input (Adr i0 ) of the bus master (ECU) by the first bus node (BK1) with a first logic level if the bus node address of the first bus node (BK1) is invalid and the level at the address input (Adr o1 ) of this first bus node (BK1) has a first logical value and setting the level of the address input (Adr i1 ) of this first bus node (BK1) to a second logical value when the level of this address input (Adr i1) of this first bus node (BK1) is not transmitted through the address output (Adr o2 ) of the bus node (BK2) following the first bus node (BK1) of the bus nodes ((BK2) to [BK n ]) is overwritten; - While the addressing state exists: Signaling of a bus node address to all bus nodes ((BK1) to [BK n ]) by the bus master (ECU) and acceptance of the signalled bus node address as a valid bus node address by that bus node (BK j ) the bus nodes ((BK1) to [BK n ]), whose bus node address is invalid and whose address input [Adr ij ] has a second logical value and repeating this signaling by the bus master (ECU) until the address input (Adr i0 ) of the bus master (ECU) has a second logical value; - Moving the bus nodes ((BK1) to [BK n]) into a second operating state different from the addressing state when the address input (Adr i0 ) of the bus master (ECU) has a second logical value. [2] Method according to the preceding claim 1, comprising the step - Using the line [L1 to L n ] in the second operating state as an interrupt line.

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