Simulation device based on daisy chain communication

Abstract

The utility model relates to the field of battery management systems, in particular to a daisy chain communication-based simulation device, which comprises an FPGA + ARM (Field Programmable Gate Array + Advanced RISC Machines) controller, a simulation branch and a BMS (Battery Management System) main controller, the analog branch comprises a differential circuit and a control circuit; the differential circuit comprises a signal buffer circuit, an ESD (Electro-Static Discharge) protection circuit, an LTC6820 circuit and an isolation transformer which are connected in sequence; a control signal output by the FPGA + RAM controller passes through the signal buffer circuit, the ESD protection circuit and the LTC6820 circuit and then is converted into a source current driving differential signal and a suction current driving differential signal which are matched with the isolation transformer. The isolation transformer sends the data to the BMS main controller; the control circuit comprises an SPI communication working mode switching circuit; the SPI communication working mode switching circuit is respectively connected with the FPGA + RAM controller and the LTC6820 circuit; the FPGA + RAM controller can select one of four communication working modes and communication clock rates of the LTC6820 through the SPI communication working mode switching circuit, and through the technical scheme, the FPGA + RAM controller has the advantages that the cost is reduced, the anti-interference capability is enhanced, and the communication rate is improved.

Description

Technical Field

[0001] The utility model relates to a simulation device, in particular to a simulation device based on daisy chain communication. Background Art

[0002] Battery Management System (BMS) is one of the core technologies in the field of electric vehicles and energy storage. With the development of the new energy market, the reliability and cost of battery management systems have attracted more and more attention. In the application field of BMS, the modular and distributed layout of battery packs has the advantages of optimizing weight distribution and maximizing space utilization. It mainly adopts a master-slave architecture battery management system. The communication methods between the main board and the slave board are mainly divided into CAN communication and daisy chain communication. For data communication links, although CAN communication can fully suppress noise through isolation, the specific implementation scheme is complex and the hardware cost is very high;

[0003] Daisy chain communication uses fewer components, has a simpler solution, and has more advantages. The low-voltage asynchronous full-duplex differential transmitter (LTC6820) can effectively reduce the impact of common-mode voltage swing caused by system noise by converting four-wire SPI signals into differential twisted pair communication pulse signals and isolating them through a low-cost transformer. In the point-to-point daisy chain configuration, it allows a long transmission distance and is more suitable for modular applications. The mainstream solution is that the motherboard controller provides an isoSPI interface and acts as a master station. The ADC unit of multiple battery monitoring chips collects multiple battery information and integrates an isoSPI interface as a slave station to realize information interaction. This daisy chain solution requires multiple groups of real batteries and multiple groups of battery monitoring chips to participate, which is costly. Therefore, a simulation device based on daisy chain communication is needed. Using one LTC6820 as a slave station can simulate multiple groups of real batteries and multiple groups of battery monitoring chips to test the motherboard controller. Utility Model Content

[0004] In order to solve the problems in the related art, the present application provides an analog device based on daisy chain communication, which solves the problem of high cost.

[0005] The technical solution is as follows:

[0006] A simulation device based on daisy chain communication, characterized in that it includes an FPGA+ARM controller, a simulation branch and a BMS main controller; the simulation branch includes a differential circuit and a control circuit;

[0007] The differential circuit includes a signal buffer circuit, an ESD protection circuit, an LTC6820 circuit and an isolation transformer; the FPGA+ARM controller is connected to the signal buffer circuit, the signal buffer circuit is connected to the ESD protection circuit, the ESD protection circuit is connected to the LTC6820 circuit, the LTC6820 circuit is connected to the isolation transformer, and the isolation transformer is connected to the BMS main controller;

[0008] The control signal output by the FPGA+RAM controller is subjected to impedance matching and signal level adaptation after passing through the signal buffer circuit, and is sent to the ESD protection circuit; the ESD protection circuit performs static electricity and surge protection on the signal emitted by the signal buffer circuit, and sends it to the LTC6820 circuit; the LTC6820 circuit is used to convert the signal emitted by the ESD protection circuit into a source current and a sink current drive differential signal adapted to the isolation transformer, and the LTC6820 circuit can output four communication working modes and communication clock rates; the isolation transformer is used to send the source current and the sink current drive differential signal emitted by the LTC6820 circuit to the BMS main controller;

[0009] The control circuit includes an SPI communication working mode switching circuit; the FPGA+RAM controller is connected to the SPI communication working mode switching circuit, and the SPI communication working mode switching circuit is connected to the LTC6820 circuit; the FPGA+RAM controller can select one of the four communication working modes and communication clock rates of LTC6820 through the SPI communication working mode switching circuit.

[0010] Through the above technical solution, by setting up the analog branch, with the BMS main controller as the master station and the analog branch as the slave station, the simulation of multiple battery acquisition boards plus multiple batteries can be realized according to the control instructions of the FPGA+ARM controller, and the LTC6820 circuit can be controlled to select one of the four working modes according to the control instructions of the FPGA+ARM controller, thereby reducing costs.

[0011] Furthermore, the analog branch includes a main analog circuit and a slave analog circuit with the same structure, and the main analog circuit and the slave analog circuit are connected in parallel.

[0012] Furthermore, it also includes a real-time machine, which is connected to the FPGA+ARM controller, and the real-time machine communicates with the FPGA+ARM controller via EtherCAT; the FPGA+ARM controller is used to perform model calculations on the battery pack model and feed back status information of the battery pack to the real-time machine, and the FPGA+ARM controller is controlled by the real-time machine.

[0013] Furthermore, the isolation transformer and the BMS main controller are connected via a twisted pair cable, the length of the twisted pair cable is controlled by the actually required transmission distance and the expected signal-to-noise ratio, and the BMS main controller is used to unpack the battery pack model parameters.

[0014] Through the above technical solution, by setting up a twisted pair, the anti-interference capability can be enhanced, and then by adapting the parameters, a longer distance can be transmitted, and the communication rate is also improved.

[0015] Furthermore, the LTC6820 circuit is provided with an MSTR pin, a 14th pin, a 15th pin, an isolation interface IP and an isolation interface IM, the MSTR pin is grounded, the 14th pin is connected in series with a voltage divider resistor Rb1 and then connected in parallel with the 15th pin, and is connected in series with a voltage divider resistor Rb2, and the voltage divider resistor Rb2 is grounded;

[0016] The differential signal driving current IBIAS and the receiving signal comparator voltage threshold ICMP outputted by the 14th and 15th pins respectively are controlled by the resistance values ​​of the voltage-dividing resistors Rb1 and Rb2, IBIAS=2V / (Rb1+Rb2), ICMP=0.5*IBIAS*R2; a resistor Rm is connected in parallel at both ends of the isolation interface IP and the isolation interface IM, and is connected in series with the isolation transformer, the differential driving current Id=20*IBIAS outputted by the isolation interface IP and the isolation interface IM, and the voltage amplitude transmitted through the 1:1 isolation transformer is Id*Rm / 2.

[0017] Furthermore, the LTC6820 circuit is provided with an SPI communication module and an operating mode module, the SPI communication module is connected to the FPGA+ARM controller, and the operating mode module is connected to the SPI communication operating mode switching circuit; the operating mode module is used to control the operating mode and communication clock rate of the LTC6820 circuit, the LTC6820 circuit communicates with the FPGA+ARM controller through the SPI communication module, and the operating mode and communication clock rate of the LTC6820 circuit are controlled by the FPGA+ARM controller through the operating mode module.

[0018] In summary, the beneficial effects of a simulation device based on daisy chain communication are:

[0019] 1. By setting the first analog branch and the second analog branch, with the BMS main controller as the master station and the first analog branch and the second analog branch as the slave station, the multi-channel battery acquisition board plus multi-channel batteries can be simulated by packing and unpacking the battery pack model according to the control instructions of the FPGA+ARM controller, and the LTC6820 circuit can be controlled to select one of the four working modes according to the control instructions of the FPGA+ARM controller, thereby reducing costs;

[0020] 2. By setting up twisted pair cables, the anti-interference ability can be enhanced, and then by adapting the parameters, the transmission distance can be longer and the communication rate can be improved.

[0021] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present utility model, and together with the description, are used to explain the principles of the present utility model.

[0023] Figure 1 is a communication diagram of a simulation device based on daisy chain communication;

[0024] Figure 2 A communication diagram of an LTC6820 circuit and an isolation transformer in a simulation device based on daisy chain communication;

[0025] In the figure, 1. Real-time machine; 2. FPGA+RAM controller; 3. SPI communication working mode switching circuit; 4. Signal buffer circuit; 5. ESD electrostatic protection circuit; 6. LTC6820 circuit; 7. Isolation transformer; 8. BMS main controller. DETAILED DESCRIPTION

[0026] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the utility model. Instead, they are only examples of devices and methods consistent with some aspects of the utility model as detailed in the attached claims.

[0027] In a possible embodiment, as shown in the attached Figure 1-2 As shown, a simulation device based on daisy chain communication includes an FPGA+ARM controller, a simulation branch and a BMS main controller 8; the simulation branch includes a differential circuit and a control circuit;

[0028] The differential circuit includes a signal buffer circuit 4, an ESD protection circuit, an LTC6820 circuit 6 and an isolation transformer 7; the FPGA+ARM controller is connected to the signal buffer circuit 4, the signal buffer circuit 4 is connected to the ESD protection circuit, the ESD protection circuit is connected to the LTC6820 circuit 6, the LTC6820 circuit 6 is connected to the isolation transformer 7, and the isolation transformer 7 is connected to the BMS main controller 8;

[0029] The control signal output by the FPGA+RAM controller 2 is impedance matched and signal level adapted after passing through the signal buffer circuit 4, and is sent to the ESD protection circuit; the ESD protection circuit performs static electricity and surge protection on the signal sent by the signal buffer circuit 4, and sends it to the LTC6820 circuit 6; the LTC6820 circuit 6 is used to convert the signal sent by the ESD protection circuit into a source current and a sink current drive differential signal adapted to the isolation transformer 7; the LTC6820 circuit 6 can output four communication working modes and communication clock rates; the isolation transformer 7 is used to send the source current and the sink current drive differential signal sent by the LTC6820 circuit 6 to the BMS main controller 8;

[0030] The control circuit includes an SPI communication working mode switching circuit 3; the FPGA+RAM controller 2 is connected to the SPI communication working mode switching circuit 3, and the SPI communication working mode switching circuit 3 is connected to the LTC6820 circuit 6; the FPGA+RAM controller 2 can select one of the four communication working modes and communication clock rates of the LTC6820 through the SPI communication working mode switching circuit 3 to achieve flexible configuration.

[0031] It also includes a real-time machine 1, which is connected to an FPGA+ARM controller. The real-time machine 1 communicates with the FPGA+ARM controller via EtherCAT. The FPGA+ARM controller is used to perform model calculations on the battery pack model and feed back status information of the battery pack to the real-time machine 1. The FPGA+ARM controller is controlled by the real-time machine 1, that is, the FPGA+ARM controller receives control commands from the real-time machine 1 via EtherCAT and feeds back status information to the real-time machine 1.

[0032] With the BMS main controller 8 as the master station and the analog branch as the slave station, the situation of simulating multiple battery acquisition boards plus multiple batteries can be realized by packaging and unpacking the battery pack model according to the control instructions of the FPGA+ARM controller. In addition, the LTC6820 circuit 6 can be controlled to select one of the four working modes according to the control instructions of the FPGA+ARM controller, thereby reducing costs.

[0033] The isolation transformer 7 and the BMS main controller are connected via a twisted pair cable. The length of the twisted pair cable is controlled by the actual required transmission distance and the desired signal-to-noise ratio. The BMS main controller 8 is used to unpack the battery pack model parameters. The twisted pair cable can enhance the anti-interference capability, and then, by adapting the parameters, it can transmit over a longer distance and improve the communication rate.

[0034] The LTC6820 circuit 6 is provided with an MSTR pin, a 14th pin, a 15th pin, an isolation interface IP and an isolation interface IM, the MSTR pin is grounded, the 14th pin is connected in series with a voltage divider resistor Rb1 and then connected in parallel with the 15th pin, and is connected in series with a voltage divider resistor Rb2, and the voltage divider resistor Rb2 is grounded;

[0035] The differential signal driving current IBIAS and the receiving signal comparator voltage threshold ICMP outputted from the 14th and 15th pins are controlled by the resistance values ​​of the voltage divider resistors Rb1 and Rb2, IBIAS = 2V / (Rb1+Rb2), ICMP = 0.5*IBIAS*R2;

[0036] A resistor Rm is connected in parallel at both ends of the isolation interface IP and the isolation interface IM, and is connected in series with the isolation transformer 7. The differential drive current Id=20*IBIAS output by the isolation interface IP and the isolation interface IM, and the voltage amplitude transmitted through the 1:1 isolation transformer 7 is Id*Rm / 2.

[0037] The LTC6820 circuit 6 is provided with an SPI communication module and a working mode module, the SPI communication module is connected to the FPGA+ARM controller, and the working mode module is connected to the SPI communication working mode switching circuit 3; the working mode module is used to control the working mode and communication clock rate of the LTC6820 circuit 6, the LTC6820 circuit 6 communicates with each other through the SPI communication module and the FPGA+ARM controller, and the working mode and communication clock rate of the LTC6820 circuit 6 are controlled by the FPGA+ARM controller through the working mode module.

[0038] Operation principle: The battery pack model simulates a multi-channel battery acquisition board and multi-channel battery information through code packaging, and then downloads the battery pack model to the FPGA+RAM controller 2 for model calculation. It receives the control command of the real-time machine 1 through EtherCAT communication and feeds back the status information to the real-time machine 1. The FPGA+ARM controller sends the control signal to the signal buffer circuit 4 through SPI. The control signal output by the FPGA+RAM controller 2 is impedance matched and signal level adapted after passing through the signal buffer circuit 4, and then sent to the ESD protection circuit. The ESD protection circuit performs static electricity and surge protection on the received signal and sends it to the LTC6820 circuit 6; LTC6820 circuit 6 converts the received signal into source current and sink current drive differential signals adapted to the isolation transformer 7, and sends it to the isolation transformer 7. During this process, the FPGA+RAM controller 2 can select one of the four communication working modes and communication clock rates of LTC6820 through the SPI communication working mode switching circuit 3. The isolation transformer 7 sends the source current and sink current drive differential signals to the BMS main controller 8 through the twisted pair cable. The BMS main controller 8 receives the information sent from the isolation transformer 7, and after being decoded by the LTC6820 in the BMS main controller 8, the battery pack model parameters are unpacked and processed, thereby realizing information interaction.

[0039] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the present invention. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not present in the present invention. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present invention are indicated by the appended claims.

[0040] It should be understood that the present invention is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A simulation device based on daisy chain communication, characterized in that: It includes an FPGA+ARM controller, an analog branch and a BMS main controller; the analog branch includes a differential circuit and a control circuit; The differential circuit includes a signal buffer circuit, an ESD protection circuit, an LTC6820 circuit and an isolation transformer; the FPGA+ARM controller is connected to the signal buffer circuit, the signal buffer circuit is connected to the ESD protection circuit, the ESD protection circuit is connected to the LTC6820 circuit, the LTC6820 circuit is connected to the isolation transformer, and the isolation transformer is connected to the BMS main controller; The control signal output by the FPGA+RAM controller is subjected to impedance matching and signal level adaptation after passing through the signal buffer circuit, and is sent to the ESD protection circuit; the ESD protection circuit performs static electricity and surge protection on the signal emitted by the signal buffer circuit, and sends it to the LTC6820 circuit; the LTC6820 circuit is used to convert the signal emitted by the ESD protection circuit into a source current and a sink current drive differential signal adapted to the isolation transformer, and the LTC6820 circuit can output four communication working modes and communication clock rates; the isolation transformer is used to send the source current and the sink current drive differential signal emitted by the LTC6820 circuit to the BMS main controller; The control circuit includes an SPI communication working mode switching circuit; the FPGA+RAM controller is connected to the SPI communication working mode switching circuit, and the SPI communication working mode switching circuit is connected to the LTC6820 circuit; the FPGA+RAM controller can select one of the four communication working modes and communication clock rates of LTC6820 through the SPI communication working mode switching circuit.

2. A simulation device based on daisy chain communication according to claim 1, characterized in that: The analog branch includes a main analog circuit and a slave analog circuit with the same structure, and the main analog circuit and the slave analog circuit are connected in parallel.

3. The simulation device based on daisy chain communication according to claim 1, characterized in that: It also includes a real-time machine, which is connected to the FPGA+ARM controller, and the real-time machine communicates with the FPGA+ARM controller via EtherCAT; the FPGA+ARM controller is used to perform model calculations on the battery pack model and feed back status information of the battery pack to the real-time machine, and the FPGA+ARM controller is controlled by the real-time machine.

4. The simulation device based on daisy chain communication according to claim 1, characterized in that: The isolation transformer and the BMS main controller are connected via a twisted pair cable, the length of which is controlled by the actually required transmission distance and the desired signal-to-noise ratio. The BMS main controller is used to unpack the battery pack model parameters.

5. The simulation device based on daisy chain communication according to claim 1, characterized in that: The LTC6820 circuit is provided with an MSTR pin, a 14th pin, a 15th pin, an isolation interface IP and an isolation interface IM, the MSTR pin is grounded, the 14th pin is connected in series with a voltage divider resistor Rb1 and then connected in parallel with the 15th pin, and is connected in series with a voltage divider resistor Rb2, and the voltage divider resistor Rb2 is grounded; The differential signal driving current IBIAS and the receiving signal comparator voltage threshold ICMP outputted from the 14th pin and the 15th pin are controlled by the resistance values ​​of the voltage-dividing resistors Rb1 and Rb2, IBIAS=2V / (Rb1+Rb2), ICMP=0.5*IBIAS*R2; A resistor Rm is connected in parallel at both ends of the isolation interface IP and the isolation interface IM, and is connected in series with the isolation transformer. The differential drive current Id=20*IBIAS output by the isolation interface IP and the isolation interface IM, and the voltage amplitude transmitted through the 1:1 isolation transformer is Id*Rm / 2.

6. The simulation device based on daisy chain communication according to claim 1, characterized in that: The LTC6820 circuit is provided with an SPI communication module and a working mode module, the SPI communication module is connected to the FPGA+ARM controller, and the working mode module is connected to the SPI communication working mode switching circuit; The working mode module is used to control the working mode and communication clock rate of the LTC6820 circuit. The LTC6820 circuit communicates with the FPGA+ARM controller through the SPI communication module. The working mode and communication clock rate of the LTC6820 circuit are controlled by the FPGA+ARM controller through the working mode module.

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