ANALOGUE-TO-DIGITAL CONVERTER WITH INVERTER-BASED AMPLIFIER

Abstract

Analog-to-digital converter (100), ADC, featuring: an input terminal (102) which is configured to receive an analog input voltage signal (VIN); a first ADC stage (108) which is coupled to the input terminal (102) and is configured to output a first digital value (D1) corresponding to the analog input voltage signal (VIN) and a first analog residual signal (VRES1) corresponding to a difference between the first digital value (D1) and the analog input signal (VIN); a first inverter-based residual amplifier (114) configured to receive the first analog residual signal (VRES1), amplify the first analog residual signal (VRES1) and output a first amplified residual signal (VRES1G); a second ADC stage (116) configured to receive the first amplified residual signal (VRES1G) and output a second digital value (D2) corresponding to the first amplified analog residual signal (VRES1G) and output a second analog residual signal (VRES2) corresponding to a difference between the second digital value (D2) and the first amplified analog residual signal (VRES1G); a second inverter-based residual amplifier (118) configured to receive the second analog residual signal (VRES2), amplify the second analog residual signal (VRES2) and output a second amplified residual signal (VRES2G); a third ADC stage (120) configured to receive the second amplified residual signal (VRES2G) and output a third digital value (D3) corresponding to the second amplified analog residual signal (VRES2G); and a control unit (300, 330) coupled to the first ADC stage (108), the second ADC stage (116) and the third ADC stage (120) and configured to combine the first digital value (D1), the second digital value (D2) and the third digital value (D3) into a digital output signal (DOUT) which represents the analog input voltage signal (VIN); wherein the first ADC stage (108) is configured to sample the analog input voltage signal (VIN) during a first operating phase (10, phi1), to convert the analog input voltage signal (VIN) to the first digital value (D1) during a second operating phase (20, phi2), and to retain the first analog residual signal (VRES1) during a third operating phase (30, phi3); wherein the first residual amplifier (114) is deactivated during the first operating phase (10, phi1), is reset during the second operating phase (20, phi2), and is configured to amplify the first analog residual signal (VRES1) during the third operating phase (30, phi3); and wherein the second ADC stage (116) is set up to sample the amplified first analog residual signal (VRES1) during the third operating phase (30, phi3) and to convert the analog input voltage signal (VIN) during the first operating phase (10, phi1), and to convert the amplified first analog residual signal (VRES1) during the first operating phase (10, phi1) and the second operating phase into the second digital value (D2).

Description

TECHNICAL BACKGROUND

[0001] Analog-to-digital converters (ADCs or A / D converters) are used in a variety of applications to convert a sampled analog signal into a digital signal. There are several ADC architectures, such as pipeline, flash, sigma-delta, successive approximation register (SAR), and others. A pipeline or subranging (two-stage) ADC uses two or more subdivision stages. It performs a rough conversion of an analog input voltage to a rough digital value, which is then converted back to an analog signal using a digital-to-analog converter (DAC). The rough value is compared to the input voltage using an analog comparator, and the difference or remainder is then further refined and the results combined. A successive approximation ADC uses a comparator to successively narrow down a range that includes the input voltage.In each subsequent step, the converter compares the input voltage with the output of a DAC, which can represent the midpoint of a selected voltage range. At each step in this process, the approximation is stored in a successive approximation register (SAR). The steps continue until the desired resolution is achieved.

[0002] US 9,444,406 B1 discloses an ADC in a pipeline architecture. CN 106 817 131 A discloses an ADC in a pipeline SAR architecture. US 9,219,492 B1 discloses an ADC in a pipeline architecture with SAR support. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for clarity of explanation. Fig. Figure 1 is a block diagram illustrating aspects of an analog-to-digital converter (“ADC”) system in accordance with some embodiments. Fig. Figure 2 is a block diagram showing examples of further aspects of the ADC system. Fig. 1 in accordance with some embodiments describes. Fig. Figure 3A is a pipeline diagram illustrating example control signals for operating phases in accordance with some embodiments. Fig. Figure 3B is a graphic illustrating the operation of different system components for example operating phases in accordance with some embodiments. Fig. Figure 4 is a circuit diagram illustrating an example of a sub-ADC used in the ADC system of Fig. 2 is shown in accordance with some embodiments. Fig. Figure 5 is a signal diagram illustrating examples of control signals for the sub-ADC located in Fig. 4 is shown in accordance with some embodiments. Fig. Figure 6 is a circuit diagram illustrating an example of a residual DAC used in the ADC system of Fig. 2 is shown in accordance with some embodiments. Fig. Figure 7 is a signal diagram illustrating examples of control signals for the residual DAC, which is located in Fig. 6 is shown in accordance with some embodiments. Fig. Figure 8 is a circuit diagram illustrating an example of an inverter-based residual amplifier in accordance with some embodiments. Fig. Figure 9 is a circuit diagram showing an example of a control circuit for the inverter-based residual amplifier of Fig. 8 illustrated in accordance with some embodiments. Fig. Figure 10 is a circuit diagram showing an example of another control circuit for the inverter-based residual amplifier of Fig. 8 illustrated in accordance with some embodiments. Fig. Figure 11 is a signal diagram illustrating example waveforms generated by the control circuits of Fig. 9 and Fig. 10 can be produced in accordance with some embodiments. Fig. Figure 12 is a circuit diagram showing an example of the second and third sub-ADCs of Fig. 2 illustrated in accordance with some embodiments. Fig. Figure 13 is a flowchart illustrating an example of an ADC procedure in accordance with some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and not to be construed as limitations. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the FIGS. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation shown in the FIGS. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0006] Analog-to-digital converters (ADCs or A / Ds) convert an analog signal into a digital signal. Typical ADC designs, such as pipeline, flash, sigma-delta, successive approximation register (SAR), etc., can consume too much silicon area, draw too much power, and therefore be too expensive for certain applications. Furthermore, with some known ADC methods, it can be difficult to achieve a sufficiently high signal-to-noise ratio (SNR) and conversion bandwidth in low-voltage, low-power deep-submicron processes. For example, some well-known pipeline ADC methods use high-gain amplifiers, which are difficult to implement in FinFET processes. In accordance with aspects disclosed herein, the ADC is more resistant to process, voltage, and temperature (PVT) variations by using a low-voltage residual amplifier.

[0007] Fig. Figure 1 is a block diagram illustrating an example of an ADC 100 that uses an inverter-based residual amplifier. The ADC 100 includes an input terminal 102, which is configured to accept an analog input signal V. IN to receive. A first ADC stage 108 is coupled to the input terminal 102 and configured to receive a first digital value D1 corresponding to the analog input voltage signal V. IN , as well as a first analog residual signal V RES1 corresponding to a difference between the first digital value D1 and the analog input signal V IN to output. The first digital value D1 can, for example, represent the most significant digits (MSB) of a digital output signal D. OUT be.

[0008] An inverter-based residual amplifier 114 receives the first analog residual signal V RES1 and amplifies the first analog residual signal V RES1 , to obtain a first amplified residual signal VRES1G to output. A second ADC stage 116 receives the first amplified residual signal V. RES1G and outputs a second digital value D2 corresponding to the first amplified analog residual signal V RES1G A calibration and digital error correction block 122 is coupled to the first and second ADC stages 108, 116 to convert the first digital value D1 and the second digital value D2 into a digital output signal D. OUT to combine with an output terminal 124, which carries the analog input voltage signal V IN The adjustment and digital correction block 122 can be implemented by any suitable processing element.

[0009] As explained below, some examples of the first ADC stage 108 include a sub-ADC 112, such as a SAR ADC, which is configured to take the analog input voltage signal V INto convert to the first digital value D1. A digital-to-analog converter (DAC) 110 receives the first analog input voltage signal V. IN and the first digital value D1 and gives the first analog residual signal V RES1 based on this. Additional subsequent ADC stage(s) 116, depending on the desired resolution of the digital output signal D OUT It may be set up similarly to the first ADC stage 108, and may contain further components.

[0010] Fig. Figure 2 illustrates further aspects of the example ADC 100 from Fig. 1. In the Fig. The example shown contains the analog input voltage signal V. IN Differential input signals V IP and V IM, which are received at the analog input voltage connection 102. These signals are received by the first ADC stage 108, which further generates a clock signal CLKS via a clock generator 106 and a reference voltage V. ref The sub-ADC 112 can comprise a SAR ADC, which includes a tracking and holding circuit 130, and a SAR logic block 132, which can be implemented by a suitably programmed processing element. The tracking and holding circuit 130 is connected to receive the analog differential input signals V. IP , V IM to sample and provide an output signal to a comparator 134, which is coupled to the SAR logic block 132. The sub-ADC 112 outputs the first digital value D1, which is the MSB of the digital output signal D. OUT It can be. In the illustrated example, the D1 digital output is five bits.

[0011] The first digital output D1 is also an output to the DAC 110, which is configured to convert the first digital output signal D1 into an analog signal and to combine the converted D1 signal with the input voltage signals V IP , V IM to compare and the first residual signal V RES1 to output. In the illustrated example, the first residual signal is V RES1 a differential voltage signal, V RESP1 and V RESM1 contains signals that are output to the first residual amplifier 114. The residual amplifier 114 amplifies the analog residual signals V RESP1 , V RESM1 and outputs the amplified residual signal V RES1G out of.

[0012] The amplified residual signal V RES1GThe signal is received by the second ADC stage 116, which may also include a SAR ADC. In some implementations, the structure of the second ADC stage 116 is similar to that of the first ADC stage 108. The second ADC stage 116 performs the A / D conversion of the amplified residual signal V. RES1G to output a second digital signal D2, which contains the next most significant bits (5 bits, for example) of the digital output signal D OUT This represents the signal received by the alignment and digital error correction stage 122. The second ADC stage 116 also outputs a second residual signal as analog differential residual signals V. RESP2 and V RESM2 from which are received by the second residual amplifier 118. The second residual amplifier 118 outputs an amplified second residual signal V. RES2Gfrom which a subsequent ADC stage, such as a third ADC stage 120, can be received. As with the second ADC stage 116, the structure of the third ADC stage 120 can be similar to that of the first ADC stage 108 and can therefore also include a SAR ADC.

[0013] The third ADC stage 120 performs the A / D conversion of the second amplified residual signal V. RES2G to output a third digital signal D3, which represents the LSBs (for example, 8 bits) of the digital output signal D OUT This represents the signal received by the alignment and digital error correction stage 122. The first, second, and third digital signals D1, D2, D3 are combined in the alignment and digital error correction stage 122 before being output as a digital output signal D. OUT are output. In the illustrated example, the calibration and digital error correction stage 122 provides a 16-bit digital output signal D. OUTready, which includes the 5-bit D1 signal, the 5-bit D2 signal and the 8-bit D3 signal minus two error check bits.

[0014] Fig. Figure 3A is a pipeline diagram illustrating examples of control signals for three operating phases of the ADC 100. In some embodiments, the ADC 100 generally operates in response to first, second, and third phase control signals phi1, phi2, and phi3. Furthermore, in some examples, a third operating phase is twice as long as either the first or second operating phase, and therefore the third phase control signal has approximately twice the duration of either the first or second phase control signal phi1, phi2. In other words, for a given clock cycle, the first and second phase control signals phi1, phi2 are each at a logic high for 25% of the cycle, while the third control signal phi3 is at a logic high for 50% of the clock cycle.

[0015] Fig. 3B is a graphic that summarizes operations during the different operational phases described in Fig. Figure 3A illustrates the ADC system 100. In some examples, the sub-ADC 112 and the remaining DAC 110 of the first ADC stage 108 sample the analog input voltage signals V during the first operating phase 10 (first phase control signal phi1 is high). IP , V IM as shown in Operation 12. The first residual amplifier 114 is deactivated as shown in Operation 14. Additionally, the common-mode sensing capacitors of residual amplifier 114 are recharged, allowing the common-mode capacitors to be used to control the output common-mode of the residual amplifier. During the second control phase 20 (second phase control signal phi2 is high), the first ADC stage 108 performs the A / D conversion of the analog input voltage signals V. IP , V IMIn operation 22, the residual amplifier 114 is reset to operation 24. During the third control phase 30 (third phase control signal phi3 is high), the first residual signals V RESP1 , V RESM1 , which are output by the first ADC stage 108, are kept in operation by the residual DAC 110 32 and the first residual amplifier 114 amplifies the received residual signal V RESP1 , V RESM1 , to obtain the amplified residual signal V RES1G to output in operation 34. Furthermore, during the third control phase 30, the second ADC stage 116 samples the amplified residual signals V. RES1G and V RES2G from which the first residual amplifiers 114 receive. During the subsequent first and second operating stages 10, 20, the second ADC stage 116 performs the A / D conversion of the amplified residual signals V RES1G and V RES2G out of.

[0016] As mentioned previously, some embodiments, such as the embodiment described in Fig. Figure 2 illustrates additional ADC stages and residual amplifiers. In addition to the first residual amplifier 114 and the second ADC stage 116, the ADC system 100, which is shown in Fig. Figure 2 shows the second residual amplifier 118 and the third ADC stage 120. In implementations such as the example of Fig. 2. The additional stages, such as the second residual amplifier 118 and the third ADC stage 120, perform corresponding operations during the respective operating phases. Therefore, the second residual amplifier 116 is also deactivated during the first operating phase 10, reset during the second operating phase 20, and amplifies the second residual signals V. RESP2 , V RESM2 During the third operating phase, 30. Similarly, the third ADC stage performs 120 A / D conversion of received amplified residual signals V. RESPG2 , V RESM2G during the first and second control phases.

[0017] Fig. Figure 4 shows an example of the sub-ADC 112 of the first ADC stage 108. In the illustrated example, the sub-ADC 112 is a SAR ADC. A SAR ADC uses a comparator to successively narrow a range that includes the input voltage. In each subsequent step, the converter compares the input voltage to the output of a digital-to-analog converter. Therefore, the SAR ADC 112 of the illustrated example includes the tracking and holding circuit 130, the comparator 134, and the SAR logic block 132. The SAR logic 132 receives a clock signal CLKS and outputs a pulsed control signal φ. ADC1 ready for the tracking and holding circuit 130. The control signal φ ADC1 controls the operation of a plurality of switches 150, which are operatively connected to one side of a plurality of capacitors Co-CN. In the illustrated example, there are two sets of capacitors 152a, 152b, each connected to the analog differential voltage inputs V. IPand V IM Accordingly. Each of the sets of capacitors 152a, 152b contains a plurality of capacitors Co-CN, where N can correspond to the number of bits to be converted, such as the LSB bits of the first digital signal D1, which is in Fig. Figure 2 is shown. In some examples, capacitors C1-CN are binary weighted and capacitor Co is a "dummy LSB" capacitor. The minimum capacitor size C is approximately 2 fF in some embodiments.

[0018] Fig. Figure 5 illustrates an example of the relationship between control signals for the first control phase of the ADC 100, containing the first phase control signal phi1 and the control signal φ. ADC1 , which is output by the SAR logic block 132. The SAR control signal φ ADC1 controls the switches 150 to connect the capacitors 152a, 152b between the analog input signal V IP , V IM or the reference voltage signal V refand to connect to a ground rail. The first phase control signal phi1 further controls the switches 154 to selectively connect the capacitors either with the analog input signal V. RESP , V RESM or the reference voltage signal V ref to connect, and switch 156, selectively with the other side of capacitors 152a, 152b to a common-mode voltage V CM to connect.

[0019] When the first phase control signal phi1 is high, the switches 150 operate around the cover plates of the capacitors Co-CN of the sets of capacitors 152a, 152b with the analog input voltage signals V IP , V IM to connect. At the same time, the high phi1 signal connects the base plates of capacitors Co-CN of the sets of capacitors 152, 152b to the common-mode voltage signal V. CM , to the analog input signal V IP , V IM to scan. As in Fig. As shown in Figure 5, the phi1 control signal becomes low during the second control phase and the SAR logic block 132 outputs the SAR control signal φ. ADC1 off. The SAR control signal φ ADC1 contains a series of pulses 160 derived from the second phase control signal phi2 to control the SAR binary search algorithm and generate the first digital output signal D1, which determines the MSBs of the analog input voltage V IP , V IM This represents the SAR logic block 132, which outputs a digital control signal φ. RADC from, which is used to operate residual DAC facilities such as in Fig. 6 shown to control.

[0020] Fig. Figure 6 illustrates an example of the residual DAC 110 of the first ADC stage 108 of the ADC 100. The residual DAC 110 includes a tracking and holding circuit with a binary-weighted capacitor array. In particular, the illustrated binary-weighted capacitor array includes two sets of capacitors 172a and 172b, corresponding to the analog differential voltage inputs V1 and V2, respectively. IP and V IM Each of the sets of capacitors 172a, 172b contains a plurality of capacitors Co-CN, where N can correspond to the number of bits to be converted. The capacitors Co-CN can be sized for low-noise residual generation as determined by the "kT / C" thermal noise specification. A plurality of switches 174 is operatively connected to one side of the capacitors Co-CN of the sets of capacitors 172a, 172b. The switches 174 are connected by φ RADCClock phase signals, output by the SAR logic block 132, are controlled to selectively connect one side of the capacitors Co-CN to a ground rail 180 or a voltage rail 182. The voltage rail 182 is selectively connected either to the differential input voltages V IM , V IP or the reference voltage V ref connected by switch 190, which responds to the first phase control signal phi1. The first phase control signal phi1 further controls switch 192 to selectively connect the base plates of capacitors Co-CN to the common-mode voltage V. CM to connect.

[0021] As in Fig. Figure 6 shows that when the first phase control signal phi1 is high, switches 190 couple the voltage rail 182 to the analog input signals V IP , V IM and switches 192 couple the base plates of the capacitors to the common-mode voltage signal V CMso that the remaining DAC 110 processes the analog input voltage signals V IP , V IM tracked. As in Fig. As shown in Figure 7, when the first phase control signal phi1 becomes low, the φ control RADC digital residual signal pulses 162, the switches 174, the capacitors Co-CN with the reference voltage V ref to connect the analog differential residual signals V RESP , V RESM to produce.

[0022] Fig. Figure 8 illustrates an example of the inverter-based residual amplifier 114. The example residual amplifier 114 contains three inverter-based stages 206, 208, and 210. The inverter-based stages allow for a near rail-to-rail output span and provide a highly dynamic charging current. The in Fig. The exemplary inverter-based residual amplifier 114 shown in Figure 8 receives and amplifies the differential residual voltage signal V. RESM ,V RESPand is therefore essentially "mirrored" about a vertical center line of the amplifier circuit. Thus, the second and third stages 206, 208 each contain left and right sections on each side of the symmetrical first stage 106 in a completely differential manner. This is just one example, and it should be welcomed that other designs are possible for implementing an inverter-based residual amplifier. The amplifier 114 is connected between a voltage supply rail 216, configured to receive a supply voltage AVDD, and ground. In some embodiments, the amplifier 114 is configured to operate with a low-voltage supply of, for example, less than 1.0 V. In the illustrated embodiment, the AVDD supply voltage is 0.8 volts. The inverter-based stages, which operate dynamically with a low-voltage supply, consume less power than a conventional cascode class A residual amplifier.

[0023] The first stage 206 contains input terminals 201, 202, which are configured to receive the analog differential residual signals V RESM or V RESP to receive. The input terminals 201, 202 are coupled to first inverters 310, 311, whose outputs are coupled to the second stage 208 at nodes 312, 313. In the illustrated example, the first inverter 310 comprises transistors M3, M5, and the second inverter 311 comprises transistors M4, M6. The outputs of the first inverters 310, 311 of the first stage 206 are further connected to the gate terminals of transistors M7 and M8, respectively, which couple the supply voltage terminal 216 to the first inverters 310, 311. The transistors M7, M8 therefore control the current flow to the first inverters 310, 311 based on the inverse input voltage signals V. RESP , V RESMAn activation transistor Mo has its source connected to ground and is configured to receive an activation signal EN at its gate, which is the complement of the phi1 control signal. Therefore, the activation transistor Mo selectively activates or deactivates amplifier 114 effectively in response to the phi1 control signal, from which the activation EN signal is derived. Transistors M1 and M2 are connected between the first and second inverters 310 and 311, respectively, and the drain of the activation transistor Mo. Transistors M1 and M2 are configured to receive a bias signal V. BIASN or the common-mode feedback signal V CMat their gate, which sets the bias current of the first stage 206. In some implementations, transistors Mo, M7, and M8 operate in the linear region, while transistors M1 and M2 operate in the saturation region and therefore act as constant current sources. Accordingly, the first amplifier stage 206 functions as a differential input pair.

[0024] The output nodes 312, 313 of the inverters 310, 311 of the first stage are coupled to the input of the second amplifier stage 208. For simplification, only those in Fig. Section 8, which considered the right-hand parts of the second and third amplifier stages 208 and 210, was discussed in detail. The second stage 208 is configured to selectively embed a neutral zone between the current paths that drive the output of amplifier 114 by employing a dynamic current reduction technique via transistors M11 and M12, which are operated in a triode region—that is, as variable resistors.

[0025] In particular, in Fig. In the example shown in Figure 8, the current control transistor M11 is connected between the AVDD voltage supply terminal 216 and a lower second-stage inverter 320. The current control transistor M12 is connected between the ground terminal and an upper second-stage inverter 322. The lower and upper second-stage inverters 320 and 322 contain transistors M9 / M10 and M13 / M14, respectively. The gates of the current control transistors M11 and M12 are configured to receive second differential phase control signals V. ctp, or V ctn to receive. As discussed below, the differential control signals V ctp , V ctn The current control transistors M11 and M12 are used to selectively modulate the resistance of the control transistors M11 and M12. Therefore, they are operated to selectively change the effective trigger points of the lower and upper second-stage inverters 320 and 322 and to control the neutral zone in the third stage 210 during amplification of the residual signal V. RESP , V RESM is set up.

[0026] The lower and upper inverters 320, 322 of the second stage provide intermediate differential voltage signals VM1, VP1 to the third amplifier stage 210, which is the output stage of the residual amplifier 114. The third stage 210 contains first and second output transistors M16, M17, which are connected between the AVDD supply voltage terminal 216 and ground. The output transistors M16, M17 form a third-stage inverter 324, which amplifies the differential residual signals V RESP1G , V RESM1Gat output terminals 214. A first control transistor M15 is connected between the gate of the first output transistor M16 and ground, and a second control transistor M18 is connected between the gate of the second output transistor M17 and the AVDD supply voltage terminal 216. The gate of the first control transistor M15 is configured to receive the first phase control signal phi1, while the second gate control transistor M18 is configured to receive the complement of the first phase control signal phi1z.

[0027] As mentioned previously, the lower and upper inverters 320, 322 of the second stage of the second amplifier stage 208 provide intermediate differential voltage signals VM1, VP1 to the third amplifier stage 210. The second amplifier stage 208 in Fig. The example shown in Figure 8 simply contains the lower and upper inverters 320 and 322 connected between the supply voltage input terminal 216 and ground. Therefore, the second stage 208 operates at a very high gain – the intermediate differential voltage signals VP1 and VM1 may tend to move towards the supply voltage level and ground. This could result in unstable operation.

[0028] To stabilize the operation of the residual amplifier 114, the second stage 208 is set up to create a neutral zone in the third stage 210. In particular, the second-stage differential control signals V ctp , V ctn The current control transistors M11 and M12 of the second stage receive the signal to selectively disconnect the upper inverter 322 and the lower inverter 320 of the second stage from the AVDD supply voltage terminal 216 and ground, respectively. This in turn disconnects the second and first output transistors M17 and M16, respectively.

[0029] Fig. 9 and Fig. 10 illustrative examples of control circuits for providing the differential control signals V ctp , V ctn second stage, which are received by the current control transistors M11, M12 of the second stage 208 of the residual amplifier 114. The in Fig. 9 shown V ctp Control circuit 300 contains transistors M32 and M31, which are connected between a Vdd voltage terminal and ground. Transistor M31 is configured to receive the second phase control signal phi2, and transistor M32 is configured to receive the complement of the first phase control signal phi1z. A node 302 is formed at the junction of transistors M32 and M31, which is connected to an output terminal 304 for outputting the control signal V. ctp is connected. A capacitor 310 is further connected between node 302 and ground. A resistor 306 is connected between a reference voltage V refp_dzand connected to a switch 308. The switch 308 is operated in response to the third phase control signal phi3, a portion of the reference voltage V. refp_dz to selectively connect to node 302.

[0030] In some examples, the Vdd voltage is lower than the AVDD voltage connected to the supply voltage terminal 216 of the residual amplifier 114. For example, in some embodiments the AVDD voltage may be 0.8 volts and the corresponding Vdd voltage level may be 0.75 volts. The reference voltages V refp_dz and V refn_dz are set at a level of approximately half the Vdd voltage level. In the illustrated example, V refp_dz 0.4 volts and V refn_dz is 0.3 volts.

[0031] The in Fig. 10 V shown ctnControl circuit 330 contains transistors M30 and M29, which are connected between the Vdd terminal and ground. Transistor M29 is configured to receive the first phase control signal phi1, and transistor M30 is configured to receive the complement of the second phase control signal phi2z. A node 332 is formed at the junction of transistors M30 and M29, which is connected to an output terminal 344 for outputting the control signal V. ctn is connected. A capacitor 340 is further connected between node 332 and ground, and a negative reference voltage V is applied. refn_dz is connected to node 332 via a resistor 336 and a switch 338. The switch 338 is operated in response to the third phase control signal phi3.

[0032] Fig. Figure 11 shows examples of different waveforms that affect the operation of the V ctp and V ctn Control circuits 300, 330 from Fig. 9 and Fig. 10 illustrate. Fig. Figure 11 illustrates example signals for the first, second and third control phases phi1, phi2, phi3, as well as the reference input signals V refp_dz , V refn_dz and control output signals V ctp , V ctn for the control circuits 300, 330 from Fig. 9 and Fig. 10. Fig. 11 further illustrates a signal V ctp -V ctn , which is the difference between the control signals V ctp and V ctn shows.

[0033] During the first operating phase, the first phase control signal phi1 is high, while the second and third phase control signals phi2 and phi3 are low. Therefore, during the first control phase, the phi1z, phi2, and phi3 control signals are all low, while the phi2 and phi2z signals are both high. The low phi3 signal opens switches 308 and 338, which sets the reference voltages V refp_dz and V refn_dz from their corresponding nodes 302 and 226. With regard to Fig. 9. The low phi2 signal switches off the NMOS transistor M31, and the low phi1z signal switches on the PMOS transistor M32, which connects node 302 to the Vdd terminal and the V ctp The control signal charges to almost the Vdd voltage level. Now, regarding Fig. 10. The high phi2z signal switches off the PMOS transistor M30, which disconnects node 330 from the Vdd voltage terminal. The high phi1 signal switches on the NMOS transistor M29, which connects node 330 to ground and the V ctn Signal at output port 334 is low.

[0034] Back to Fig. 8 becomes the low control signal V ctn The gate of the current-control NMOS transistor M12 of the upper inverter 322 receives the high control signal V. ctp The low control signal V is received at the gate of the PMOS current control transistor M11 of the lower inverter 320. ctnThis switches off transistor M12 and disconnects the upper inverter 320 of the second stage 208 from ground. The high control signal V ctp Switches off transistor M11 and cuts off the lower inverter 320 of the second stage 208 from the AVDD connector 216, which cuts off the first amplifier stage 208 from the third amplifier stage 212.

[0035] The high first phase control signal phi1 and its low complement signal phi1z, which are received at the respective gates of the control transistors M15 and M18, switch these control transistors on, which in turn switches off the output transistors M16 and M17 of the third amplifier stage 210.

[0036] In relation to Fig. 9 and Fig. During the second operating phase, the second phase control signal phi2 is high, while the first and third phase control signals phi1 and phi3 are low. Switches 308 and 338 remain open based on the low phi3 signal, which determines the reference voltages V. refp_dz and V refn_dz from their corresponding nodes 302 and 336. With regard to Fig. 9. The high phi2 signal switches the NMOS transistor M31 on, and the high phi1z signal switches the PMOS transistor M32 off, which connects node 302 to the ground terminal and the V ctp low pulls. In relation to Fig. 10 the phi1 signal switches off the NMOS transistor M29 and the low phi2z signal switches on the PMOS transistor M30, which connects node 330 to the Vdd voltage terminal.

[0037] The low V ctpThe signal received at the gate of transistor M11 of the lower inverter 320 switches on the PMOS transistor M11, which connects the lower inverter 320 to the AVDD power supply terminal 216. The high V ctnThe signal received at the gate of transistor M12 of the upper inverter 322 switches on the NMOS transistor M12, which connects the upper inverter 322 to ground. The upper and lower inverters 322 and 320 are therefore each connected between the AVDD supply terminal 216 and ground. As mentioned earlier, the phi1 signal is low during the second control phase, and its complement phi1z is high. The high phi1z signal received at the gate of the second control transistor M18 switches transistor M18 off, while the low phi1 signal received at the gate of the first control transistor M15 switches transistor M15 off. Therefore, the output transistors M16 and M17 of the third amplifier stage 210 are coupled between the AVDD power supply terminal 216 and ground, and the residual amplifier 114 is automatically zeroed out during the second control phase.

[0038] During the third operating phase, the first and second phase control signals phi1 and phi2 are both low. The first and second complement phase control signals phi1z and phi2z are therefore both high. These signals cause transistors M29, M30, M31, and M32 to all turn off. The third phase control signal phi3 goes high, which closes switches 308 and 338 to set the reference voltages V refp_dz and V refn_dz to connect to their corresponding nodes 302 and 336. Accordingly, the control signals V oscillate. ctp and V ctn at the V refp_dz and V refn_dz Voltage levels, which previously mentioned are approximately at the midpoint between ground and Vdd. The V ctp -V ctn The waveform in FIG. shows this intermediate control signal level more clearly. The control signals V ctp and V ctn at the V refp_dz and V refn_dzVoltage levels are applied to the gates of the second-stage current control transistors M11 and M12, respectively, as shown in Fig. Figure 8 shows this. This changes the effective tripping point of the second-stage inverters 320 and 322, pulling the intermediate voltages VM1 and VP1 away from the AVDD and ground rail voltages to a stable range.

[0039] By using multiple inverter-based stages, lower voltage requirements are needed because the inverter-based stages allow for nearly a rail-to-rail output span. Also, since the slew rate current of an inverter behaves like a digitally switched current source, the inverter-based stages provide a highly dynamic charging current. Additionally, as the process scale decreases, the operating performance of the residual amplifier 114 improves because the time delay of the inverters decreases with size. Therefore, the conversion rate of the inverter-based gain improves with process scaling. Furthermore, less power is consumed because power consumption is reduced by dynamic current control signals V. ctn , V ctp The values ​​are determined and applied to transistors M12 and M11 of the second amplifier stage 208.

[0040] As mentioned previously, the amplified residual signal V RES1Goutput to one or more subsequent ADC stages. In the Fig. In the second example shown, there are second and third ADC stages 116 and 120. Other embodiments could contain more or fewer ADC stages. The amplified first residual signal V MSP1G is received by the second ADC stage 116, which performs the A / D conversion of the amplified residual signal V RES1G executes and the second digital signal D2, as well as the second residual signal V RESP2 , V RESM2 outputs. The second residual amplifier 118, which, as in Fig. As shown in section 8, the amplified second residual signal V is set up and operated. RES2G from which the signal is received by the third ADC stage 120. The third ADC stage 120 performs the A / D conversion of the second residual differential signal V. RESP2 , V RESM2 to output the third digital signal D3, which represents the LSBs of the digital output signal D OUT represents.

[0041] Fig. Figure 12 illustrates an exemplary implementation of the second and third ADC stages 116, 120 in accordance with some embodiments. In particular, in the illustrated embodiment, the second and third ADC stages 116, 120 each contain a SAR ADC. The SAR ADCs of the second and third ADC stages 116, 120 include a tracking and holding circuit 430, a comparator 434, and a SAR logic block 432. The SAR logic 432 receives the clock signal CLKS and outputs pulsed control signals φ. ADC2 (Control signals of the second ADC stage) and φ ADC3 (Control signals of the third ADC stage) are provided to the tracking and holding circuit 430. The control signals φ ADC2 , φ ADC3 are derived from the complement of the third phase control signal phi3, since the second and third ADC stages use the amplified residual signals V RES1G , V RES2G Scan during the third operating phase.

[0042] The control signals φ ADC2 , φADC3 The second and third stages control the operation of a plurality of switches 450, which are operationally connected to one side of a plurality of capacitors Co-CM. There are two sets of capacitors 452a and 452b, corresponding to the analog differential residual signals V. RESP1G , V RESM1G and V RESP2G , V RESM2G Each of the sets of capacitors 452a, 452b contains a plurality of capacitors Co-CM, where M can correspond to the number of bits to be converted, which in the illustrated example corresponds to the 5 bits of the D2 signal and 8 bits of the D3 signal. In some examples, the capacitors C1-CM can be binary weighted and the capacitor Co is a "dummy LSB" capacitor.

[0043] The control signals φ ADC2 , φ ADC3Switches 450 control the capacitors 152a and 152b to connect an analog input voltage rail 458 to ground. The third phase control signal, phi3, further controls switches 454 to selectively switch the analog input voltage rail 458 between the analog residual signals V. RESP1G , V RESM1G or V RESP2G , V RESM2G and the reference voltage V ref to connect. The third phase control signal phi3 further controls switch 456, selectively controlling the other side of capacitors Co-CM with the common-mode feedback signal V. CM to connect.

[0044] When the third phase control signal phi3 is high, switches 450 operate to connect the cover plates of capacitors Co-CM of the sets of capacitors 452a, 452b to the analog residual signals V RESP1G , V RESM1G or V RESP2G , V RESM2Gto connect. The high phi3 signal further operates the switches 456 to connect the base plates of capacitors Co-CM of the sets of capacitors 452a, 452b with the common-mode feedback voltage signal V. CM to connect the analog residual signal V RESP1G , V RESM1G or V RESP2G , V RESM2G to sample. The second and third SAR control signals φ ADC2 , φ ADC3 Each contains a series of pulses that control the SAR binary search algorithm and generate the second and third digital output signals D2, D3.

[0045] Fig. Figure 13 is a flowchart illustrating an ADC 500 process in accordance with aspects of the present disclosure. With regard to Fig. 13 together with Fig. 1 and Fig.In operation 510, an analog input voltage signal VIN is sampled during a first operating phase 10. In operation 512, the inverter-based residual amplifier 114 is deactivated during the first operating phase 10. The analog input voltage signal VIN is converted to a first digital value D1 corresponding to the analog input voltage signal VIN during a second operating phase 20 in operation 514. In operation 516, a first analog residual signal VRES1 is determined corresponding to a difference between the first digital value D1 and the analog input signal VIN during the second operating phase 20. The first analog residual signal VRES1 is amplified by the inverter-based residual amplifier 114 during a third operating phase 10 in operation 518. In operation 520, the amplified first analog residual signal V RES1G to a second digital value D2 corresponding to the amplified first analog residual signal V RES1Gconverted and the first and second digital values ​​D1, D2 are combined to form a digital output signal DOUT, which represents the analog input voltage signal in operation 522.

[0046] Accordingly, the present disclosure includes examples of a multi-stage hybrid ADC with inverter-based residual amplifiers connecting the ADC stages. In accordance with some disclosed examples, the residual amplifier is a complete three-stage differential residual amplifier. The first stage is a differential input pair. The second stage embeds a neutral zone between the paths that drive the output transistors of the third amplifier stage. The third stage operates at sub-threshold operating levels, ensuring a high output impedance to form a dominant pole for stable feedback operation. Furthermore, disclosed examples are accessible for implementation in advanced low-voltage deep submicron process technologies.

[0047] In accordance with some embodiments, an ADC system includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and configured to output a first digital value corresponding to the analog input voltage signal and a first analog residual signal corresponding to a difference between the first digital value and the analog input signal. A first inverter-based residual amplifier is configured to receive the first analog residual signal, amplify the first analog residual signal, and output a first amplified residual signal.A second ADC stage is configured to receive the first amplified residual signal and output a second digital value corresponding to the first amplified analog residual signal, and a second analog residual signal corresponding to the difference between the second digital value and the first amplified analog residual signal. A second inverter-based residual amplifier is configured to receive the second analog residual signal, amplify the second analog residual signal, and output a second amplified residual signal. A third ADC stage is configured to receive the second amplified residual signal and output a third digital value corresponding to the second amplified analog residual signal. A control unit is coupled to the first, second, and third ADC stages and configured to combine the first, second, and third digital values ​​into a digital output signal that represents the analog input voltage signal.

[0048] In accordance with further disclosed examples, an ADC includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residual signal corresponding to a difference between the first digital value and the analog input signal. A first inverter-based residual amplifier is configured to receive the first analog residual signal, amplify the first analog residual signal, and output a first amplified residual signal. In some embodiments, the first inverter-based residual amplifier includes a first amplifier stage having an input inverter coupled between the first and second voltage terminals. The first-stage inverter is configured to receive the first analog residual signal.A second amplifier stage comprises first and second inverters coupled between the first and second voltage terminals and configured to receive an output from the first amplifier stage. Accordingly, first and second control devices are configured to control the current flow through the first and second inverters in response to a control signal. A third amplifier stage includes an output inverter coupled between the first and second voltage terminals and configured to receive an output from the second amplifier stage. A control circuit is coupled to the first and second control devices and is configured to generate the control signal.

[0049] In accordance with other examples, an ADC method involves sampling an analog input voltage signal during a first operating phase and disabling an inverter-based residual amplifier during this same phase. The analog input voltage signal is converted to a first digital value corresponding to the analog input voltage signal during a second operating phase. A first analog residual signal corresponding to the difference between the first digital value and the analog input signal is determined during the second operating phase. The first analog residual signal is amplified by the inverter-based residual amplifier during a third operating phase.The amplified first analog residual signal is converted to a second digital value corresponding to the amplified first analog residual signal, and the first and second digital values ​​are combined into a digital output signal that represents the analog input voltage signal.

[0050] The foregoing describes features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can already use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments presented herein. Those skilled in the art should also understand that such equivalent designs do not deviate from the nature and scope of the present disclosure and that they can make various changes, substitutions, and deviations therein without deviating from the nature and scope of the present disclosure.

Claims

[1] Analog-to-digital converter (100), ADC, comprising: an input terminal (102) configured to receive an analog input voltage signal (VIN); a first ADC stage (108) coupled to the input terminal (102) and configured to output a first digital value (D1) corresponding to the analog input voltage signal (VIN) and a first analog residual signal (VRES1) corresponding to a difference between the first digital value (D1) and the analog input signal (VIN); a first inverter-based residual amplifier (114) configured to receive the first analog residual signal (VRES1), amplify the first analog residual signal (VRES1), and output a first amplified residual signal (VRES1G); a second ADC stage (116) configured to receive the first amplified residual signal (VRES1G) and output a second digital value (D2) corresponding to the first amplified analog residual signal (VRES1G) and output a second analog residual signal (VRES2) corresponding to a difference between the second digital value (D2) and the first amplified analog residual signal (VRES1G); a second inverter-based residual amplifier (118) configured to receive the second analog residual signal (VRES2), amplify the second analog residual signal (VRES2), and output a second amplified residual signal (VRES2G); a third ADC stage (120) configured to receive the second amplified residual signal (VRES2G) and to output a third digital value (D3) corresponding to the second amplified analog residual signal (VRES2G); and a control unit (300, 330) coupled to the first ADC stage (108), the second ADC stage (116) and the third ADC stage (120) and configured to combine the first digital value (D1), the second digital value (D2) and the third digital value (D3) into a digital output signal (DOUT) representing the analog input voltage signal (VIN); wherein the first ADC stage (108) is configured to sample the analog input voltage signal (VIN) during a first operating phase (10, phi1), to convert the analog input voltage signal (VIN) to the first digital value (D1) during a second operating phase (20, phi2), and to maintain the first analog residual signal (VRES1) during a third operating phase (30, phi3); wherein the first residual amplifier (114) is deactivated during the first operating phase (10, phi1), is reset during the second operating phase (20, phi2), and is configured to amplify the first analog residual signal (VRES1) during the third operating phase (30, phi3); and wherein the second ADC stage (116) is configured to sample the amplified first analog residual signal (VRES1) during the third operating phase (30, phi3) and to convert the analog input voltage signal (VIN) during the first operating phase (10, phi1), and to convert the amplified first analog residual signal (VRES1) during the first operating phase (10, phi1) and the second operating phase into the second digital value (D2). [2] The ADC (100) of claim 1, wherein the first ADC stage (108) comprises a successive approximation register, SAR ADC configured to convert the analog input voltage signal (VIN) into the first digital value (D1). [3] The ADC (100) of claim 2, wherein the SAR ADC (100) includes a sample and hold circuit (130) comprising an array of binary weighted capacitors (Co-CN) configured to sample the analog input voltage (VIN). [4] ADC (100) according to one of the preceding claims, wherein the first ADC stage (108) comprises a digital-to-analog converter, DAC, (110) configured to receive the first analog input voltage signal (VIN) and the first digital value (D1) and to output the first analog residual signal (VRES1). [5] The ADC (100) of any preceding claim, wherein the inverter-based amplifier (114) comprises a first amplifier stage (206) connected between a first voltage supply terminal and a ground terminal, the first amplifier stage (206) comprising: a first inverter (310, 311) having a residual input terminal configured to receive the analog residual signal; and an activation terminal configured to receive an activation signal to deactivate the residual amplifier during the first operating phase (10, phi1). [6] The ADC (100) of claim 5, wherein the inverter-based amplifier (114) comprises: a second amplifier stage (208) comprising a first inverter (310, 311) connected between the first power supply terminal and the ground terminal and receiving an output of the first amplifier stage (206), and a second inverter (320) connected between the first power supply terminal and the ground terminal and receiving the output of the first amplifier stage (206); a third amplifier stage (210) comprising an inverter connected between the first voltage supply terminal and the ground terminal and receiving an output of the second amplifier stage (208); wherein the second amplifier stage (208) is arranged to selectively create a neutral zone in the third amplifier stage (210). [7] Analog-to-digital converter (100), ADC, comprising: an input terminal (102) configured to receive an analog input voltage signal (VIN); a first ADC stage (108) coupled to the input terminal (102) and configured to output a first digital value (D1) corresponding to the analog input voltage signal (VIN) and a first analog residual signal (VRES1) corresponding to a difference between the first digital value (D1) and the analog input signal (VIN); a first inverter-based residual amplifier (114) configured to receive the first analog residual signal (VRESP, VRESM, VRES1), amplify the first analog residual signal (VRESP, VRESM, VRES1), and output a first amplified residual signal (VRESP1G, VRESM1G, VRES1G), the first inverter-based residual amplifier (114) comprising: - a first amplifier stage (206) having an input inverter (310, 311) coupled between the first voltage terminal (216, Vdd) and the second voltage terminal, the first stage inverter (310, 311) being configured to receive the first analog residual signal (VRES1); - a second amplifier stage (208) comprising first and second inverters (320, 322) coupled between the first voltage terminal (216, Vdd) and the second voltage terminal and configured to receive an output of the first amplifier stage (206) and corresponding first and second control devices (M11, M12, M21, M22) configured to control control current flow through the first and second inverters (320, 322) in response to a control signal (Vctp, Vctn); - a third amplifier stage (210) having an output inverter (324) coupled between the first voltage terminal (216, Vdd) and the second voltage terminal and configured to receive an output of the second amplifier stage (208); and - a control circuit (300, 330) coupled to the first and second control devices (M11, M12, M21, M22) and configured to generate the control signal (Vctp, Vctn); wherein the second amplifier stage (208) is arranged to selectively create a neutral zone in the third amplifier stage (210). [8] The ADC (100) of claim 7, wherein the first control device (M11, M21) is connected between the first inverter (320) and the first voltage terminal (216, Vdd), and wherein the second control device (M12, M22) is connected between the second inverter (322) and the second voltage terminal. [9] The ADC (100) of claim 7 or 8, wherein the first control device (M11, M21) comprises a PMOS transistor, and the second control device (M12, M22) comprises an NMOS transistor, and wherein the first and second control devices (M11, M12, M21, M22) are operated in a triode region. [10] ADC (100) according to one of the preceding claims 7 to 9, wherein the control circuit (300, 330) is arranged to output the control signal (Vctp, Vctn) at a first voltage level during a first operating phase (10, phi1), a second voltage level during a second operating phase (20, phi2) and a third voltage level between the first and second voltage levels during a third operating phase (30, phi3). [11] The ADC (100) of any one of the preceding claims 7 to 10, wherein the output inverter (324) of the third amplifier stage (210) comprises a first transistor (M17, M27) and a second transistor (M16, M26) coupled between the first voltage terminal (216, Vdd) and the second voltage terminal, and wherein the third amplifier stage (210) includes first and second control devices (M18, M28, M15, M25) coupled to the respective one of the first transistor (M17, M27) and the second transistor (M16, M26) for selectively disconnecting the output inverter (324) from the first voltage supply terminal (216, Vdd) and the second voltage supply terminal. [12] The ADC (100) of claim 11, wherein the first amplifier stage (206) includes an enable transistor (Mo) configured to selectively enable or disable the first amplifier (114), and wherein the first control device (M18, M28) and the second control device (M15, M25) of the output inverter (324) and the enable transistor (Mo) are controlled in response to a first operating phase control signal (phi1). [13] ADC (100) according to one of the preceding claims 7 to 12, further comprising a second ADC stage (116) configured to receive the first amplified residual signal (VRESP1G, VRESM1G, VRES1G) and to convert the first amplified residual signal (VRESP1G, VRESM1G, VRES1G) into a second digital value (D2). [14] Method (500) comprising: Sampling (510) an analog input voltage signal (VIN) during a first operating phase (10, phi1); Deactivating (512) an inverter-based residual amplifier (114) during the first operating phase (10, phi1); Converting (514) the analog input voltage signal (VIN) into a first digital value (D1) corresponding to the analog input voltage signal (VIN) during a second operating phase (20, phi2); Determining (516) a first analog residual signal (VRES1) corresponding to a difference between the first digital value (D1) and the analog input signal (VIN) during the second operating phase (20, phi2); Amplifying (518) the first analog residual signal (VRES1) by the inverter-based residual amplifier (114) during a third operating phase (30, phi3); Converting (520) the amplified first analog residual signal (VRES1G) into a second digital value (D2) corresponding to the amplified first analog residual signal (VRES1G); and Combining (522) the first digital value (D1) and the second digital value (D2) to form a digital output signal (DOUT) representing the analog input voltage signal (VIN); wherein the inverter-based residual amplifier (114) comprises a first amplifier stage (206), a second amplifier stage (208), and a third amplifier stage (210), and wherein the method (500) further comprises selectively creating a neutral zone in the third stage (210). [15] The method (500) of claim 14, wherein the second amplifier stage (208) comprises a control transistor (M11, M12, M21, M22) operated in a triode region, and wherein the method (500) further comprises generating a control signal (Vetp, Vctn) for the control transistor (M11, M12, M21, M22), the control signal (Vctp, Vctn) having a first voltage level during the first operating phase (10, phi1), a second voltage level during the second operating phase (20, phi2), and a third voltage level between the first and second voltage levels during the third operating phase (30, phi3).

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