Semiconductor circuit and distance measuring device

Abstract

A semiconductor circuit (1) comprising: an oscillator (2) configured to output an oscillation signal whose frequency depends on a first input signal; a counter (3, 3a) configured to count a number of cycles of the oscillation signal; a first circuit (4, 4a) configured to output a first digital signal based on a first number of cycles counted by the counter (3, 3a) within one clock cycle of a clock signal (CLK), wherein the first input signal is digitally converted into the first digital signal; a second circuit (5, 5a) configured to output a second digital signal based on a second number of cycles counted by the counter (3, 3a) in one period from a reference time of the clock signal (CLK) to an input time of a second input signal within one clock cycle of the clock signal (CLK), the period being digitally converted into the second digital signal; and a computer (7) configured to measure, based on the first digital signal and the second digital signal, a time from when a light signal is emitted until the time when a reflected light signal is received, obtained by the light signal reflected from an object, and to calculate a distance to the object based on the time, wherein the computer (7) is further configured to calculate the distance based on a value obtained by adding the number of clock cycles of the clock signal (CLK) in the period from the input start time of the first input signal to the input time of the second input signal to a value obtained by dividing the second digital signal by the first digital signal.

Description

AREA

[0001] Embodiments of the present disclosure relate to a semiconductor circuit and a distance measuring device. BACKGROUND

[0002] Research and development in the field of autonomous driving technology is underway. In autonomous driving technology, it is necessary to measure the distance between a vehicle and surrounding objects with high accuracy. This distance measurement is achieved by measuring the time interval between the emission of a light signal from a vehicle and the reception of a reflected light signal from an object. Generally, this time interval is roughly measured by an analog-to-digital converter (ADC) and then measured with high precision by a time-to-digital converter (TDC).

[0003] Conventionally, an ADC and a TDC for a distance measuring device have different functions and are therefore configured by separate circuits, whereby a mounting area becomes large when these circuits are mounted on the same chip, leading to an increase in power consumption.

[0004] US 2011 / 0 148 676 A1 discloses a digital phase-locked loop with dithering, while US 2017 / 0 234 985 A1 concerns methods and devices for time-of-flight imaging, and US 2018 / 0 306 926 A1 concerns a lidar detector with a plurality of time-to-digital converters integrated on a detector chip. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram representing a schematic configuration of a semiconductor circuit according to a first embodiment; Fig. 2 is a waveform diagram illustrating the operation of the semiconductor circuit of Fig. 1 illustrates; Fig. 3 is a block diagram illustrating a schematic configuration of the semiconductor circuit, in which a comparator and a calculator are located in the semiconductor circuit of Fig. 1 are provided; Fig. 4 is a diagram that represents a relationship between a start signal and a first input signal; Fig. Figure 5 is a waveform diagram illustrating an exemplary light signal emitted by a light source and a reflected light signal; Fig. Figure 6 is a diagram illustrating a method for measuring time corresponding to distance, in the case where a second input signal is present at time ttrg. Fig. 2 passes; Fig. Figure 7 is a block diagram representing a schematic configuration of a semiconductor circuit according to a second embodiment; Fig. Figure 8 is a circuit diagram representing an exemplary voltage-controlled oscillator (VCO); Fig. Figure 9 is a block diagram illustrating an internal configuration of a first phase sensor; Fig. 10 is a signal waveform diagram illustrating the input / output timing of the semiconductor circuit according to the second embodiment; Fig. 11 is a diagram illustrating how an interpolation unit works; Fig. Figure 12 is a block diagram showing a schematic configuration of a distance measuring device 20 with a semiconductor circuit according to a third embodiment; Fig. 13 is a block diagram representing a schematic configuration of a semiconductor circuit according to a fourth embodiment; Fig. 14 is a waveform diagram illustrating an example in which an oscillation frequency changes within a clock cycle; Fig. 15 is a block diagram representing a schematic configuration of a semiconductor circuit according to a fifth embodiment; Fig. 16 is a signal waveform diagram illustrating the input / output times of the semiconductor circuit according to the fifth embodiment; Fig. 17 is a block diagram that shows a schematic configuration of a semiconductor circuit according to a variation of Fig. 15 represents; and Fig. Figure 18 is a block diagram representing a schematic configuration of a semiconductor circuit according to a sixth embodiment. DETAILED DESCRIPTION

[0005] The present invention is defined by the independent claims. Preferred embodiments are defined in the dependent claims. Further aspects are given for a better understanding of the invention.

[0006] The embodiments of the present disclosure are described below with reference to the accompanying drawings. While the following embodiments mainly describe characteristic configurations and operations in a semiconductor circuit and a distance measuring device, there may be configurations and operations that are omitted from the following description. (First embodiment)

[0007] Fig. Figure 1 is a block diagram representing a schematic configuration of a semiconductor circuit 1 according to a first embodiment. The semiconductor circuit 1 of Fig. Figure 1 shows a circuit configuration to be mounted on the same semiconductor substrate. Semiconductor circuit 1 of Fig. 1 includes an oscillator 2, a cycle counter 3, a first arithmetic unit (first circuit) 4 and a second arithmetic unit (second circuit) 5. In this specification, the first arithmetic unit 4 and the second arithmetic unit 5 are collectively referred to as arithmetic unit 10.

[0008] Oscillator 2 outputs an oscillation signal whose frequency is modulated according to a first input signal. Oscillator 2 is, for example, a voltage-controlled oscillator (hereinafter referred to as VCO 2). VCO 2 outputs an oscillation signal whose frequency is modulated according to the signal level of the first input signal.

[0009] The cycle counter 3 measures the number of cycles of the oscillation signal. More precisely, the cycle counter 3 measures the number of cycles of the oscillation signal contained in one clock cycle for each clock cycle of a clock signal CLK. The clock signal CLK is a signal that is asynchronous to the oscillation signal of VCO 2. The cycle of the oscillation signal of VCO 2 fluctuates, while the clock cycles of the clock signals CLK are constant.

[0010] The first processing unit 4 outputs a first digital signal in the first clock cycle of the clock signal CLK. This signal is derived from the first digitally converted input signal, based on the first number of cycles measured by the cycle counter 3. In other words, the first processing unit 4 outputs the first digital signal based on the first number of cycles counted by the cycle counter 3 within one of the clock cycles of the clock signal, where the first input signal is digitally converted into the first digital signal. The first digital signal is a signal derived from the oscillation frequency of VCO 2, which is digitally converted for each clock cycle. Since the oscillation frequency of VCO 2 depends on the signal level of the first input signal, the first digital signal is a signal derived from the first digitally converted input signal.

[0011] The cycle count measuring instrument 3 includes, for example, a counter 3a. Counter 3a counts the number of cycles of the oscillation signal contained in each clock cycle. Counter 3a resets its count value at the point in time when the clock signal CLK transitions. The point in time when the clock signal CLK transitions is, for example, the point in time when the clock signal CLK changes from low to high.

[0012] The first processing unit 4 includes, for example, a flip-flop (hereinafter referred to as FF) 4a. The FF 4a holds the counter value of the counter 3a at the time of the transition of the clock signal CLK. The signal held by the FF 4a is intended to be the first digital signal. In this way, the cycle count meter 3 and the first processing unit 4 function as an analog-to-digital converter (hereinafter referred to as ADC).

[0013] The second processing unit 5 outputs a second digital signal based on the second number of cycles measured by the cycle counter 3 within a period from the reference time of the clock signal until the transition of the second input signal. That is, the second processing unit 5 outputs the second digital signal based on the second number of cycles counted by the cycle counter 3 within a period from a reference time of the clock signal until the arrival of the second input signal within one clock cycle of the clock signal, with the period being digitally converted into the second digital signal. The second processing unit 5 includes, for example, a flip-flop 5a. The flip-flop 5a holds the count value of the counter 3a at the time of the transition of the second input signal. The signal held by the flip-flop 5a is the second digital signal.In this way, the cycle count measuring instrument 3 and the second computing unit 5 function as a time-to-digital converter (hereinafter referred to as TDC).

[0014] As described above, the semiconductor circuit 1 of Fig. Figure 1 presents a circuit configuration that integrates the oscillator 2, the ADC, and the TDC. In particular, since the oscillator 2 and the counter 3a are shared by the ADC and the TDC, the ADC and the TDC do not need to contain the oscillator 2 and the counter 3a separately, thus reducing circuit size and power consumption.

[0015] Fig. 2 is a waveform diagram that illustrates the operation of semiconductor circuit 1 of Fig. Figure 1 illustrates a waveform of the oscillation signal of VCO 2. The oscillation frequency of the VCO 2 signal changes depending on the signal level of the first input signal. Each section, represented by dashed lines in Fig. Divided by 2, each clock cycle of the clock signal CLK is... Although Fig. 2 illustrates an exemplary case where, for the sake of simplicity, the oscillation frequency of the VCO 2 oscillation signal changes every clock cycle; in reality, the oscillation frequency of the VCO 2 oscillation signal can change within a clock cycle.

[0016] In the example of Fig. Counter 3a counts the values ​​4, 4, 6, 9, 9, 9, and 5 for the clock cycles t1 to t2, t2 to t3, t3 to t4, t4 to t5, t5 to t6, and t6 to t7, respectively. The respective count values ​​are held in flip-flop 4a at times t2, t3, t4, t5, t6, and t7. Therefore, the first digital signal changes in the sequence 4, 4, 6, 9, 9, 9, and 5 in each clock cycle.

[0017] Assuming that the second input signal transitions between times t4 and t5 at time ttrg, the FF 4a holds the count value of counter 3a at time ttrg. The count value in this case is 4, and therefore the second digital signal is 4.

[0018] Fig. Figure 3 is a block diagram illustrating a schematic configuration of semiconductor circuit 1, in which a comparator 6 and a calculator 7 are located in semiconductor circuit 1. Fig. 1 are planned.

[0019] Comparator 6 generates a second input signal by comparing the physical value of the first input signal to a reference value. The physical value relates to the power, envelope, frequency, integral, pulse width, or similar characteristic of the first input signal, and its specific content is not limited as long as it is a physical value capable of quantitatively evaluating the properties of the first input signal. Comparator 6 causes the second input signal to transition when, for example, the physical value exceeds a reference quantity. In a case where the physical value is the signal level, comparator 6 causes the second input signal to transition when the signal level of the first input signal exceeds a predetermined threshold. For example, causing the second input signal to transition means that the second input signal changes from low to high.In this way, the second input signal acts as a trigger signal and the comparator 6 as a trigger generation unit.

[0020] Based on the first digital signal and the second digital signal, computer 7 measures the time from the emission of a light signal to the reception of a reflected light signal, which is obtained from the light signal reflected by an object, and calculates a distance to the object base from the measured time.

[0021] Fig. Figure 4 is a diagram that illustrates the relationship between a start signal and the first input signal. A light signal, such as a laser beam, is emitted by a light source 22 according to the timing of the start signal, and a reflected light signal from an object, such as a vehicle, is applied to a light detector 23, such as a light receiving sensor, which is converted into a first input signal, which is an electrical signal.

[0022] Fig. Figure 5 is a waveform diagram illustrating an example of the light signal emitted by the light source 22 and the reflected light signal. The reflected light signal is received by the light detector 23 along with ambient light, such as sunlight. Because the propagation distance of the reflected light signal is longer, its intensity is weaker and difficult to distinguish from the ambient light. Fig. 5 is the reflected light signal in bold.

[0023] Comparator 6 causes the second input signal to pass through if, for example, the signal level of the first input signal exceeds a predefined threshold. Computer 7 measures the time from the moment of the start signal until the time the reflected light signal is received, converted back into the first input signal, and fed into oscillator 2, and converts this time into a distance.

[0024] Fig. Figure 6 is a diagram illustrating a method for measuring a time-of-flight (ToF) corresponding to a distance when the second input signal is received at time ttrg in Fig. 2 transitions. Time t1 is the time of the start signal. The first digital signal output by the first processing unit 4 during the clock cycle from time t4 to t5 is 9, the second digital signal output by the second processing unit 5 is 4, and since there are three clock cycles from time t1 to t4, the computer 7 measures the time ToF from the time of the start signal to the transition time of the second input signal as 3 + (4 / 9) and calculates a distance from the speed of light from the time ToF.

[0025] As described above, in the first embodiment the oscillator 2 and the counter 3a are shared by the first computing unit 4, which functions as an ADC, and the second computing unit 5, which functions as a TDC, so that the ADC and the TDC do not need to include a dedicated oscillator 2 and counter 3a, thereby reducing circuit size and power consumption. (Second embodiment)

[0026] A second embodiment is a more specific version of the configuration of the semiconductor circuit 1 according to the first embodiment.

[0027] Fig. Figure 7 is a block diagram representing a schematic configuration of a semiconductor circuit 1 according to the second embodiment. The semiconductor circuit 1 of Fig. 7 includes an oscillator 2, a first phase sensor 11, a second phase sensor 12, a third phase sensor 13, a first arithmetic unit 4 and a second arithmetic unit 5. The first arithmetic unit 4 and the second arithmetic unit 5 are contained in an arithmetic unit 10.

[0028] Oscillator 2 outputs an oscillation signal whose frequency is modulated according to a first input signal. Oscillator 2 is, for example, a VCO 2. Fig. Figure 8 is a circuit diagram that illustrates an example of the VCO 2. The VCO 2 of Fig. Component 8 includes a ring oscillator 14 and a P-channel metal-oxide-semiconductor (PMOS) transistor 15. The ring oscillator 14 is configured such that several variable delay inverters 14a, which can control a delay time, are connected in a ring. The PMOS transistor 15 supplies the supply voltage to the plurality of variable delay inverters 14a according to a signal level of the first input signal. Each variable delay inverter 14a switches a signal propagation delay corresponding to the voltage level of the supply. When the signal propagation delay of each variable delay inverter 14a changes, an oscillation frequency of the ring oscillator 14 also changes. Accordingly, the VCO 2 of Fig. 8 the oscillation frequency basis on the signal level of the first input signal, for example the voltage or current level.

[0029] The first phase sensor 11 outputs a digital phase signal DPA, obtained by sampling the phase of the VCO 2 oscillation signal for each cycle of a clock signal CLK. The second phase sensor 12 outputs a second digital phase signal DPT, obtained by sampling the phase of the VCO 2 oscillation signal at the time a second input signal transitions. That is, the second phase sensor 12 outputs the digital signal of the second phase based on sampling the phase of the oscillation signal at the input time of the second input signal. The third phase sensor 13 outputs a third digital phase signal, obtained by sampling the phase of the clock signal CLK at the time the second input signal transitions. That is, the third phase sensor 13 outputs the digital signal of the third phase based on sampling the phase of the clock signal at the input time of the second input signal.

[0030] The first processing unit 4 outputs a first digital signal for each clock cycle of the clock signal CLK, which is obtained from the first digitally converted input signal based on the digital phase signal DPA. The first phase sensor 11 and the first processing unit 4 function as an ADC.

[0031] The second processing unit 5 outputs a second digital signal corresponding to one period until the second input signal transitions. That is, the second processing unit 5 outputs the second digital signal corresponding to the period until the second input signal is received. The first phase sensor 11, the second phase sensor 12, and the second processing unit 5 operate as a TDC (transistor-controlled digital converter).

[0032] Fig. Figure 9 is a block diagram illustrating an internal configuration of the first phase sensor 11. As shown in Fig. As shown in Figure 9, the first phase sampler 11 includes a counter 11a, a flip-flop 11b, a plurality of flip-flops 11c, an encoder 11d and an adder 11e.

[0033] Counter 11a, for example, is an up counter that counts upwards at the transition time of the VCO 2 oscillation signal. The transition time of the VCO 2 oscillation signal is, for example, the point at which the oscillation signal changes from low to high. FF 11b holds a count value of counter 11a for each clock cycle. The value held in FF 11b corresponds to an integer digital phase signal of the VCO 2 oscillation signal.

[0034] The multiple flip-flops (FFs) 11c keep the output signals of the multiple variable-delay inverters 14a in the ring oscillator 14 synchronized with the transition time of the clock signal CLK. The encoder 11d encodes the signal held by each FF 11c into a digital decimal phase signal and outputs it. With each output signal of every variable-delay inverter 14a in the ring oscillator 14 held at the transition time of the clock signal CLK, it becomes possible to obtain a digital phase signal with a higher resolution than that obtained from the oscillation signal of the VCO 2 measured by the counter 11a.

[0035] The adder 11e adds the integer digital phase signal held in the FF 11b and the digital decimal phase signal encoded by the encoder 11d to produce a first digital phase signal DPA.

[0036] The second phase sensor 12, for example, has a block configuration as described in Fig. Figure 9 shows the second input signal instead of the clock signal CLK. Fig. 9 is entered. In this case, the encoder 11d outputs a digital decimal phase signal of the oscillation signal of VCO 2 at the time of the transition of the second input signal.

[0037] Fig. Figure 10 is a signal waveform diagram representing the input / output time of the semiconductor circuit 1 according to the second embodiment. Time t1 is the time of the start signal. During the period between time t1 and time t2, the signal level of the first input signal is a predetermined base level. It should be noted that in Fig. 10. It is assumed that the first input signal contains no noise signals, such as ambient light. If the signal level of the first input signal is at the base level, VCO 2 oscillates at a fixed oscillation frequency that corresponds to the base level. Therefore, the count value of counter 3a increases linearly. The dashed lines in Fig. The 10 indicate the times at which the clock signal CLK transitions, and each interval between the dashed lines is a clock cycle.

[0038] The first phase sensor 11 outputs a digital phase signal DPA, which is obtained by digitizing the phase of the oscillation signal of the VCO 2 synchronously at the time of the transition of the clock signal CLK.

[0039] If the signal level of the first input signal changes from time t2 to t5, the oscillation frequency of the oscillation signal of VCO 2 changes according to the signal level. Fig. Figure 10 illustrates an exemplary case where the second input signal transitions at time t4. The second phase sensor 12 outputs a second digital phase signal DPT, which is obtained by digitizing the phase of the oscillation signal of VCO 2 synchronously with the transition time of the second input signal. The third phase sensor 13 outputs a third digital phase signal, which is obtained by digitizing the phase of the clock signal CLK synchronously with the transition time of the second input signal. The digital signal of the third phase represents an integer time of the clock signal CLK.

[0040] The first processing unit 4 outputs a first digital signal, which is obtained from the DPA output of the first digital phase signal from the first phase sensor 11, subject to time differentiation. The first digital signal is a signal obtained by digitizing the oscillation frequency of the VCO 2 oscillation signal for each clock cycle. Since the oscillation frequency of the VCO 2 oscillation signal depends on the first input signal, the first digital signal is also dependent on the first input signal. For example, the first digital signal is a signal obtained by digitizing the signal level of the first input signal.

[0041] The second processing unit 5 generates a second digital signal basis by processing the interpolation of two or more first digital phase signals DPA close to the second digital phase signal DPT and the third digital phase signal. More precisely, the second processing unit 5 obtains a fractional time corresponding to the second digital phase signal DPT by polynomial interpolation of the two or more digital phase signals DPA and determines an integer time basis on the third digital phase signal, thereby generating a second digital signal basis on the fractional time and the integer time.

[0042] The second processing unit 5 includes, for example, an interpolation unit 5a and an adder 5b. The interpolation unit 5a generates a fractional time signal based on the first digital phase signal DPA and the second digital phase signal DPT. The adder 5b adds the third digital phase signal, which is an integer time signal generated by the third phase sensor 13, and the fractional time signal generated by the interpolation unit 5a to produce a second digital signal. The second digital signal is a time-digital signal from the time of the start signal until the time of the transition of the second input signal.

[0043] Fig. Figure 11 is a graphic illustrating the operation of the interpolation unit 5a. Fig. Figure 11 is a diagram showing the first phase digital signals DPA with a horizontal axis representing time and a vertical axis representing the data values ​​of the first phase digital signal DPA and the second phase digital signal DPT. Three phase digital signals DPA[t1], DPA[t2], and DPA[t3] close to the phase digital signal DPT are recorded, and a quadratic interpolation curve is generated that passes through these three diagrams. The phase digital signal DPT is then placed on the quadratic interpolation curve to determine its timing. This determined time is the point at which the second input signal transitions, i.e., the trigger time.

[0044] The quadratic interpolation curve is expressed, for example, by the following formula (1). f(t)=at2+bt+c

[0045] The interpolation unit 5a, conversely, calculates the fractional time from the quadratic interpolation curve of formula (1) based on the following formula (2). fractional time=f−1(DPT)

[0046] It should be noted that, in addition to the quadratic polynomial interpolation described above, the interpolation unit 5a can perform any interpolation, such as Lagrange interpolation and Newton interpolation. The interpolation processing of the interpolation unit 5a can also be performed even if the oscillation frequency of VCO 2 changes, and fractional time can be measured with high accuracy.

[0047] As described above, the second computing unit 5 obtains the integer time by capturing the phase of the clock signal CLK with the transition time of the second input signal as a reference, and obtains the fractional time by capturing the phase of the oscillation signal of the VCO 2 with the transition time of the second input signal as a reference, thereby enabling a highly accurate time-to-digital conversion.

[0048] In this way, in the semiconductor circuit 1 according to the second embodiment, the VCO 2 and the first phase sampler 11 are shared by the first computing unit 4, which functions as an ADC, and the second computing unit 5, which functions as a TDC, thereby reducing circuit size and power consumption. (Third embodiment)

[0049] Fig. Figure 12 is a block diagram showing a schematic configuration of a distance measuring device 20 with a semiconductor circuit 1 according to a third embodiment. The distance measuring device 20 of Fig. 12 includes a control unit 21, a light source 22, a light detector 23, an analog front assembly (hereinafter referred to as AFE) 24 and a computer 25.

[0050] The control unit 21 controls the emission time of the light source 22. When the control unit 21 sends a start signal to the light source 22, the light source 22 emits a light signal. The light source 22 is a laser diode or a light-emitting device (LED). The light signal emitted by the light source 22 (hereinafter referred to as the first light signal) is scattered by an object 19 in a monitoring area, and the scattered light is applied to the distance measuring device 20. In addition to the light source 22, other ambient light, such as sunlight, is also applied to the distance measuring device 20 as direct light or reflected light from the object 19.

[0051] The light incident on the distance measuring device 20 is converted into an electrical signal by the light detector 23. The light detector 23 can, for example, include a photodiode, an avalanche photodiode, a single-photon avalanche photodiode, or the like. The light detector 23 receives a second light signal, which includes a reflected light signal received from the first light signal emitted by the light source 22 and reflected by the object 19, and converts it into a first input signal, which is an electrical signal.

[0052] The first input signal, an electrical signal converted by the light detector 23, is fed into the AFE unit 24, and the amplitude and time information of the electrical signal are converted into digital values. Here, the time information is the point in time at which the amplitude of the electrical signal exceeds a certain threshold, representing a time-of-flight (ToF) from the time the outgoing beam is emitted until the time the AFE unit 24 detects the scattered light via the light detector 23. The AFE unit 24 can be configured, for example, by the semiconductor circuit 1 according to the second embodiment. The AFE unit 24 outputs a first digital signal and a second digital signal representing the light reception time of the reflected light signal based on the first input signal.

[0053] Computer 25 measures the distance to object 19 by which the first light signal is reflected. More precisely, computer 25 measures the time from the moment of the start signal until the transition of a second input signal and, based on this time, measures a distance to object 19 (Base).

[0054] Each unit of the distance measuring device 20 from Fig. Component 12 can be mounted on a semiconductor substrate and processed into a chip. Alternatively, the light source 22 alone can be a separate chip, or the light source 22 and the light detector 23 can be separate chips.

[0055] In this way, in the third embodiment, the distance measuring device 20 can be configured using the semiconductor circuit 1 according to the second embodiment. (Fourth embodiment)

[0056] Fig. Figure 13 is a block diagram representing a schematic configuration of a semiconductor circuit 1 according to a fourth embodiment. The semiconductor circuit 1 of Fig. 13 includes, in addition to the configuration of semiconductor circuit 1 of Fig. 7 also includes a comparator 6. Based on a first input signal, the comparator 6 generates a second input signal. More precisely, the comparator 6 generates a second input signal by comparing the physical value of the first input signal with a predefined reference value. In a case where the physical value is the signal level, the comparator 6 can cause the second input signal to transition when the signal level of the first input signal exceeds a predefined reference level. In this way, the comparator 6 functions as a trigger generation unit, producing a second input signal that is a trigger signal.

[0057] To properly extract reflected light embedded in ambient light, comparator 6 sets a reference value and a reference level to detect a reflected light component present in the first input signal. When the reflected light component is detected, the second input signal is brought to a transition.

[0058] Semiconductor circuit 1 of Fig. 13 can be used for the AFE unit 24 in the distance measuring device 20 of Fig. 12 can be used.

[0059] In this way, in the fourth embodiment, the comparator 6 is provided and the second input signal is generated from the first input signal, whereby the reflected light of the object 19 can be adequately extracted from the light incident on the distance measuring device 20 in order to generate the second input signal. (Fifth embodiment)

[0060] An oscillation signal from VCO 2 is frequency-modulated according to a first input signal. Accordingly, as shown in Fig. Figure 14 shows that the oscillation frequency of the oscillation signal can change significantly within a single clock cycle. In particular, in a signal region corresponding to a reflected light component contained in the initial input signal, the signal amplitude can increase rapidly in a short time. In this case, the oscillation frequency of the VCO 2 signal increases rapidly, and immediately thereafter, the oscillation frequency decreases rapidly, resulting in oscillation frequency instability.

[0061] In the semiconductor circuit 1 according to the first to third embodiments described above, the accuracy of a complement process can be impaired by the input of an unstable oscillation signal. Therefore, a semiconductor circuit 1 according to a fifth embodiment is intended to take measures against an unstable oscillation signal.

[0062] Fig. Figure 15 is a block diagram representing a schematic configuration of the semiconductor circuit 1 according to the fifth embodiment, and Fig. Figure 16 is a signal waveform diagram representing the input / output timing of the semiconductor circuit 1 according to the fifth embodiment. The semiconductor circuit 1 of Fig. 15 includes, in addition to the configuration of semiconductor circuit 1 of Fig. 13 also a delay unit 26. The delay unit 26 delays a second input signal, output by a comparator 6, by a predetermined time. The predetermined time must be a time until the end of the signal range corresponding to the reflected light component contained in the first input signal. More precisely, the predetermined time is preferably a time until the oscillation frequency of the oscillation signal of the VCO 2 has stabilized after the end of the signal range including the reflected light component.

[0063] If the second input signal is delayed by the delay unit 26 by a predetermined time, the second signal transition (a trigger signal is output) is delayed at time t2 by a predetermined time from time t1, whereas originally the second signal was present at time t1. Fig. 16 transitions (a trigger signal is output). In the event that the oscillation signal is stable at time t2 without changing a frequency significantly within the clock cycle, a first phase sensor 11 and a second phase sensor 12 can generate a first digital phase signal DPA and a second digital phase signal DPT with high accuracy.

[0064] Fig. 17 is a block diagram showing a schematic configuration of a semiconductor circuit 1 according to a variation of Fig. 15 represents the semiconductor circuit 1 of Fig. 17 includes the delay unit 26, which was added to the front stage of VCO 2, as well as the semiconductor circuit 1 of Fig. 13. The delay unit 26 delays the first input signal by a predetermined time and then feeds it into the VCO 2. The VCO 2 outputs a frequency-modulated oscillation signal based on the delayed input signal, which is obtained from the first input signal being delayed for the predetermined time.

[0065] The comparator 6 generates a second input signal based on the original first input signal, which is not delayed. The first phase sensor 11 and the second phase sensor 12 output the first digital phase signal DPA and the second digital phase signal DPT based on the oscillation signal, which is subject to frequency modulation based on the delayed input signal. The digital phase signal DPA and the digital phase signal DPT are delayed by a predetermined time from the transition time of the second input signal. Thus, since the first digital phase signal DPA and the second digital phase signal DPT are generated based on the stabilized oscillation signal, analogous to Fig. 15 the first digital phase signal DPA and the second digital phase signal DPT are generated after the oscillation signal has been stabilized.

[0066] In the fifth embodiment, the delay unit 26 is provided to delay the second input signal generated by the comparator 6 by a predetermined time, or to delay the first input signal input to the VCO 2 by a predetermined time, wherein the first digital phase signal DPA and the second digital phase signal DPT can be generated by the first phase sampler 11 and the second phase sampler 12 after the oscillation frequency of the VCO 2 oscillation signal has stabilized. (Sixth embodiment)

[0067] Fig. Figure 18 is a block diagram representing a schematic configuration of a semiconductor circuit 1 according to a sixth embodiment. The semiconductor circuit 1 of Fig. 18 includes, in addition to the configuration of the semiconductor circuit 1 of Fig. Figure 7 comprises a digital-to-analog (DAC) converter 27, a differentiator 28, and a loop filter 29. The DAC 27 converts a DPA output of a first digital phase signal from a first phase sensor 11 into an analog phase signal. The differentiator 28 outputs a first input signal and a difference signal between an output signal of the DAC 27 and the first input signal. The loop filter 29 inputs a signal obtained from the difference signal, which is integrated into a VCO 2 in place of the first input signal. The loop filter 29 acts as an integrator.

[0068] In semiconductor circuit 1 of Fig. The VCO 2 and the first phase sensor 11 are contained in a delta-sigma analog-to-digital converter (ADC). The first digital phase signal (DPA) is fed back to the input side of the VCO 2 by the DAC 27 and the loop filter 29, which further reduces the quantization noise at the time of the ADC conversion.

[0069] It should be noted that the DAC 27 and the differentiator 28 are from Fig. 18 to the semiconductor circuit 1 of Fig. 15 or Fig. 17 can be added.

[0070] Although certain embodiments have been described, these embodiments are presented only as examples and are not intended to limit the scope of the inventions. In fact, the new methods and systems described herein can be embodied in a multitude of other forms; furthermore, various omissions, substitutions, and modifications to the form of the methods and systems described herein can be made without departing from the spirit of the inventions. The appended claims and their equivalents are intended to cover such forms or modifications that would fall within the scope and spirit of the inventions.

Claims

[1] A semiconductor circuit (1) comprising: an oscillator (2) configured to output an oscillation signal whose frequency depends on a first input signal; a counter (3, 3a) configured to count a number of cycles of the oscillation signal; a first circuit (4, 4a) configured to output a first digital signal based on a first number of cycles counted by the counter (3, 3a) within one clock cycle of a clock signal (CLK), wherein the first input signal is digitally converted into the first digital signal; a second circuit (5, 5a) configured to output a second digital signal based on a second number of cycles counted by the counter (3, 3a) in a period from a reference time of the clock signal (CLK) to an input time of a second input signal within one clock cycle of the clock signal (CLK), the period being digitally converted into the second digital signal; and a computer (7) configured to measure, based on the first digital signal and the second digital signal, a time from which a light signal is emitted to the time at which a reflected light signal obtained by the light signal reflected from an object is received, and to calculate a distance to the object based on the time, wherein the calculator (7) is further configured to calculate the distance based on a value obtained by adding the number of clock cycles of the clock signal (CLK) in the period from the input start time of the first input signal to the input time of the second input signal with a value obtained by dividing the second digital signal by the first digital signal. [2] The semiconductor circuit (1) according to claim 1, further comprising: a comparator (6) configured to generate the second input signal by comparing a value of the first input signal with a reference value. [3] A semiconductor circuit (1) comprising: an oscillator (2) configured to output an oscillation signal whose frequency depends on a first input signal; a first phase sampler (11) configured to output a digital signal of the first phase based on sampling a phase of the oscillation signal in one clock cycle of a clock signal (CLK); a second phase sampler (12) configured to output a second digital phase signal based on sampling the phase of the oscillation signal at an input timing of a second input signal; a third phase sampler (13) configured to output a third digital phase signal based on sampling a phase of the clock signal (CLK) at the input time of the second input signal; a first circuit (4, 4a) configured to output a first digital output signal based on the first phase digital signal, wherein the first input signal is digitally converted into the first digital output signal; a second circuit (5, 5a) configured to generate a second digital signal according to a period until the input time of the second input signal based on the first-phase digital signal, the second-phase digital signal, and the third-phase digital signal, wherein the period is digitally converted into the second digital signal; and a computer (7) configured to measure, based on the first digital signal and the second digital signal, a time from which a light signal is emitted to the time at which a reflected light signal obtained by the light signal reflected from an object is received, and to calculate a distance to the object based on the time, wherein the calculator (7) is further configured to calculate the distance based on a value obtained by adding the number of clock cycles of the clock signal (CLK) in the period from the input start time of the first input signal to the input time of the second input signal with a value obtained by dividing the second digital signal by the first digital signal. [4] The semiconductor circuit (1) according to claim 3, wherein the first circuit (4, 4a) generates the first digital signal by performing a time differentiation of the digital signal of the first phase, and the second circuit (5, 5a) generates the second digital signal based on processing the interpolation of two or more of the first-phase digital signals near the second-phase digital signal and the third-phase digital signal. [5] The semiconductor circuit (1) according to claim 4, wherein the second circuit (5, 5a) obtains a fractional time corresponding to the second-phase digital signal by polynomial interpolation of the two or more of the first-phase digital signal, obtains an integer time based on the third-phase digital signal, and generates the second digital signal based on the fractional time and the integer time. [6] The semiconductor circuit (1) according to claim 3, further comprising: a delay unit (26) configured to delay the second input signal, wherein the second phase sampler (12) outputs the digital signal of the second phase at a time when the second input signal delayed by the delay unit (26) transitions, and the third phase sampler (13) outputs the digital signal of the third phase at the time of transition of the delayed second input signal. [7] The semiconductor circuit (1) according to claim 3, further comprising: a delay unit (26) configured to delay the first input signal, wherein the oscillator (2) outputs the oscillation signal whose frequency is modulated according to a signal level of the first input signal delayed by the delay unit (26). [8] The semiconductor circuit (1) according to claim 3, further comprising: a comparator (6) configured to generate the second input signal by comparing a physical value of the first input signal with a reference value. [9] The semiconductor circuit (1) according to claim 8, wherein the physical value is power, an envelope shape, a frequency, an integral value or a pulse width of the first input signal. [10] The semiconductor circuit (1) according to claim 3, further comprising: a digital-to-analog (DA) converter (27) configured to convert the first phase digital signal into an analog phase signal; and a loop filter (29) configured to input to the oscillator (2) an integrated signal based on a difference signal between the first input signal and the phase-analog signal instead of the first input signal. [11] A distance measuring device (20) comprising: a light source (22) configured to emit a first light signal according to a timing of a start signal; a light detector (23) configured to receive a second light signal including a reflected light signal of the first light signal reflected from an object, and to convert the second light signal into the first input signal, wherein the first input signal is an electrical signal; a front assembly (24) configured to receive the semiconductor circuit (1) according to claim 1 and, based on the first input signal, to output the first digital signal and the second digital signal representing a reception time of the reflected light signal; and a distance calculation unit (25) configured to measure, based on the first digital signal and the second digital signal, a time from the time of the start signal to the input time of the second input signal, and to measure a distance to the object based on the measured time. [12] The distance measuring device (20) according to claim 11, further comprising: a comparator (6) configured to generate the second input signal by comparing a physical value of the first input signal with a reference value. [13] A distance measuring device (20) comprises: a light source (22) configured to emit a first light signal according to a timing of a start signal; a light detector (23) configured to receive a second light signal including a reflected light signal of the first light signal reflected from an object and convert the second light signal into the first input signal, wherein the first input signal is an electrical signal; a front assembly (24) comprising the semiconductor circuit (1) according to claim 3 and outputting, based on the first input signal, the first digital signal and the second digital signal representing a reception time of the reflected light signal; and a distance calculation unit (25) configured to measure, based on the first digital signal and the second digital signal, a time from the time of the start signal to the input time of the second input signal, and to measure a distance to the object based on the measured time. [14] The distance measuring device (20) according to claim 13, wherein the first circuit (4, 4a) generates the first digital signal by performing a time differentiation of the digital signal of the first phase, and the second circuit (5, 5a) generates the second digital signal based on processing the interpolation of two or more of the first-phase digital signals near the second-phase digital signal and the third-phase digital signal. [15] The distance measuring device (20) according to claim 14, wherein the second circuit (5, 5a) obtains a fractional time corresponding to the second-phase digital signal by polynomial interpolation of the two or more of the first-phase digital signal, obtains an integer time based on the third-phase digital signal, and generates the second digital signal based on the fractional time and the integer time. [16] The distance measuring device (20) according to claim 13, further comprising: a delay unit (26) configured to delay the second input signal, wherein the second phase sampler (12) outputs the digital signal of the second phase at the input time of the second input signal and the third phase sampler (13) outputs the digital signal of the third phase at the input time of the delayed second input signal transitions. [17] The distance measuring device (20) according to claim 13, further comprising: a delay unit (26) configured to delay the first input signal, wherein the oscillator (2) outputs the oscillation signal whose frequency is modulated according to a signal level of the first input signal delayed by the delay unit (26). [18] The distance measuring device (20) according to claim 13, further comprising: a comparator (6) configured to generate the second input signal by comparing a physical value of the first input signal with a reference value. [19] The distance measuring device (20) according to claim 18, wherein the physical value is power, an envelope shape, a frequency, an integral value or a pulse width of the first input signal.

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