Structures for bidirectional switches and methods for manufacturing such structures

Abstract

Structure, comprehensive: a substrate (10) with a first trench (23) and a second trench (25); a first substrate contact (22) in the first trench (23) and a second substrate contact (24) in the second trench (25); a bidirectional switch (54) on the substrate (10), wherein the bidirectional switch (54) comprises a first source / drain electrode (38), a second source / drain electrode (40), a channel layer (16) with an extension region (39) between the first source / drain electrode (38) and the second source / drain electrode (40), a first gate structure (28) and a second gate structure (30); a first substrate bias switch (50) on the substrate (10), wherein the first substrate bias switch (50) comprises a gate structure (26), a first source / drain electrode (34) coupled to the first substrate contact (22), a second source / drain electrode (36) coupled to the first source / drain electrode (38) of the bidirectional switch (54), and a channel layer (16) with an extension region (35) laterally between the gate structure (26) and the first source / drain region (34); and a second substrate bias switch (52) on the substrate (10), wherein the second substrate bias switch (52) comprises a gate structure (32), a first source / drain electrode (44) coupled to the second substrate contact (24), a second source / drain electrode (42) coupled to the second source / drain electrode (40) of the bidirectional switch (54), and a channel layer (16) with an extension area (43) laterally between the gate structure (32) and the first source / drain electrode (42), wherein the gate structure (26) of the first substrate bias switch (50) is coupled to the first gate structure (28) of the bidirectional switch (54) and the gate structure (32) of the second substrate bias switch (52) is coupled to the second gate structure (28) of the bidirectional switch (54).

Description

background

[0001] The present invention relates to the manufacture of semiconductor devices and integrated circuits, and in particular to structures for bidirectional switches and methods for manufacturing such structures.

[0002] Bidirectional switches are used in AC-AC matrix converters, solar micro-inverters, battery management, and other power applications. High-voltage power electronic components, such as high electron mobility transistors found in bidirectional switches, can be fabricated using III-V compound semiconductors to take advantage of their material properties, such as a charge carrier mobility greater than that of silicon and a higher critical electric field strength than silicon. This allows for higher voltage operation with lower drain-source resistance and smaller device size. III-V compound semiconductors contain Group III elements (aluminum, gallium, indium) in combination with Group V elements (nitrogen, phosphorus, arsenic, antimony).A high electron mobility transistor can incorporate a heterojunction between crystalline III-V compound semiconductor materials with different band gaps, e.g., a heterojunction between binary gallium nitride and trinary aluminum gallium nitride. During operation, a two-dimensional electron gas is generated near an interface at the heterojunction.

[0003] Unlike metal-oxide-semiconductor field-effect transistors, high electron mobility transistors lack a biased body diode between the source and drain. The absence of a body diode is advantageous for switching applications because it allows for improved bidirectional current flow. However, existing bidirectional switches do not account for the substrate bias during operation.

[0004] For certain switching applications, a pair of high-electron-mobility transistors can be connected in series to form a bidirectional switch. However, series connection requires that each component be designed to provide half the total desired switch resistance.

[0005] Patent application US 2014 / 0374766A1 describes a semiconductor device comprising a bidirectional gallium nitride field-effect transistor formed on III-N layers over a substrate, wherein the substrate is non-insulating, and the bidirectional gallium nitride field-effect transistor having a first source / drain node and a second source / drain node. The semiconductor device further comprises a first terminal connected between the first source / drain node and the substrate, and a second terminal connected between the second source / drain node and the substrate.

[0006] According to US patent 2020 / 0105741A1, a semiconductor device is known. This semiconductor device comprises a first HEMT (High Electron Mobility Transistor) device arranged within a semiconductor structure and comprising a first source, a first drain, and a first gate; a second HEMT device arranged within the semiconductor structure and comprising a second source coupled to the first drain, a second drain, and a second gate; and a transistor device configured as a diode, arranged within the semiconductor structure and comprising a third source, a third gate, and a third drain coupled to the second gate.

[0007] Patent application US 2017 / 0357283A1 discloses a substrate voltage control circuit. This circuit comprises a first connection terminal, a second connection terminal, a substrate voltage control terminal, a first switch with a first source, a first drain, and a first gate, wherein the first source is connected to the substrate voltage control terminal and the first drain is connected to the first connection terminal, a first resistor connected between the first gate and the second connection terminal, a second switch with a second source, a second drain, and a second gate, wherein the second source is connected to the substrate voltage control terminal and the second drain is connected to the second connection terminal, and a second resistor connected between the second gate and the first connection terminal.

[0008] Improved structures for a bidirectional switch and methods for creating such structures are needed. Summary

[0009] In one embodiment of the invention, a structure according to independent claim 1 is provided, wherein more advantageous embodiments thereof are defined in dependent claims 2 to 12.

[0010] In another embodiment of the invention, a method according to independent claim 13 is provided, wherein more advantageous embodiments thereof are defined in dependent claims 14 and 15. Brief description of the drawings

[0011] The accompanying drawings, which form part of this description, show various embodiments of the invention and, together with the general description of the invention above and the detailed description of the embodiments below, serve to explain the embodiments of the invention. In the drawings, the same reference numerals refer to the same features in the different views. Fig. Figure 1 is a cross-sectional view of a structure in a first manufacturing stage according to embodiments of the invention. Fig. 2 is a cross-sectional view of the structure in a Fig. 1. The following manufacturing stage. Fig. 3 is a circuit diagram of the structure made up of Fig. 2. Fig. Figure 4 is a view of a layout of a structure according to embodiments of the invention. Fig. Figures 5-8 are cross-sectional views of structures according to embodiments of the invention. Fig. Figure 9 is a view of a layout of a structure according to embodiments of the invention. Detailed description

[0012] With reference to Fig. 1 and according to embodiments of the invention, a layer stack 12 is formed on a substrate 10. The substrate 10 can be a bulk substrate with a single-crystal semiconductor material (e.g., single-crystal silicon). In one embodiment, the single-crystal semiconductor material of the substrate 10 can be single-crystal silicon with a <111> -crystal orientation. In other embodiments, the substrate 10 can be made of silicon carbide, sapphire or gallium nitride.

[0013] The layer stack 12 can comprise a buffer layer 14, a channel layer 16, and a barrier layer 18, each comprising one or more compound semiconductor layers. The layers 14, 16, and 18 can be serially deposited to form the layer stack using an epitaxial growth technique, such as metal-organic chemical vapor deposition, gas-phase epitaxy, or molecular beam epitaxy. A nucleation layer (not shown) can be provided between the layer stack 12 and the substrate 10. The layers 14, 16, and 18 can each have a single-crystal crystal structure or, alternatively, a substantially single-crystal crystal structure with varying degrees of crystalline defects.The buffer layer 14 can comprise a binary or ternary III-V compound semiconductor material such as gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination of these materials, which is tailored in terms of material composition, doping, and / or layer thickness to compensate for lattice mismatches, differences in thermal properties, and differences in mechanical properties between the substrate material 10 and the channel layer 16 material. The channel layer 16, which is arranged above the buffer layer 14, can comprise a binary III-V compound semiconductor material, such as gallium nitride, and can be undoped. The barrier layer 18, which is arranged above the channel layer 16, can comprise a ternary III-V compound semiconductor, e.g., aluminum gallium nitride with 15 to 35 atomic percent aluminum, which forms a heterogeneous interface with the channel layer 16 of varying composition.The barrier layer 18, together with the material properties of the channel layer 16, contributes to the generation of a two-dimensional electron gas at the interface between layers 16 and 18 during operation of the device.

[0014] Isolation zones 20 are formed in the layer stack 12. These isolation zones 20 can be formed, for example, by masked ion implantation of a species such as nitrogen or argon. The isolation zones 20 can be used to enclose and localize the two-dimensional electron gas layer formed during operation. Alternatively, the isolation zones 20 can also be trenches whose depth is sufficient to penetrate the two-dimensional electron gas layer formed during operation.

[0015] Substrate contacts 22, 24 are formed, extending through corresponding sections of layers 14, 16, 18 of the layer stack 12 and into sections of the substrate 10 below the layer stack 12. The substrate contacts 22, 24, located at the periphery of the device structure, can be formed by structuring grooves 23, 25 using lithography and etching processes and by filling the grooves 23, 25 with a planarized conductor, such as plugs made of tungsten-containing or doped polysilicon. The substrate contacts 22, 24 are electrically insulated from the surrounding sections of layers 14, 16, 18 of the layer stack 12 by the insulating regions 20.

[0016] The gate structures 26, 28, 30, and 32 are formed on different sections of the layer stack 12. Gate structures 28 and 30 are arranged laterally between gate structure 26 and gate structure 32. The gate structures 26, 28, 30, and 32 can comprise a gate 27 and a gate metal layer 29 arranged on and above the gate 27. Each gate 27 can be arranged in contact with the barrier layer 18. In one embodiment, each gate 27 can be in direct contact with the barrier layer 18. The gates 27 can be formed from a doped III-V compound semiconductor, such as p-gallium nitride or p-aluminum gallium nitride doped with magnesium. The gate metal layers 29 can be formed from one or more metals, such as aluminum-copper, titanium nitride, titanium, etc.

[0017] The gates 27 can be formed by structuring a layer of a doped III-V compound semiconductor (e.g., p-type gallium nitride) using lithography and etching processes, followed by the deposition of a dielectric layer 31 (e.g., silicon dioxide, aluminum oxide, or silicon nitride) to passivate the surface of the barrier layer 18 and to coat the sidewalls of the gates 27. At the locations of the gates 27, openings are structured in the dielectric layer 31, followed by the deposition of a layer of one or more metals, structuring using lithography and etching processes, and annealing to establish the gate metal layers 29. A dielectric gate cover layer (not shown) can be formed over the gate structures 26, 28, 30, 32 and the dielectric layer 31.

[0018] With reference to Fig. 2, in which identical reference signs refer to identical features in Fig. In a subsequent manufacturing phase, source / drain electrodes 34, 36, 38, 40, 42, 44 are formed on different sections of the layer stack 12. The source / drain electrodes 34, 36, 38, 40, 42, 44 can be made of an ohmic metal such as titanium, titanium nitride, aluminum, silicon, or a combination of these materials. The source / drain electrodes 34, 36, 38, 40, 42, 44 can be formed by structuring windows extending through the dielectric layer 31 and, optionally, partially through the barrier layer 18, by depositing a layer of the ohmic metal, by structuring the deposited layer using lithography and etching processes, and by annealing. The source / drain electrodes 34, 36, 38, 40, 42, 44 can be arranged in contact with the barrier layer 18 and in one embodiment can be in direct contact with the barrier layer 18.One of the insulation areas 20 is arranged laterally in the layer stack 12 between the source / drain electrode 36 and the source / drain electrode 38, and another of the insulation areas 20 is arranged laterally in the layer stack 12 between the source / drain electrode 40 and the source / drain electrode 42.

[0019] A substrate bias switch 50, which provides a substrate bias, comprises the source / drain electrode 34, the source / drain electrode 36, and the gate structure 26, which is arranged laterally between the source / drain electrode 34 and the source / drain electrode 36. In one embodiment, the source / drain electrode 34 can be a drain of the substrate bias switch 50, and the source / drain electrode 36 can be a source of the substrate bias switch 50. An extension region 35, formed by a section of the channel layer 16, is arranged laterally between the source / drain electrode 34 and the gate structure 26. The extension region 35 is electrically isolated from the section of the channel layer 16 through which the substrate contact 22 passes by one of the isolation regions 20.

[0020] A substrate bias switch 52, which provides the substrate bias, comprises the source / drain electrode 42, the source / drain electrode 44, and the gate structure 32, which is arranged laterally between the source / drain electrode 42 and the source / drain electrode 44. In one embodiment, the source / drain electrode 44 can be a drain of the substrate bias switch 52, and the source / drain electrode 42 can be a source of the substrate bias switch 52. An extension area 43, formed by a section of the channel layer 16, is located laterally between the source / drain electrode 42 and the source / drain electrode 44. The extension area 43 is electrically isolated from the section of the channel layer 16 through which the substrate contact 24 passes by one of the isolation areas 20. The substrate bias switch 52 is structurally similar to the substrate bias switch 50.

[0021] A bidirectional switch 54, capable of bidirectional switching, comprises the source / drain electrode 38, the source / drain electrode 40, and the gate structures 28 and 30, which are arranged laterally between the source / drain electrode 38 and the source / drain electrode 40. A laterally located extension area 39, formed by a section of the channel layer 16, is situated between the source / drain electrode 38 and the source / drain electrode 40. The gate structures 28 and 30 are separated by a distance sufficient to support the operating voltage of the bidirectional switch 54 when it functions as a switch. The bidirectional switch 54 can operate in an enrichment mode, which requires the application of a positive bias voltage to either the gate structure 28 or the gate structure 30 to change the direction.

[0022] The source / drain electrodes 34, 36, 38, 40, 42, 44 may include optional field plates (not shown) that overlap with the respective extension areas 35, 39, 43. The gate metal layers 29 may include optional field plates (not shown) formed by extending the gate metal over the respective extension areas or by adding additional metal layers that overlap the respective extension areas 35, 39, 43.

[0023] This is followed by middle-of-line and back-end-of-line processing, which includes the formation of contacts, vias, and wiring for the metallization levels of an interconnect structure arranged above the substrate 10 and connected to the substrate bias switches 50, 52, and the bidirectional switch 54. The source / drain electrode 36 of the substrate bias switch 50 and the source / drain electrode 38 of the bidirectional switch 54 are both physically and electrically connected to a metal feature 56 in a metallization level 55 of the interconnect structure. The source / drain electrode 42 of the substrate bias switch 52 and the source / drain electrode 40 of the bidirectional switch 54 are both physically and electrically coupled to a metal feature 58 in the metallization level 55 of the interconnect structure.Vias and a metal feature 66 define a connection 60 in the metallization plane 57 of the connection structure, which couples the source / drain electrode 34 of the substrate bias switch 50 to the substrate contact 22. Vias and a metal feature 68 define a connection 62 in the metallization plane 57 of the connection structure, which connects the source / drain electrode 44 of the substrate bias switch 52 to the substrate contact 24.

[0024] In one embodiment, the metal features 56, 58 and the intermediate compounds 60, 62 can be contained in a first metallization layer (M1) of the compound structure, which is closest to the substrate 10. The metal features 56, 58 and the compounds 60, 62 can be formed in one or more dielectric layers 64, which are formed, for example, from silicon dioxide and / or silicon nitride. Additional metallization layers of the compound structure can be formed above layer M1, and a top metallization layer can contain bond pads.

[0025] With regard to the Fig. 2 and Fig. 3 and according to embodiments of the invention, the substrate bias switches 50, 52 and the bidirectional switch 54 can be used in a circuit to provide a lateral bidirectional switch that couples a power device 70 and a power device 72. The power device 70 is coupled to the gate structure 28 of the bidirectional switch 54, and the power device 72 is coupled to the gate structure 30 of the bidirectional switch 54. In one embodiment, the power devices 70, 72 can be alternating current (AC) power sources.

[0026] The substrate bias switches 50 and 52 provide an active, internal substrate bias during operation of the bidirectional switch 54, without any external connections. In this respect, the gate structure 26 of the substrate bias switch 52 is coupled to the gate structure 28 of the bidirectional switch 54, and the gate structure 32 of the substrate bias switch 52 is coupled to the gate structure 30 of the bidirectional switch 54. This gate coupling can be achieved by a U-shaped gate structure in which the gate structures 26 and 28 are arms, and another U-shaped gate structure in which the gate structures 30 and 32 are arms, as shown in Fig. 4 is best shown.

[0027] The substrate 10 is biased via the substrate contact 22 when the gate structures 26, 28 are biased to the "on" state during operation, by a current supplied from the source / drain electrode 36 in an internal connection that includes the channel under the gate structure 26, the extension area 35, the source / drain electrode 34, and the connection 60. The substrate 10 is biased via the substrate contact 24 when the gate structures 30, 32 are biased to the "on" state during operation, by a current supplied from the source / drain electrode 42 in an internal connection that includes the channel under the gate structure 32, the extension area 43, the source / drain electrode 44, and the connection 62.

[0028] In one embodiment, a gate resistor 74 can be provided, which is coupled in series with the gate structures 26, 28, and a gate resistor 76 can be provided, which is coupled in series with the gate structures 30, 32. The gate resistor 74 can be used to adjust the turn-on speed of the substrate bias switch 50, and the gate resistor 76 can be used to adjust the turn-on speed of the substrate bias switch 52. In an alternative embodiment, the gate resistors 74, 76 can be omitted.

[0029] In one embodiment, the source / drain electrode 36 defines a source of the substrate bias switch 50, which is coupled to the source / drain electrode 38, which, depending on the direction of current flow between the power components 70, 72, provides either a source or a drain of the bidirectional switch 54, and the source / drain electrode 34 defines a drain of the substrate bias switch 50, which is coupled to the substrate contact 22 via the connection 60.In one embodiment, the source / drain electrode 42 defines a source of the substrate bias switch 52, which is coupled to the source / drain electrode 40, which, depending on the direction of current flow between the power components 70, 72, provides either a source or a drain of the bidirectional switch 54, and the source / drain electrode 44 defines a drain of the substrate bias switch 52, which is coupled to the substrate contact 24 via the connection 62.

[0030] With reference to Fig. 4, in which the same reference signs refer to the same features in Fig. 2, and according to embodiments of the invention, the bidirectional switch 54 can comprise multiple gate structures 26, 28, arranged as gate fingers, and multiple gate structures 30, 32, also arranged as gate fingers. The multiple gate structures 26, 28 can be arranged in parallel and connected together at one end. The multiple gate structures 26, 28 are typically connected by a bond pad 80 in the connection structure. The multiple gate structures 30, 32 can be arranged in parallel and connected together at one end. The multiple gate structures 30, 32 are typically coupled by a bond pad 82 in the connection structure.

[0031] Metal structures 56 are arranged between the gate structures 28, with source / drain electrodes arranged under each metal structure 56, as shown by the source / drain electrodes 36, 38 under the metal structures 56 in Fig. Figure 2 shows that metal features 58 are arranged between the gate structures 30, with source / drain electrodes arranged under each metal feature 58, as indicated by the source / drain electrodes 40, 42 under the metal features 58 in Figure 2. Fig. Figure 2 shows that the metal features 56 are typically connected to a bond pad 84 in the interconnect structure. The metal features 58 are typically coupled to a bond pad 86 in the interconnect structure. The optional gate resistors 74 and 76 can be provided by portions of the substrate 10.

[0032] With reference to Fig. 5, in which identical reference signs refer to identical features in Fig. 2, and according to alternative embodiments of the invention, the metal feature 66 of the compound 60 and the metal feature 68 of the compound 62 can be formed in a metallization plane 57 that is arranged above the metallization plane 55 in the compound structure. In one embodiment, the metallization plane 57 can be a second metallization plane (M2) of the compound structure, which is separated from the substrate 10 only by the M1 plane of the compound structure. The placement of the metal features 56, 58 of the compounds 60, 62 in the M2 plane above the M1 plane can be advantageous for higher voltage applications (e.g., voltages above 200 volts).

[0033] With reference to Fig. 6, in which the same reference signs refer to the same features in Fig. 2, and according to alternative embodiments of the invention, the substrate 10 can be a silicon-on-insulator substrate comprising a fixture layer 90, a buried oxide layer 91, and a handle substrate 92 separated from the fixture layer 90 by the buried oxide layer 91. The fixture layer 90 can be formed from single-crystal semiconductor material (e.g., single-crystal silicon) and serve as a seed layer for the growth of the layer stack 12. The buried oxide layer 91 can be formed from silicon dioxide, and the handle substrate 92 can be formed from single-crystal silicon.

[0034] With reference to Fig. 7, in which identical reference signs refer to identical features in Fig. 2, and according to alternative embodiments of the invention, the substrate 10 can be an engineered substrate comprising a handle substrate 94 formed from a polycrystalline ceramic material closely matched to the thermal expansion properties of the layer stack 12 materials. In one embodiment, the handle substrate 94 can be formed from polycrystalline aluminum nitride, which closely matches the thermal expansion properties of gallium nitride. In another embodiment, the handle substrate 94 can be formed from polycrystalline silicon carbide, which also closely matches the thermal expansion properties of gallium nitride. The handle substrate 94 is covered with a layer stack 95 comprising engineered layers, such as layers of silicon dioxide, silicon nitride, polysilicon, etc.The layer stack 95 is covered with a seed layer 96, which is adapted for the growth of the layer stack 12. In certain embodiments, the seed layer 96 can be made of single-crystal silicon with an orientation <111> , single-crystal gallium nitride or single-crystal silicon carbide. In the illustrated embodiment, the substrate contacts 22, 24 extend into the seed layer 96 and are connected to the seed layer 96.

[0035] With reference to Fig. 8, in which the same reference signs refer to the same features in Fig. 7, and according to alternative embodiments of the invention, the substrate contacts 22, 24 can penetrate through the nucleation layer 96 and into the layer stack 95 of processed layers. By penetrating through the nucleation layer 96, the substrate contacts 22, 24 are coupled to the nucleation layer 96.

[0036] With reference to Fig. 9, in which identical reference signs refer to identical features in Fig. 4, and according to alternative embodiments of the invention, the substrate contacts 22, 24 can be relocated to positions adjacent to source / drain electrodes located below the metal features 56, as shown by the source / drain electrodes 36, 38 below the metal features 56 in Fig. 2 is illustrated, and they can be adjacent to source / drain electrodes located below the metal features 58, as shown by the source / drain electrodes 40, 42 below the metal features 58 in Fig. 2 is illustrated.

[0037] The processes described above are used in the fabrication of integrated circuits. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (e.g., a single wafer containing multiple unpackaged chips), as bare chips, or in packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic substrate with leads attached to a mainboard or other higher-level substrate) or in a multi-chip package (e.g., a ceramic substrate with surface contacts and / or buried contacts). In each case, the chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices, either as part of an intermediate or a final product.

[0038] References in this document to terms modified by approximations such as "approximately," "about," and "essentially" are not to be limited to the exact value. The approximation may correspond to the accuracy of an instrument used to measure the value and, unless otherwise specified depending on the accuracy of the instrument, may indicate + / - 10% of the stated value(s).

[0039] References to terms such as "vertical," "horizontal," etc., are used here only as examples to establish a frame of reference. The term "horizontal" as used here is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal just defined. The term "lateral" refers to a direction within the horizontal plane.

[0040] A feature that is "connected" or "coupled" to another feature can be directly connected or coupled to that other feature. Alternatively, one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature that is "on" or "in contact" with another feature can be directly on or in direct contact with that other feature. Alternatively, one or more intervening features can be present. A feature can be "directly on" or in "direct contact" with another feature if no intervening features are present.A feature can be “indirectly on” or in “indirect contact” with another feature if at least one intermediate feature is present.

Claims

[1] Structure, comprehensive: a substrate (10) with a first trench (23) and a second trench (25); a first substrate contact (22) in the first trench (23) and a second substrate contact (24) in the second trench (25); a bidirectional switch (54) on the substrate (10), wherein the bidirectional switch (54) comprises a first source / drain electrode (38), a second source / drain electrode (40), a channel layer (16) with an extension region (39) between the first source / drain electrode (38) and the second source / drain electrode (40), a first gate structure (28) and a second gate structure (30); a first substrate bias switch (50) on the substrate (10), wherein the first substrate bias switch (50) comprises a gate structure (26), a first source / drain electrode (34) coupled to the first substrate contact (22), a second source / drain electrode (36) coupled to the first source / drain electrode (38) of the bidirectional switch (54), and a channel layer (16) with an extension region (35) laterally between the gate structure (26) and the first source / drain region (34); and a second substrate bias switch (52) on the substrate (10), wherein the second substrate bias switch (52) comprises a gate structure (32), a first source / drain electrode (44) coupled to the second substrate contact (24), a second source / drain electrode (42) coupled to the second source / drain electrode (40) of the bidirectional switch (54), and a channel layer (16) with an extension area (43) laterally between the gate structure (32) and the first source / drain electrode (42), wherein the gate structure (26) of the first substrate bias switch (50) is coupled to the first gate structure (28) of the bidirectional switch (54) and the gate structure (32) of the second substrate bias switch (52) is coupled to the second gate structure (28) of the bidirectional switch (54). [2] Structure according to claim 1, wherein the substrate (10) is a handle substrate (94) formed from a polycrystalline ceramic material, has a stack of layers (95) of machined layers on the handle substrate (94) and a nucleation layer (96) on the stack of layers (95) of machined layers, and the first substrate contact (22) and the second substrate contact (24) are connected to the nucleation layer (96). [3] Structure according to claim 1, wherein the substrate (10) comprises silicon. [4] Structure according to claim 1, wherein the substrate (10) comprises a device layer (90), a buried oxide layer (91) and a handle substrate (92) separated from the device layer (90) by the buried oxide layer (91), and wherein the first substrate contact (22) and the second substrate contact (24) are coupled to the device layer (90). [5] Structure according to claim 1, wherein the extension area (39) of the bidirectional switch (54) is a first section of a III-V compound semiconductor layer (16), the extension area (35) of the first substrate bias switch (50) is a second section of the III-V compound semiconductor layer (16) and the first substrate contact (22) extends through a third section of the III-V compound semiconductor layer (16) and into the substrate (10). [6] Structure according to claim 5, further comprising: an insulation region (20) which is arranged laterally in the III-V compound semiconductor layer (16) between the second section of the III-V compound semiconductor layer (16) and the third section of the III-V compound semiconductor layer (16). [7] Structure according to claim 1, wherein the first substrate contact (22) is arranged next to the first source / drain electrode (38) of the bidirectional switch (54). [8] Structure according to claim 1, further comprising: a gate resistor (74) coupled in series with the gate structure (26) of the first substrate bias switch (50) and the first gate structure (28) of the bidirectional switch (54). [9] Structure according to claim 1, further comprising: a connection structure with a connection (60) that connects the first source / drain electrode (34) of the first substrate bias switch (50) to the first substrate contact (22). [10] Structure according to claim 9, wherein the connection structure has a first metallization level (55) and a second metallization level (57), the first metallization level (55) being arranged between the second metallization level (57) and the first substrate contact (22), and the connection (60) having a metal feature (66) arranged in the first metallization level (55). [11] Structure according to claim 9, wherein the connection structure has a first metallization level (55) and a second metallization level (57), the first metallization level (55) being arranged between the second metallization level (57) and the first substrate contact (22), and the connection (60) having a metal feature (66) being arranged in the second metallization level (57). [12] Structure according to claim 1, wherein the extension area (39) of the bidirectional switch (54) and the extension area (35) of the first substrate bias switch (50) are formed from gallium nitride. [13] Procedures, including: a formation of a first trench (23) and a second trench (25) in a substrate (10); a formation of an initial substrate contact (22) in the first trench (23); a forming of a bidirectional switch (54) on the substrate (10), wherein the bidirectional switch (54) comprises a first source / drain electrode (38), a second source / drain electrode (40), a channel layer (16) with an extension region (39) between the first source / drain electrode (38) and the second source / drain electrode (40), a first gate structure (28) and a second gate structure (30); forming a first substrate bias switch (50) on the substrate (10), wherein the first substrate bias switch (50) comprises a gate structure (26), a first source / drain electrode (34) coupled to the first substrate contact (22), a second source / drain electrode (36) coupled to the first source / drain electrode (38) of the bidirectional switch (54), and a channel layer (16) with an extension area (35) laterally between the gate structure (26) and the first source / drain area (34); a formation of a second substrate contact (24) in the second trench (25); and forming a second substrate bias switch (52) on the substrate (10), wherein the second substrate bias switch (52) comprises a gate structure (32), a first source / drain electrode (44) coupled to the second substrate contact (24), a second source / drain electrode (42) coupled to the second source / drain electrode (40) of the bidirectional switch (54), and a channel layer (16) with an extension area (43) laterally between the gate structure (32) and the first source / drain electrode (44), wherein the gate structure (26) of the first substrate bias switch (50) is coupled to the first gate structure (28) of the bidirectional switch (54) and the gate structure (32) of the second substrate bias switch (52) is coupled to the second gate structure (30) of the bidirectional switch (54). [14] The method of claim 13, further comprising: forming a connection structure with a connection (60) that couples the first source / drain electrode (34) of the first substrate bias switch (50) to the first substrate contact (22). [15] Method according to claim 13, wherein the extension area (39) of the bidirectional switch (54) is a first section of a III-V compound semiconductor layer (16), the extension area (35) of the first substrate bias switch (50) is a second section of the III-V compound semiconductor layer (16), the first substrate contact (22) extends through a third section of the III-V compound semiconductor layer (16) and into the substrate (10), and further comprising: a formation of an isolation region (20) which is arranged laterally in the III-V compound semiconductor layer (16) between the second section of the III-V compound semiconductor layer (16) and the third section of the III-V compound semiconductor layer (16).

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