Semiconductor module with reduced decrease in heat dissipation and reduced thermal interference between semiconductor chips

Abstract

Semiconductor module (100, 200, 300, 400, 500, 600, 700), exhibiting: - a large number of semiconductor chips (5); - a module substrate (20, 20A) on which the multitude of semiconductor chips (5) are mounted; - a heat sink (10) on which the module substrate (20, 20A) is mounted; and - a filler (TG) that is filled between the module substrate (20, 20A) and the heat sink (10), where: - the module substrate (20, 20A) has: - a heat radiating plate (1) and - an insulating substrate (2, 12) arranged on the heat-radiating plate (1) on which the plurality of semiconductor chips (5) are mounted, - the heat-radiating plate (1) has: - a plurality of recessed partial areas (RP) arranged on a surface opposite the heat sink (10), and - at least one groove (GR), - the plurality of depression sub-areas (RP) is arranged in areas that lie below arrangement areas of the plurality of semiconductor chips (5), such that the total area of ​​the depression sub-areas (RP) corresponding to a semiconductor chip (5) is fixed at 25% or less of the area of ​​the semiconductor chip (5), - which has at least one groove (GR) located in a region situated beneath a region between at least one of the plurality of semiconductor chips (5) and an adjacent other semiconductor chip (5), and - the filler (TG) is also filled into the multitude of depression sub-areas (RP).

Description

Background of the inventionField of the invention

[0001] The present disclosure relates to a semiconductor module, and more particularly to a semiconductor module in which a decrease in heat radiation property is suppressed and in which thermal interference between semiconductor chips is reduced. Description of the background technology

[0002] In order to improve the heat radiation characteristics of a semiconductor module, Japanese Patent Application Laid-Open No. 2013-120866 A discloses a configuration in which countless small honeycomb-shaped holes are arranged in the heat radiation plane of a semiconductor chip to trap voids generated in a filler between a heat radiation plate and a heat sink, thereby suppressing heat transfer from the semiconductor chip to the heat sink from being blocked and maintaining the heat radiation characteristic of the semiconductor module. Summary

[0003] As in Japanese Patent Application Laid-Open No. JP 2013-120866 A, the time during which a favorable heat radiation property is maintained is simply limited by arranging small honeycomb-shaped holes in the heat radiation plane of the semiconductor chip to capture voids, and in view of the operation time for actual use of the semiconductor module, there is a problem that a sufficient effect cannot be obtained from the viewpoint of maintaining the heat radiation property.

[0004] JP H10-41440 A discloses a module configured to thermally insulate a heat-generating element from other circuit elements by forming a heat-interrupting groove on a radiating base. By forming a heat-interrupting groove on a metallic base for supporting a circuit board with circuit elements mounted thereon, the protruding portion of the mounting area of ​​the circuit element on the metallic base or base plate is defined in sections to narrow the heat conduction path, thereby connecting it and the protruding portion of the mounting area of ​​the adjacent circuit element on the metallic base. Since this suppresses mutual thermal interference between the circuit elements, the heat conducted from the circuit elements through the metallic base or base plate is independently conducted to the side of a radiating plate.Therefore, such a defect can be prevented from causing the peripheral circuit element of the heat-generating circuit element to experience a thermal effect therefrom, reducing its operating efficiency and shortening its service life.

[0005] JP 2013-120866 A describes a semiconductor device that can be manufactured inexpensively, has excellent cooling properties, and comprises an insulating substrate with a conductor circuit connected to a back electrode of a semiconductor chip via solder, a thermal grease coated with the conductor circuit on a heat radiation plane of the insulating substrate, a heat sink connected to the heat radiation plane, and a plurality of recesses formed with the conductor circuit on the heat radiation plane of the insulating substrate, which recesses are separated from each other because each recess is surrounded by the heat radiation plane. When the semiconductor chip generates heat, the thermal grease is heated, and voids mixed into the thermal grease appear on a surface and move upward. At the same time, the insulating substrate with the conductor circuit is heated, causing deformation.Since the created cavities are divided and enclosed in the recesses, the heat transfer from the insulating substrate with the conductor circuit to the heat sink is not disturbed and the minimum heat radiation properties of the semiconductor device can be maintained.

[0006] An object is to provide a semiconductor module capable of suppressing deterioration of heat radiation property due to aging and maintaining the heat radiation property.

[0007] The object underlying the invention is achieved in a semiconductor module according to the invention with the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0008] According to the present invention, the semiconductor module comprises a plurality of semiconductor chips, a module substrate on which the plurality of semiconductor chips are mounted, a heat sink on which the module substrate is mounted, and a filler filled between the module substrate and the heat sink. The module substrate comprises a heat radiation plate and an insulating substrate arranged on the heat radiation plate and on which the plurality of semiconductor chips are mounted. The heat radiation plate has a plurality of recessed portions arranged on a surface opposite the heat sink and at least one groove. The plurality of recessed portions are arranged in areas underlying arrangement areas of the plurality of semiconductor chips, such that the total area of ​​the recessed portions corresponding to one semiconductor chip is set to 25% or less of the area of ​​the semiconductor chip.the at least one groove is arranged in a region which lies below a region between at least one of the plurality of semiconductor chips and an adjacent other semiconductor chip, and the filler is also filled into the plurality of recess portions.,

[0009] According to the above semiconductor module, a plurality of recessed portions are arranged on the surface of the heat radiating plate facing the heat sink, and the plurality of recessed portions are also filled with a filler. Therefore, when pumping occurs due to thermal deformation of the heat radiating plate, the filler filled in the plurality of recessed portions is extruded toward the surface facing the heat sink, so that the filler is replenished and the deterioration of the heat radiation property of the semiconductor module can be suppressed. Furthermore, by disposing at least one groove, thermal interference due to heat generation between adjacent semiconductor chips can be mitigated and the maximum temperature of the entire semiconductor module can be lowered to suppress the occurrence of pumping.

[0010] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Short description of the drawings Fig. 1 is a cross-sectional view illustrating a configuration of a main part of a semiconductor module according to Embodiment 1; Fig. 2 is a cross-sectional view illustrating the configuration of the main part of the semiconductor module according to Embodiment 1; Fig. 3 is a plan view of a module substrate of the semiconductor module according to Embodiment 1, viewed from the bottom side; Fig. 4 is a cross-sectional view illustrating the configuration of the main part of the semiconductor module according to Embodiment 2; Fig. 5 is a plan view of a semiconductor module according to Embodiment 3, viewed from the upper surface side; Fig. 6 is a circuit diagram illustrating a configuration of an inverter circuit mounted on the semiconductor module according to Embodiment 3; Fig. 7 is a plan view of a semiconductor module according to Embodiment 4, viewed from the upper surface side; Fig. 8 is a plan view of a semiconductor module according to Embodiment 5, viewed from the upper surface side; Fig. 9 is a plan view of a semiconductor module according to Embodiment 6, viewed from the upper surface side; and Fig. 10 is a plan view of a semiconductor module according to Embodiment 7, viewed from the upper surface side. Description of the preferred embodiments<Ausführungsform 1>

[0011] Fig. 1 is a cross-sectional view illustrating a configuration of a main part of a semiconductor module 100 according to an embodiment 1. As shown in Fig. 1, in the semiconductor module 100, the insulating substrate 2 is bonded to the upper surface of the heat radiating plate 1 with a bonding material (not illustrated) such as a solder or an adhesive. A circuit pattern 3 is arranged on the upper surface of the insulating substrate 2, and a plurality of semiconductor chips 5 such as electric power transistor chips and electric power diode chips are bonded to the circuit pattern 3 via a bonding material 4 such as a solder. A laminated structure of the heat radiating plate 1, the insulating substrate 2, and the circuit pattern 3 is conveniently referred to as a module substrate 20.

[0012] The insulating substrate 2 is made of a resin or a ceramic material, and the heat radiation plate 1 is made of a material having excellent heat radiation properties such as aluminum (Al) or copper (Cu).

[0013] As in Fig. As illustrated in FIG. 1, the semiconductor module 100 includes a heat sink 10 disposed on the lower surface side of the heat radiation plate 1, and a thermal grease TG such as a silicone paste, that is, a filler, is filled between the lower surface of the heat radiation plate 1 and the upper surface of the heat sink 10. Although the semiconductor module 100 is housed in a case made of resin or the like and sealed with a resin or the like, its illustration will be omitted in the following description.

[0014] The circuit structure 3 consists of a conductor such as Al or Cu and is formed by metallizing the surface of the insulating substrate 2.

[0015] In Fig. 1, the main electrodes on the upper surface side of the plurality of semiconductor chips 5 are connected to each other by wire bonding via wires WR made of Al, and Fig. 1 represents only one cross section of the semiconductor module 100. In another cross section of the semiconductor module 100, there is also a portion where the main electrode on the upper surface side of the semiconductor chip 5 and the circuit pattern 3 are connected via the wire WR.

[0016] As in Fig. 1, a plurality of recessed portions RP and a plurality of grooves GR are arranged on the lower surface of the heat radiation plate 1. The recessed portions RP are arranged to be substantially uniformly distributed in the regions of the radiation plate 1 located below the arrangement regions of the semiconductor chips 5, and the grooves GR are arranged in the regions located below the regions between semiconductor chips 5. Both the recessed portions RP and the grooves GR are arranged to extend from the outermost surface of the lower surface of the heat radiation plate 1 in the thickness direction of the heat radiation plate 1, and both are provided with a depth that does not extend through the heat radiation plate 1. Further, the depth D1 of the recessed portions RP is set to the maximum value of about 300 μm, for example.

[0017] The grooves GR are provided to prevent thermal interference between the heat-generating semiconductor chips 5, and the depth D2 of the grooves GR is formed deeper than the depth D1 of the recessed portions RP. That is, thermal interference between the semiconductor chips 5 is suppressed by making the depth D2 of the grooves GR as deep as possible within a range where no ground fault or the like occurs between the semiconductor chips 5 and the heat sink 10.

[0018] Furthermore, if the area of ​​the recessed portions RP is increased, there is a concern that the area contacting the heat radiation plate 1 and the area contacting the heat sink 10 will be affected. Therefore, it is desirable that the area of ​​the recessed portions RP be made as small as possible and that the recessed portions RP be arranged uniformly.

[0019] That is, if the area of ​​the recess portions RP is too large, temperature differences may occur between the semiconductor chips 5 due to variations in the heat radiation property when a plurality of semiconductor chips 5 are arranged. Therefore, it is desirable that the area of ​​the recess portions RP be made as small as possible to uniform the heat radiation property.

[0020] The thermal conductivity from the heat-radiating plate 1 to the heat sink 10 depends on the material, area, and shape of the heat-radiating plate 1, and the thermal conductivity and viscosity of the paste vary depending on the type of thermal paste TG to be used. Therefore, it is generally difficult to specify the area and arrangement density of the recess portions RP. For example, if specified in relation to the size of the mounted semiconductor chips 5, the total area of ​​the recess portions RP corresponding to one semiconductor chip 5 is set to 25% or less of the area of ​​the semiconductor chip 5, and the total area of ​​the plurality of recess portions RP and the plurality of grooves GR is set to approximately 25% to 50% of the area of ​​the heat-radiating plate 1.

[0021] Here, the area of ​​the recessed portions RP represents the area perpendicular to the depth direction of the recessed portions RP, i.e., the opening area of ​​the recessed portions RP, and the area of ​​the grooves GR represents the area perpendicular to the depth direction of the grooves GR, i.e., the opening area of ​​the grooves GR. The shape of the recessed portions RP in plan view can be a circular shape or a polygon such as a quadrilateral, a pentagon, or a hexagon.

[0022] The Fig. The semiconductor module 100 illustrated in Figure 1 illustrates a configuration in which the insulating substrate 2 is directly bonded to the upper surface of the radiating plate 1, while in Fig. 2 illustrates a semiconductor module 100A in which a circuit pattern 13 is formed on the upper surface of a ceramic substrate 15, and an insulating substrate 12, on which a copper film 14 is formed on the lower surface, is bonded to the heat radiating plate 1 via a bonding material 11 such as a solder. A laminated structure of the heat radiating plate 1, the bonding material 11, and the insulating substrate 12 is conveniently referred to as a module substrate 20A. In Fig. 2 are the same components as those of the with reference to Fig. 1 are designated by the same reference numerals, and repeated description is omitted.

[0023] In Fig. 2, a plurality of module substrates 20A are mounted on the heat radiation plate 1, and a plurality of semiconductor chips 5 are bonded to each of them.

[0024] Fig. 3 is a plan view of the module substrate 20A, viewed from the bottom. The plurality of recessed portions RP are arranged so as to be substantially uniformly distributed in the regions underlying the semiconductor chip array regions 5.

[0025] The grooves GR are arranged in an elongated rectangular shape between the arrangement regions of the recessed portions RP, and the length of their long side is set to be longer along the long side of the rectangular semiconductor chip 5 in plan view. The length of the short side of the groove GR is preferably the shortest possible length within the range that can be machined by one process and is set to, for example, 0.1 mm.

[0026] A maximum gap of approximately 0.05 mm is created between the heat-radiating plate 1 and the heat sink 10; therefore, thermal grease TG is filled to eliminate the gap. At this time, the recessed portions RP are also filled with thermal grease TG. The grooves GR do not need to be filled with thermal grease TG.

[0027] The effects of providing such recessed portions RP are as follows. When the semiconductor module 100, specifically the heat-radiating plate 1, is thermally deformed due to the thermal cycle caused by the heat generated by the semiconductor chips 5, pumping occurs in some cases, in which the thermal grease TG filled in the gap between the heat-radiating plate 1 and the heat sink 10 is forced outward.

[0028] When pumping occurs, the amount of the filled thermal paste TG is reduced, a gap is generated between the heat radiation plate 1 and the heat sink 10, which reduces the heat radiation property of the semiconductor module 100.

[0029] However, by providing the recessed portions RP and filling them with thermal grease TG, when pumping occurs, air flows into the recessed portions RP, which extrudes or pushes the thermal grease TG filled in the recessed portions RP toward the surface opposite the heat sink 10, thereby filling the gap between the heat radiation plate 1 and the heat sink 10 with thermal grease TG. This ensures that the decrease in the heat radiation property of the semiconductor module 100 is suppressed.

[0030] Furthermore, by providing the grooves GR, thermal interference due to heat generation of the semiconductor chips 5 between adjacent semiconductor chips 5 can be mitigated, which lowers the maximum temperature of the entire semiconductor module 100. As a result, the thermal stress is reduced and the amount of change in the deformation of the heat radiation plate 1 is reduced, resulting in the suppression of the occurrence of pumping itself. <Ausführungsform 2>

[0031] Fig. 4 is a cross-sectional view illustrating a configuration of a main part of a semiconductor module 200 according to Embodiment 2. In Fig. 4 are the same components as those of the with reference to Fig. 1 are designated by the same reference numerals, and a repeated description is omitted.

[0032] As in Fig. As illustrated in Figure 4, in the semiconductor module 200, the cross-sectional shape of the recessed portions RP is dome-shaped. With this shape, the recessed portions RP have no corners, so that the stress generated in the heat-radiating plate 1 can be easily dissipated, and fatigue fracture of the heat-radiating plate 1 can be prevented.

[0033] The effect of suppressing the decrease in the heat radiation property by providing the recess portions RP and the effect of mitigating thermal interference by providing the grooves GR are the same as those in Embodiment 1. <Ausführungsform 3>

[0034] Fig. 5 is a plan view of a semiconductor module 300 according to Embodiment 3, viewed from the upper surface side, i.e., the side where the semiconductor chips are arranged. In Embodiment 3, its characteristics lie in the arrangement of the grooves GR, and the grooves GR are illustrated by dashed lines, and the illustration of the recess portions RP is omitted.

[0035] The Fig. The semiconductor module 300 illustrated in Figure 5 has a high-side phase HS with a high potential and a low-side phase LS with a low potential, and has a two-phase semiconductor module configuration consisting of a plurality of chip pairs, wherein each chip pair includes an insulated gate bipolar transistor (IGBT) chip and a freewheeling diode (FWD) chip connected in parallel in both the high-side phase HS and the low-side phase LS. The plurality of chip pairs in the high-side phase HS are driven in parallel, and the plurality of chip pairs in the low-side phase LS are driven in parallel.

[0036] The configuration of the semiconductor module is not limited to two phases, and the present disclosure can be applied to a single-phase semiconductor module, a three-phase semiconductor module, and a six-phase semiconductor module. Furthermore, a semiconductor chip other than the IGBT chip and the diode chip can also be used as the semiconductor chip. The present disclosure is also applicable to series-driven semiconductor modules.

[0037] As in Fig. As illustrated in FIG. 5, in the semiconductor module 300, the grooves GR are arranged in the high-side phase HS and the low-side phase LS in the regions of the heat radiation plate 1 located below the regions between the pairs of IGBT chips and FWD chips. The length of the long side of the groove GR is set longer than the length of the arrangement of the chip pair of the IGBT chip and the FWD chip.

[0038] As in Fig. 5, the IGBTs 1 to 4 and the FWDs 1 to 4 in the high-side phase HS are mounted on the circuit pattern 3, and the IGBTs 5 to 8 and the FWDs 5 to 8 in the low-side phase LS are mounted on the circuit pattern 31, and the anodes of the FWDs 1 to 4 of the high-side phase HS and the circuit pattern 31 of the low-side phase LS are connected by wires WR.

[0039] Fig. 6 is a circuit diagram showing a configuration of a semiconductor module 300 of Fig. 5 mounted two-phase inverter circuit. The Fig. The inverter circuit illustrated in Figure 6 comprises IGBTs 1 to 4 as high-side semiconductor chips and FWDs 1 to 4 connected antiparallel to IGBTs 1 to 4, and IGBTs 5 to 8 as low-side semiconductor chips and FWDs 5 to 8 connected antiparallel to IGBTs 5 to 8.

[0040] The collectors of IGBTs 1 to 4 are commonly connected to a power line C1, the emitters of IGBTs 5 to 8 are commonly connected to a power line E2, and the emitters of IGBTs 1 to 4 and the collectors of IGBTs 5 to 8 are commonly connected to an output line OT.

[0041] As in Fig. 5, by disposing the grooves GR in the high-side phase HS and the low-side phase LS in the regions of the heat radiation plate 1 below the regions between the pairs of the IGBT chips and the FWD chips, thermal interference between pairs of chips that generate heat at the same time can be mitigated and the maximum temperature of the entire semiconductor module 300 can be lowered.

[0042] Furthermore, by arranging the grooves GR, the thermal stress is reduced by reducing the temperature difference in the semiconductor module 300, and this makes pumping less likely to occur, and the thermal paste TG is less replenished from the recess portions RP, making it less likely that the thermal paste in the recess portions RP is used up, thereby extending the time during which the thermal paste can be replenished from the recess portions RP. <Ausführungsform 4>

[0043] Fig. 7 is a plan view of a semiconductor module 400 according to Embodiment 4, viewed from the upper surface side, i.e., the side where the semiconductor chips are arranged. In Embodiment 4, its characteristics lie in the arrangement of the groove GR, and the groove GR is illustrated by dashed lines, and the illustration of the recess portions RP is omitted.

[0044] In the Fig. In the semiconductor module 400 illustrated in Figure 7, a groove GR is arranged along the long sides of the circuit patterns 3 and 31 in the region of the heat radiation plate 1 located below the area between the circuit pattern 3 of the high-side phase HS and the circuit pattern 31 of the low-side phase LS. That is, a groove GR is arranged along the arrangement of a first chip group and a second chip group in the area located below the area between the first chip group and the second chip group, which operate complementarily.

[0045] By disposing such a groove GR, thermal interference from one of the complementarily driven chip pairs of the high-side phase HS or the chip pairs of the low-side phase LS with the other phase is suppressed, and the number of semiconductor chips having the maximum temperature is reduced, thereby reducing the temperature difference in the semiconductor module 400. This reduces thermal stress and makes pumping less likely to occur, and the thermal paste TG is less replenished from the recess portions RP, which makes it less likely that the thermal paste TG in the recess portions RP is used up, thereby extending the time during which the thermal paste TG can be replenished from the recess portions RP. <Ausführungsform 5>

[0046] Fig. 8 is a plan view of a semiconductor module 500 according to Embodiment 5, viewed from the upper surface side, i.e., the side where the semiconductor chips are arranged. In Embodiment 5, its characteristics lie in the arrangement of the grooves GR, and the grooves are illustrated by dashed lines, and the illustration of the recess portions RP is omitted.

[0047] In the Fig. In the semiconductor module 500 illustrated in FIG. 8, the groove GR is arranged in a region of the heat radiation plate 1 that lies below the area between the array of IGBTs 1 to 4 and the array of FWDs 1 to 4 mounted on the circuit pattern 3 of the high-side phase HS, along the array of IGBTs 1 to 4 and FWDs 1 to 4. Similarly, the groove GR is arranged in a region of the heat radiation plate 1 that lies below the area between the array of IGBTs 5 to 8 and the array of FWDs 5 to 8 mounted on the circuit pattern 31 of the low-side phase LS, along the array of IGBTs 5 to 8 and FWDs 5 to 8.

[0048] In the semiconductor module 500, among the pairs of IGBT chips and FWD chips in actual use, the temperature of the IGBT chips tends to be the highest because the IGBT chips consume a lot of power and generate a lot of heat. Therefore, by disposing the grooves GR, thermal interference from semiconductor chips other than the IGBT chips, such as the FWD chips, can be mitigated and the maximum temperature of the entire semiconductor module 500 can be reduced. It should be noted that the IGBT chips are referred to as the first semiconductor chips, and the FWD chips, whose power consumption is lower than that of the IGBT chips, are referred to as the second semiconductor chips. <Ausführungsform 6>

[0049] Fig. 9 is a plan view of a semiconductor module 600 according to Embodiment 6, viewed from the upper surface side, i.e., the side where semiconductor chips are arranged. In Embodiment 6, its characteristics lie in the arrangement of the groove GR, and the groove GR is illustrated by dashed lines, and the illustration of the recess portions RP is omitted.

[0050] The Fig. The semiconductor module 600 illustrated in Fig. 9 uses different insulating substrates 12 for the high-side phase HS and the low-side phase LS, and the groove GR is arranged in a region of the heat radiation plate 1 located below the region between the insulating substrate 12 for the high-side phase HS and the insulating substrate 12 for the low-side phase LS along the long sides of the insulating substrates 12.

[0051] The insulating substrates 12 have, as with reference to Fig. 2 described ceramic substrates 15 whose heat radiation property is not good; however, by using different insulating substrates 12 for the high-side phase HS and the low-side phase LS and by disposing the groove GR, thermal interference from one of the complementary heat-generating chip pairs of the high-side phase HS or the chip pairs of the low-side phase LS to the other phase is suppressed, and the number of semiconductor chips having the maximum temperature is reduced, thereby reducing the temperature difference in the semiconductor module 600.This reduces thermal stress and makes it less likely that pumping out will occur, and the thermal paste TG is less replenished from the recess sub-regions RP, which makes it less likely that the thermal paste TG in the recess sub-regions RP will be used up, thereby extending the time during which the thermal paste TG can be replenished from the recess sub-regions RP. <Ausführungsform 7>

[0052] Fig. 10 is a plan view of a semiconductor module 700 according to Embodiment 7, viewed from the upper surface side, i.e., the side where the semiconductor chips are arranged. In Embodiment 7, its characteristics lie in the arrangement of the grooves GR, and the grooves GR are illustrated by dashed lines, and the illustration of the recess portions RP is omitted.

[0053] In the Fig.In the semiconductor module 700 illustrated in Fig. 10, the grooves GR are arranged in the high-side phase HS and the low-side phase LS in the regions of the heat radiation plate 1 located below the regions between the pairs of the IGBT chips and the FWD chips, and a groove GR is arranged along the long sides of the circuit patterns 3 and 31 in the region of the heat radiation plate 1 located below the region between the circuit pattern 3 of the high-side phase HS and the circuit pattern 31 of the low-side phase LS.Further, a groove GR is formed in a region of the heat radiation plate 1 located below the region between the array of IGBTs 1 to 4 and the array of FWDs 1 to 4 mounted on the circuit pattern 3 of the high-side phase HS, along the array of IGBTs 1 to 4 and FWDs 1 to 4, and a groove GR is formed in a region of the heat radiation plate 1 located below the region between the array of IGBTs 5 to 8 and the array of FWDs 5 to 8 mounted on the circuit pattern 31 of the low-side phase LS, along the array of IGBTs 5 to 8 and FWDs 5 to 8.

[0054] By arranging a plurality of grooves GR extending in the horizontal direction and the vertical direction in plan view in this way, the IGBTs 1 to 8 and the FWDs 1 to 8 arranged in a matrix can be individually thermally isolated, which mitigates thermal interference between individual semiconductor chips. Therefore, the maximum temperature of the entire semiconductor module 700 can be significantly reduced. <Anwendungsbeispiel eines Halbleiterchips>

[0055] As a semiconductor chip 5, a metal oxide semiconductor field-effect transistor (MOSFET) and a Schottky barrier diode (SBD) can be used. Further, as the semiconductor chip 5, in addition to a silicon semiconductor, a wide bandgap semiconductor having a wider bandgap than Si, such as SiC (silicon carbide), can also be used. Compared with a silicon device, a SiC device using SiC has excellent withstand voltage characteristics, high allowable current density, and high heat resistance, so that its operation at high temperatures is feasible. Furthermore, the application example is not limited to SiC, and other wide bandgap semiconductors such as gallium nitride (GaN) can also be used.

[0056] In the present disclosure, embodiments may be combined, appropriately modified, or omitted without departing from the scope of the invention.

Claims

[1] Semiconductor module (100, 200, 300, 400, 500, 600, 700), comprising: - a plurality of semiconductor chips (5); - a module substrate (20, 20A) on which the plurality of semiconductor chips (5) are mounted; - a heat sink (10) on which the module substrate (20, 20A) is mounted; and - a filler (TG) filled between the module substrate (20, 20A) and the heat sink (10), where: - the module substrate (20, 20A) comprises: - a heat radiation plate (1) and - an insulating substrate (2, 12) arranged on the heat radiation plate (1) and on which the plurality of semiconductor chips (5) are mounted, - the heat radiation plate (1) has: - a plurality of recessed portions (RP) arranged on a surface opposite the heat sink (10), and - at least one groove (GR), - the plurality of recessed portions (RP) are arranged in regions which lie below arrangement regions of the plurality of semiconductor chips (5), so that the total area of ​​the recessed portions (RP) corresponding to a semiconductor chip (5) is set to 25% or less of the area of ​​the semiconductor chip (5), - the at least one groove (GR) is arranged in a region which lies below a region between at least one of the plurality of semiconductor chips (5) and an adjacent other semiconductor chip (5), and - the filler (TG) is also filled into the plurality of recessed portions (RP). [2] The semiconductor module (100, 200, 300, 400, 500, 600, 700) according to claim 1, wherein a depth (D2) of the at least one groove (GR) is formed deeper than the depth (D1) of the plurality of recess portions (RP). [3] The semiconductor module (100, 200, 300, 400, 500, 600, 700) according to claim 1, wherein a cross-sectional shape of each of the plurality of recess portions (RP) is dome-shaped. [4] Semiconductor module (100, 200, 300, 400, 500, 600, 700) according to claim 1, wherein: - the plurality of semiconductor chips (5) are arranged in parallel and controlled simultaneously and - the at least one groove (GR) is arranged under a region between the plurality of semiconductor chips (5) of the heat radiation plate (1). [5] Semiconductor module (100, 200, 300, 400, 500, 600, 700) according to claim 1, wherein: - the plurality of semiconductor chips (5) comprises: - a first chip group arranged in parallel and controlled simultaneously, and - has a second chip group arranged in parallel and controlled simultaneously, - the first chip group and the second chip group are controlled complementarily and - the at least one groove (GR) is arranged under a region between an arrangement of the first chip group and an arrangement of the second chip group of the heat radiation plate (1). [6] Semiconductor module (100, 200, 300, 400, 500, 600, 700) according to claim 1, wherein: - the plurality of semiconductor chips (5) comprises: - parallel connected and adjacent first semiconductor chips (IGBT) and - second semiconductor chips (FWD) which have a lower power consumption than that of the first semiconductor chips (IGBT), and - the at least one groove (GR) is arranged in a region below a region between the first semiconductor chips (IGBT) and the second semiconductor chips (FWD) of the heat radiation plate (1). [7] Semiconductor module (100, 200, 300, 400, 500, 600, 700) according to claim 1, wherein: - the insulating substrate (2, 12) comprises a plurality of ceramic substrates (15) and - the at least one groove (GR) is arranged in a region below a region between the plurality of ceramic substrates (15) of the heat radiation plate (1). [8] Semiconductor module (100, 200, 300, 400, 500, 600, 700) according to claim 1, wherein: - the plurality of semiconductor chips (5) is arranged in a matrix and - the at least one groove (GR) is arranged under a region between the plurality of semiconductor chips (5) of the heat radiation plate (1).

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