Thin-film transmitter assembly substrate and electronic device containing it

Abstract

Electronic device comprising: a board (PNL) containing at least one thin-film transistor (Tr); and a control circuit (GDC) for controlling the panel (PNL), wherein the panel (PNL) contains: a substrate (600); a first electrode (610) which is arranged on the substrate (600); a first insulating film (620) arranged on the first electrode (610); a hole (621) in the first insulating film (620), wherein the hole (621) exposes a section of the first electrode (610); an active layer (630) which is arranged on and in contact with a section of the first insulating film (620) and with the exposed section of the first electrode (610); a second insulating film (640) arranged on top of the active layer (630); a gate electrode (650) which is arranged on the second insulating film (640); a third insulating film (660) arranged on the gate electrode (650); and a second electrode (670) and a third electrode (680) arranged on the third insulating film (660), wherein the second electrode (670) and the third electrode (680) are spaced apart from each other and electrically connected to the active layer (630), wherein the active layer (630) contains a first channel region (731) and a second channel region (732) which are spaced apart from each other, and wherein the first channel area (731) and the second channel area (732) each contain an area that is positioned on a side surface of the first insulating film (620) that defines the hole (621), wherein the active layer (630) comprises a first active layer (1031) arranged on a section of the first insulating film (620) and on a first section of the hole (621), and a second active layer (1032) arranged on another section of the first insulating film (620) and on a remaining second section of the hole (621), wherein the first active layer (1031) comprises: a first section (1031a) in which N + -Obstacle ions are implanted; a second section (1032a) spaced apart from the first section (1031a) and arranged on the exposed section of the first electrode (610) in the hole (621) of the first insulating film (620); and a third section (1033a) between the first section (1031a) and the second section (1032a), wherein the third section (1033a) comprises a section arranged on the first insulating film (620), a section arranged on a side face of the first insulating film (620), and a section arranged on the first electrode (610) exposed in the hole (621) of the first insulating film (620), and the second active layer contains (1032): a fourth section (1031b), in which P + -Obstacle ions are implanted; a fifth section (1032b) spaced apart from the fourth section (1031b) and arranged on the exposed section of the first electrode (610) in the hole (621); and a sixth section (1033b) between the fourth section (1031b) and the fifth section (1032b), wherein the sixth section (1033b) includes a section arranged on the first insulating film (620), a section arranged on the side surface of the first insulating film (620), and a section arranged on the first electrode (610) in the hole (621) of the first insulating film (620).

Description

BACKGROUND Technical area

[0001] Embodiments of the disclosure relate to a thin-film transistor array substrate and an electronic device containing it. Description of related field

[0002] The growth of the intelligent society leads to an increased demand for various types of electronic devices, such as display devices or lighting devices. Such an electronic device might include a panel with data lines and gate lines, a data driver for controlling the data lines, and a gate driver for controlling the gate lines.

[0003] To control a board, which is a core component of such an electronic device, numerous transistors with different functions can be arranged.

[0004] Consequently, the tablet manufacturing process is inevitably complicated and difficult. Therefore, the transistor's device performance may be degraded if ease of processing is a priority.

[0005] Furthermore, the transistor should be more integrated to achieve excellent properties in the electronic device, such as high resolution. However, since it is technically difficult to reduce the transistor's area indefinitely due to process and design problems, it is advantageous to control the area occupied by the transistor without degrading its properties.

[0006] US 2020 / 0119154A1 describes a thin-film transistor with a first electrode, an insulating layer with a side wall, an active layer with a channel-forming side wall region arranged thereon, and a second electrode connected thereto.

[0007] US 2020 / 0161475A1 describes an electronic device comprising a panel and a transistor, the channel area of ​​which extends partly along the side surface and partly on the top surface of an insulation pattern.

[0008] US 2020 / 0312991A1 describes a field-effect transistor with a substrate, source, semiconductor area arranged above it, drain, a polarization layer placed on top of it, and a gate next to the semiconductor end.

[0009] US 2016 / 0300899A1 describes a thin-film transistor with a ring-shaped gate, the active layer of which consists of three areas, the slanted third area carrying the channel which lies at least partially inside the gate ring. SUMMARY

[0010] The task is to create a thin-film transistor arrangement substrate (or thin-film transistor assembly) containing a vertical structure transistor capable of implementing a short channel and integration, and an electronic device containing it.

[0011] Another task is to create a thin-film transistor array substrate that occupies a reduced area and has improved current characteristics, and an electronic device that incorporates it.

[0012] It is yet another task to create a thin-film transistor array substrate containing a vertically structured transistor capable of element miniaturization and a short channel as well as improved ease of processing, and an electronic device containing it.

[0013] One or more of these problems are solved by the features of the independent claims. According to one aspect of the invention, an electronic device comprises a display panel containing at least one thin-film transistor and a control circuit for controlling the panel.The board can include a substrate, a first electrode arranged on the substrate, a first insulating film containing a hole exposing a section of an upper surface of the first electrode, an active layer in contact with a section of an upper surface of the first insulating film and with a section of an upper surface of the first electrode, a second insulating film arranged on the active layer, a gate electrode arranged on the second insulating film, a third insulating film arranged on the gate electrode, and a second electrode and a third electrode arranged on the third insulating film, spaced apart from each other and electrically connected to the active layer.The active layer contains a first channel area and a second channel area that are spaced apart from each other, with the first channel area and the second channel area containing an area that is positioned on a lateral surface of the hole of the first insulating film.

[0014] According to one aspect of the disclosure, a thin-film transistor array substrate comprises a substrate, a first electrode arranged on the substrate, a first insulating film containing a hole exposing a section of an upper surface of the first electrode, an active layer in contact with a section of an upper surface of the first insulating film and with the section of the upper surface of the first electrode, a second insulating film arranged on the active layer, a gate electrode arranged on the second insulating film, a third insulating film arranged on the gate electrode, and a second electrode and a third electrode arranged on the third insulating film, spaced apart from each other and electrically connected to the active layer, the active layer comprising a first channel region and a second channel region spaced apart from each other.contains and wherein the first channel area and the second channel area contain an area that is positioned on a side face of the hole of the first insulating film.

[0015] According to one aspect, an electronic device comprises a board containing at least one thin-film transistor; and a drive circuit coupled to and driving the board; wherein the board comprises a substrate; a first electrode arranged on the substrate; a first insulating film arranged on the first electrode; a hole within the first insulating film, the hole exposing a section of an upper surface of the first electrode; an active layer in contact with a section of an upper surface of the first insulating film and with the section of the upper surface of the first electrode; a second insulating film arranged on the active layer; a gate electrode arranged on the second insulating film; and a third insulating film arranged on the gate electrode.and a second electrode and a third electrode arranged on the third insulating film, wherein the second electrode and the third electrode are spaced apart from each other and electrically connected to the active layer, wherein the active layer comprises a first channel region and a second channel region spaced apart from each other, and wherein the first channel region and the second channel region comprise a region positioned on a side face of the hole of the first insulating film.

[0016] The active layer can be an oxide semiconductor.

[0017] The active layer can comprise a first region and a second region, which are arranged on the section of the upper surface of the first insulating film and spaced apart from each other. Furthermore, the active layer can comprise a third region, which is arranged between the first region and the second region and is located on the section of the upper surface of the insulating film, on the side face of the hole in the first insulating film, and on the first electrode in the hole.

[0018] The gate electrode can overlap the third region of the active layer.

[0019] The second electrode can be in contact with the first area of ​​the active layer and / or the third electrode can be in contact with the second area of ​​the active layer.

[0020] The third area can contain the first channel area and the second channel area, which are spaced apart from each other.

[0021] The first channel region can originate from the first region of the active layer. The first channel region can be located on the section of the upper surface of the first insulating film and / or on a section of the side surface of the hole in the first insulating film and / or on the section of the upper surface of the first electrode that overlaps the hole.

[0022] The second channel area can originate from the second area of ​​the active layer.

[0023] The length of the first channel area and the length of the second channel area can be directly proportional to the height of the first insulating film.

[0024] The third region may contain a connecting section positioned between the first and second channel regions, for example, when the transistor containing the active layer is in an on-state. The resistance value of the connecting section may be higher than the resistance values ​​of the first and second channel regions combined.

[0025] The first electrode can contain at least one depression. A section of the depression in the first electrode can overlap the entire hole in the first insulating film.

[0026] The length of the first channel area and the length of the second channel area can be directly proportional to the height of the depression of the first electrode.

[0027] According to the invention, the active layer comprises a first active layer arranged on a section of the upper surface of the first insulating film and on a section of the hole. The active layer comprises a second active layer arranged on another section of the upper surface of the first insulating film and on a remaining section of the hole.

[0028] According to the invention, the first active layer comprises a first section, a second section spaced apart from the first section and located on the upper surface of the first electrode within the hole of the first insulating film, and a third section located between the first section and the second section. The third section comprises a section located on an area that does not overlap the hole of the first insulating film, a section located on an area that overlaps the side surface of the hole of the first insulating film, and a section located on the upper surface of the first electrode within the hole of the first insulating film. The first section is an area where N+ impurity ions are implanted.

[0029] The third section of the first active layer can be a channel area of ​​the first active layer. The length of the third section can be directly proportional to the height of the hole in the first insulating film.

[0030] According to the invention, the second active layer comprises a fourth section, a fifth section spaced apart from the fourth section and located on the upper surface of the first electrode within the hole of the first insulating film, and a sixth section located between the fourth and fifth sections. The sixth section comprises a section located on an area that does not overlap the hole of the first insulating film, a section located on an area that overlaps the side surface of the hole of the first insulating film, and a section located on the upper surface of the first electrode within the hole of the first insulating film. The fourth section is an area in which P+ impurity ions are implanted.

[0031] The sixth section of the second active layer can be a channel area of ​​the second active layer. The length of the sixth section can be proportional to the height of the hole in the first insulating film.

[0032] In the hole of the first insulating film, a section of the first active layer can overlap a section of the second active layer.

[0033] The first electrode can be a source electrode, and the second and third electrodes can be drain electrodes.

[0034] The same signal can be applied to the second and third electrodes. Different signals can be applied to the second and third electrodes.

[0035] The width of the first electrode can be greater than the width of the active layer.

[0036] According to one aspect of the invention, a thin-film transistor assembly comprises: a first electrode on a substrate, wherein the first electrode has a first surface; a first insulating film on the first surface of the first electrode; a hole passing through the first insulating film and exposing the first surface of the first electrode; an active layer on the first insulating film and on the hole, wherein the active layer is in contact with the first surface of the first electrode at the hole; a second insulating film on the active layer; a gate electrode on the second insulating film; a second electrode on the active layer, wherein the second electrode passes through the second insulating film so that it is electrically connected to the active layer;and a third electrode on the active layer, wherein the third electrode is spaced apart from and opposite the second electrode, the third electrode passing through the second insulating film so that it is electrically connected to the active layer.

[0037] The first insulating film may have a first inclined surface formed by the hole passing through it. The first insulating film may have a second surface opposite the first surface of the first electrode. The active layer may extend from the first surface of the first electrode at the hole to the first inclined surface of the first insulating film and / or may at least partially overlap the second surface of the first insulating film.

[0038] The second electrode can overlap a section of the active layer that at least partially overlaps the second surface of the first insulating film.

[0039] The first insulating film may have a second inclined surface opposite the first inclined surface formed by the hole passing through the first insulating film. The first insulating film may have a third surface opposite the first surface of the first electrode. The active layer may extend from the first surface of the first electrode at the hole to the second inclined surface of the first insulating film and / or may at least partially overlap the third surface of the first insulating film.

[0040] The third electrode can overlap a section of the active layer that at least partially overlaps the third surface of the first insulating film. The second surface of the first insulating film and the third surface of the first insulating film can be spaced apart and / or coplanar.

[0041] The first electrode may contain a second surface adjacent to the first surface, with the first surface of the first electrode being located within a depression section of the first electrode. The first electrode may contain an inclined surface between the first surface and the second surface. The width of the hole extending across the first insulating film may be less than the width of the depression section.

[0042] The active layer and / or the second insulating film and / or the gate electrode may contain a recessed section at a corresponding location of the depression section of the first electrode.

[0043] According to one aspect of the disclosure, an electronic device comprises at least one thin-film transistor, wherein the at least one thin-film transistor includes: a first electrode on a substrate, the first electrode having a first surface; a first insulating film on the first surface of the first electrode; a hole passing through the first insulating film and exposing the first surface of the first electrode; an active layer on the first insulating film and on the hole, the active layer being in contact with the first surface of the first electrode at the hole; a second insulating film on the active layer; a gate electrode on the second insulating film; a second electrode on the active layer, the second electrode passing through the second insulating film so that it is electrically connected to the active layer;a third electrode on the active layer, wherein the third electrode is spaced apart from and opposite the second electrode, the third electrode passing through the second insulating film so that it is electrically connected to the active layer.

[0044] According to embodiments of the disclosure, a thin-film transistor array substrate containing a vertical structure transistor capable of implementing a short channel and integration, and an electronic device containing it, can be created.

[0045] According to embodiments of the disclosure, a thin-film transistor array substrate, which occupies a reduced area and has improved current characteristics, and an electronic device containing it can be created.

[0046] According to embodiments of the disclosure, a thin-film transistor array substrate containing a vertically structured transistor capable of element miniaturization and short channel capability, as well as improved processing efficiency, and an electronic device containing it can be created. DESCRIPTION OF THE MULTIPLE DRAWING VIEWS

[0047] The above and further tasks, features and advantages of the present disclosure will become clearer from the following detailed description together with the accompanying drawings; they show: Fig. 1 a view schematically representing a system configuration of an electronic device according to embodiments of the disclosure; Fig. 2A a view that represents an example of a system implementation of an electronic device according to embodiments of the disclosure; Fig. 2B a view schematically representing a structure of a subpixel contained in an active area when an electronic device is a display device, according to embodiments of the disclosure; Fig. 3 a view that represents a structure of a subpixel SP, where a panel PNL is a panel of organic light-emitting diodes (OLED panel), according to embodiments of the disclosure; Fig. 4 a view showing an exemplary 3T-1C structure (3-transistor-1-capacitor structure) in which a subpixel SP further contains a second transistor T2 which is electrically connected between a second node N2 of a drive transistor DRT and a reference voltage line RVL; Fig. 5 a view schematically representing a gate drive circuit GDC arranged on a panel PNL according to embodiments of the disclosure; Fig. 6 a view representing a switch-off state (OFF state) of a transistor arranged in an electronic device according to embodiments of the disclosure; Fig. 7 a view representing an ON state of a transistor arranged in an electronic device according to embodiments of the disclosure; Fig. 8 and Fig. 9 views showing a cross-sectional structure of a transistor according to embodiments of the disclosure; Fig. 10 and Fig. 11 views showing the structure of a transistor, which is a transistor made of polycrystalline silicon; Fig. 12 a view showing a vertically structured transistor connected to a pixel electrode when the vertically structured transistor is arranged in a subpixel according to embodiments of the disclosure; Fig. 13 a view showing a vertically structured transistor connected to an organic light-emitting diode when the vertically structured transistor is arranged in a subpixel according to embodiments of the disclosure; Fig. 14 a view representing a structure in which a transistor is applied to two subpixels according to embodiments of the disclosure; and Fig. 15 a view which presents a comparison between the S-coefficient (SS) of a transistor Tr and its corresponding increment of current according to embodiments of the disclosure and the S-coefficient (SS) of a transistor Tr and its corresponding increment of current according to a comparative example. DETAILED DESCRIPTION

[0048] In the following description of examples or embodiments of the present disclosure, reference is made to the accompanying drawings, which show by way of example specific examples or embodiments that can be implemented and in which the same reference numerals and symbols may be used to designate the same or similar components, even if they are shown in different accompanying drawings. Furthermore, in the following description of examples or embodiments of the present disclosure, detailed descriptions of well-known functions and components included herein are omitted where it is determined that the description would make the subject matter of some embodiments of the present disclosure rather unclear.The terms used here, such as "containing," "exhibiting," "encompassing," "forming," "consisting of," and "formed of," are generally intended to permit the addition of other components, unless the terms are used with the word "only." As used here, singular forms are intended to include plural forms, unless the context clearly indicates otherwise.

[0049] To describe elements of the present revelation, terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used. Each of these terms is not used to determine the nature, order, sequence, or number of elements, etc., but is used solely to distinguish the respective element from other elements.

[0050] When it is mentioned that a first element is "connected or coupled," "in contact," or "overlapping," etc., with a second element, this is to be interpreted as meaning that the first element can not only be "directly connected or coupled," or "in direct contact or overlapping," with the second element, but that a third element can also be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled," "in contact or overlapping," etc., via a fourth element. The second element can be contained within at least one of the two or more elements that are "connected or coupled," "in contact or overlapping," etc., with each other.

[0051] When relative terms such as "after", "subsequent", "next", "before" and the like are used to describe processes or operations of elements or configurations or sequences or steps in operating, processing, manufacturing procedures, these terms may be used to describe non-sequential or non-sequential processes or operations unless the term "direct" or "immediate" is used together with them.

[0052] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, and the like shown in the accompanying drawings to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited to them.

[0053] One dimension, which includes the size and thickness of each component shown in the drawing, is shown for convenience of description and the present disclosure is not limited to the size and thickness of the component shown.

[0054] Whenever dimensions, relative sizes, etc., are mentioned, it should also be noted that these numerical values ​​for elements or characteristics, or corresponding information (e.g., level, range, etc.), include a tolerance or error range (e.g., approximately 5%–10%) that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Furthermore, the term "capable" encompasses all meanings of the term "can."

[0055] The following section describes various embodiments of the disclosure in detail with reference to the attached drawings.

[0056] Fig. Figure 1 is a view that schematically represents a system configuration of an electronic device according to embodiments of the disclosure.

[0057] Electronic devices according to embodiments of the disclosure may include display devices, lighting devices, light-emitting devices, and the like. For the sake of clarity, the following description focuses primarily on display devices. However, embodiments of the disclosure may also be applied to various other electronic devices, such as lighting devices or light-emitting devices, as well as to display devices, as long as they contain transistors.

[0058] According to embodiments of the disclosure, an electronic device may include a PNL panel for displaying images or emitting light and a control circuit for controlling the PNL panel.

[0059] A PNL table can contain multiple data lines DL, multiple gate lines GL, and multiple subpixels SP, which are defined by the multiple data lines DL and by the multiple gate lines GL and are arranged in a matrix type.

[0060] In the PNL table, the multiple data lines DL and the multiple gate lines GL can be arranged intersectingly. For example, the multiple gate lines GL can be arranged in rows or columns, and the multiple data lines DL can be arranged in columns or rows. For the sake of clarity, it is assumed that the multiple gate lines GL are arranged in rows and that the multiple data lines DL are arranged in columns.

[0061] For example, depending on the subpixel structure, the PNL board can have different types of signal lines, as well as multiple data lines (DL) and multiple gate lines (GL). Furthermore, the PNL board can have drive voltage lines, reference voltage lines, or common voltage lines.

[0062] The PNL board can be different types of boards, such as a liquid crystal display board (LCD board) and an organic light-emitting diode board (OLED board).

[0063] The type of signal lines arranged on the PNL board can be varied, for example, depending on the subpixel structure or the board type. According to this disclosure, the concept of a signal line can include electrodes to which signals are applied.

[0064] The PNL board can contain an active area A / A for displaying illustrations or images and a non-active area N / A in which no image is displayed, surrounding the active area A / A. The non-active area N / A is also referred to here as a border area.

[0065] The active area A / A contains several subpixels SP for displaying images.

[0066] The inactive area N / A has a terminal block for electrical connection to a data driver DDR and may have multiple data link lines for connecting the terminal block to the multiple data lines DL. The multiple data link lines may be extensions of the multiple data lines DL to the inactive area N / A or may be separate patterns electrically connected to the multiple data lines DL.

[0067] Furthermore, the inactive section N / A can contain gate-related lines for transmitting a voltage (or signal) necessary for gate control to a gate driver GDR via connection pads that are electrically connected to the data driver DDR. These gate-related lines can include, for example, clock lines for transmitting clock signals, gate voltage lines for transmitting gate voltages VGH and VGL, and gate control signal lines for transmitting various control signals necessary for generating sample signals. Unlike the gate lines GL, which are located in the active section A / A, the gate-related lines are located in the inactive section N / A.

[0068] The control circuit can include the data driver DDR for controlling the multiple data lines DL, the gate driver GDR for controlling the multiple gate lines GL, and a controller CTR for controlling the data driver DDR and the gate driver GDR.

[0069] The DDR data driver can control the multiple DL data lines by outputting a data voltage to the multiple DL data lines.

[0070] The gate driver GDR can control the multiple gate lines GL by outputting sampling signals to the multiple gate lines GL.

[0071] The CTR controller can control the operation of the DDR data driver and the GDR gate driver by supplying various control signals DCS and GCS, which are necessary for the operation of the DDR data driver and the GDR gate driver. Furthermore, the CTR controller can supply image data DATA to the DDR data driver.

[0072] The CTR controller begins sampling in accordance with a timing control implemented in each individual frame, converts the externally inputted image data into image data DATA suitable for the data signal format used in the DDR data driver, outputs the image data DATA and controls the data control at a time suitable for sampling.

[0073] To control the data driver DDR and the gate driver GDR, the controller CTR receives timing control signals from the outside (e.g., from a host system), such as a vertical synchronization signal (VSync), a horizontal synchronization signal (HSync), an input data enable signal (DE), or a clock signal CLK, generates various control signals, and outputs the control signals to the data driver DDR and the gate driver GDR.

[0074] As an example, the CTR controller for controlling the GDR gate driver outputs various gate control signals GCS, which include a gate start pulse (GSP), a gate shift clock (GSC) and a gate output enable signal (GOE).

[0075] To control the DDR data driver, the CTR controller outputs various data control signals DCS, which include, for example, a Source Start Pulse (SSP), a Source Sample Clock (SSC), and a Source Output Enable (SOE) signal.

[0076] The CTR controller can be a timing controller used in typical display technology, or a control device that can perform other control functions as well as the functions of the timing controller.

[0077] The CTR controller can be implemented as a component separate from the DDR data driver, or the CTR controller can be implemented together with the DDR data driver as an integrated circuit.

[0078] The DDR data driver receives the image data DATA from the CTR controller and applies a data voltage to the multiple DL data lines, thereby controlling them. The DDR data driver is also referred to here as a source driver.

[0079] The DDR data driver can exchange various signals with the CTR controller via different interfaces.

[0080] The gate driver GDR controls the multiple gate lines GL by successively supplying sample signals to the multiple gate lines GL. The gate driver GDR is also referred to here as a sampler driver.

[0081] The gate driver GDR supplies sequential sampling signals of an on voltage or an off voltage to the multiple gate lines GL according to the control of the controller CTR.

[0082] When a specific gate line is opened by the gate driver GDR, the data driver DDR converts the image data DATA received by the controller CTR into an analog data voltage and supplies the analog data voltage to the several data lines DL.

[0083] For example, depending on control schemes or panel designs, the DDR data driver may only be positioned on one side (e.g., on the top or bottom side) of the PNL panel, and in some cases, the DDR data driver may be positioned on either of the two opposite sides (e.g., both on the top and bottom side) of the PNL panel.

[0084] For example, depending on control schemes or panel designs, the gate driver GDR may only be positioned on one side (e.g., on the left or right side) of the panel PNL, and in some cases the gate driver GDR may be positioned on either of the two opposite sides (e.g., both on the left and on the right side) of the panel PNL.

[0085] The DDR data driver can contain one or more integrated source driver circuits (SDICs).

[0086] Each integrated source driver circuit (SDIC) can contain a shift register, a buffer circuit, a digital-to-analog converter (DAC), and an output buffer. In some cases, the DDR data driver may also include one or more analog-to-digital converters (ADCs).

[0087] Each integrated source driver circuit (SDIC) can be connected to the contact pad of the PNL board in an automatic foil bonding (TAB) or chip-on-glass (COG) configuration, or it can be mounted directly on the PNL board. In some cases, each SDIC can be integrated and mounted on the PNL board. Each SDIC can also be implemented in a chip-on-film (COF) configuration. In this case, each SDIC can be mounted on a circuit film and electrically connected to the PNL board's data lines (DL) via the circuit film.

[0088] The gate driver GDR can contain multiple gate drive circuits GDC. Each of these multiple gate drive circuits can correspond to multiple gate lines GL.

[0089] Each gate drive circuit (GDC) can contain, for example, a shift register and a level converter.

[0090] Each gate drive circuit (GDC) can be connected to the contact pad of the PNL board in an automatic foil bonding (TAB) or chip-on-glass (COG) configuration. Each gate drive circuit (GDC) can be implemented in a chip-on-film (COF) configuration. In this case, each gate drive circuit (GDC) can be mounted on a circuit film and electrically connected to the gate lines (GL) of the PNL board via the circuit film. Each gate drive circuit (GDC) can be implemented in a gate-in-panel (GIP) configuration and embedded in the PNL board. In other words, each gate drive circuit (GDC) can be formed directly on the PNL board.

[0091] Fig. 2A is a view that represents an example of a system implementation of an electronic device according to embodiments of the disclosure. Fig. 2B is a view that schematically represents a structure of a subpixel contained in an active area when an electronic device is a display device according to embodiments of the disclosure.

[0092] Based on Fig. 2A The data driver DDR can be implemented in the electronic device according to embodiments of the disclosure and the various types (TAB, COG, COF etc.) in a chip-on-film type (COF type) and the gate driver GDR can be implemented in a gate-in-panel type (GIP type) under various types (TAB, COG, COF, GIP etc.).

[0093] The DDR data driver can contain one or more integrated source driver circuits (SDICs). Fig. 2A represents an example in which the DDR data driver is implemented with several integrated source driver circuits SDIC.

[0094] If the DDR data driver is implemented in a COF type, any SDIC integrated source driver circuit implementing the DDR data driver can be mounted on the source-side SF circuit film.

[0095] One side of the source-side circuit film SF can be electrically connected to the connection area section (a group of connection areas) that is present in a non-active area N / A of the panel PNL.

[0096] On the source-side circuit film SF, lines for electrically connecting the integrated source driver circuit SDIC and the panel PNL can be arranged.

[0097] The electronic device may include one or more printed circuit boards (SPCB) for circuit interconnection between multiple integrated source driver circuits (SDIC) and other devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0098] The other side of the source-side circuit film SF, on which the integrated source driver circuit SDIC is mounted, can be connected to one or more source printed circuit boards SPCB.

[0099] In other words, one side of the source-side circuit film SF, on which the integrated source driver circuit SDIC is mounted, can be electrically connected to the inactive area N / A of the board PNL, and the other side of it can be electrically connected to the source printed circuit board SPCB.

[0100] A controller CTR can be arranged on the control board CPCB to control the operation of, for example, the data driver DDR and the gate driver GDR.

[0101] Furthermore, an integrated power management circuit PMIC can be arranged on the control board CPCB for supplying various voltages or currents to the board PNL, the data driver DDR and the gate driver GDR, or for controlling various voltages or currents that are to be supplied to them.

[0102] The source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be interconnected by at least one connecting element (CBL). The connecting element (CBL) can be, for example, a flexible printed circuit board (FPC) or a flexible ribbon cable (FFC).

[0103] One or more source printed circuit boards (SPCBs) and control printed circuit boards (CPCBs) can be integrated into a printed circuit board.

[0104] If the gate driver GDR is implemented in a gate-in-panel type (GIP type), the multiple gate drive circuits GDC contained in the gate driver GDR can be formed directly on the inactive area N / A of the panel PNL.

[0105] Each of the multiple gate drive circuits GDC can output a corresponding scanning signal SCAN to a corresponding gate line GL arranged in the active area A / A in the panel PNL.

[0106] The multiple gate drive circuits GDC arranged on the PNL board can receive various signals (e.g. clock signal, high-level gate voltage (VGH), low-level gate voltage (VGL), start signal (VST), reset signal (RST), etc.) that are necessary to generate the sampling signal via the gate drive-related lines located in the inactive area N / A.

[0107] The gate-related lines located in the non-active area N / A can be electrically connected to the source-side circuit film SF, which is located closest to the multiple gate-drive circuits GDC.

[0108] The multiple subpixels SP can be arranged within the active area A / A. For example, the multiple subpixels SP can contain an emission area EA and a non-emission area NEA.

[0109] The non-emission region NEA can contain several transistors DRT, T1, and T2. The electrode that overlaps the emission region EA can be electrically connected to at least one transistor DRT located in the non-emission region NEA.

[0110] This will be demonstrated below using the following examples. Fig. 3 and Fig. 4 discussed in detail.

[0111] Fig. Figure 3 is a view that represents a structure of a subpixel SP when a panel PNL is an organic light-emitting diode (OLED) panel according to embodiments of the disclosure.

[0112] Based on Fig. 3 Each subpixel SP in the display panel PNL, which is an OLED panel, can further include a first transistor T1 for transmitting a data voltage Vdata to a first node N1, which corresponds to a gate node of the drive transistor DRT, and to a storage capacitor Cst for maintaining the data voltage Vdata, which corresponds to a picture signal voltage, or a voltage corresponding to the data voltage Vdata, for the time of a single frame.

[0113] The organic light-emitting diode (OLED) can include a first electrode 301 (an anode electrode or a cathode electrode), an organic layer 302 containing at least one light-emitting layer, and a second electrode 303 (a cathode electrode or anode electrode).

[0114] As an example, a base voltage EVSS can be applied to the second electrode 303 of the organic light-emitting diode OLED.

[0115] The control transistor DRT supplies a control current to the organic light-emitting diode OLED and thereby controls the organic light-emitting diode OLED.

[0116] The control transistor DRT contains the first node N1, the second node N2 and the third node N3.

[0117] The first node N1 of the drive transistor DRT is a node that corresponds to the gate node and can be electrically connected to the source node or the drain node of the first transistor T1.

[0118] The second node N2 of the control transistor DRT can be electrically connected to the first electrode 301 of the organic light-emitting diode OLED and can be the source node or the drain node.

[0119] The third node N3 of the drive transistor DRT can be a node to which a drive voltage EVDD is applied, can be electrically connected to a drive voltage line DVL to supply the drive voltage EVDD, and can be the drain node or the source node.

[0120] The control transistor DRT and the first transistor T1 can be implemented as n-transistors or as p-transistors.

[0121] The first transistor T1 can be electrically connected to the data line DL and to the first node N1 of the control transistor DRT and can receive a sampling signal SCAN via the gate line and the gate node and be controlled by this signal.

[0122] The first transistor T1 can be switched on by the sampling signal SCAN, whereby it transmits the data voltage Vdata supplied by the data line DL to the first node N1 of the control transistor DRT.

[0123] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the control transistor DRT.

[0124] The storage capacitor Cst is an external capacitor that is deliberately designed to be outside the drive transistor DRT, but is not a parasitic capacitor (e.g. Cgs or Cgd), which is an internal capacitor located between the first node N1 and the second node N2 of the drive transistor DRT.

[0125] The structure of each exemplary in Fig. The subpixel shown in Figure 3 is a 2T-1C structure (2-transistor-1-capacitor structure), which is merely an example for the description and may further contain one or more transistors or, in some cases, one or more capacitors. The multiple subpixels may have the same structure, or some of the multiple subpixels may have different structures.

[0126] Fig. Figure 4 is a view that shows an example of a 3T-1C (3-transistor-1-capacitor) structure in which a subpixel SP further contains a second transistor T2 that is electrically connected between a second node N2 of the drive transistor DRT and a reference voltage line RVL.

[0127] Based on Fig. 4. A second transistor T2 can be electrically connected between a second node N2 of a control transistor DRT and a reference voltage line RVL, and it can receive a second sampling signal SCAN2 via the gate node so that its on / off is controlled.

[0128] The drain node or the source node of the second transistor T2 can be electrically connected to the reference voltage line RVL, and the source node or the drain node of the second transistor T2 can be electrically connected to the second node N2 of the drive transistor DRT.

[0129] The second transistor T2 can be switched on, for example, during a display control period and can be switched on during a detection control period to detect the characteristic values ​​of the control transistor DRT or the characteristic values ​​of the organic light-emitting diode OLED.

[0130] The second transistor T2 can be switched synchronously with a relevant control timing (e.g. a display control timing or an initialization timing in the display control duration) by the second sampling signal SCAN2, whereby the reference voltage Vref supplied to the reference voltage line RVL is transferred to the second node N2 of the control transistor DRT.

[0131] This allows the second transistor T2 to be switched on synchronously with a relevant control timing (e.g. a sampling timing control in the display control duration) by the second sampling signal SCAN2, whereby the voltage of the second node N2 of the control transistor DRT is transferred to the reference voltage line RVL.

[0132] In other words, the second transistor T2 can control the voltage state of the second node N2 of the drive transistor DRT or transfer the voltage of the second node N2 of the drive transistor DRT to the reference voltage line RVL.

[0133] The reference voltage line RVL can be electrically connected to an analog-to-digital converter that detects the voltage of the reference voltage line RVL, converts the voltage into a digital value, and outputs detection data containing the digital value.

[0134] The analog-to-digital converter can be included in the integrated source driver circuit (SDIC) that implements the DDR data driver.

[0135] The acquisition data output from the analog-to-digital converter can be used to acquire the characteristic values ​​(e.g., the threshold voltage or the mobility) of the drive transistor DRT or the characteristic values ​​(e.g., the threshold voltage) of the organic light-emitting diode (OLED).

[0136] A storage capacitor Cst can be an external capacitor that is deliberately designed to be outside the drive transistor DRT, but not a parasitic capacitor (e.g. Cgs or Cgd), which is an internal capacitor that is present between the first node N1 and the second node N2 of the drive transistor DRT.

[0137] Both the control transistor DRT and the first transistor T1 and the second transistor T2 can be an n-type transistor or a p-type transistor.

[0138] The first sampling signal SCAN1 and the second sampling signal SCAN2 can be separate gate signals. In this case, the first sampling signal SCAN1 and the second sampling signal SCAN2 can be applied to the gate node of the first transistor T1 and the gate node of the second transistor T2, respectively, via different gate lines.

[0139] In some cases, the first sampling signal SCAN1 and the second sampling signal SCAN2 can be the same gate signals. In this case, the first sampling signal SCAN1 and the second sampling signal SCAN2 can be applied together via the same gate line to the gate node of the first transistor T1 and to the gate node of the second transistor T2.

[0140] The structure of each in Fig. 3 and Fig. The 4 subpixels shown are merely an example for the description and may also contain one or more transistors or, in some cases, one or more storage capacitors.

[0141] The multiple subpixels can have the same structure, or some of the multiple subpixels can have a different structure.

[0142] Fig. Figure 5 is a view schematically representing a gate drive circuit GDC arranged on a PNL board according to embodiments of the disclosure.

[0143] Based on Fig. 5. Each gate drive circuit GDC can contain a pull-up transistor Tup, a pull-down transistor Tdown, and a control switch circuit CSC.

[0144] The control switch circuit CSC is a circuit that controls the voltage of node Q, which corresponds to the gate node of the pull-up transistor Tup, and the voltage of node QB, which corresponds to the gate node of the pull-down transistor Tdown, and can contain multiple switches (e.g. transistors).

[0145] The pull-up transistor Tup is a transistor that supplies a gate signal Vgate to the gate line GL via the gate signal output node Nout. This signal corresponds to a first voltage level (e.g., the high voltage VGH). The pull-down transistor Tdown is a transistor that supplies a second voltage signal Vgate to the gate line GL via the gate signal output node Nout. This second voltage corresponds to a low voltage (e.g., the low voltage VGL). The pull-up transistor Tup and the pull-down transistor Tdown can be turned on at different timing settings.

[0146] The pull-up transistor Tup is electrically connected between a clock signal application node Nclk, to which the clock signal CLK is applied, and a gate signal output node Nout, which is electrically connected to the gate line GL, and is switched on or off by the voltage of node Q.

[0147] The gate node of the pull-up transistor Tup is electrically connected to node Q. The drain or source node of the pull-up transistor Tup is electrically connected to the clock signal application node Nclk. The source or drain node of the pull-up transistor Tup is electrically connected to the gate signal output node Nout, from which the gate signal Vgate is output.

[0148] The pull-up transistor Tup can be switched on by the voltage of node Q and outputs the gate signal Vgate with the voltage VGH at a high level to the gate signal output node Nout during the time period with a high level of the clock signal CLK.

[0149] The gate signal Vgate, output at the gate signal output node Nout, at a high level voltage VGH, is fed to the corresponding gate line GL.

[0150] The pulldown transistor Tdown can be electrically connected between the gate signal output node Nout and the base voltage node Nvss and is switched on or off by the voltage of node QB.

[0151] The gate node of the pulldown transistor Tdown is electrically connected to node QB. The drain or source node of the pulldown transistor Tdown is electrically connected to the base voltage node Nvss to receive a base voltage VSS, which is a constant voltage. The source or drain node of the pulldown transistor Tdown is electrically connected to the gate signal output node Nout, from which the gate signal Vgate is output.

[0152] The pulldown transistor Tdown is switched on by the voltage at node QB, outputting a low-level gate signal Vgate at the gate signal output node Nout, corresponding to the voltage VGL. This gate signal Vgate can then be applied to the corresponding gate line GL via the gate signal output node Nout, corresponding to the low-level voltage VGL. The low-level gate signal Vgate could, for example, be the base voltage VSS.

[0153] The control switch circuit (CSC) can contain two or more transistors and has main nodes such as a node Q, a node QB, a set node S (also called a start node), and a reset node R. In some cases, the control switch circuit (CSC) may also include an input node into which various voltages, such as the drive voltage VDD, are applied.

[0154] The node Q in the control switch circuit CSC is electrically connected to the gate node of the pull-up transistor Tup and repeats the charging and discharging process.

[0155] The QB node in the CSC control switch circuit is electrically connected to the gate node of the pulldown transistor Tdown and repeats the charging and discharging process.

[0156] The set node S in the control switch circuit CSC receives the set signal SET to indicate the start of the gate control of the corresponding gate control circuit GDC.

[0157] The set signal SET applied to the set node S can be a start signal VST that is input from outside the gate driver GDR, or it can be a feedback signal (carry-over signal) of the gate signal Vgate that is output by the gate drive circuit GDC of the preceding stage before the current gate drive circuit GDC.

[0158] The reset signal RST applied to the reset node R in the control switch circuit CSC can be a reset signal for simultaneously initializing the gate control circuits GDC of all stages, or it can be a carry signal input from another stage (preceding or subsequent stage).

[0159] The control switch circuit CSC charges node Q in response to the set signal SET and discharges node Q in response to the reset signal RST. The control switch circuit CSC can include an inverter circuit to charge or discharge both node Q and node QB with different timing.

[0160] As in Fig. As shown in Figure 3, the driver transistor DRT and the first transistor T1 can be arranged in each of the multiple subpixels SP in the active area A / A of the panel PNL, which corresponds to the OLED panel. However, the present embodiments are not limited to this and can be arranged in the active area A / A of the panel PNL, which corresponds to the OLED panel, as shown in Figure 3. Fig. As shown in diagram 4, three or more transistors are arranged.

[0161] As in Fig. As shown in 2A, various transistors (Tup, Tdown and transistors in the CSC) can also be used, which function as shown in Fig. The gate drive circuit GDC shown in Figure 5 is located in the non-active area N / A, which is the outside of the active area A / A of the PNL board, when the gate drive circuit GDC is implemented in a GIP type, i.e., when the gate drive circuit GDC is embedded in the PNL board.

[0162] The transistors arranged in the active region A / A and / or in the inactive region N / A of the PNL board exhibit device performance (e.g., mobility or on / off performance) that varies depending on the channel length of the active layer. Accordingly, a structure of a dual-type parallel transistor capable of improving device performance is described below.

[0163] Furthermore, a structure of a transistor is described which has a short channel and is free from the deterioration of current characteristics with a reduction of the area occupied by the transistor.

[0164] For example, the following description focuses mainly on a driver transistor of the electronic device, although transistors according to embodiments of the disclosure are not limited to this. For example, the description can also refer to T1 from Fig. 3, on T1 and T2 Fig. 4 and turn on Tup and Tdown Fig. 5 can be applied.

[0165] Fig. Figure 6 is a view representing a switched-off state (OFF state) of a transistor arranged in an electronic device according to embodiments of the disclosure. Fig. Figure 7 is a view representing an on-powered (ON) state of a transistor arranged in an electronic device according to embodiments of the disclosure.

[0166] Fig. 6 and Fig. 7 are cross-sectional views along line AB from Fig. 2B.

[0167] At least one of the transistors arranged in the electronic device according to embodiments of the disclosure can include a transistor Tr with a vertical structure in which a channel region 731, 732 is formed in a direction transverse to a direction of a surface of the substrate (e.g. an upper surface USS of the substrate 600) when it is driven.

[0168] For example, this means that the channel regions 731 and 732 of the active layer 630, which are contained in the vertically structured transistor Tr, include a region that is not parallel to the top surface USS of the structure 600. In general, the vertically structured transistor Tr can contain any structure that includes a region where the angle between the channel regions 731 and 732 of the active layer 630 and the substrate 600 is greater than 0° and less than 180°.

[0169] Based on Fig. In embodiment 7, a channel region 731 (or a first channel region 731) forms an angle α with respect to the upper surface USS of the substrate 600. More precisely, in embodiments in which a first electrode 610 is present, the first channel region 731 forms an angle α with respect to the upper surface of the first electrode 610. Similarly, a channel region 732 (or a second channel region 732) forms an angle β with respect to the upper surface USS of the substrate 600. More precisely, in embodiments in which a first electrode 610 is present, the second channel region 732 forms an angle β with respect to the upper surface of the first electrode 610. As described above, the angles α and β are greater than 0° and less than 180°. In some embodiments, the angle α of the first channel region 731 is equal to the angle β of the second channel region 732.According to other embodiments, the angle α of the first channel area 731 can be different from the angle β of the second channel area 732.

[0170] As in Fig. As shown in Figure 7, the first channel section 731 extends from a connecting section 733, located between the first channel section 731 and the second channel section 732, to a first section 631. The first channel section 731 is arranged along an inclined surface IS of the first insulating film 620 at an angle of inclination (e.g., angle α). Similarly, the second channel section 732 extends from the connecting section 733 to a second section 632. The second channel section 732 is arranged along an inclined surface of the second insulating film 620 at an angle of inclination (e.g., angle β).

[0171] Based on Fig. 6 and Fig. 7. According to embodiments of the disclosure, the transistor Tr can include a first electrode 610, an active layer 630, a gate electrode 650, a second electrode 670 and a third electrode 680.

[0172] For example, the first electrode 610 can be arranged on the substrate 600.

[0173] Although Fig. 6 and Fig. 7. If the first electrode 610 represents a structure in which it has a single layer, embodiments of the disclosure are not limited thereto and the first electrode 610 may have a multilayer structure of two or more layers.

[0174] The first electrode 610 can contain any of the metals such as aluminium (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta) and titanium (Ti) or alloys thereof, but embodiments of the disclosure are not limited thereto.

[0175] The first electrode 610 can be the source electrode of the transistor Tr.

[0176] A first insulating film 620 can be arranged on the substrate 600 and on the first electrode 610, the insulating film having at least one hole 621 that exposes a section (e.g. the exposed section EP) of an upper surface US of the first electrode 610.

[0177] The first insulating film 620 can contain an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON).

[0178] An active layer 630 can be arranged on the first insulating film 620 and on the first electrode 610.

[0179] The active layer 630 can be arranged on the side surface (e.g., on the inclined surface IS) of the first insulating film 620 in the hole 621 of the first insulating film 620 and can be arranged on the upper surface US of the first electrode 610. The active layer 630 can extend to the circumference of the hole 621 of the first insulating film 620.

[0180] More precisely, the active layer 630 can be arranged on a section of the upper surface UPS of the first insulating film 620 and can be arranged on the side surface (e.g., the inclined surface IS) of the first insulating film 620 in the hole 621 where the first insulating film 620 exposes the upper surface US of the first electrode 610. The active layer 630 can be in contact with the upper surface US of the first electrode 610 in the hole 621 of the first insulating film 620.

[0181] Accordingly, the active layer 630 can have a structure with at least one step. Although the exemplary figures show one step containing an inclined surface IS, other embodiments can contain multiple steps, each containing more than one.

[0182] The active layer 630 can, for example, be formed from an oxide semiconductor. If the active layer 630 is an oxide semiconductor, it can contain zinc oxide (ZnO) and / or zinc tin oxide (ZTO) and / or zinc indium oxide (ZIO) and / or indium oxide (InO) and / or titanium oxide (TiO) and / or indium gallium zinc oxide (IGZO) and / or indium zinc tin oxide (IZTO), although the active layer 630 is not limited to these components according to embodiments of the disclosure.

[0183] For example, the active layer 630 can contain an IGZO-based oxide semiconductor material (InGaZnO-based) (where the concentration of In can be greater than that of Ga), an IZO-based oxide semiconductor material (InZnO-based), an IGZTO-based oxide semiconductor material (InGaZnSnO-based), an ITZO-based oxide semiconductor material (InSnZnO-based), an FIZO-based oxide semiconductor material (FeInZnO-based), an oxide semiconductor material based on ZnO, an oxide semiconductor material based on SIZO (SiInZnO-based), or an oxide semiconductor material based on ZnON (Zn oxynitride-based).

[0184] Although Fig. 6 and Fig. 7. If the active layer 630 is a single layer, embodiments of the disclosure are not limited to this and the active layer 630 may have a multilayer structure of two or more layers.

[0185] A second insulating film 640 can be arranged on the active layer 630.

[0186] The second insulating film 640 can contain an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON).

[0187] The gate electrode 650 of the transistor Tr can be arranged on the second insulating film 640.

[0188] Although Fig. 6 and Fig. 7. If the gate electrode 650 represents a structure in which it has a single layer, embodiments of the disclosure are not limited thereto and the gate electrode 650 may have a multilayer structure of two or more layers.

[0189] The gate electrode 650 can contain any of the metals such as aluminium (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta) and titanium (Ti) or alloys thereof, but embodiments of the disclosure are not limited thereto.

[0190] The gate electrode 650 can overlap a section of both the first electrode 610 and the active layer 630.

[0191] The gate electrode 650 can overlap the hole 621 of the first insulating film 620.

[0192] A third insulating film 660 can be arranged on the gate electrode 650.

[0193] The third insulating film 660 can contain an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON).

[0194] The second electrode 670 and the third electrode 680 of the transistor Tr can be spaced apart from each other and arranged on the third insulating film 660.

[0195] The second electrode 670 can come into contact with the first area 631 of the active layer 630 via a contact hole provided in the second insulating film 640 and in the third insulating film 660.

[0196] The third electrode 680 can be in contact with the second area 632 of the active layer 630 via a further contact hole provided in the second insulating film 640 and in the third insulating film 660.

[0197] The second electrode 670 and the third electrode 680 can be the drain electrode of the transistor Tr.

[0198] The active layer 630, which is electrically connected to the second electrode 670 and to the third electrode 680, can contain a first area 631, a second area 632 and a third area 633.

[0199] As in Fig. 6 and Fig. As shown in Figure 7, the first area 631 and the second area 632 of the active layer 630 can be areas arranged on the first insulating film 620, and they can be doped areas (or conductive areas).

[0200] The third area 633 of the active layer 630 can be located between the first area 631 and the second area 632.

[0201] The third area 633 of the active layer 630 can be arranged from a section of the upper surface of the first insulating film 620 on the side surface of the hole 621 of the first insulating film 620 and can be arranged on the upper surface of the first electrode 610, overlapping the hole 621 of the first insulating film 620.

[0202] Based on Fig. 6. The resistance values ​​of the first region 631 and the second region 632 of the active layer 630 can be smaller than the resistance value of the third region 633 of the active layer 630 when the transistor Tr is in an OFF state (e.g., when no gate bias is applied).

[0203] In other words, the first and second regions 631 and 632 of the active layer 630 are doped regions (or conductive regions) and can therefore have a higher concentration of charge carriers (e.g. electrons) than the third region 633.

[0204] The first to third regions 631, 632, and 633 of the active layer 630 can be formed as a single unit. For example, the first to third regions 631, 632, and 633 of the active layer 630 can be formed continuously and interconnected. A width W defined by each opposite end of the active layer 630 can be greater than a width WW defined by each opposite end of the gate electrode 650. The width W of the active layer 630 can be smaller than that of the first electrode 610. As shown in Fig. As shown by the dotted lines in Figure 6, two opposite ends of the third region 633 of the active layer 630 can correspond to two opposite ends of the gate electrode 650.

[0205] The width of the first electrode 610 can be greater than the width W of the active layer 630. Accordingly, it is possible to prevent light incident from below the substrate 600 from reaching the active layer 630. The width W of the active layer 630 and the width of the first electrode 610 are lengths along a direction perpendicular to the direction in which the first electrode 610 is stacked on the substrate 600, and the width W of the active layer 630 can represent the shortest distance between the two opposite ends of the active layer 630.

[0206] In other words, since the first electrode 610 serves both as a light barrier (or light shield) and as the source electrode of transistor Tr, it is possible to simplify the structure of transistor Tr and the manufacturing process, while saving on manufacturing costs (since, for example, the additional manufacturing step of forming a light shield beneath the transistor is eliminated). That is, the new vertically structured transistor according to one or more embodiments not only creates an improved channel design, but also uses fewer components, which also results in fewer manufacturing steps and reduced costs.

[0207] The entire third area 633 of the active layer 630 can overlap the gate electrode 650 along the direction in which the first electrode 610 is stacked on the substrate 600.

[0208] Based on Fig. 7. In the active layer 630, channel areas 731 and 732 can be provided with a lower charge carrier concentration than other areas when the transistor Tr is in an ON state (e.g., when a gate bias is applied).

[0209] Channel areas 731 and 732 may be contained in the third area 633 of the active layer 630.

[0210] If no gate bias is applied to transistor Tr, the resistance value of the third region 633 is greater than the resistance values ​​of the first and second regions 631 and 632 of the active layer 630, so that charge carriers present in the first and second regions 631 and 632 may have difficulty moving to the third region 633.

[0211] In contrast, the charge carrier concentration in a sub-region of the third region 633 of the active layer 630, which overlaps the gate electrode 650, may be increased due to the gate field when a gate bias voltage is applied to the transistor Tr.

[0212] Accordingly, charge carriers present in the first and second regions 631 and 632 of the active layer 630 can move through the third region 633 to the first electrode 610.

[0213] In this case, one section of the third region 633 can be a path over which the charge carriers move, but the other section of the third region 633 cannot allow charge carriers to move over it.

[0214] The third region 633 of the active layer 630, in which charge carriers are moved while a gate bias is applied to the transistor Tr, can be defined as a first channel region 731 and as a second channel region 732.

[0215] In other words, when transistor Tr is in an ON state, the third area 633 of the active layer 630 can contain the first channel area 731, the second channel area 732 and a connecting section 733.

[0216] Based on Fig. 7 the first channel area 731 can originate from the first area 631 of the active layer 630 and be arranged on a section of the upper surface of the first insulating film 620 and can be arranged on the side surface of the hole 621 of the first insulating film 620 and be arranged up to a section of the upper surface of the first electrode 610 that overlaps the hole 621.

[0217] The second channel area 732 can originate from the second area 632 of the active layer 630 and can be arranged on a section of the upper surface of the first insulating film 620 and can be arranged on the side surface of the hole 621 of the first insulating film 620 and can be arranged up to a section of the upper surface of the first electrode 610 that overlaps the hole 621.

[0218] The connecting section 733 of the third area 633 can be in contact with the upper surface of the first electrode 610, which overlaps the hole 621 of the first insulating film 620, and can be arranged between the first channel area 731 and the second channel areas 732.

[0219] The first channel area 731 and the second channel area 732 can be arranged symmetrically with respect to the connecting section 733 of the third area 633.

[0220] The length of both the first channel area 731 and the second channel area 732 can be the sum of a first length of the area arranged on the first insulating film 620, a second length of the area arranged on the side surface (the side surface in the hole) of the first insulating film 620, and a third length of the area in contact with the upper surface of the first electrode 610.

[0221] The first and third lengths of both the first and second channel regions 731 and 732 can be lengths in a direction parallel to the surface of the substrate 600.

[0222] The second length of both the first and second channel regions 731 and 732 can correspond to the length of the side surface of the first insulating film 620 where the active layer 630 is located.

[0223] The length of both the first and second channel regions 731 and 732 of the active layer 630 includes the second length and can therefore be set by the length of the side surface of the first insulating film 620.

[0224] If the height T (the length in the direction in which the first electrode 610 is stacked on the substrate 600) of the first insulating film 620 is reduced, the length of the side surface of the first insulating film 620 is also reduced, and the lengths of the first and second channel regions 731 and 732 of the active layer 630 can also be reduced. In other words, the lengths of the first and second channel regions 731 and 732 of the active layer 630 can be directly proportional to the length of the side surface of the first insulating film 620.

[0225] In other words, instead of determining the lengths of the first and second channel regions 731 and 732 of the active layer 630 by a separate process (e.g. photolithography), in the vertically structured transistor Tr according to embodiments of the disclosure, it is possible to adjust the lengths of the first and second channel regions 731 and 732 of the active layer 630 only by adjusting the length (or height T of the first insulating film 620) of the side surface of the first insulating film 620.

[0226] When the transistor Tr is in an ON state according to embodiments of the disclosure, charge carriers moving from the first and second regions 631 and 632 of the active layer 630 can move through the first and second channel regions 731 and 732 to the first electrode 610.

[0227] Since the charge carriers in this case move along the shortest path, the charge carriers do not move to the third area 633, which is positioned far from the first area 631 and from the second area 632.

[0228] Accordingly, the connecting section 733 of the active layer 630 can be present between the first channel area 731 and the second channel area 732. The connecting section 733 can be positioned between the first channel area 731 and the second channel area 732, and the first and second channel areas 731 and 732 can be formed as a single unit with the connecting section 733.

[0229] Since charge carriers do not move to the junction 733 of the active layer 630 when the transistor Tr is in an ON state, the resistance value of the junction 733 of the active layer 630 can be higher than the resistance value of the first and second channel regions 731 and 732.

[0230] As in Fig. As shown in Figure 7, the transistor Tr, according to embodiments of the disclosure, can contain two drain electrodes (e.g., the second electrode 670 and the second electrode 680). The same signal can be applied to each drain electrode.

[0231] The structure of the transistor Tr with vertical structure according to embodiments of the disclosure is not limited thereto and different signals can be applied to the second electrode 670 and to the third electrode 680.

[0232] In other words, the gate electrode 650 (G) of transistor Tr can be connected to an input line Vin, which is connected to an external input terminal; the first electrode 610, which is the source electrode (S) of the vertically structured transistor Tr, can be connected to ground EVSS; and the same output line Vout or different output lines Vout can be connected to the second electrode 670 and to the third electrode 680, which are the drain electrodes (D, D1 D2).

[0233] Although the transistor Tr contains a source electrode, an active layer 630 and a gate electrode 650, the transistor Tr can thus have two channel regions 731 and 732 because it has two drain electrodes.

[0234] Meanwhile, horizontally structured transistors for small sizes require photolithography to reduce the channel length of the active layer. However, reducing the channel length is limited by the limitations of photolithography systems.

[0235] Furthermore, the transistors Tr formed in the electronic device (e.g. the PNL board) may have irregular, uneven channel area lengths, even though the photolithography system forms an active layer with a short channel.

[0236] In contrast, in the vertically structured transistor Tr according to one embodiment, a section of the active layer 630 and a section of the source electrode (e.g., the first electrode 610) can be in contact with each other at a step beneath the active layer 630, and the drain electrodes (e.g., the second electrode 670 and the third electrode 680) are included, to which the same or different signals are applied. Thus, photolithography is not required to form an active layer with a short channel area, since the vertically structured transistor Tr contains two channel areas 731 and 732 with short lengths.

[0237] According to embodiments of the disclosure, it is possible to have such an effect as if two transistors with a short channel area were arranged, without increasing the number of transistors Tr.

[0238] Accordingly, it is possible to improve current characteristics while reducing the area occupied by the transistor Tr.

[0239] Based on Fig. 6 and Fig. 7 is created by allowing the active layer 630 to have at least one step using the hole 621 of the first insulating film 620, in which the channel regions 731 and 732 have a direction that intersects the surface of the substrate 600. However, the structure is not limited to this according to the disclosure.

[0240] Fig. 8 and Fig. Figure 9 are views that represent a cross-sectional structure of a transistor according to embodiments of the disclosure.

[0241] Fig. 8 and Fig. 9 are cross-sectional views along line AB from Fig. 2B.

[0242] Essentially the same configurations and effects as described above are not repeated below.

[0243] Based on Fig. 8 and Fig. 9 According to embodiments of the disclosure, the transistor Tr can include a first electrode 610, an active layer 630, a gate electrode 650, a second electrode 670 and a third electrode 680.

[0244] The first electrode 610 can contain at least one depression 811.

[0245] The first insulating film 620 can be arranged on the substrate 600 where the first electrode 610 is located.

[0246] The first insulating film 620 can be arranged on a section of the upper surface of the first electrode 610. As shown in Fig. 8 and Fig. As shown in Figure 9, the first insulating film 620 can be arranged, for example, to expose a section of the upper surface of the first electrode 610 in an area that overlaps the recess 811 of the first electrode 610.

[0247] In other words, a section of the recess 811 of the first electrode 610 can overlap the entire hole 621 of the first insulating film 620.

[0248] Fig. 8 and Fig. Figure 9 represents the structure in which the first insulating film 620 is partially arranged in the recess 811 of the first electrode 610. However, the structure of the transistor Tr according to embodiments of the disclosure is not limited to this.

[0249] For example, the first insulating film 620 cannot overlap a section of the recess 811 of the first electrode 610.

[0250] In other words, the first insulating film 620 can be arranged to expose a section of the upper surface of the first electrode 610 in an area that overlaps the recess 811 of the first electrode 610.

[0251] An active layer 630 can be arranged on the first insulating film 620 and on the first electrode 610.

[0252] The active layer 630 can contain a first area 631, a second area 632 and a third area 633.

[0253] The active layer 630 can have a structure that covers the recess 811 of the first electrode 610. In other words, the active layer 630 can overlap the entire recess 811 of the first electrode 610 and can also be arranged in a surrounding area of ​​the recess 811 of the first electrode 610.

[0254] Accordingly, the active layer 630 can be formed in such a way that it has at least one step due to the depression 811 of the first electrode 610.

[0255] The first area 631 and the second area 632 of the active layer 630 can be in contact with the first insulating film 620.

[0256] A portion of the third region 633 of the active layer 630 can be in contact with the upper surface of the first electrode 610 in the recess 811 of the first electrode 610. The remaining portion of the third region 633 can be in contact with a portion of the upper surface of the first insulating film 620. For example, the remaining portion of the third region 633 can be in contact with the surface of the first insulating film 620 located in a region that does not overlap the recess 811 of the first electrode 610, and it can also be in contact with the surface of the first insulating film 620 located in the region corresponding to the recess 811 of the first electrode 610.

[0257] A second insulating film 640 can be arranged on the active layer 630.

[0258] A gate electrode 650 can be arranged on the second insulating film 640.

[0259] The gate electrode 650 can overlap a section of both the first electrode 610 and the active layer 630.

[0260] A section of the gate electrode 650 can overlap the entire recess 811 of the first electrode 610.

[0261] The gate electrode 650 cannot overlap a section of the active layer 630 in an area that does not overlap the recess 811 of the first electrode 610. For example, the gate electrode 650 cannot overlap either the first area 631 or the second area 632 of the active layer 630.

[0262] A third insulating film 660 can be arranged on the gate electrode 650.

[0263] The second electrode 670 and the third electrode 680 of the transistor Tr can be spaced apart from each other and arranged on the third insulating film 660.

[0264] As in Fig. As shown in Figure 8, the resistance values ​​of the first region 631 and the second region 632 of the active layer 630 can be lower than the resistance value of the third region 633 of the active layer 630 when the transistor Tr is in an OFF state (when no gate bias is applied).

[0265] As in Fig. As shown in Figure 9, channel areas 731 and 732 in the active layer 630 can have a lower charge carrier concentration than other areas when the transistor Tr is in an ON state (when a gate bias is applied).

[0266] When the transistor Tr is in an ON state, the third area 633 of the active layer 630 can contain the first channel area 731, the second channel area 732 and a connecting section 733.

[0267] Based on Fig. 9 the first channel area 731 can originate from the first area 631 of the active layer 630 and be arranged on a section of the upper surface of the first insulating film 620 and be arranged in an area corresponding to a section of the side surface of the recess 811 of the first electrode 610 and be arranged up to a section of the upper surface of the first electrode 610 that overlaps the recess 811.

[0268] The second channel area 732 can originate from the second area 632 of the active layer 630 and be arranged on a section of the upper surface of the first insulating film 620 and can be arranged in an area corresponding to a section of the side surface of the recess 811 of the first electrode 610 and can be arranged up to a section of the upper surface of the first electrode 610 that overlaps the recess 811.

[0269] The connecting section 733 of the third area 633 can be in contact with the upper surface of the first electrode 610 in the recess 811 of the first electrode 610 and can be arranged between the first channel area 731 and the second channel areas 732.

[0270] The first channel area 731 and the second channel area 732 can be arranged symmetrically with respect to the connecting section 733 of the third area 633.

[0271] Based on Fig. 8 and Fig. 9. The first channel region 731 forms an angle α' with respect to the upper surface USS of the substrate 600. More precisely, according to this embodiment, in which a first electrode 610 with a recess 811 is present, a lower surface BS of the first channel region 731 forms an angle α' with respect to an upper surface USR of the first electrode 610 in the recess 811. Similarly, the second channel region 732 forms an angle β' with respect to the upper surface USS of the substrate 600. More precisely, according to this embodiment, a lower surface of the second channel region 732 forms an angle β' with respect to the upper surface USR of the first electrode 610 in the recess 811. As described above, the angles α' and β' are greater than 0° and less than 180°. According to some embodiments, the angle α' of the first channel area 731 is equal to the angle β' of the second channel area 732.According to other embodiments, the angle α' of the first channel region 731 can differ from the angle β' of the second channel region 732. According to some embodiments in which a recess is present in the first electrode 610, the angle α' can be larger than the angle α (see ). Fig. 6 and Fig. 7). Similarly, the angle β' can be larger than the angle β (see Fig. 6 and Fig. 7) be.

[0272] According to one embodiment, as described in Fig. As shown in Figure 8, the width WR of the recess section 811 is greater than the width WA of the hole 621 (e.g., the area where the hole 621 exposes the surfaces of the first electrode 610).

[0273] According to one embodiment, the subsequent layers deposited on the recessed section 811 also contain a recessed section at corresponding locations of the respective layers (e.g. 640, 650, 660) due to the recessed section 811 of the first electrode 610.

[0274] In Fig. 9 the length of both the first and second channel regions 731 and 732 can be proportional to the height of the depression 811 of the first electrode 610 where the active layer 630 is located.

[0275] In other words, it is possible to adjust the length of both the first and second channel sections 731 and 732 by adjusting the height of the recess 811 of the first electrode 610.

[0276] As in the two Fig. 8 and Fig. As shown in Figure 9, the first electrode 610 contains an uppermost surface or top surface which is in contact with and faces the first insulating film 620. Unlike in the figures shown in Fig. 6 and Fig. In the embodiments shown in Figure 7, the first electrode 610 includes the recessed section 811. Accordingly, the upper surface of the first electrode 610 has at least three parts or sections. The first electrode 610 includes in the recessed section 811 a top surface USE, which is above a top surface USR. Furthermore, the first electrode 610 includes an inclined surface ISE between the top surface USE of the first electrode 610 and the top surface USR of the first electrode 610 in the recessed section 811.

[0277] Although in connection with Fig. Although a configuration has been described in sections 6 to 9 in which the active layer 630 is an oxide semiconductor, embodiments of the disclosure are not limited thereto.

[0278] For example, the transistor Tr can be a CMOS transistor.

[0279] This will be demonstrated below using the following examples. Fig. 10 and Fig. 11 described.

[0280] Fig. 10 and Fig. Figure 11 shows views representing the structure of a transistor, which is a transistor made of polycrystalline silicon.

[0281] Fig. 10 and Fig. 11 are cross-sectional views along line AB from Fig. 2B.

[0282] Essentially the same configurations and effects as those described above are not described again below.

[0283] Based on Fig. 10 and Fig. 11. A first electrode 610 can be arranged on the substrate 600. A first insulating film 620 with at least one hole 621, which exposes a section of an upper surface of the first electrode 610, can be arranged on the substrate 600 and on the first electrode 610.

[0284] An active layer 630 can be arranged on the first insulating film 620 and on the first electrode 610.

[0285] The active layer 630 can contain a first active layer 1031 and a second active layer 1032.

[0286] The first and second active layers 1031 and 1032 can be made of polysilicon, but embodiments of the disclosure are not limited to this.

[0287] Based on Fig. 10 The first active layer 1031 can contain a first section 1031a and a second section 1032a spaced apart from each other, and it can contain a third section 1033a positioned between the first section 1031a and the second section 1032a.

[0288] Based on Fig. 10. The first section 1031a of the first active layer 1031 may be an area where N + -Impairment ions are implanted. The second section 1032a and the third section 1033a of the first active layer 1031 may be regions where no ions are implanted.

[0289] The structure of the first active layer 1031 according to embodiments of the disclosure is not limited thereto and ions can also be implanted in the second section 1032a.

[0290] The third section 1033a of the first active layer 1031 can be a channel region through which charge carriers move when the transistor Tr is in an ON state. The third section 1033a can include a section located on a region that does not overlap the hole 621 of the first insulating film 620, a section located on a region that overlaps the side face of the first hole 621 of the first insulating film 620, and a section located on the upper surface of the first electrode 610 in the hole 621 of the first insulating film 620.

[0291] When the transistor Tr is in an ON state, charge carriers from the first section 1031a can move from the third section 1033a through the contact area between the third section 1033a and the first electrode 610 to the first electrode 610.

[0292] Based on Fig. 10 the second active layer 1032 may further contain a fourth section 1031b and a fifth section 1032b spaced apart from each other, and a sixth section 1033b positioned between the fourth section 1031b and the fifth section 1032b.

[0293] Based on Fig. 10. The fourth section 1031b of the second active layer 1032 may contain a region where P + -Impairment ions are implanted. The fifth section 1032b and the sixth section 1033b of the second active layer 1032 may be regions where no ions are implanted.

[0294] The structure of the second active layer 1032 according to embodiments of the disclosure is not limited thereto and ions can also be implanted in the fifth section 1032b.

[0295] The sixth section 1033b of the second active layer 1032 can be a channel region through which charge carriers move when the transistor Tr is in an ON state. The sixth section 1033b can include a section located on a region that does not overlap the hole 621 of the first insulating film 620, a section located on a region that overlaps the side face of the hole 621 of the first insulating film 620, and a section located on the upper surface of the first electrode 610 in the hole 621 of the first insulating film 620.

[0296] The channel area of ​​both the first active layer 1031 and the second active layer 1032 can have a length that is the sum of the length of the section located on the area that does not overlap the hole 621 of the first insulating film 620, the length of the section located on the area that overlaps the side surface of the hole 621 of the first insulating film 620, and the length of the section located on the first electrode 610 in the hole 621 of the first insulating film 620.

[0297] When the transistor Tr is in an ON state, charge carriers from the fourth section 1031b can move from the sixth section 1033b through the contact area between the sixth section 1033b and the first electrode 610 to the first electrode 610.

[0298] In other words, the channel area of ​​both the first and second active layers 1031 and 1032 can be adjusted by the height of the first insulating film 620.

[0299] Based on Fig. 10. A section of the first active layer 1031 and a section of the second active layer 1032 can overlap in the hole 621 of the first insulating film 620.

[0300] For example, a section of the second section 1032a of the first active layer 1031 and a section of the fifth section 1032b of the second active layer 1032 can overlap.

[0301] As described above, the area occupied by the transistor Tr can be reduced, thereby increasing the degree of device integration, since a section of the first active layers 1031 and a part of the second active layers 1032 are arranged overlapping.

[0302] The second insulating film 640 can be arranged on the first and second active layers 1031 and 1032.

[0303] A gate electrode 650 can be arranged on the second insulating film 640.

[0304] In the gate electrode 650, the first section 1031a of the first active layer 1031 and the fourth section 1031b of the second active layer 1032 cannot overlap the gate electrode.

[0305] A third insulating film 660 can be arranged on the gate electrode 650.

[0306] A second electrode 670 and a third electrode 680 of the transistor Tr can be spaced apart from each other and arranged on the third insulating film 770.

[0307] The second electrode 670 can be electrically connected to the first section 1031a of the first active layer 1031 or to the fourth section 1031b of the second active layer 1032, and the third electrode 680 can be electrically connected to the other.

[0308] Based on Fig. 10. The gate electrode 650 of transistor Tr can be connected to an input line Vin, which is connected to an external input terminal, and the second and third electrodes 670 and 86, which are drain electrodes, can be connected to different output lines Vout, which are connected to external output terminals. Furthermore, the first electrode 610, which is the source electrode, electrically connected to the first and second active layers 1031 and 1302, can be connected to ground EVSS.

[0309] Although Fig. 10 represents a structure in which the second active layer 1032 is arranged on a section of the first active layer 1031 in the hole 621 of the first insulating film 620, embodiments of the disclosure are not limited thereto.

[0310] As in Fig. As shown in Figure 11, the first active layer 1031 can be arranged on a section of the second active layer 1032.

[0311] Thus, a transistor Tr can contain the first active layer 1031 of NMOS and the second active layer 1032 of PMOS, and it can contain one source electrode, one gate electrode, and two drain electrodes. Accordingly, it is possible to implement a vertically structured transistor with a complementary metal-oxide-semiconductor (CMOS) structure by using different types of active layers (e.g., P-type and N-type).

[0312] Such a vertically structured transistor Tr can be applied to the PNL board, which is an electronic device, and which is in Fig. Transistor Tr shown in 6 to 11 with vertical structure can be arranged in the subpixel SP of the active area and can be connected to the pixel electrode.

[0313] This will be demonstrated below using the following examples. Fig. 12 described.

[0314] Fig. Figure 12 is a view showing a vertical structure transistor connected to a pixel electrode when the vertical structure transistor is arranged in a subpixel according to embodiments of the disclosure.

[0315] Based on Fig. 12. Among the vertical transistors Tr arranged in the subpixel SP in the active area A / A, there can be a transistor DRT in which the first electrode 610 should be electrically connected to the pixel electrode 1211.

[0316] A passivation layer 1210 can be arranged while covering the gate electrode 650 of the transistor Tr. Although Fig. 12. While the description represents a configuration in which the passivation layer 1210 is arranged on the gate electrode 650, embodiments of the disclosure are not limited to this and other components, such as another insulating film, can be added between the gate electrode 650 and the passivation layer 1210.

[0317] The pixel electrode 1211 can be positioned on the passivation layer 1210. The pixel electrode 1211 can be connected to the first electrode 610 through a hole in the passivation layer 1210. The first electrode 610 can be the source electrode, but embodiments of the disclosure are not limited to this.

[0318] For example, the pixel electrode 1211 can also be connected to the drain electrode.

[0319] Although Fig. 12 represents a configuration in which the transistor Tr of the disclosure is arranged in the active region A / A, the transistor Tr can be arranged in the non-active region according to embodiments of the disclosure, which is the outside of the panel PNL.

[0320] Since the area occupied by the transistor Tr with a vertical structure is smaller than the area occupied by the transistor Tr with a horizontal structure, the inactive area (also referred to as a border area) can be reduced when the transistor TR is arranged in the inactive area according to embodiments of the disclosure.

[0321] Furthermore, the transistor Tr can exhibit high current characteristics even though it is located in a small area, since a transistor Tr has two channel regions.

[0322] Furthermore, according to embodiments of the disclosure, the transistor Tr can exhibit one-current characteristics because the active layer 630 has a short channel. Additionally, by adjusting the thickness (or height) of the first insulating film 620, which overlaps the channel area, or the thickness (or height) of the first electrode 610 such that it is larger only in one section, the S-coefficient can be increased, which makes it possible to increase the available data voltage range.

[0323] In other words, the transistor Tr according to embodiments of the disclosure can exhibit high-current characteristics while suitably increasing the S-coefficient.

[0324] As in Fig. As shown in 13, the transistor Tr can be connected to the organic light-emitting diode according to embodiments of the disclosure.

[0325] Fig. Figure 13 is a view showing a vertically structured transistor connected to an organic light-emitting diode when the vertically structured transistor is arranged in a subpixel according to embodiments of the disclosure.

[0326] Based on Fig. 13 the anode electrode 301 of the organic light-emitting diode can be arranged on the passivation layer 1210.

[0327] A bank 1300 can be arranged on a section of the passivation layer 1210 and the anode electrode 301.

[0328] The organic layer 302 of the organic light-emitting diode can be arranged on bank 1300 and on the anode electrode 301. The cathode electrode 303 can be arranged on the organic layer 302.

[0329] The first electrode 610 of the transistor Tr according to embodiments of the disclosure can be electrically connected to the anode electrode 301 of the organic light-emitting diode arranged on the passivation layer 1210.

[0330] Although Fig. 12 and Fig. 13. To represent a structure in which the transistor Tr is used in a subpixel according to embodiments of the disclosure, embodiments of the disclosure are not limited thereto.

[0331] Fig. Figure 14 is a view that represents a structure in which a transistor is applied to two subpixels according to embodiments of the disclosure.

[0332] Based on Fig. 14 the first pixel electrode 1411 can be electrically connected to the second electrode 670 of the transistor Tr and the second pixel electrode 1412, which is spaced apart from the first pixel electrode 1411, can be electrically connected to the third electrode 680.

[0333] In other words, since the pixel electrodes in different subpixels share a transistor (e.g., a driver transistor), the structure of the electronic device can be simplified.

[0334] Although the foregoing description focuses mainly on a structure in which the transistor is a drive transistor according to embodiments of the disclosure, the transistor can also be used for other transistors included in the electronic device according to embodiments of the disclosure.

[0335] If the transistor is used as a control transistor, other signals can be applied to the second and third electrodes 670 and 680.

[0336] The following is based on Fig. 15 a comparison between the S-coefficient (SS) of a transistor Tr and its corresponding current increment according to embodiments of the disclosure and the S-coefficient (SS) of a transistor Tr and its corresponding current increment according to a comparative example is described.

[0337] Fig. Figure 15 is a view that presents a comparison between the S-coefficient (SS) of a transistor Tr and its corresponding current increment according to embodiments of the disclosure and the S-coefficient (SS) of a transistor Tr and its corresponding current increment according to a comparative example.

[0338] Based on Fig. 15. Comparison example 1 can have a structure in which the thickness of the insulating film arranged under the active layer of the normal transistor with coplanar structure is 50 nm, and comparison example 2 can have a structure in which the thickness of the insulating film arranged under the active layer of the normal transistor with coplanar structure is 400 nm.

[0339] The embodiment 1 can have a structure in which the thickness of the first insulating film 620 arranged under the active layer 630 of the transistor according to embodiments of the disclosure is 50 nm and the embodiment 2 can have a structure in which the thickness of the first insulating film 620 arranged under the active layer 630 of the transistor according to embodiments of the disclosure is 400 nm.

[0340] The SS value and the current increment from Fig. 15 can be derived from current value data according to the gate voltage of each transistor.

[0341] Based on Fig. 15 The SS value of the transistor according to comparison example 1 is high, but the current increment is very low compared to the transistors according to comparison example 1, embodiment 1 and embodiment 2.

[0342] The SS value of the transistor according to comparison example 2 is low compared to that of comparison example 1, and the current increment can be very low compared to those of the transistors according to embodiment 1 and embodiment 2.

[0343] In contrast, the transistors according to embodiment 1 and embodiment 2 can have a higher SS value than the transistor according to comparative example 1 and a higher current increment than the transistors according to comparative example 1 and comparative example 2.

[0344] In other words, the transistors according to embodiments 1 and 2 can have a high SS value and a high current increment.

[0345] According to embodiments of the disclosure, a thin-film transistor array substrate containing a vertical structure transistor capable of implementing a short channel and integration, and an electronic device containing it, can be created.

[0346] According to embodiments of the disclosure, a thin-film transistor array substrate, occupying a reduced area and with improved current characteristics, and an electronic device containing it can be created.

[0347] According to embodiments of the disclosure, a thin-film transistor arrangement substrate containing a vertically structured transistor capable of element miniaturization and a short channel as well as improved processing convenience, and an electronic device containing it, can be created.

Claims

[1] Electronic device comprising: a board (PNL) containing at least one thin-film transistor (Tr); and a control circuit (GDC) for controlling the panel (PNL), wherein the panel (PNL) contains: a substrate (600); a first electrode (610) which is arranged on the substrate (600); a first insulating film (620) arranged on the first electrode (610); a hole (621) in the first insulating film (620), wherein the hole (621) exposes a section of the first electrode (610); an active layer (630) which is arranged on and in contact with a section of the first insulating film (620) and with the exposed section of the first electrode (610); a second insulating film (640) arranged on top of the active layer (630); a gate electrode (650) which is arranged on the second insulating film (640); a third insulating film (660) arranged on the gate electrode (650); and a second electrode (670) and a third electrode (680) arranged on the third insulating film (660), wherein the second electrode (670) and the third electrode (680) are spaced apart from each other and electrically connected to the active layer (630), wherein the active layer (630) contains a first channel region (731) and a second channel region (732) which are spaced apart from each other, and wherein the first channel area (731) and the second channel area (732) each contain an area that is positioned on a side surface of the first insulating film (620) that defines the hole (621), wherein the active layer (630) comprises a first active layer (1031) arranged on a section of the first insulating film (620) and on a first section of the hole (621), and a second active layer (1032) arranged on another section of the first insulating film (620) and on a remaining second section of the hole (621), wherein the first active layer (1031) comprises: a first section (1031a) in which N + -Obstacle ions are implanted; a second section (1032a) spaced apart from the first section (1031a) and arranged on the exposed section of the first electrode (610) in the hole (621) of the first insulating film (620); and a third section (1033a) between the first section (1031a) and the second section (1032a), wherein the third section (1033a) comprises a section arranged on the first insulating film (620), a section arranged on a side face of the first insulating film (620), and a section arranged on the first electrode (610) exposed in the hole (621) of the first insulating film (620), and the second active layer contains (1032): a fourth section (1031b), in which P + -Obstacle ions are implanted; a fifth section (1032b) spaced apart from the fourth section (1031b) and arranged on the exposed section of the first electrode (610) in the hole (621); and a sixth section (1033b) between the fourth section (1031b) and the fifth section (1032b), wherein the sixth section (1033b) includes a section arranged on the first insulating film (620), a section arranged on the side surface of the first insulating film (620), and a section arranged on the first electrode (610) in the hole (621) of the first insulating film (620). [2] Electronic device according to claim 1, wherein the active layer (630) is an oxide semiconductor. [3] Electronic device according to any of the preceding claims, wherein the active layer (630) comprises: a first area (631) and a second area (632) arranged on the first insulating film (620) and spaced apart from each other; and a third area (633) between the first area (631) and the second area (632), wherein the third area (633) is arranged on the first insulating film (620), on the side surface of the first insulating film (620) and on the first electrode (610) in the hole (621). [4] Electronic device according to claim 3, wherein the gate electrode (650) overlaps the third region (633) of the active layer (630) in a direction perpendicular to the substrate (600). [5] Electronic device according to claim 3 or 4, wherein the second electrode (670) is in contact with the first region (631) of the active layer (630) and the third electrode (680) is in contact with the second region (632) of the active layer (630). [6] Electronic device according to claim 3, 4 or 5, wherein the third area (633) contains the first channel area (731) and the second channel area (732). [7] Electronic device according to claim 6, wherein the first channel area (731) extends from the first area (631) of the active layer (630) into the hole (621) and is arranged on the first insulating film (620), on the side surface of the first insulating film (620) and on the exposed section of the first electrode (610) in the hole (621); and / or wherein the second channel area (732) extends from the second area (632) of the active layer (630) into the hole (621) and is arranged on the first insulating film (620), on the side surface of the first insulating film (620) and on the exposed section of the first electrode (610) in the hole (621). [8] Electronic device according to claim 6 or 7, wherein the third area (633) includes a connecting section (733) that connects the first channel area (731) and the second channel area (732), and wherein a resistance value of the connecting section (733) is higher than a resistance value of the first channel area (731) and the second channel area (732). [9] Electronic device according to one of the preceding claims, wherein the first electrode (610) contains at least one recess (811), and wherein the hole (621) of the first insulating film (620) is arranged inside the recess (811). [10] Electronic device according to claim 1, wherein the third section (1033a) of the first active layer (1031) is a channel region of the first active layer (1031), and / or wherein a length of the third section (1033a) is directly proportional to a height of the hole (621) of the first insulating film (620). [11] Electronic device according to claim 1 or 10, wherein the sixth section (1033b) of the second active layer (1032) is a channel region of the second active layer (1032), and / or wherein a length of the sixth section (1033b) is proportional to a height of the hole (621) of the first insulating film (620). [12] Electronic device according to claim 1, 10 or 11, wherein a section of the first active layer (1031) in the hole (621) of the first insulating film (620) overlaps a section of the second active layer (1032). [13] Electronic device according to any of the preceding claims, wherein the first electrode (610) is a source electrode and the second electrode (670) and the third electrode (680) are drain electrodes. [14] Electronic device according to one of the preceding claims, wherein a width of the first electrode (610) is greater than a width of the active layer (630). [15] Thin-film transistor arrangement comprising: a first electrode (610); a first insulating film (620) on the first electrode (610); a hole (621) that passes through the first insulating film (620) and exposes the first electrode (610); an active layer (630) on the first insulating film (620) and in the hole (621), wherein the active layer (630) is in contact with the first electrode (610) in the hole (621); a second insulating film (640) on the active layer (630); a gate electrode (650) on the second insulating film (640); a second electrode (670) on the active layer (630), wherein the second electrode (670) extends through the second insulating film (640) so that it is electrically connected to the active layer (630); and a third electrode (680) on the active layer (630), wherein the third electrode (680) is spaced apart from the second electrode (670), wherein the third electrode (680) passes through the second insulating film (640) so that it is electrically connected to the active layer (630), wherein the active layer (630) comprises a first active layer (1031) arranged on a section of the first insulating film (620) and on a first section of the hole (621), and a second active layer (1032) arranged on another section of the first insulating film (620) and on a remaining second section of the hole (621), wherein the first active layer (1031) comprises: a first section (1031a) in which N + -Obstacle ions are implanted; a second section (1032a) spaced apart from the first section (1031a) and arranged on the exposed section of the first electrode (610) in the hole (621) of the first insulating film (620); and a third section (1033a) between the first section (1031a) and the second section (1032a), wherein the third section (1033a) comprises a section arranged on the first insulating film (620), a section arranged on a side face of the first insulating film (620), and a section arranged on the first electrode (610) exposed in the hole (621) of the first insulating film (620), and the second active layer contains (1032): a fourth section (1031b), in which P + -Obstacle ions are implanted; a fifth section (1032b) spaced apart from the fourth section (1031b) and arranged on the exposed section of the first electrode (610) in the hole (621); and a sixth section (1033b) between the fourth section (1031b) and the fifth section (1032b), wherein the sixth section (1033b) includes a section arranged on the first insulating film (620), a section arranged on the side surface of the first insulating film (620), and a section arranged on the first electrode (610) in the hole (621) of the first insulating film (620). [16] Thin-film transistor arrangement according to claim 15, wherein the first insulating film (620) has a first inclined surface defining the hole (621) passing through the first insulating film (620) and a second surface facing away from the first electrode (610), and wherein the active layer (630) extends from the first electrode (610) in the hole (621) across the first inclined surface of the first insulating film (620) to the second surface of the first insulating film (620) and overlaps the second surface of the first insulating film (620). [17] Thin-film transistor arrangement according to claim 16, wherein the second electrode (670) and / or the third electrode (680) is in contact with a section of the active layer (630) which at least partially overlaps the second surface of the first insulating film (620). [18] Thin-film transistor arrangement according to claim 16 or 17, wherein the first electrode includes a recessed section (811), and wherein a width of the hole (621) passing through the first insulating film (620) is smaller than a width of the recessed section (811). [19] Thin-film transistor arrangement according to claim 18, wherein the active layer (630) and / or the second insulating film (640) and / or the gate electrode (650) includes a recessed section corresponding to the recessed section (811) of the first electrode (610). [20] Electronic device comprising: at least one thin-film transistor, wherein the at least one thin-film transistor comprises a thin-film transistor arrangement according to any one of claims 15 to 19.

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