Semiconductor chip stack architecture and connection method for it

Abstract

Semiconductor chips in a stack are interconnected by metal traces instead of bond wires or by silicon vias (TSVs). The semiconductor chips in the stack are arranged in a step configuration, such that a step corner is defined between the top surface of the first semiconductor chip in the stack and a side wall of the second semiconductor chip in the stack. A step ramp is formed at the step corner. The step ramp defines a slope extending between the top surface of the first semiconductor chip and a top surface of the second semiconductor chip. A metal trace is formed across a bond pad associated with the first semiconductor chip, the step ramp, and a bond pad associated with the second semiconductor chip.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Application 63 / 510,912, entitled "SEMICONDUCTOR DIE STACKING ARCHITECTURE AND CONNECTION METHOD THEREFORE," filed June 29, 2023, the entire disclosure of which is hereby incorporated by reference in its entirety. BACKGROUND

[0002] Chip stacking is a chip stacking technique in which multiple semiconductor chips are stacked on top of each other and bonded together to form a single unit. Current chip stacking architectures use bond wires or through-silicon vias (TSVs) to connect the various semiconductor chips in the stack.

[0003] However, bond wires can limit the performance of the semiconductor stack. For example, bond wires are typically associated with one or more parasitic effects that prevent the semiconductor stack from achieving very high performance. While TSVs can be used instead of bond wires and can make the semiconductor stack very high-performance, forming TSVs in the various semiconductor chips of the semiconductor stack is both time-consuming and costly.

[0004] Accordingly, it would be advantageous to connect semiconductor chips of a semiconductor stack without bond wires or TSVs while simultaneously making the semiconductor stack very powerful. SUMMARY

[0005] The present application describes an architecture for stacking semiconductor chips and connecting the semiconductor chips with metal lines (also referred to herein as "transmission lines") instead of bond wires or silicon vias (TSVs). Compared to bond wires, the metal lines are less susceptible to parasitic effects. The metal lines are also more cost-effective to manufacture than TSVs. The metal lines can also enable the stack of semiconductor chips to perform as well as a stack of semiconductor chips interconnected by TSVs.

[0006] As will be described in more detail herein, the semiconductor chips are arranged in a stack and can be used in a semiconductor package. The stack of semiconductor chips can be arranged in a stair-step configuration such that a step corner is formed or defined between a top surface of a first semiconductor chip in the stack and a sidewall of a second semiconductor chip in the stack. A step ramp is formed in the step corner. The step ramp defines an incline extending between the top surface of the first semiconductor chip and a top surface of the second semiconductor chip. A metal line is formed over a bond pad associated with the first semiconductor chip, the step ramp, and a bond pad associated with the second semiconductor chip.

[0007] Because the metal line extends along the slope of the step ramp, the connection length between the bond pad associated with the first semiconductor chip and the bond pad associated with the second semiconductor chip is shorter than the connection length using a bond wire. Additionally, using metal lines instead of bond wires allows for the use of smaller bond pads. Smaller bond pads also allow for a smaller / narrower pitch between the various bond pads on a given semiconductor chip. Thus, more connections can be made between the various semiconductor chips. As a result, the semiconductor package can achieve higher power / frequency than semiconductor packages using bond wires.

[0008] Accordingly, examples of the present disclosure describe a stack of semiconductor chips for a semiconductor package. In one example, the stack of semiconductor chips is formed by a first semiconductor chip and a second semiconductor chip. The first semiconductor chip and the second semiconductor chip define a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip. A step ramp is formed in the step corner. A transmission line is formed over a first bond pad associated with the first semiconductor chip, the step ramp, and a second bond pad associated with the second semiconductor chip.

[0009] The present application also describes a method for manufacturing a stack of semiconductor chips for a semiconductor package. In one example, the method includes stacking a second semiconductor chip on a first semiconductor chip to form a semiconductor chip stack. The semiconductor chip stack defines a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip. A step ramp is formed in the step corner. Additionally, a transmission line is formed over a first bond pad associated with the first semiconductor chip, the step ramp, and a second bond pad associated with the second semiconductor chip.

[0010] In another example, the present application describes a semiconductor package including a stack of semiconductor chips formed by a first semiconductor chip and a second semiconductor chip. In one example, the first semiconductor chip and the second semiconductor chip define a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip. The semiconductor package also includes a ramp means formed in the step corner and a transfer means. The transfer means is formed over a first interconnect means associated with the first semiconductor chip, the ramp means, and a second interconnect means associated with the second semiconductor chip.

[0011] This Summary is intended to provide a selection of concepts in simplified form, which are further described below in the Detailed Description. This Summary is neither intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Non-limiting and non-exhaustive examples are described with reference to the following figures. Fig. 1 illustrates a stack of semiconductor chips for a semiconductor package according to an example. Fig. 2 illustrates a first operation in a manufacturing method in which a number of semiconductor chips are stacked together to form a stack of semiconductor chips, according to an example. Fig. 3 illustrates a second operation in the manufacturing method in which a step ramp is formed in each step corner of the stack of semiconductor chips, according to an example. Fig. 4 illustrates a third operation in the manufacturing method in which a photoresist layer is provided on the stack of semiconductor chips, according to an example. Fig. 5 illustrates a fourth operation in the manufacturing process in which a pattern generation process is used to write or expose one or more patterns onto the bond pads and / or the step ramps of the stack of semiconductor chips, according to an example. Fig. 6 illustrates a fifth operation in the manufacturing process in which a metal layer is deposited on the exposed bond pads and / or the step ramps of the stack of semiconductor chips, according to an example. Fig. 7 illustrates a sixth operation in the manufacturing method in which a further photoresist layer is provided on the stack of semiconductor chips, according to an example. Fig. 8 illustrates a seventh process in the manufacturing method in which an electroplating process is performed on the metal layer, according to an example. Fig. 9 illustrates an eighth operation in the manufacturing method in which the first photoresist layer and the second photoresist layer are removed from the stack of semiconductor chips, according to an example. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which, for purposes of illustration, certain embodiments or examples are shown. These aspects may be combined, other aspects may be employed, and structural changes may be made without departing from the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0014] Current semiconductor chip stacking architectures require the use of bond wires or silicon vias (TSVs) to connect the various semiconductor chips in a stack of semiconductor chips. However, bond wires are subject to parasitic effects (e.g., resistance, inductance) that can reduce the overall performance of the semiconductor chip stack. While TSVs eliminate the parasitic effects of bond wires, forming TSVs in a semiconductor chip stack is time-consuming and costly.

[0015] To counteract this, the present application describes an architecture for stacking semiconductor chips in which metal lines (also referred to herein as "transmission lines") are used as interconnects instead of bond wires or silicon vias (TSVs). For example, a semiconductor package includes a stack of semiconductor chips. The semiconductor chips are arranged in a stair-step configuration such that a step corner is defined between a top surface of a first semiconductor chip and a sidewall of a second semiconductor chip. During manufacturing or fabrication, a step ramp is formed in the step corner. The step ramp defines an incline extending between the top surface of the first semiconductor chip and a top surface of the second semiconductor chip.A metal line (or a metal layer) is formed over a bond pad associated with the first semiconductor chip, the step ramp, and a bond pad associated with the second semiconductor chip.

[0016] By replacing bond wires with metal lines, the length of the connections between the various semiconductor chips in the stack of semiconductor chips is reduced. For example, the metal line extends from the bond pad on the first semiconductor chip upward (or downward) over the incline of the step ramp and overlies the bond pad on the second semiconductor chip. Thus, the length of the connection between the bond pads is shorter than with a connection formed with a bond wire.

[0017] Additionally, the metal wire allows for smaller bond pads than those typically used with bond wires. Because the bond pads are smaller, the spacing between the bond pads can also be smaller than the spacing between bond wires. Due to the smaller spacing between bond pads, more bond pads and associated connections can be added to the semiconductor stack, helping to increase the performance of the semiconductor package. The metal lines can also enable more semiconductor die to be incorporated into the semiconductor die stack than with bond wire solutions.

[0018] The metal lines are also more cost-effective to manufacture than TSVs. However, the metal lines can also enable the stack of semiconductor chips to perform as well as a stack of semiconductor chips connected by TSVs.

[0019] Accordingly, the present application describes many technical advantages, including, but not limited to, enabling the fabrication of high-density semiconductor packages having a greater number of semiconductor die than current semiconductor packages; increasing the number of interconnections between semiconductor dies in a stack of semiconductor dies; and improving the electrical performance of semiconductor packages compared to semiconductor packages that use bond wires to make electrical connections.

[0020] These benefits and other examples are in Fig. 1 to Fig. 9 and described in more detail.

[0021] Fig. 1 illustrates a stack of semiconductor chips 100 for a semiconductor package according to one example. The stack of semiconductor chips 100 includes a first semiconductor chip 105, a second semiconductor chip 110, a third semiconductor chip 115, and a fourth semiconductor chip 120. In one example, each semiconductor chip is a memory chip, such as a NAND flash memory chip. Although a NAND flash memory chip is specifically mentioned, the memory chip may be any type of volatile or non-volatile memory chip. In another example, the stack of semiconductor chips 100 may include any type of stackable semiconductor chip and / or stackable integrated circuit.

[0022] In one example, the first semiconductor chip 105 is provided or mounted on a surface of a substrate 125 or a printed circuit board (PCB). The substrate 125 may include one or more conductive balls 130 that enable the semiconductor package to be electrically and / or communicatively coupled to, or otherwise connected to, a computer component or electronic device.

[0023] The second semiconductor chip 110 is mounted on a top surface of the first semiconductor chip 105. In one example, the second semiconductor chip 105 is mounted on the first semiconductor chip 105 using a die attach film (DAF). Although DAF is specifically mentioned, the second semiconductor chip 110 may also be mounted on the top surface of the first semiconductor chip 105 using other mounting techniques. Likewise, the third semiconductor chip 115 is mounted on a top surface of the second semiconductor chip 110, and the fourth semiconductor chip 120 is mounted on a top surface of the third semiconductor chip 115.

[0024] The semiconductor chips are each stacked one above the other or otherwise arranged in a stair-step configuration. Thus, a step corner 135 may be defined between a top surface of one semiconductor chip and a sidewall of another semiconductor chip. For example, a step corner 135 may be defined by a top surface of the first semiconductor chip 105 and a sidewall of the second semiconductor chip 110. A length and / or a height of the step corner 135 may vary depending on a thickness or height of each semiconductor chip, a length of each semiconductor chip, and / or a position of each semiconductor chip relative to the semiconductor chip on which it is stacked.

[0025] In one example, a step ramp 150 is provided or otherwise formed in each step corner 135. The step ramp 150 may be made of a polymer or other material. The step ramp 150 forms a planar surface (or a substantially planar surface) between a top surface of one semiconductor chip and a top surface of another semiconductor chip. For example, a step ramp 150 may be formed between the top surface of the first semiconductor chip 105 and the sidewall of the second semiconductor chip 110.

[0026] In one example, the angle of the planar surface of the step ramp 150 is between forty-five degrees and twenty degrees (or less). Although a specific range is stated, the angle of the planar surface of the step ramp 150 may be greater than forty-five degrees. In another example, the angle of the planar surface of the step ramp 150 may be based on a number of factors, including, but not limited to, a thickness or height of each semiconductor die, a length of each semiconductor die, and / or a position of each semiconductor die relative to the semiconductor die on which it is stacked. Although a planar or substantially planar surface is described, the surface of the step ramp 150 may be concave or convex.

[0027] Each semiconductor chip in the stack of semiconductor chips 100 may also include a bond pad 140. The bond pad 140 may be provided on a top surface of each semiconductor chip. The bond pad 140 may be used to electrically and / or communicatively couple the semiconductor chips to each other and / or to a substrate finger 145 provided on the substrate 125. Although Fig. 1 illustrates a single bond pad 140 on each semiconductor chip, each semiconductor chip may include multiple bond pads 140. In one example, a pitch between the bond pads 140 on a particular semiconductor chip may be between forty micrometers (µm) and thirty µm (or less). In contrast, a pitch between bond pads of a stack of semiconductor chips using bond wires is typically between eighty µm and one hundred µm.

[0028] As previously stated, the semiconductor die stack 100 does not use bond wires, TSVs, or solder connections to interconnect the individual semiconductor die. Thus, higher performance, lower cost, and higher stack density can be achieved than semiconductor die stacks that use bond wires, TSVs, and / or solder connections.

[0029] To achieve higher performance and higher stack density at lower cost, a metal line 155 is provided over the bond pads 140 and the step ramp 150 associated with each semiconductor chip. For example, the metal line 155 may form a transmission line or connection between the bond pad 140 on the first semiconductor chip 105 and the bond pad 140 on the second semiconductor chip 110. The metal line 155 may also extend up (or down) the step ramp 150 provided between the first semiconductor chip 105 and the second semiconductor chip 110. The metal line 155 may also connect the bond pads 140 of the various semiconductor chips to the substrate finger 145.

[0030] Because the metal line 155 extends up (or down) each step ramp 150, a shorter connection pitch is achieved than when using bond wires. Additionally, the metal line 155 allows the bond pads 140 to be spaced closer together (e.g., a pitch between forty micrometers (µm) and thirty µm (or less)), as previously described. A smaller pitch between the bond pads 140 means that additional bond pads 140 and associated transmission lines can be added to the stack of semiconductor chips 100. Additional transmission lines can enable higher performance capabilities compared to a stack of semiconductor chips communicatively coupled via bond wires. Using metal lines 155 instead of bond wires also allows more semiconductor chips to be added to a stack than with current bond wire solutions.

[0031] In one example, the metal line 155 may be formed of copper. Although copper is specifically mentioned, other materials may also be used. In another example, the metal line 155 is plated with copper (e.g., using a copper electroplating process).

[0032] In one example, the stack of semiconductor chips 100 may also include an additional metal layer or ground plane. In one example, the additional metal layer may be used to construct the ground plane. For example, the ground plane may be positioned beneath the metal lines 155 and / or beneath the step ramp 150. In another example, the ground plane may be used to form a transmission line. In such examples, the ground plane may increase the signal integrity of interconnect lines connecting the various semiconductor chips in the stack of semiconductor chips 100 to the substrate 125.

[0033] Fig. 2 to Fig. 9 show and describe various processes for manufacturing a stack of semiconductor chips, in which the semiconductor chips of the stack are connected to each other without bond wires, TSVs, or solder connections. In one example, the various processes described in Fig. 2 to Fig. 9 are used to produce the stack of semiconductor chips 100 shown in Fig. 1 is shown and described.

[0034] Fig. 2 illustrates a first operation in a manufacturing method in which a number of semiconductor chips are stacked together to form a stack of semiconductor chips 200, according to an example. As shown in Fig. As shown in Figure 2, the semiconductor chips are stacked on top of each other and arranged in a stair-step configuration.

[0035] For example, a first semiconductor chip 205 is stacked on or otherwise coupled to a substrate 225. A second semiconductor chip 210 may be stacked on or otherwise coupled to a top surface of the first semiconductor chip 205. Likewise, a third semiconductor chip 215 may be stacked on the second semiconductor chip 210, and a fourth semiconductor chip 220 may be stacked on the third semiconductor chip 215. Although four semiconductor chips are shown and described, any number of semiconductor chips may be stacked on top of one another to form the stack of semiconductor chips 200. Although semiconductor chips are specifically mentioned, the stack of semiconductor chips 200 may include any type of stackable semiconductor chip and / or stackable integrated circuit.

[0036] In one example, each semiconductor die may be attached to another semiconductor die (or to the substrate 225) using a die attach film (DAF). Although a DAF is specifically mentioned, other materials and / or methods may be used to create the stack of semiconductor dies 200 and / or to attach the semiconductor dies to each other and / or to the substrate 225.

[0037] When the semiconductor chips are stacked in the stair-step configuration, a step corner 250 is defined. For example, when the second semiconductor chip 210 is stacked on the first semiconductor chip 205, a step corner 250 is defined between a top surface of the first semiconductor chip 205 and a sidewall of the second semiconductor chip 210. Similar step corners 250 can be defined between the substrate 225 and the first semiconductor chip 205, between the second semiconductor chip 210 and the third semiconductor chip 215, and between the third semiconductor chip 215 and the fourth semiconductor chip 220.

[0038] Each semiconductor chip may also include a bond pad 245. For example, the first semiconductor chip 205 may include a bond pad 245, the second semiconductor chip 210 may include a bond pad 245, and so on. The bond pad 245 may be formed from a conductive material such as copper, silver, gold, solder, or another material or a combination of materials.

[0039] The substrate 225 may also include a bond pad or other connection mechanism (e.g., a substrate finger 230). The substrate finger 230 may be electrically and / or communicatively coupled to one or more conductive traces 235 formed in or otherwise connected to the substrate 225. The conductive traces 235 may also be communicatively and / or electrically coupled to one or more solder balls 240 provided on a bottom surface of the substrate 225. Although solder balls 240 are specifically mentioned, other connection mechanisms may also be used to electrically and / or communicatively couple the substrate 225 to an electronic device or component.

[0040] Fig. 3 illustrates a second operation in the manufacturing method in which a step ramp 300 is formed in each step corner 250 of the stack of semiconductor chips 200, according to one example. In one example, the step ramp 300 is formed from a polymer or other material. The step ramp 300 may be used to form a planar or substantially planar surface within each step corner 250 defined by the stack of semiconductor chips 200. Although a planar or substantially planar surface is specifically mentioned, the surface of the step ramp 250 may be concave or convex.

[0041] In one example, the surface of the step ramp 300 may have an angle of approximately 45 degrees or less. However, the angle of the flat surface of the step ramp 300 may be based on a number of factors, as previously described.

[0042] The step ramp 300 can provide a shortest path between the various bond pads 245 of the different semiconductor chips in the stack of semiconductor chips 200. Furthermore, the step ramp 300 can also be used to prevent a short circuit between a metal line or a transmission line and the silicon from which the semiconductor chips are formed.

[0043] In one example, the step ramp 300 may extend from (or near) a bond pad 245 on a top surface of the first semiconductor chip 205 and upward or along a sidewall of the second semiconductor chip 210. The step ramp 300 may also extend around an upper corner of the sidewall of the second semiconductor chip 210 and at least partially along a top surface of the second semiconductor chip 210 (e.g., at least partially to the bond pad 245 on the top surface of the second semiconductor chip 210).

[0044] Fig. 4 illustrates a third operation in the manufacturing method in which a photoresist layer 400 is provided over the stack of semiconductor chips 200, according to an example. As shown in Fig. As shown in Figure 4, the photoresist layer 400 may be provided over exposed portions of the substrate 225, the step ramp 300, the bond pads 245, and / or the substrate finger 230. In one example, the photoresist layer 400 is provided over the stack of semiconductor chips 200 using a spraying process. The spraying process may be used to achieve a uniform or substantially uniform thickness. Although a spraying process is specifically mentioned, the photoresist layer 400 may be provided over the stack of semiconductor chips 200 using any suitable technique.

[0045] Fig. 5 illustrates a fourth operation in the manufacturing process, in which a pattern generation process is used to write or expose one or more patterns onto the bond pads 245 and / or the step ramps 300 of the stack of semiconductor chips 200, according to one example. The pattern generation process may also be used to write or expose one or more patterns onto the substrate finger 230.

[0046] In one example, the pattern generation process uses a laser (e.g., laser lithography) or ultraviolet light to create the pattern or otherwise expose the bond pads 245, the substrate finger 230, and / or the step ramps 300 for further processing. In one example, a laser scribe or other mechanism performing the pattern generation process may move in an XY direction and a Z direction to account for changes in the height of the stack of semiconductor chips 200.

[0047] Fig. 6 illustrates a fifth operation in the manufacturing process, in which a metal layer 600 is deposited on the exposed bond pads 245 and / or the step ramps 300 of the stack of semiconductor chips 200, according to one example. The metal layer 600 may also be provided on the substrate finger 230 and / or an exposed photoresist layer 400.

[0048] In one example, metal layer 600 is used to form transmission lines, metal lines, or interconnects for semiconductor chip stack 200. Metal layer 600 may be deposited or otherwise formed on bond pads 245 and / or step ramps 300 using a vacuum deposition process. Although a vacuum deposition process is specifically mentioned, other thin metal deposition processes may also be used.

[0049] The metal layer 600 may be formed of copper. Although copper is specifically mentioned, other conductive materials such as gold, silver, or a combination of conductive materials may also be used to form the metal layer 600.

[0050] Fig. 7 illustrates a sixth operation in the manufacturing process, in which a further photoresist layer 700 is provided over the stack of semiconductor chips 200, according to an example. In addition to adding a second photoresist layer 700, a second pattern generation process may also be used to write or expose one or more patterns onto the metal layer 600 formed over the bond pads 245, the step ramp 300, and / or the substrate finger 230. In one example, the second photoresist layer 700 and the second pattern generation process may be similar to the process described above with respect to Fig. 4 and Fig. be similar to the procedure described in 5.

[0051] Additionally, the sixth process may also be used to form or expose a plating contact 710 associated with the stack of semiconductor chips 200. The plating contact 710 may be used to enable electrical current flow during a second metal deposition process, as described with respect to Fig. 8 will be described in more detail.

[0052] Fig. 8 illustrates a seventh operation in the manufacturing process in which an electroplating process is performed on the metal layer 600, according to one example. In one example, the electroplating process is used to form a coating 800 (enlarged for illustrative purposes) or a plate over the exposed metal layer 600. The coating 800 may be formed on all or portions of the metal layer 600. The coating 800 may be used to improve or otherwise increase the conductivity of the metal layer 600 on the stack of semiconductor chips 200. In one example, the coating 800 is formed of copper. Although copper is specifically mentioned, other conductive materials may also be used.

[0053] Fig. 9 illustrates an eighth operation in the manufacturing method in which the first photoresist layer and the second photoresist layer are removed from the stack of semiconductor chips 200, according to an example. Fig. 9 may be used as part of a semiconductor package. In another example, the stack of semiconductor chips 200 may be similar to the stack of semiconductor chips 100 shown with respect to Fig. 1 shown and described.

[0054] Accordingly, examples of the present disclosure describe a stack of semiconductor chips for a semiconductor package, comprising: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip define a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip; a step ramp formed in the step corner; and a transmission line formed on a first bond pad associated with the first semiconductor chip, the step ramp, and a second bond pad associated with the second semiconductor chip, wherein the transmission line electrically connects the first and second bond pads. In one example, the step ramp is formed from a polymer.In one example, the step ramp forms an angle of approximately forty-five degrees between the surface of the first semiconductor chip and the sidewall of the second semiconductor chip. In one example, the step ramp forms an angle of less than forty-five degrees between the surface of the first semiconductor chip and the sidewall of the second semiconductor chip. In one example, the stack of semiconductor chips also includes a metal coating provided over the transmission line, the first bond pad, and the second bond pad. In one example, the metal coating is copper. In one example, the first semiconductor chip is associated with a plurality of bond pads, each of the plurality of bond pads having a pitch of approximately thirty micrometers (µm).

[0055] The present application also describes a method of assembling a stack of semiconductor chips for a semiconductor package, comprising: stacking a second semiconductor chip on a first semiconductor chip to form the stack of semiconductor chips, wherein the first semiconductor chip and the second semiconductor chip define a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip; forming a step ramp in the step corner; and forming a transmission line over a first bond pad associated with the first semiconductor chip, the step ramp, and a second bond pad associated with the second semiconductor chip, the transmission line electrically connecting the first and second bond pads. In one example, the method also includes providing a photoresist layer over the step ramp, the first bond pad, and the second bond pad prior to forming the transmission line.In one example, the method also includes preparing the first bond pad and the second bond pad for the transmission line using a laser lithography process based at least in part on providing the photoresist layer over the first bond pad and the second bond pad. In one example, the method also includes forming a metal coating over at least a portion of the transmission line, the first bond pad, and the second bond pad. In one example, the metal coating is copper. In one example, the step ramp is formed from a polymer.

[0056] In another example, a stack of semiconductor chips for a semiconductor package is disclosed. In one example, the stack of semiconductor chips comprises a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip, the first semiconductor chip and the second semiconductor chip defining a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip; a ramp means formed in the step corner; and a transfer means formed on a first interconnect means associated with the first semiconductor chip, the ramp means, and a second interconnect means associated with the second semiconductor chip, the transfer means electrically connecting the first and second interconnect means of the first and second semiconductor chips. In one example, the ramp means is formed from a polymer.In one example, the ramp means forms an angle of approximately forty-five degrees between the surface of the first semiconductor chip and the sidewall of the second semiconductor chip. In one example, the ramp means forms an angle of less than forty-five degrees between the surface of the first semiconductor chip and the sidewall of the second semiconductor chip. In one example, the stack of semiconductor chips also includes a coating means provided over the transfer means, the first connecting means, and the second connecting means. In one example, the coating means is made of copper. In one example, the first semiconductor chip is associated with a plurality of connecting means, each of the plurality of connecting means having a pitch of approximately thirty micrometers (µm).

[0057] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of the disclosure in any way. The aspects, examples, and details provided in this disclosure are considered sufficient to convey the claimed disclosure and to enable others to make and use the best mode of the claimed disclosure.

[0058] The claimed disclosure is not to be construed as being limited to any one aspect, example, or detail in this disclosure. Whether shown and described in combination or separately, the various features are intended to be selectively rearranged, included, or omitted to produce various embodiments having a particular set of features. Given the description and illustration of the present application, those skilled in the art will be able to conceive variations, modifications, and alternative aspects that remain within the spirit of the broader aspects of the general inventive concept embodied in this application and do not depart from the broader scope of the claimed disclosure.

[0059] References herein to an element by a label such as "first," "second," and so on generally do not limit the quantity or order of those elements. Rather, these labels may be used as a method of distinguishing between two or more elements or instances of an element. Therefore, a reference to the first and second elements does not imply that only two elements may be used or that the first element precedes the second element. Furthermore, unless otherwise noted, a set of elements may include one or more elements.

[0060] Terminology in the form of "at least one of A, B, or C" or "A, B, C, or a combination thereof" used in the specification or claims means "A or B or C, or a combination of these elements." For example, this terminology may include A or B or C or A and B or A and C or A and B and C or 2A or 2B or 2C or 2A and B, and so on. As an additional example, "at least one of: A, B, or C" is intended to cover A, B, C, AB, AC, BC, and ABC, as well as multiples of the same members. Likewise, "at least one of: A, B, and C" is intended to cover A, B, C, AB, AC, BC, and ABC, as well as multiples of the same members.

[0061] Similarly, as used herein, a phrase referring to a list of elements joined with "and / or" refers to any combination of the elements. For example, "A and / or B" is intended to cover A alone, B alone, or A and B together. As another example, "A, B, and / or C" is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 510,912

[0001]

Claims

[1] A stack of semiconductor chips for a semiconductor package, comprising: a first semiconductor chip: a second semiconductor chip stacked on the first semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip define a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip; a step ramp formed in the step corner; and a transmission line formed on a first bond pad associated with the first semiconductor chip, the step ramp, and a second bond pad associated with the second semiconductor chip, the transmission line electrically connecting the first and second bond pads. [2] A stack of semiconductor chips according to claim 1, wherein the step ramp is formed from a polymer. [3] The stack of semiconductor chips of claim 1, wherein the step ramp forms an angle of about forty-five degrees between the surface of the first semiconductor chip and the sidewall of the second semiconductor chip. [4] The stack of semiconductor chips of claim 1, wherein the step ramp forms an angle of less than forty-five degrees between the surface of the first semiconductor chip and the sidewall of the second semiconductor chip. [5] The stack of semiconductor chips according to claim 1, further comprising a metal coating provided over the transmission line, the first bond pad and the second bond pad. [6] A stack of semiconductor chips according to claim 5, wherein the metal coating is copper. [7] The stack of semiconductor chips of claim 1, wherein the first semiconductor chip is associated with a plurality of bond pads, and wherein each of the plurality of bond pads has a pitch of approximately thirty micrometers (µm). [8] A method of assembling a stack of semiconductor chips for a semiconductor package, comprising: Stacking a second semiconductor chip on a first semiconductor chip to form a stack of semiconductor chips, wherein the first semiconductor chip and the second semiconductor chip define a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip; Forming a step ramp in the step corner; and Forming a transmission line over a first bond pad associated with the first semiconductor chip, the step ramp, and a second bond pad associated with the second semiconductor chip, the transmission line electrically connecting the first and second bond pads. [9] The method of claim 8, further comprising providing a photoresist layer over the step ramp, the first bond pad, and the second bond pad prior to forming the transmission line. [10] The method of claim 9, further comprising preparing the first bond pad and the second bond pad for the transmission line using a laser lithography process based at least in part on providing the photoresist layer over the first bond pad and the second bond pad. [11] The method of claim 8, further comprising forming a metal coating over at least a portion of the transmission line, the first bond pad, and the second bond pad. [12] The method of claim 11, wherein the metal coating is copper. [13] The method of claim 8, wherein the step ramp is formed from a polymer. [14] A stack of semiconductor chips for a semiconductor package, comprising: a first semiconductor chip: a second semiconductor chip stacked on the first semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip define a step corner between a surface of the first semiconductor chip and a sidewall of the second semiconductor chip; a ramp means formed in the step corner; and a transfer means formed on a first connecting means associated with the first semiconductor chip, the ramp means, and a second connecting means associated with the second semiconductor chip, the transfer means electrically connecting the first and second connecting means of the first and second semiconductor chips. [15] A stack of semiconductor chips according to claim 14, wherein the ramp means is formed from a polymer. [16] The stack of semiconductor chips of claim 14, wherein the step ramp forms an angle of approximately forty-five degrees between the surface of the first semiconductor chip and the sidewall of the second semiconductor chip. [17] The stack of semiconductor chips of claim 14, wherein the step ramp forms an angle of less than forty-five degrees between the surface of the first semiconductor chip and the sidewall of the second semiconductor chip. [18] The stack of semiconductor chips according to claim 14, further comprising a coating agent provided over the transfer agent, the first connecting agent and the second connecting agent. [19] A stack of semiconductor chips according to claim 18, wherein the coating agent consists of copper. [20] A stack of semiconductor chips according to claim 14, wherein the first semiconductor chip is associated with a plurality of interconnecting means, and wherein each of the plurality of interconnecting means has a pitch of approximately thirty micrometers (µm).

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