Circuit arrangement for reducing dead time losses of an inverter and electrical system

Abstract

The present invention relates to a circuit arrangement for reducing dead-time losses of an inverter and an electrical system, wherein the circuit arrangement comprises: a half-bridge arrangement comprising a first switch (10) and a second switch (15), a load (20), a control unit (30) and a driver unit (40), wherein the first switch (10) is designed as a junction field-effect transistor, the half-bridge arrangement is configured to be connected to a DC voltage source (50) and to provide an AC voltage to the load (20) by means of a complementary control of the first switch (10) and the second switch (15) by the control unit (30) on the basis of a voltage (UDC) of the DC voltage source (50), wherein the control unit (30) is configuredto maintain a dead time between the complementary switching of the first switch (10) and the second switch (15), and wherein the driver unit (40) is configured, on the basis of a control by the control unit (30), to provide a gate of the first switch (10) with a dead time voltage (UT) during a switch-on process and / or during a switch-off process of the first switch (10) during the dead time, which dead time voltage is smaller than a threshold voltage of the first switch (10) and greater than a voltage (UA) provided for blocking the first switch (10) outside the dead time.

Description

State of the art

[0001] The present invention relates to a circuit arrangement for reducing dead time losses of an inverter and an electrical system with such a circuit arrangement.

[0002] To control n-channel self-conducting junction field-effect transistors (JFETs), a gate driver is usually used, which provides two different voltage levels for switching the field-effect transistors on and off.

[0003] A conventional gate driver has two output states; it is usually controlled by a control signal with two logic levels and provides a voltage of 0 V or a slightly positive voltage to turn the transistor on or a negative voltage to turn the transistor off between the gate and source terminals of the JFET transistor.

[0004] When JFET transistors are used as switches in a voltage-supplied pulse-controlled inverter with an inductive load and alternating current direction, it is necessary to prevent a simultaneous on-state in the respective JFET transistors of a half-bridge to avoid a DC-link short circuit. The alternating direction of the load current leads to a periodically repeated use of the JFET transistors in the 3rd quadrant, in which a reverse current is applied to the JFET transistors.

[0005] Safe operation of such a pulse-controlled inverter with an inductive load is ensured by ensuring a dead time (or blanking time) between the respective switch-on phases of the JFET transistors.

[0006] During the dead time, both JFET transistors within a half-bridge are switched off and load currents flow through an existing freewheeling path of the upper or lower JFET transistor of this half-bridge, depending on the current direction.

[0007] G. Kampitsis, P. Stefas, N. Chrysogelos, S. Papathanassiou and S. Manias, “Assessment of the reverse operational characteristics of SiC JFETs in a diodeless inverter,” IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, 2013, pp. 477-482, doi: https: / / doi.org / 10.1109 / IECON.2013.6699182, discloses a 3-phase, 2-level half-bridge-based circuit topology (a so-called “B6 topology”) based on a JFET transistor implementation. Disclosure of the invention

[0008] According to a first aspect of the present invention, a circuit arrangement for reducing dead time losses of an inverter, in particular a voltage-supplied pulse-controlled inverter, is proposed, wherein the circuit arrangement comprises a half-bridge arrangement comprising a first switch and a second switch, a load, a control unit and a driver unit, wherein at least the first switch is designed as a junction field-effect transistor (JFET).

[0009] The load is connected to a center point of the half-bridge arrangement and is at least partially, and preferably predominantly, an inductive load. The half-bridge arrangement is configured to be connected to a DC voltage source, which can be configured, for example, as an intermediate circuit capacitor, and to provide an AC voltage to the load by means of complementary control of the first switch and the second switch by the control unit based on a voltage of the DC voltage source.

[0010] It should be noted that the first switch can be used as the "low-side" switch of the half-bridge arrangement (ie, as a switch that is closer to the low potential of the DC voltage source) or as the "high-side" switch of the half-bridge arrangement (ie, as a switch that is closer to the high potential of the DC voltage source), while the second switch occupies the other arrangement position within the half-bridge.

[0011] The control unit is configured to maintain a dead time between the complementary switching of the first switch and the second switch to prevent a short circuit of the DC voltage source via simultaneously switched switches. The control unit is configured, for example, as an ASIC, FPGA, processor, digital signal processor, microcontroller, or similar.

[0012] Based on control by the control unit, the driver unit is configured to provide a dead-time voltage (i.e., a voltage applied at least partially during the dead time of the first switch) to a gate of the first switch during a turn-on process and / or during a turn-off process of the first switch during the dead time, which dead-time voltage is lower than a threshold voltage of the first switch and higher than a voltage provided for blocking the first switch outside of the dead time. The use of a JFET therefore requires that the dead-time voltage be a more negative voltage than the negative threshold voltage of the JFET in order to keep the first switch in an off state during the dead time.

[0013] The inventive control of the gate of the first switch offers the particular advantage that dead-time losses can be reduced by using the dead-time voltage during respective switching operations, since a voltage drop across the first switch in the 3rd quadrant (reverse operation) can be reduced by increasing the gate voltage due to the electrical properties of junction transistors. This enables, for example, a reduction in the chip area of ​​the first switch due to the associated lower load on the first switch, which can, for example, lead to cost savings.

[0014] The subclaims show preferred developments of the invention.

[0015] Further preferably, the dead-time voltage is a voltage that is as close as possible to the threshold voltage of the first switch while maintaining a required predefined tolerance. By keeping the dead-time voltage as close as possible to the threshold voltage, particularly low dead-time losses can be achieved. By taking the tolerance into account when determining the dead-time voltage, it can be ensured that the first switch is reliably in the off state.

[0016] Particularly preferably, the dead time voltage is between -11.5 V and -19.5 V, preferably between -12 V and -18 V and particularly preferably between -13 V and -15 V, without thereby imposing a restriction to these voltage ranges.

[0017] Further preferably, the second switch is also designed as a junction field effect transistor, while the circuit arrangement is configured to control the second switch during the dead time in a manner corresponding to the control of the first switch.

[0018] In an advantageous embodiment of the present invention, the circuit arrangement is configured to dynamically adapt the dead-time voltage depending on current boundary conditions. In this way, for example, temperature influences and / or a value of a switched current and / or an intermediate circuit voltage and / or a gate voltage and / or a gate current and / or a junction temperature of the respective switches, etc., can be taken into account when determining a suitable dead-time voltage, so that, for example, despite changing boundary conditions, the lowest possible dead-time voltage can be set in order to achieve the lowest possible dead-time losses.

[0019] In a further advantageous embodiment of the present invention, the circuit arrangement is configured to dynamically adapt a time and / or duration of the provision of the dead-time voltage within the dead time depending on current boundary conditions (e.g., those mentioned above). In other words, it is not necessary for the dead-time voltage to be applied during the entire dead time. Instead, advantages according to the invention can also be achieved if the dead-time voltage is applied only in a partial phase of the dead time.

[0020] Advantageously, it is furthermore possible for the driver unit to be configured to provide respective voltages for switching on and / or off respective switches and / or the dead-time voltage on the basis of voltage-controlled branches which are switched by corresponding transistors and / or on the basis of current-controlled branches.

[0021] Furthermore, it is possible for the driver unit to be configured to provide the dead-time voltage based on a Zener diode. For example, the dead-time voltage can advantageously be derived from the voltage provided for switching off the first switch and / or the second switch outside of the dead time by using the Zener diode.

[0022] In a further advantageous embodiment of the present invention, the driver unit is configured to independently provide the dead-time voltage in response to receiving a control signal for switching on and / or switching off from the control unit. In other words, the driver unit is configured to receive only signals for switching on and off from the control unit and, in response to these signals, to generate the dead-time voltage provided for the dead time itself and / or to apply it to the gate of the respective switch. For this purpose, suitable delay elements can be provided in the driver unit, for example, on the basis of which the dead-time voltage is automatically switched to a voltage different from the dead-time voltage after a predefined time in order to apply a regular switch-on voltage or a regular switch-off voltage to the gate of the respective switch.Alternatively or additionally, the driver unit is configured to provide the dead-time voltage in response to receiving a control signal for providing the dead-time voltage from the control unit. In this case, the control unit itself specifies all gate voltages accordingly.

[0023] According to a second aspect of the present invention, an electrical system is proposed which comprises a circuit arrangement according to the first aspect of the invention and a DC voltage source, wherein the DC voltage source is configured to provide a DC voltage to the circuit arrangement, and wherein the circuit arrangement is configured to generate an AC voltage based on the DC voltage and to operate the load using the AC voltage. The features, combinations of features, and the advantages resulting therefrom correspond to those explained in connection with the first aspect of the invention, so that reference is made to the above explanations to avoid repetition. Short description of the drawings

[0024] Embodiments of the invention are described in detail below with reference to the accompanying drawings. In the drawing: Fig. 1 is a circuit diagram of an embodiment of an electrical system according to the invention with a circuit arrangement according to the invention; and Fig. 2 exemplary signal curves within the circuit arrangement according to the invention. Embodiments of the invention

[0025] Fig. 1 shows a circuit diagram of an embodiment of an electrical system according to the invention with a circuit arrangement according to the invention for reducing dead time losses of an inverter.

[0026] The circuit arrangement comprises a half-bridge arrangement comprising a first switch 10 and a second switch 15. For the sake of simplicity, only the first switch 10 is embodied as an n-channel junction field-effect transistor, whereby the second switch 15 can also advantageously be embodied as a junction field-effect transistor. Accordingly, the control system according to the invention described below for the first switch 10 can be readily implemented for the second switch 15 as well, as will be readily apparent to those skilled in the art.

[0027] An inductive load 20, through which a load current IL flows, is arranged at a center point M of the half-bridge arrangement. The circuit arrangement according to the invention further comprises a control unit 30 designed as a microcontroller, a first driver unit 40, and a second driver unit 45, wherein the second driver unit 45 is provided for the second switch 15 and is configured to control the second switch 15 based on a second control signal S' provided by the circuit unit 30. If the second switch 15 is designed as a junction field-effect transistor, the second driver unit 45 can preferably be designed analogously to the first driver unit 40.

[0028] The half-bridge arrangement is electrically connected to an intermediate circuit capacitor 50, which essentially behaves like a DC voltage source.

[0029] By means of a complementary control of the first switch 10 and the second switch 15 by the control unit 30, the half-bridge arrangement is configured to provide an alternating voltage to the load 20 on the basis of a voltage UDC of the intermediate circuit capacitor 50.

[0030] The control unit 30 is configured to maintain a dead time between the complementary switching of the first switch 10 and the second switch 15 on the basis of a first control signal S and the second control signal S' in order to prevent a short circuit of the intermediate circuit capacitor 50.

[0031] The first driver unit 40 is configured, on the basis of control by the control unit 30, to provide a gate of the first switch 10 with a dead-time voltage UT during a switch-on operation and / or during a switch-off operation of the first switch 10 during the dead time, which dead-time voltage is smaller than a threshold voltage of the first switch 10 and greater than a switch-off voltage UA provided for blocking the first switch 10 outside the dead time.

[0032] In addition, the first driver unit 40 is configured to provide a turn-on voltage UE in response to a control by the control unit 30 in order to turn on the first switch 10.

[0033] The dead time voltage UT provided by the first driver unit 40 here corresponds, for example, to a value of -13 V, while the turn-on voltage UE corresponds, for example, to a value of 0 V and the turn-off voltage corresponds, for example, to a value of -20 V.

[0034] Advantageously, the circuit arrangement is configured to dynamically adapt the dead-time voltage UT depending on current boundary conditions in order to always achieve an optimal reduction of dead-time losses while simultaneously ensuring an off state of the first switch 10 during the dead-time phases.

[0035] Further advantageously, the first driver unit 40 is configured to provide the dead-time voltage UT by means of a Zener diode (not shown) on the basis of the turn-off voltage UA.

[0036] Fig. 2 shows exemplary signal curves within the circuit arrangement according to the invention during a switch-off process of the Fig. 1, wherein the respective horizontal axes of the diagrams represent a time t.

[0037] The top diagram in Fig. 2 shows a second signal S', on the basis of which the Fig. 1 is controlled. The second signal S' has a signal state SE when the second switch 15 is to be switched on or left in the switched-on state, and it has a signal state SA when the second switch 15 is to be switched off or left in the switched-off state. Furthermore, in this diagram, the switching between the complementary switching of the first switch 10 (see Fig. 1) and the second switch 15 required dead time.

[0038] The second diagram from the top in Fig. Figure 2 shows respective signal states SE, ST, SA of a first signal S, on the basis of which the first switch 10 is controlled. The signal states SE and SA correspond to the states in the first diagram, while the additional state ST is responsible for activating the Fig. 1 described dead time voltage UT is provided.

[0039] The third diagram from the top in Fig. 2 shows through the Fig. The first driver unit 40 described in Figure 1 generates gate voltages Ugs, which can assume the voltage values ​​UE (turn-on voltage), UT (dead-time voltage), UA (turn-off voltage) for driving the gate of the first switch 10. Furthermore, the threshold voltage Uth of the first switch 10 is shown.

[0040] The fourth diagram from the top in Fig. 2 shows the drain-source voltages of the first switch 10 corresponding to the control voltages UE, UT, UA.

[0041] The fifth diagram from the top in Fig. 2 shows the drain current Id flowing through the first switch 10.

[0042] From the bottom diagram in Fig. 2 shows the reduced power loss (solid line) achieved due to the control according to the invention during the dead time phase T in comparison to power loss (dashed-dotted line) due to a conventional control.

[0043] It should be noted in general that the respective Fig. 2 can preferably represent a switching-on process of the first switch 10 in a time-mirrored form. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] G. Kampitsis, P. Stefas, N. Chrysogelos, S. Papathanassiou and S. Manias, “Assessment of the reverse operational characteristics of SiC JFETs in a diodeless inverter,” IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, 2013, pp. 477-482

[0007] https: / / doi.org / 10.1109 / IECON.2013.6699182,

[0007]

Claims

[1] Circuit arrangement for reducing dead time losses of an inverter comprising: - a half-bridge arrangement comprising a first switch (10) and a second switch (15), - a load (20), - a control unit (30), and - a driver unit (40), wherein - at least the first switch (10) is designed as a junction field effect transistor, - the load (20) is connected to a center point of the half-bridge arrangement and is at least partially an inductive load, - the half-bridge arrangement is designed to be connected to a DC voltage source (50) and to provide an AC voltage to the load (20) by means of a complementary control of the first switch (10) and the second switch (15) by the control unit (30) on the basis of a voltage (UDC) of the DC voltage source (50), - the control unit (30) is arranged to maintain a dead time (T) between the complementary switching of the first switch (10) and the second switch (15) in order to prevent a short circuit of the DC voltage source (50), and - the driver unit (40) is configured, on the basis of control by the control unit (30), to provide a gate of the first switch (10) with a dead-time voltage (UT) during a switch-on process and / or during a switch-off process of the first switch (10) during the dead time (T), which dead-time voltage is lower than a threshold voltage (Uth) of the first switch (10) and higher than a voltage (UA) provided for blocking the first switch (10) outside the dead time (T). [2] Circuit arrangement according to claim 1, wherein the dead-time voltage (UT) is a voltage which is as close as possible to the threshold voltage (Uth) of the first switch (10) while maintaining a required predefined tolerance and is below the threshold voltage (Uth). [3] Circuit arrangement according to one of the preceding claims, wherein the dead time voltage is between -11.5 V and -19.5 V, preferably between -12 V and -18 V and particularly preferably between -13 V and -15 V. [4] Circuit arrangement according to one of the preceding claims, wherein - the second switch (15) is designed as a junction field effect transistor, and - the circuit arrangement is arranged to carry out a control of the second switch (15) during the dead time (T) in a manner corresponding to the control of the first switch (10). [5] Circuit arrangement according to one of the preceding claims, wherein the circuit arrangement is arranged to dynamically adapt the dead-time voltage (UT) as a function of current boundary conditions. [6] Circuit arrangement according to one of the preceding claims, wherein the circuit arrangement is arranged to dynamically adapt a time and / or a duration of a provision of the dead time voltage (UT) within the dead time (T) depending on current boundary conditions. [7] Circuit arrangement according to one of the preceding claims, wherein the driver unit (40) is arranged to generate respective voltages (UE, UA) for switching on and / or for switching off respective switches (10, 15) and / or the dead time voltage (UT) on the basis of - voltage-controlled branches, which are switched by corresponding transistors, and / or - to provide current-carrying branches. [8] Circuit arrangement according to one of the preceding claims, wherein the driver unit (40) is arranged to provide the dead-time voltage (UT) on the basis of a Zener diode. [9] Circuit arrangement according to one of the preceding claims, wherein the driver unit (40) is arranged - to provide the dead-time voltage (UT) independently in response to receipt of a control signal (S) for switching on and / or switching off from the control unit (30), and / or - to provide the dead-time voltage (UT) in response to receipt of a control signal (S) for providing the dead-time voltage (UT) from the control unit (30). [10] Electrical system comprising: - a circuit arrangement according to one of the preceding claims, and - a DC voltage source (50), wherein - the DC voltage source (50) is arranged to provide the circuit arrangement with a DC voltage (UDC), and - the circuit arrangement is designed to generate an alternating voltage on the basis of the direct voltage (UDC) and to operate the load (20) by means of the alternating voltage.

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