GATE DRIVER ERROR MESSAGE

Abstract

Concepts are provided for identifying the gate driver of a gate driver system that has reported a fault. The gate driver system includes a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a fault detected by the respective gate driver and an operating state. Timing arrangements are provided for each of the gate drivers, each timing arrangement configured to switch a common node to a first state in response to the fault output node of the respective gate driver being placed in the fault state. Then, after a predetermined period of time has elapsed since a trigger event, the common node is released from the first state.Since the predetermined time period is different for each of the timing devices (and thus each of the gate drivers), the time period between the trigger event and the release of the common node from the first state can be measured to identify the gate driver that reported a fault (i.e., the gate driver that switched the common node to the first state). Thus, the proposed concept allows for the identification of the gate driver that reported the fault while using only a single output pin (e.g., connected to the common node).

Description

FIELD OF THE INVENTION

[0001] The present invention relates to gate drivers and, more particularly, to systems and methods for identifying the gate driver that has reported a fault. BACKGROUND OF THE INVENTION

[0002] Gate drivers are power amplifiers that accept a low-power input from a controller and generate a high-current drive input to the gate of a high-power transistor (e.g., an IGBT or power MOSFET). For example, a motor drive system may include six gate drivers, each providing an input to a respective gate of a high-power transistor. Gate drivers often include a pin (i.e., a fault output node) for reporting a fault detected by the gate driver. This pin can report internal faults of the gate driver and / or faults of the transistor the gate driver controls.

[0003] However, the fault output node of each gate driver is typically connected to a single I / O pin to reduce the number of I / O pins of a controller. Thus, once a fault is detected by one of the gate drivers, the single I / O pin indicates the presence of the fault, but the identity of the gate driver reporting the fault is lost. In other words, with this connection method, it is difficult to distinguish which gate driver reported the fault, especially if the fault is triggered by random noise.

[0004] The inventors have thus identified a need to identify the gate driver that reported the error while minimizing the required number of I / O pins. SUMMARY OF THE INVENTION

[0005] According to one aspect of the invention, a gate driver system is provided. The gate driver system comprises a plurality of gate drivers, each gate driver having an error output node switchable between an error state indicating an error detected by the respective gate driver and an operating state. The system further comprises: a common node switchable between a first state and a second state; a timing arrangement for each of the gate drivers, each timing arrangement being connected to the fault output node of the respective gate driver and the common node, each timing arrangement being configured to: Setting the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state; and Releasing the common node from the first state in response to a predetermined period of time having elapsed since a trigger event, wherein the predetermined period of time of each timing arrangement is different.

[0006] Concepts are provided for identifying the gate driver of a gate driver system that has reported a fault. The gate driver system includes a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a fault detected by the respective gate driver and an operating state. Timing arrangements are provided for each of the gate drivers, each timing arrangement configured to switch a common node to a first state in response to the fault output node of the respective gate driver being placed in the fault state. Then, after a predetermined period of time has elapsed since a trigger event, the common node is released from the first state.Since the predetermined time period is different for each of the timing devices (and thus each of the gate drivers), the time period between the trigger event and the release of the common node from the first state can be measured to identify the gate driver that reported a fault (i.e., the gate driver that switched the common node to the first state). Thus, the proposed concept allows for the identification of the gate driver that reported the fault while using only a single output pin (e.g., connected to the common node).

[0007] In typical gate drivers, all error output nodes (each corresponding to a gate driver) are connected to a common node. This serves to minimize the number of I / O pins required to report an error. As a result, when an error is detected by a gate driver (or a selection of gate drivers), the common node indicates that an error is detected by one (or more) of the gate drivers, but does not indicate which gate driver reported the error. Identifying the gate driver that reported the error can be useful for locating and subsequently correcting the cause of the error.

[0008] Of course, alternatively, each of the error output nodes can be connected to a different I / O pin. Once an error is detected by one of the gate drivers, the corresponding I / O pin indicates that an error is present, and the position is determined in a simple manner. However, this method requires a large number of I / O pins.

[0009] The disclosed invention provides a solution to this problem without increasing the number of I / O pins required to report the error. In particular, the disclosed invention enables the identification of the gate driver that reported the error. This is achieved via a timing arrangement associated with each of the gate drivers that initially sets the common node to the first state and only releases the common node from the first state after a predetermined period of time. Accordingly, an entity observing only the common node will initially be aware of the presence of an error when the common node is set to the first state and will be able to identify the gate driver that reported the error by monitoring the time period between a trigger event and the release of the common node from the first state.

[0010] That is, since the trigger event and the predetermined time period associated with each gate driver (provided by the timing arrangement) are known, the common node can be monitored to identify the gate driver associated with the reported fault. Accordingly, the common node can be connected to a single I / O pin to report both the detection and location of the fault.

[0011] In some embodiments, the first state may be a low state and the second state may be a high state. That is, each timing device may individually set the common node to a low state in response to the respective gate driver's fault output node being placed in the fault state. Then, the common node may be released from the low state (i.e., pulled / switched to the high state) after a predetermined period of time associated with the respective timing device.

[0012] Accordingly, a falling edge of the common node may indicate that a fault output node of at least one of the gate drivers has been placed in the fault state. Then, after a predetermined period of time since a trigger event, a rising edge of the common node may indicate that the gate driver has the fault output node placed in the fault state. In other words, the time period between the trigger event and the rising edge at the common node will indicate which of the fault output nodes has been placed in the fault state (and thus provide clues to the location of the fault).

[0013] However, in some embodiments, the first state may be a high state and the second state may be a low state. Accordingly, a rising edge of the common node may indicate that a fault output node of at least one of the gate drivers has been placed in the fault state. Then, after a predetermined period of time since a trigger event, a falling edge of the common node may indicate that the gate driver has the fault output node placed in the fault state. In other words, the time period between the trigger event and the falling edge at the common node will indicate which of the fault output nodes has been placed in the fault state (thus providing clues to the location of the fault).

[0014] The system may further include a controller connected to the common node. The controller may be configured to measure a time period between the trigger event and the switching of the common node to the second state and identify the gate driver corresponding to the detected fault based on the measured time period and the predetermined time period of each respective timing arrangement.

[0015] The controller can therefore identify the gate driver having the fault output node that has transitioned to the fault state by monitoring / measuring / determining a time between the tiger event and the transition of the common node to the second state. That is, the controller can query a list of predetermined time periods and associated gate drivers and compare the time period elapsed since the tiger event and the transition of the common node to the second state against the list to determine the gate driver associated with the reported fault.

[0016] Of course, other means for providing the identity of the gate driver may be implemented in other embodiments. For example, a sensor output may be provided to indicate the time of the trigger event, followed by the time at which the common node switches to the second state. A user may then be able to tell (from the time duration of the two sensor outputs) which gate driver reported the error.

[0017] The trigger event can be either the common node being put into the first state or the fault output node of the respective gate driver being put into the operating state.

[0018] In other words, in some cases, each of the timing devices is configured to delay a respective predetermined time period from the time it places the common node in the first state before releasing the common node from the first state. That is, the timing device maintains the common node in the first state until the predetermined time period has elapsed, at which time the common node is released from the first state.

[0019] In other cases, each of the timing devices is configured to delay a respective predetermined time period from the time the fault output node of the associated gate driver is brought into the operating state (from the fault state) before releasing the common node from the first state. In other words, the timing device waits a predetermined time period from a reset signal that resets each of the fault output nodes to the operating state.

[0020] If the triggering event is the common node being placed in the first state, each timing arrangement may include a ramp generator and control logic. The ramp generator may be configured to generate a ramped output voltage in response to the fault output node of the respective gate driver being placed in the fault state. The control logic may be configured to place the common node in the first state in response to the fault output node of the respective gate driver being placed in a fault state and the ramped output voltage not satisfying a first voltage condition, and to release the common node from the first state in response to the ramped output voltage satisfying the first voltage condition.

[0021] This means that the ramp generator outputs a rising or falling voltage after the fault output node is placed in the fault state. The control logic monitors the output voltage of the ramp generator and compares the output voltage to a first voltage condition. Depending on the result of the comparison (i.e., whether the output voltage satisfies the first voltage condition or not), the common node is either placed in the first state or released from the first state. The common node is released from the first state as soon as the output voltage satisfies the first condition.

[0022] Accordingly, each timing arrangement is configured to place the common node into the first state and to release the common node from the first state after a predetermined period of time since the trigger event (i.e., the common node is placed into the first state). Either the rate at which the rate generator varies its associated output voltage or the first voltage condition can be adjusted to ensure this operation according to the predetermined period of time.

[0023] In some embodiments, the ramp generator of each timing arrangement may be configured to generate the respective ramped output voltage such that the respective ramped output voltage satisfies the first voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the trigger event. In this case, the first voltage condition of each timing arrangement may be the same.

[0024] In this case, the ramp generator of each timing device is different to ensure that each timing device has a different associated predetermined time period. In fact, each ramp generator requires a different amount of time for its associated output voltage to satisfy the first voltage condition.

[0025] Alternatively, the first voltage condition of each timing arrangement may be selected such that the ramped output voltage generated by the respective ramp generator satisfies the respective first voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the triggering event.

[0026] In this case, the first voltage condition of each timing device is different to ensure that each timing device has a different associated predetermined time period. Indeed, if the ramp generator of each respective timing device is the same, each ramp generator requires a different time period to satisfy the respective voltage condition of each timing device.

[0027] The control logic of each timing arrangement may be further configured to place the common node into the first state in response to the ramped output voltage satisfying a second common voltage condition and the first voltage condition.

[0028] Accordingly, once the common voltage condition is met, the common node is returned to the first state. This can be useful to further indicate that a fault has been detected. That is, the common node is returned to the first state indicating a fault after being released for the purpose of indicating the identity of the gate driver reporting the fault.

[0029] In some cases, the ramp generator may include a capacitor, a current source, and a switch arranged to allow the current source to charge the capacitor in response to the fault output node of the respective gate driver being placed in the fault state.

[0030] This can provide a simple and inexpensive ramp generator for the purposes of the invention. However, other ramp generator arrangements are possible and would be readily apparent to those skilled in the art.

[0031] The capacitance of the capacitor and / or a current strength of the current source of each ramp generator can be selected such that the respective ramp-shaped output voltage meets the first voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the trigger event. In this case, the first voltage condition of each timing arrangement can be the same.

[0032] In fact, the capacitor and / or the current source of the ramp generator are parameters that can be changed to ensure that the output voltage meets the voltage condition after the respective predetermined period of time.

[0033] If the triggering event is the fault output node of the respective gate driver being placed in the operating state, each timing arrangement may include a ramp generator and control logic. The ramp generator may be configured to generate a ramped output voltage in response to the fault output node of the respective gate driver being placed in the operating state. The control logic may be configured to place the common node in the first state in response to the fault output node of the respective gate driver being placed in a fault state and the ramped output voltage not satisfying a voltage condition. The control logic may also be configured to release the common node from the first state in response to the ramped output voltage satisfying a voltage condition.

[0034] That is, the ramp generator outputs a rising or falling voltage after the fault output node is placed in the operating state (i.e., the fault output node is reset). The control logic sets the common node to the first state in response to the fault output node being placed in the fault state. The control logic then monitors the ramp generator's output voltage (once the fault output node is reset) and compares the output voltage to a voltage condition. The common node is released from the first state once the output voltage meets the first condition.

[0035] In some embodiments, the ramp generator of each timing arrangement may be configured to generate the respective ramped output voltage such that the respective ramped output voltage satisfies the voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the trigger event. In this case, the voltage condition of each timing arrangement may be the same.

[0036] Alternatively, the voltage condition of each timing arrangement may be selected such that the ramped output voltage generated by the respective ramp generator satisfies the respective voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the trigger event.

[0037] The control logic of each timing arrangement may include a comparator configured to compare the ramped output voltage and a reference voltage (the reference voltage based on the voltage condition) and to place the common node into the first state or release the common node from the first state based on the comparison.

[0038] In some embodiments, the system may further comprise a biasing arrangement configured to bias the common node to the second state. Each timing arrangement may further comprise a switching arrangement connected to the common node, wherein the switching arrangement of each respective timing arrangement is configured to place the common node into the first state in response to the fault output node of the respective gate driver being placed in the fault state.

[0039] As a result of the biasing arrangement, the common node is switched to the second state once the common node is released from the first state. Meanwhile, the switching arrangement of each of the timing arrangements allows the timing arrangement to pull or switch the common node to the first state. Accordingly, the common node will be in the second state if none of the switching arrangements pulls the common node to the first state. If one or more of the timing arrangements switch / switch the common node through the respective switching arrangements, the common node is placed in the first state until all timing arrangements allow the common node to be released.

[0040] Additionally, a method is provided for determining a location of a fault in a gate driver system comprising a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a fault detected by the respective gate driver and an operating state. The method comprises: Setting a common node to a first state in response to the fault output node of one of the gate drivers being set to the fault state; and Releasing the common node from the first state in response to a predetermined period of time having elapsed since a trigger event, the predetermined period of time being associated with the gate driver whose output node is placed in the fault state, and wherein the predetermined time period associated with each gate driver is different. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The invention will now be described by way of example with reference to the accompanying drawings in which: Fig. 1 is a circuit diagram showing a gate driving system according to a generalized example of the prior art; Fig. 2 is a simplified block diagram of a gate driver system according to an embodiment of the invention; Fig. 3 is a circuit diagram of a timing arrangement according to an embodiment of the invention; Fig. 4 a timing diagram of the circuit of Fig. 3 is; Fig. 5 is a circuit diagram of a gate driver system incorporating the timing arrangement of Fig. 3 contains; Fig. 6 a timing diagram of the general concept of the gate driver system of Fig. 5 is; Fig. 7 is a timing diagram of the gate driver system according to an embodiment of the invention in a situation where multiple gate drivers report a fault simultaneously; Fig. 8 is a circuit diagram of a timing arrangement according to another embodiment of the invention; Fig. 9 a timing diagram of the circuit of Fig. 8 is; Fig. 10 is a circuit diagram of a gate driver system incorporating the timing arrangement of Fig. 8 contains; Fig. 11 is a circuit diagram of a timing arrangement according to another embodiment of the invention; Fig. 12 a timing diagram of the circuit of Fig. 11 is; Fig. 13 a circuit diagram of the timing arrangement of Fig. 11, having a first means for setting a respective predetermined time period; Fig. 14 a circuit diagram of the timing arrangement of Fig. 11, having a second means for setting a respective predetermined time period; Fig. 15 a circuit diagram of the timing arrangement of Fig. 11, having a third means for setting an associated predetermined time period; Fig. 16 a circuit diagram of the timing arrangement of Fig. 11, which has a fourth means for setting a respective predetermined time period; and Fig. 17 is a flowchart of a method for determining a location of a fault in a gate driver system according to an embodiment of the invention.

[0042] It should be noted that these figures are schematic and not drawn to scale. Relative dimensions and proportions of parts of these figures have been exaggerated or reduced in size for clarity and convenience. DETAILED DESCRIPTION

[0043] To understand the present disclosure, it is important to understand the operation of a typical gate driver system. Fig. 1 is a circuit diagram of a gate driver system 1.

[0044] As shown, each gate driver 10a-f provides an input to a gate of a respective switch 12a-f (e.g., an IGBT, a GaN transistor, or a power MOSFET). Each gate driver 10a-f also provides the capacity to report that a fault has been detected. The fault may, for example, be an internal fault of the gate driver 10a-f, may correspond to the switch 12a-f, or a component connected to the switch 12a-f. In particular, each gate driver 10a-f reports the presence of a fault through a fault output node 14a-f. The fault output node 14a-f may be in an operating state (e.g., a high or clear state), indicating that no fault has been detected by the gate driver, or in a fault state (e.g., a low state), indicating that a fault has been detected by the respective gate driver.

[0045] Each of the fault output nodes 14a-f is typically connected to each other via a common node 20. Consequently, the common node 20 signals that a fault is present when one of the fault output nodes 14a-f is in a fault state. Thus, the gate driver 10a-f that detected the fault cannot be determined from information about the common node 20.

[0046] In particular, each of the gate drivers 10a-f is typically configured to individually pull the common node 20 to a low state (e.g., ground) when they detect a fault. Because the common node 20 is biased to a high state (e.g., VDD) by a biasing arrangement 30, the common node 20 is in the high state if none of the gate drivers 10a-f detects a fault. This binary system does not allow for reporting which of the gate drivers 10a-f detected and reported a fault.

[0047] Fig. Figure 2 shows a simplified block diagram of an embodiment of the invention. In particular, Fig. 2 shows a gate driver system 100 that enables the identification of the gate driver 10a-c that has reported an error by a common output node 20.

[0048] Similar to Fig. 1, the gate driver system 100 includes a plurality of gate drivers 10a-c. As described above, each gate driver 10a-c has a fault output node 14 that is switchable between a fault state and an operating state. Three gate drivers 10a-c are shown, but there may be only two gate drivers, or there may be more than three gate drivers.

[0049] Additionally, a timing arrangement 40a-c is provided for each of the gate drivers 10a-c. Each timing arrangement 40a-c is connected to the fault output node 14a-c of the respective gate driver 10a-c and a common node 20. That is, each gate driver 10a-c has a timing arrangement 40a-c connected between the fault output node 14a-c of the gate driver 10a-c and a common node 20. To be clear, all timing arrangements 40a-c are connected to the same common node 20.

[0050] Each timing arrangement 40a-c may be implemented separately from the gate driver 10a-c (e.g., connected to a pin of the gate driver 10a-c that outputs an error signal as the error output node 14a-c). Alternatively, one or more components of the timing arrangement 40a-c may be implemented as part of the gate driver 10a-c, with the timing arrangement 40a-c connected to an internal error node of the gate driver 10a-c as the error output node 14a-c.

[0051] The common node 20 is switchable between a first state and a second state. In the illustrated case, the common node 20 is biased toward a second state by a biasing arrangement 30 and can be switched / pulled to the first state by any of the timing arrangements 40a-c. The first state in the illustrated embodiment is a low state (i.e., a grounded state). The second state in the illustrated embodiment is a high state (i.e., VDD). However, modifications to the illustrated embodiment may be made such that the first state is a high state and the second state is a low state.

[0052] In some implementations, the common node 20 may be connected to an I / O pin that allows a user to monitor, detect, and diagnose errors.

[0053] Each timing arrangement 40a-c is configured to place the common node 20 into the first state in response to the fault output node 14a-c of the respective gate driver 10a-c being placed into the fault state. In other words, when a gate driver 10a-c detects a fault, the fault output node 14a-c is placed into a fault state. The timing arrangement 40a-c associated with the gate driver 10a-c will, in turn, place the common node 20 into the first state. In the illustrated example, this is achieved by closing a switching arrangement 50a-c, such that the common node 20 is pulled into the first (i.e., low) state.

[0054] Further, each timing arrangement 40a-c is configured to release the common node 20 from the first state in response to a predetermined period of time having elapsed since a trigger event. In the illustrated example, this is achieved by opening the switching arrangement 50a-c so that the common node 20 can be pulled back to the second (i.e., high) state by the biasing arrangement 30. In other words, the timing arrangement 40a-c controls the switching arrangement 50a-c to remove the short circuit of the common node 20 to ground after a predetermined period of time has elapsed since a trigger event.

[0055] To distinguish between the different gate drivers 10a-c, the predetermined time period of each timing device 40a-c is different. That is, each of the timing devices 40a-c releases the common node from the first state after a different time period since the same trigger event.

[0056] To be clear, the predetermined time period of each timing arrangement 40a-c may be a specific time period or may be a time range that takes into account tolerances with external components. In either case, the predetermined time periods are different in that they can be distinguished from one another (i.e., if the predetermined time periods are time ranges, then these time ranges do not overlap).

[0057] For example, if a fault is detected by a first gate driver 10a, a first timing arrangement 40a may wait 1 second since a trigger event before releasing the common node 20. In the same system, if a fault is detected by a second gate driver 10b, a second timing arrangement 40b may wait 2 seconds since a trigger event before releasing the common node 20.

[0058] Accordingly, by monitoring the common node 20 and determining a time between a trigger event and the release of the common node 20 from the first state, the gate driver 10a-c that detected the fault can be determined.

[0059] For this purpose, the gate driver system 100 may further include a controller 60 connected to the common node 20. The controller 60 is configured to measure a time period between the trigger event and the switching of the common node 20 to the second state. The controller 20 then identifies the gate driver 10a-c corresponding to the detected fault based on the measured time period and the predetermined time period of each respective timing arrangement 40a-c.

[0060] In some implementations of the invention, the triggering event may be that the common node 20 is placed in the first state. In this case, when the respective fault output node 14a-c is placed in a fault state, the timing arrangement 40a-c places the common node 20 in the first state, delays a predetermined period of time, and then releases the common node 20 from the first state. Of course, each timing arrangement 40a-c delays a different predetermined period of time, and therefore, this delay can be monitored to determine that the gate driver 10a-c is reporting the fault.

[0061] In other implementations, the trigger event may be that the fault output node 14a-c of the respective gate driver 10a-c is placed in the operating state. In other words, the trigger event is when the fault output node 14a-c is reset / cleared after being in a fault state. Thus, the trigger event may equally be the generation of a reset signal. In this case, when the fault output node 14a-c is placed in the operating state, the timing arrangement 40a-c delays a predetermined period of time and then releases the common node 20 from the first state. Of course, each timing arrangement 40a-c delays a different predetermined period of time, and therefore, this delay can be monitored to determine that the gate driver 10a-c is reporting the fault.

[0062] Of course, implementations may include other trigger events that would be readily apparent to one skilled in the art. For example, the trigger event may be the occurrence of a user signal that begins the delay before the shared node 20 is released from the first state.

[0063] With reference to Fig. 3 shows a circuit diagram of an exemplary embodiment of a timing arrangement 200 for a gate driver 10a-c according to an aspect of the present invention. The timing arrangement 200 of Fig. 3 acts according to the trigger event, which is the setting of the common node 20 into the first state. That is, the timing arrangement 200 of Fig. 3 first sets the common node 20 to the first state, delays a predetermined period of time, and then releases the common node 20 from the first state. The operation of the timing arrangement 200 of Fig. 3 is also made with reference to the timing diagram of Fig. 4.

[0064] The timing arrangement 200 may be implemented in the gate driver 10a-c. That is, the error output node 14a-c of the gate driver 10a-c may be internal, and many of the components of the timing arrangement 200 of Fig. 3 may be provided in the respective gate driver 10a-c. Of course, each of these components may also be provided separately for the respective gate driver 10a-c, with the error output node 14a-c being an error output pin of the gate driver 10a-c.

[0065] As shown, the timing arrangement 200 is connected to the error output pin 14 of a gate driver 10 and a common node 20. The timing arrangement 200 includes a ramp generator 210, control logic 220, and switching arrangement 230.

[0066] The ramp generator 210 is configured to generate a ramp-shaped output voltage in response to the fault output node 14 of the respective gate driver 10 being placed in the fault state.

[0067] In particular, the ramp generator 210 includes a capacitor 212, a current source 214, and a switch 216 arranged to enable the current source 214 to charge the capacitor 212 in response to the fault output node 14 of the respective gate driver 10 being placed in the fault state. Accordingly, the switch 216 of the ramp generator 210 closes when the fault output node 14 of the gate driver 10 is in the fault state. The current source 214 begins to charge the capacitor 212, resulting in an increasing output voltage. The increasing output voltage is provided to the input of the control logic 220.

[0068] The current source 214 may be connected in series with the capacitor 212 or may be connected in parallel with the capacitor 212. Furthermore, the current source 214 may, in principle, also be implemented as a resistor connected to a voltage source.

[0069] The output voltage profile of the ramp generator 210 can be selected by appropriately selecting the capacitance of the capacitor 212 and / or the current strength of the current source 214.

[0070] Of course, the illustrated ramp generator 210 is merely exemplary, and other topologies of the ramp generator 210 are possible and could be readily implemented. For example, the ramp generator 210 may provide a sloping voltage output. Likewise, the output voltage of the ramp generator 210 may vary in a substantially linear manner or may vary in a nonlinear manner. The ramp generator 210 simply needs to generate a monotonic and predictably varying voltage to provide to the input of the control logic 220.

[0071] Control logic 220 is configured to place common node 20 in the first state in response to the fault output node 14 of gate driver 10 being placed in a fault state and the ramped output voltage not meeting a first voltage condition. Specifically, control logic 220 closes a switch of switching arrangement 230 to pull common node 20 into a low / ground state in response to the fault output node 14 being placed in a fault state.

[0072] Control logic 220 is then configured to release common node 20 from the first state in response to the ramped output voltage satisfying the first voltage condition. Specifically, control logic 220 opens the switch of switching arrangement 230 to release common node 20 from the low / ground state in response to the ramped output voltage satisfying the first voltage condition.

[0073] Additionally, control logic 220 of timing arrangement 200 may be further configured to place common node 20 into the first state in response to the ramped output voltage satisfying a second common voltage condition and the first voltage condition. Specifically, control logic 220 closes the switch of switching arrangement 230 to place common node 20 back into the low / ground state in response to the ramped output voltage satisfying the first and second voltage conditions.

[0074] For example, the first voltage condition may be that the output voltage of the ramp generator 210 is 2 V, and the second common voltage condition may be that the output voltage of the ramp generator 210 is 2.5 V. The ramp generator 210 may have a linearly increasing output voltage of 0.5 V per second. As a result, (once the fault output node 14 of the respective gate driver 10 is placed in a fault state), the common node 20 is placed in the first state at 0 s. At 4 s, the common node 20 is released from the first state. At 5 s, the common node 20 is placed in the first state. Of course, these parameter values ​​are intended only as an illustrative example.

[0075] In general, the time period t (i.e., the predetermined time period of the timing arrangement 200) between the common node 20 being placed in the first state and being released from the first state can be formulated as follows: t=C∗VREF1I

[0076] Where C is the capacitance of capacitor 212, I is the current of current source 214, and the first voltage condition is met as soon as the voltage across capacitor 212 exceeds VREF 1.

[0077] From [1], it can be seen that the first voltage condition and / or the ramp generator output voltage 210 (e.g., the capacitance of the capacitor 212 and / or the current of the current source 214) can be changed to adjust the predetermined time period of the timing arrangement 200. Accordingly, each timing arrangement 200 of a gate driver system can have one or more different voltage conditions and ramp generator output voltages to ensure that each timing arrangement 200 has a different predetermined time period.

[0078] Fig. 4 is a timing diagram of the timing arrangement 200 of Fig. 3.

[0079] During normal operation (i.e., when gate driver 10 has not detected a fault), fault output node 14 remains in a low (i.e., operating) state. As a result, there is no voltage across capacitor 212. Following the logic gates and comparators, the output of control logic 220 means that switch 230 is off, and therefore common node 20 remains in an enabled state (and is therefore in the second state due to a biasing arrangement 30). In particular, the output of AND gate 224 is low because the fault output node is low (although first comparator 222 is high), and the output from second comparator 226 is low because there is no voltage across capacitor 212. As a result, the output from OR gate 228 is low.

[0080] Once the fault output node 14 is placed in a high (i.e., fault) state, the switch 216 is turned on and the common node 20 is pulled to the first state. This is because the fault output node 14 is in the high state, resulting in a high output from the AND gate 224 (keeping the first comparator 222 high) and a high output from the OR gate 228. At this time, the switch 216 of the ramp generator 210 is closed, so the current source 214 begins to charge the capacitor 212, resulting in an increasing voltage output from the ramp generator 210. The first comparator 222 remains in the high state because the voltage across the capacitor 212 remains below the first voltage threshold VREF1 (i.e., the first voltage condition is not met). The second comparator 226 remains low because the voltage across the capacitor 212 remains below the second voltage threshold VREF2 (i.e.i.e. the second common voltage condition is not met).

[0081] Once the voltage across capacitor 212 exceeds the first voltage threshold VREF1 (i.e., satisfies the first voltage condition), the output of first comparator 222 falls low. Accordingly, the output from AND gate 224 becomes low, as does the output of OR gate 228. The switch of switching arrangement 230 therefore opens, enabling common node 20 from the first state. This should occur after the predetermined time period (t) has elapsed since fault output node 14 was placed in a high (i.e., fault) state. Again, second comparator 226 remains low because the voltage across capacitor 212 remains below the second voltage threshold VREF2 (i.e., the second common voltage condition is not satisfied).

[0082] Finally, the output of second comparator 226 goes high once the voltage across capacitor 212 exceeds the second voltage threshold VREF2 (i.e., satisfies the second common voltage condition). Accordingly, the output of OR gate 228 goes high, pulling common node 20 back to the first low state.

[0083] The time t between the first falling edge of a signal present at the common node 20 and the first rising edge of the signal present at the common node 20 should therefore substantially correspond to the predetermined time period.

[0084] Fig. 5 illustrates a circuit diagram of a gate driver system according to an embodiment of the invention, including timing arrangements 200a-c as shown in Fig. 3 shown.

[0085] Each gate driver has an associated timing arrangement 200a-200c connected between the respective fault output pin and a common node 20. The common node 20 is biased to a high state (i.e., the second state) by the (common) bias arrangement. When one of the fault output pins is placed in a fault state, the respective timing arrangement 200a-c operates as described above.

[0086] Of course, each timing arrangement 200a-c corresponds to a different predetermined time period because it has different first voltage conditions or ramp generator output voltage waveforms, as described above. This is illustrated by the timing diagram of Fig. 6, which represents a signal at the common node 20 when either a first timing device 200a, a second timing device 200b, or a third timing device 200c associated with a fault output node is placed in a fault state. As can be seen, there is a difference between the time at which the common node 20 is placed low and the time at which the common node 20 is enabled from the low state to the high state (represented as t1-3). By monitoring this time delay, the timing device 200a-c responsible for this signal at the common node 20 (and thus the gate driver 10a-c reporting the fault) can be identified.

[0087] Assuming that more than one of the gate drivers detects a fault at the same time, the common node 20 is switched / pulled to the first state by more than one of the timing arrangements 200a-c simultaneously. This is shown in Fig. 7, where three timing arrangements 200a-c switch the common node 20 to the first state simultaneously.

[0088] In this case, the timing arrangements 200a-b configured to have shorter predetermined time periods (e.g., t1 and t2) release the common node 20 from the first state. However, the common node 20 remains in the first state because the timing arrangement 200c with the longest predetermined time period (e.g., t3) continues to pull the common node 20 into the first state. Thus, only the gate driver with the longest predetermined time period can be identified at the common node 20. This is shown in Fig. 7, since the common node 20 only returns to the second state once all timing devices 200a-c release the common node 20 from the first state.

[0089] However, this shouldn't be a problem in practice, as the faults likely need to be resolved individually. Accordingly, once the issue causing the fault on the gate driver associated with the longest predetermined time period is resolved, the gate driver associated with the second-longest predetermined time period is identified.

[0090] Finally, as in Fig. 7 and according to the Fig. 6, the common node 20 is pulled / switched back to the first state as soon as the voltage output of the ramp generator satisfies the second common voltage condition.

[0091] With reference to Fig. 8 illustrates a circuit diagram of an exemplary embodiment of a timing arrangement 300 for a gate driver 10 according to another aspect of the present invention. The timing arrangement 300 of Fig. 8 acts according to the trigger event, which is the setting of the fault output node 14 of the respective gate driver 10 into the operating state. That is, the timing arrangement 300 of Fig. 8 is configured to initially place the common node 20 into the first state, wait for a reset signal to reset the fault output node 14 to the operating state, delay a predetermined period of time, and then release the common node 20 from the first state. The operation of Fig. 8 is also described with reference to the timing diagram of Fig. 9 explained.

[0092] When a fault condition of a fault output pin / node 14 of a gate driver 10 is cleared (into the operating state), a reset pin must typically be set to one (normally low) state for a defined time before being released to another (normally high) state. Accordingly, the trigger event can be reformulated by resetting the reset pin to a second state after being set to a first state for a defined period of time. Of course, in practice, this results in the fault output pin 14 of the gate driver 10 being set to the operating state (reset from the fault state), and therefore, for simplicity, this can be considered the trigger event.In other words, the time measured between the trigger event and the enabling of the common node 20 to the second state (to identify the gate driver reporting the error) is from a rising edge of a signal at a reset pin to a rising edge of a signal at the common node 20.

[0093] Alternatively, it may be the case that the trigger event and reset is when the reset pin is initially set to the low state, rather than from the time the reset pin is enabled to the high state (e.g., the falling edge of the reset signal in Fig. 9). In other words, the trigger event is when a falling edge is present on the reset pin, causing the error output node / pin 14 to be driven into the operating state. Therefore, the output of the ramp generator 310 can begin to rise from the time the reset pin is initially pulled into the (normally low) state.

[0094] As shown, the timing arrangement 300 is connected to the fault output node 14 of a gate driver 10 and a common node 20. The timing arrangement 300 includes a ramp generator 310 and control logic 320.

[0095] The ramp generator 310 is configured to generate a ramp-shaped output voltage in response to the fault output node 14 of the respective gate driver 10 being placed into the operating state.

[0096] In particular, the ramp generator 310 includes a capacitor 312 connected to ground, a first resistor 314 and a second resistor 316 connected in parallel and provided between a voltage source and the capacitor 312, and a diode 318 that allows current to flow through the second resistor 316 and the capacitor 312 to ground.

[0097] The output of the ramp generator 310 may be connected to the control logic 320, which includes a comparator 322 to control the common node 20 to be in the first state or the second state depending on the output of the ramp generator 310. However, as discussed with respect to Fig. 10, the output of ramp generator 310 may be connected to a bus node to which outputs of ramp generators associated with other gate drivers may be connected. In this case, comparator 320 may be a common comparator that may be provided prior to input to a controller 60 for timing measurement or as part of the controller 60.

[0098] Of course, the illustrated ramp generator 310 is only exemplary, and other topologies of the ramp generator 310 are possible and could be readily implemented. For example, the ramp generator 310 may provide a sloping voltage output. The output voltage of the ramp generator 310 may vary in a substantially linear manner or may vary in a nonlinear manner. The ramp generator 310 simply needs to produce a monotonic and predictably varying output voltage.

[0099] A switch 324 is connected across the capacitor, which is controlled based on the state of the fault output node 14. Accordingly, the switch 324 closes, as shown in the timing diagram of Fig. 9 when the gate driver's fault output node 14 is in the fault state. This discharges capacitor 312 and, as a result, pulls common node 20 to ground (since the voltage across capacitor 312, which is therefore output by ramp generator 310, no longer satisfies a voltage condition). That is, the voltage across capacitor 312 drops below VREF, and therefore comparator 322 outputs a low signal. Then, switch 324 opens as the gate driver's fault output node 14 is reset to the operating state. As a result, capacitor 322 is charged by the voltage source through first resistor 314 and second resistor 316.

[0100] The time required for the voltage across capacitor 312 to reach VREF (i.e., satisfy the voltage condition) depends on the resistances of first resistor 314 and second resistor 316 and the capacitance of capacitor 312. Thus, these values ​​can be selected to achieve the desired predetermined time period of the individual timing arrangement 300.

[0101] Fig. 10 illustrates a circuit diagram of a gate driver system according to an embodiment of the invention, including timing arrangements 300a-c as shown in Fig. 8 shown.

[0102] As shown, the ramp generator of each timing arrangement 300a-c shares a common second resistor 316. Further, the output of each timing arrangement is connected to a bus node 330. Bus node 330 is, in turn, connected to a common comparator 320. Comparator 320 is configured to provide either a high or a low output to common node 20. In other words, the comparator compares the voltage at bus node 330 with a reference voltage VREF and then sets common node 20 to the first state based on the comparison or releases common node 20 from the first state based on the comparison.

[0103] In some embodiments, comparator 320 may be part of controller 60. That is, bus node 330 may be connected to a comparator 320 as part of controller 60 to measure the time elapsed since the trigger event. However, comparator 320 may also be provided separately, with an output of the comparator provided to controller 60.

[0104] For a brief explanation, when one of the fault output nodes 14a-c enters a fault state, the switch of the associated timing device 300a-c closes. This pulls bus node 330 to ground, creating a short circuit to ground while only discharging the respective capacitor associated with the timing device 300a-c. Accordingly, the voltage at bus node 330 does not satisfy the voltage condition VREF of comparator 320, and common node 20 is pulled to the first state.

[0105] Then, when the switch of timing arrangement 300a-c opens (after fault output node 14a-c has been reset to an operating state), the associated capacitor will recharge, and the voltage at bus node 330 will gradually rise. Once the voltage at bus node 330 satisfies the voltage condition VREF of comparator 320, common node 20 is enabled in the second state.

[0106] It is preferred that the second resistor 316 has a much greater resistance than each of the first resistors of the timing arrangements 300a-c. As a result, the charging time of each of the capacitors can be dominated by the respective first resistor.

[0107] Each of the capacitors of the timing arrangements 300a-c may have the same capacitance, while each of the first resistors of the timing arrangements 300a-c may have a different resistance to set a rising time to the ramp generator according to the respective predetermined time period of the timing arrangement 300a-c. Alternatively, each of the first resistors of the timing arrangements 300a-c may have the same resistance, while each of the capacitors of the timing arrangements 300a-c may have a different capacitance to set a rising time to the ramp generator according to the respective predetermined time period of the timing arrangement 300a-c.Of course, both the resistance and capacitance values ​​of each of the timing arrangements 300a-c may vary, but this may be more expensive and complicated to implement (and therefore it may be preferable to vary only one of the resistance or capacitance between each timing arrangement).

[0108] With reference to Fig. 11 illustrates a circuit diagram of another exemplary embodiment of the timing arrangement 400 for a gate driver system. The timing arrangement 400 operates according to the trigger event, which is the resetting of a stored fault indicator associated with the associated gate driver (e.g., by the SR latch 424). That is, after the fault output node 14 of the respective gate driver 10 is placed in a fault state, a fault indicator is stored. The trigger event occurs when the stored fault indicator is reset (e.g., to a run indicator). If the fault output node remains in the fault state at the time the reset occurs, a fault indicator continues to be stored, and the trigger event does not begin.

[0109] Accordingly, the timing arrangement 400 of Fig. 11 initially sets the common node 20 to the first state, waits for a reset signal that resets the error indicator, delays a predetermined period of time, and then releases the common node 20 from the first state. The operation of the timing arrangement 400 of Fig. 11 is also described with reference to the timing diagram of Fig. 12 explained.

[0110] The timing arrangement 400 of Fig. 11 can be used in / within a gate driver 10 (similar to the timing arrangement of Fig. 3). That is, the error output node 14 of the gate driver 10 may be an internal node of the gate driver 10 (ie, not an output pin), and many of the components of the timing arrangement 400 of Fig. 11 may be provided in the gate driver 10. Of course, each of these components may also be provided separately for the gate driver 10, with the error output node 14 being an output pin of the gate driver.

[0111] During normal operation of the gate driver 10 (i.e., when the gate driver 10 has not detected a fault), an output switch of the timing arrangement 400 remains open, and therefore the output of the timing arrangement 400 does not pull the common node 20 into the first state.

[0112] When an internal error signal at the error output node 14 triggers the setting of an SR latch 424, a fault indicator is stored, resulting in the Q output of the SR latch 424 being set high. The capacitor 412 of the ramp generator 410 is discharged when the Q output of the SR latch closes the switch 416 of the ramp generator 410. This causes the open drain switch 430 to close (because the voltage across the capacitor 412 no longer satisfies the voltage condition of the comparator 422), pulling the output of the timing arrangement 400 low (which in turn pulls the common node 20 low).

[0113] When the reset pin 70 is pulled low, a negative edge is generated at the clock input of the D flip-flop 426. Once the reset pin 70 is pulled high again, a positive edge is generated at the clock input of the D flip-flop 426, which clocks through a '1' to the Q output, since the D input of the D-FF 426 is permanently connected to a '1'. Accordingly, a reset of the SR latch 424, which removes the fault indicator, is caused to a run indicator, as long as the fault output node 14 is also in an run state at that time.

[0114] When the SR latch 424 is reset, the switch 416 is opened. Resetting the SR latch 424 also resets the D flip-flop 426.

[0115] Once the output voltage of the ramp generator 410 satisfies a voltage condition of the comparator 422 (i.e., once the output voltage exceeds a reference voltage value), the open drain switch 430 is opened, thereby enabling the output of the timing arrangement 400 from the low state.

[0116] In other words, the illustrated timing arrangement 400 includes a ramp generator 410 configured to generate a ramp-shaped output voltage in response to the stored fault indicator being reset while the fault output node 14 of the respective gate driver 10 (in this case, a node within the gate driver 10) is in an operating state.

[0117] For this purpose, ramp generator 410 includes a switch 416 that, when closed, discharges capacitor 412, and a current source 414 that, when switch 416 is open, charges capacitor 412. Switch 416 is controlled by internal control logic (e.g., SR latch 424, D flip-flop 426, negative edge delay 428) that causes switch 416 to open when gate driver 10 detects a fault and causes switch 416 to close in response to a valid reset signal for gate driver 10 at reset pin 70.

[0118] Timing arrangement 400 further includes output control logic (e.g., comparator 422 and open drain output switch 430) configured to place common node 20 (i.e., the output pin of gate driver 10) into the first state in response to the ramped output voltage failing to satisfy a voltage condition (i.e., when the voltage across the capacitor is less than a threshold voltage VREF). The output control logic further releases common node 20 from the first state in response to the ramped output voltage satisfying the voltage condition.

[0119] Of course, components of ramp generator 410 can be selected such that the output voltage of ramp generator 410 / the voltage across capacitor 412 satisfies the voltage condition after a predetermined period of time (which varies between timing arrangements 400). In particular, the capacitance of capacitor 412 and / or the current of current source 414 can be selected to meet this goal. Alternatively, the voltage condition implemented by comparator 422 of the control logic can be selected such that ramp generator 410 satisfies the voltage condition after the predetermined period of time.

[0120] In the illustrated embodiment, the predetermined time period can be set via a setting pin 80. Accordingly, this would allow a user to select the predetermined time period associated with each gate driver 10. In particular, components can be connected to the setting pin 80 to select a predetermined time period.

[0121] In a first implementation, as in Fig. As shown in Figure 13, the capacitor 412 of the ramp generator 410 may be provided by the adjustment pin 80. That is, instead of the capacitor 412 being an internal component, the adjustment pin 80 may be connected to the current source 414, and an external capacitor 412 may be connected between the adjustment pin 80 and ground.

[0122] In another implementation, as in Fig. As shown in Figure 14, the reference voltage VREF of comparator 422 may be provided by a reference current source 440 (which may be consistent between timing arrangements), and an external resistor 442 may be connected to the adjustment pin 80. Accordingly, the reference voltage VREF of comparator 422 may be selected based on the resistance of the external resistor 442.

[0123] Alternatively, as in Fig. As shown in Figure 15, the reference voltage VREF of the comparator 422 may be provided by a voltage divider 450 that sets a bus voltage VDD. Accordingly, a reference voltage VREF for the comparator 422 may be individually selected for each timing arrangement 400 by providing a differently divided voltage divider 450 (i.e., with different resistance values). Alternatively, the voltage divider 450 may be replaced by a voltage source selected to provide an appropriate reference voltage VREF.

[0124] Finally, as in Fig. As shown in Figure 16, the current source 414 may be implemented as a current mirror 460, where the current provided by the current mirror 460 is adjusted by an external resistor 462. In this case, the current provided by the current mirror 460 depends on the resistance of the external resistor 462, which may be selected to provide a different current for each of the timing arrangements.

[0125] Each of the timing arrangements 400a-400e may be implemented in the gate driver system 100 as described above, with different timing arrangements 40a-40c connected to different respective gate drivers 10a-10c being assigned / configured to have different predetermined time periods.

[0126] Fig. 17 illustrates a flowchart of a method 500 for determining a location of a fault in a gate driver system according to an embodiment of the invention. The gate driver system is as described with reference to Fig. 1 and Fig. 2 and includes a plurality of gate drivers. Each gate driver has an error output node (which may be a gate driver error pin or an internal gate driver node) that is switchable between an error state indicating an error detected by the respective gate driver and an operating state.

[0127] In particular, step 510 includes setting a common node to a first state in response to the fault output node of one of the gate drivers being set to the fault state. That is, if one of the fault output nodes is set to the fault state, the common node is set to a first state.

[0128] Then, in step 520, the common node is released from the first state in response to a predetermined period of time having elapsed since a trigger event. The time period (i.e., the predetermined period of time) between the trigger event and the release of the common node depends on the gate driver that reported the fault. In other words, the predetermined period of time required to release the common node is associated with the gate driver whose fault output node is placed in the fault state.

[0129] Since each gate driver is associated with a different predetermined time period, the time between the trigger event and the release of the common node can be measured to determine / identify the gate driver that reported the fault.

[0130] In the claims, any reference signs placed in parentheses are not to be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those recited in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The embodiments may be implemented by hardware comprising a plurality of different elements. In a device claim reciting a plurality of means, a plurality of those means may be embodied by one and the same hardware element. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of those measures cannot be used to advantage.Furthermore, in the appended claims, lists comprising “at least one of: A; B; and C” should be construed as (A and / or B) and / or C.

[0131] The following embodiments are disclosed: 1. A gate driver system (100) comprising a plurality of gate drivers (10a, 10b, 10c), each gate driver having an error output node (14a, 14b, 14c) switchable between an error state indicating an error detected by the respective gate driver and an operating state, the system comprising: a common node (20) switchable between a first state and a second state; a timing arrangement (40a, 40b, 40c) for each of the gate drivers, each timing arrangement being connected to the fault output node of the respective gate driver and the common node, each timing arrangement being configured to: Setting the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state; and Releasing the common node from the first state in response to a predetermined period of time having elapsed since a trigger event, wherein the predetermined period of time of each timing arrangement is different. 2. The system of embodiment 1, further comprising a controller (60) connected to the common node (20) and configured to: Measuring a time period between the tiger event and the switching of the common node to the second state; and Identifying the gate driver (10a, 10b, 10c) corresponding to the detected error based on the measured time period and the predetermined time period of each respective timing arrangement (40a, 40b, 40c). 3. The system of embodiment 1 or 2, wherein the trigger event is either the common node (20) being placed in the first state; or the fault output node (14a, 14b, 14c) of the respective gate driver (10a, 10b, 10c) being placed in the operating state. 4. The system of embodiment 1 or 2, wherein the triggering event is the common node (20) being placed in the first state, and wherein each timing arrangement (200) comprises: a ramp generator (210) configured to generate a ramp-shaped output voltage in response to the fault output node (14) of the respective gate driver (10) being placed in the fault state; and a control logic (220) configured to: Setting the common node to the first state in response to the fault output node of the respective gate driver being set to a fault state and the ramped output voltage not satisfying a first voltage condition; and Releasing the common node from the first state in response to the ramped output voltage satisfying the first voltage condition. 5. The system of embodiment 4, wherein the ramp generator (210) of each timing arrangement is configured to generate the respective ramped output voltage such that the respective ramped output voltage satisfies the first voltage condition once the respective predetermined time period of the timing arrangement (200) has elapsed since the trigger event, and wherein the first voltage condition of each timing arrangement is the same. 6. The system of embodiment 4, wherein the first voltage condition of each timing arrangement (200) is selected such that the ramped output voltage generated by the respective ramp generator (210) satisfies the respective first voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the trigger event. 7. The system of any of embodiments 4-6, wherein the control logic (220) of each timing arrangement is further configured to place the common node (20) into the first state in response to the ramped output voltage satisfying a second common voltage condition and the first voltage condition. 8. The system of any of embodiments 4-7, wherein the ramp generator (210) comprises: a capacitor (212); a power source (214); and a switch (216) arranged to enable the current source to charge the capacitor in response to the fault output node (14) of the respective gate driver (10) being placed in the fault state. 9. The system of embodiment 8, wherein a capacitance of the capacitor (212) and / or a current strength of the current source (214) of each ramp generator (210) is selected such that the respective ramp-shaped output voltage satisfies the first voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the trigger event, and wherein the first voltage condition of each timing arrangement is the same. 10. The system of any of embodiments 1-2, wherein the triggering event is that the fault output node (14) of the respective gate driver (10) is put into the operating state, and wherein each timing arrangement (300, 400-1, 400-2, 400-3, 400-4, 400-5) comprises: a ramp generator (310, 410) configured to generate a ramp-shaped output voltage in response to the fault output node (14) of the respective gate driver (10) being placed in the operating state; and a control logic (320, 420) configured to: placing the common node (20) in the first state in response to the fault output node of the respective gate driver being placed in a fault state and the ramped output voltage not satisfying a voltage condition; and Releasing the common node from the first state in response to the ramped output voltage satisfying a voltage condition. 11. The system of embodiment 10, wherein the ramp generator (310, 410) of each timing arrangement (300, 400-1, 400-2, 400-3, 400-4, 400-5) is configured to generate the respective ramped output voltage such that the respective ramped output voltage satisfies the voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the trigger event, and wherein the voltage condition of each timing arrangement is the same. 12. The system of embodiment 10, wherein the voltage condition of each timing arrangement (300, 400-1, 400-2, 400-3, 400-4, 400-5) is selected such that the ramped output voltage generated by the respective ramp generator (310, 410) satisfies the respective voltage condition once the respective predetermined time period of the timing arrangement has elapsed since the trigger event. 13. The system of any of embodiments 10-12, wherein the control logic (320, 420) of each timing arrangement comprises a comparator (322, 422) configured to: Comparing the ramped output voltage and a reference voltage (VREF), where the reference voltage is based on the voltage condition; Putting the common node (20) into the first state or releasing the common node from the first state based on the comparison. 14. The system of any of embodiments 1-13, further comprising a biasing arrangement (30) configured to bias the common node (20) to the second state, and wherein each timing arrangement (40a, 40b, 40c) further comprises a switching arrangement (50a, 50b, 50c) connected to the common node, the switching arrangement of each respective timing arrangement being configured to: Setting the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state. 15. The system of any of embodiments 1-14, wherein the first state is a low state and the second state is a high state. 16. A method for determining a position of a fault in a gate driver system (100) comprising a plurality of gate drivers (10a, 10b, 10c), each gate driver having a fault output node (14a, 14b, 14c) switchable between a fault state indicating a fault detected by the respective gate driver and an operating state, the method comprising: Setting (510) a common node (20) to a first state in response to the fault output node of one of the gate drivers being set to the fault state; and releasing (520) the common node from the first state in response to a predetermined period of time having elapsed since a trigger event, the predetermined period of time being associated with the gate driver whose fault output node is placed in the fault state, and wherein the predetermined time period associated with each gate driver is different.

Claims

[1] Gate driver system (100) comprising a plurality of gate drivers (10a, 10b, 10c), each gate driver having a fault output node (14a, 14b, 14c) which is switchable between a fault state indicating a fault detected by the respective gate driver and an operating state, the system comprising: a common node (20) that can be switched between a first state and a second state; a timing arrangement (40a, 40b, 40c) for each of the gate drivers, wherein each timing arrangement is connected to the fault output node of the respective gate driver and to the common node, wherein each timing arrangement is configured to: Setting the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state; and Releasing the common node from the first state in response to a predetermined time interval having elapsed since a trigger event, where the predetermined time interval is different for each timing arrangement. [2] System according to claim 1, further comprising a controller (60) connected to the common node (20) and configured to: Measuring the time interval between the tiger event and the switching of the common node to the second state; and Identifying the gate driver (10a, 10b, 10c) corresponding to the detected fault, based on the measured time duration and the predetermined time duration of each respective timing arrangement (40a, 40b, 40c). [3] System according to claim 1 or 2, wherein the trigger event is either the common node (20) which is set to the first state; or the fault output node (14a, 14b, 14c) of the respective gate driver (10a, 10b, 10c) which is set to the operating state. [4] System according to claim 1 or 2, wherein the triggering event is that the common node (20) is set to the first state, and wherein each timing arrangement (200) comprises: a ramp generator (210) configured to generate a ramped output voltage in response to the fault output node (14) of the respective gate driver (10) being placed in the fault state; and a control logic (220) that is configured to: Setting the common node to the first state in response to the fault output node of the respective gate driver being set to a fault state and the ramped output voltage failing to satisfy a first voltage condition; and Releasing the common node from the first state in response to the ramped output voltage satisfying the first voltage condition. [5] System according to claim 4, wherein the ramp generator (210) of each timing arrangement is configured to generate the respective ramped output voltage such that the respective ramped output voltage satisfies the first voltage condition as soon as the respective predetermined time period of the timing arrangement (200) has elapsed since the triggering event, and wherein the first voltage condition of each timing arrangement is the same. [6] System according to claim 4, wherein the first voltage condition of each timing arrangement (200) is selected such that the ramped output voltage generated by the respective ramp generator (210) satisfies the respective first voltage condition as soon as the respective predetermined time period of the timing arrangement has elapsed since the triggering event. [7] System according to any one of claims 4-6, wherein the control logic (220) of each timing arrangement is further configured to put the common node (20) into the first state in response to the ramped output voltage satisfying a second common voltage condition and the first voltage condition. [8] System according to one of claims 4-7, wherein the ramp generator (210) comprises: a capacitor (212); a power source (214); and a switch (216) arranged to allow the power source to charge the capacitor in response to the fault output node (14) of the respective gate driver (10) being placed in the fault state. [9] System according to claim 8, wherein a capacitance of the capacitor (212) and / or a current of the current source (214) of each ramp generator (210) is selected such that the respective ramped output voltage satisfies the first voltage condition as soon as the respective predetermined time period of the timing arrangement has elapsed since the triggering event, and wherein the first voltage condition of each timing arrangement is the same. [10] System according to one of claims 1-3, wherein the triggering event is that the fault output node (14) of the respective gate driver (10) is put into the operating state, and wherein each timing arrangement (300, 400-1, 400-2, 400-3, 400-4, 400-5) comprises: a ramp generator (310, 410) configured to generate a ramped output voltage in response to the fault output node (14) of the respective gate driver (10) being put into the operating state; and a control logic (320, 420) that is configured to: Moving the common node (20) to the first state in response to the fault output node of the respective gate driver being moved to a fault state and the ramped output voltage failing to satisfy a voltage condition; and Releasing the common node from the first state in response to the ramped output voltage satisfying a voltage condition. [11] System according to claim 10, wherein the ramp generator (310, 410) of each timing arrangement (300, 400-1, 400-2, 400-3, 400-4, 400-5) is configured to generate the respective ramped output voltage such that the respective ramped output voltage satisfies the voltage condition as soon as the respective predetermined time period of the timing arrangement has elapsed since the triggering event, and wherein the voltage condition of each timing arrangement is the same. [12] System according to claim 10, wherein the voltage condition of each timing arrangement (300, 400-1, 400-2, 400-3, 400-4, 400-5) is selected such that the ramped output voltage generated by the respective ramp generator (310, 410) satisfies the respective voltage condition as soon as the respective predetermined time period of the timing arrangement has elapsed since the triggering event. [13] System according to one of claims 10-12, wherein the control logic (320, 420) of each timing arrangement comprises a comparator (322, 422) configured to: Comparing the ramped output voltage and a reference voltage (VREF), where the reference voltage is based on the voltage condition; Moving the common node (20) to the first state or releasing the common node from the first state based on the comparison. [14] System according to any one of claims 1-13, further comprising a bias arrangement (30) configured to bias the common node (20) into the second state, and wherein each timing arrangement (40a, 40b, 40c) further comprises a switching arrangement (50a, 50b, 50c) connected to the common node, wherein the switching arrangement of each respective timing arrangement is configured to: Moving the common node to the first state in response to the fault output node of the respective gate driver being moved to the fault state. [15] System according to any one of claims 1-14, wherein the first state is a low state and the second state is a high state. [16] Method for determining the position of a fault in a gate driver system (100) comprising a plurality of gate drivers (10a, 10b, 10c), wherein each gate driver has a fault output node (14a, 14b, 14c) that is switchable between a fault state indicating a fault detected by the respective gate driver and an operating state, the method comprising: Setting (510) a common node (20) into a first state in response to the fault output node of one of the gate drivers being set into the fault state; and Releasing (520) the common node from the first state in response to a predetermined time interval having elapsed since a trigger event, wherein the predetermined time interval is associated with the gate driver whose fault output node has been placed in the fault state, and where the predetermined time duration assigned to each gate driver is different.

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