Semiconductor device and method for its manufacture

Abstract

Semiconductor device comprising a substrate, a die having a first and a second surface, wherein the die is embedded in the substrate, a first heat sink arranged on a first surface of the substrate, and a second heat sink arranged on a second surface of the substrate, wherein the substrate comprises a thermally conductive structure arranged between the first surface of the die and the first heat sink; and a thermally insulating structure arranged between the second surface of the die and the second surface of the substrate opposite the first surface.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device comprising an embedded component for high-voltage applications. BACKGROUND

[0002] High-voltage applications require smaller form factors due to emerging problems with stray inductances within individual packages. Therefore, it is desirable to embed semiconductor dies in a wired substrate to reduce parasitic inductances by minimizing the free length of connectors and inter-die connections. However, an embedded die operating at high voltages and high switching speeds is a significant heat source. To prevent interference with the proper operation of the die, the substrate, and any surface-mount devices (SMDs) located near the die, heat energy generated by the die must be dissipated and directed away from the heat source. A common approach to heat dissipation from a die is to attach a heat sink to one side of the substrate.However, since the heat generated by the die is conducted in all directions, there may be areas on the substrate that can become hot and are therefore potentially unsuitable for mounting SMDs or even unusable altogether. Therefore, an object of the invention is to provide a semiconductor device with improved heat transfer properties. Background information on the technical field of the invention can also be found in US Publication 2019 / 0237373A1. DESCRIPTION

[0003] The above problem is solved by the invention defined in the independent claims. Further embodiments are defined in the dependent claims.

[0004] According to a first aspect, a semiconductor device is provided, wherein the semiconductor device comprises a substrate, a die having a first and a second surface, wherein the die is embedded in the substrate, a first heat sink arranged on a first surface of the substrate, and a second heat sink arranged on a second surface of the substrate, wherein the substrate comprises a thermally conductive structure arranged between the first surface of the die and the first heat sink; and a thermally insulating structure arranged between the second surface of the die and the second surface of the substrate opposite the first surface.

[0005] According to the first aspect, the die is embedded in the substrate to reduce parasitic inductances by minimizing the free path of connections. The substrate can be a multilayer substrate comprising several metal and non-metal layers and an epoxy support. Substrate materials can include epoxy, imide, bismaleimide triazine, and benzoxazine to enable multilayer embedding. Furthermore, the substrate can be a printed circuit board (PCB) consisting of stacked metal layers embedded in an epoxy matrix. The PCB is described in detail below.

[0006] The layers in the substrate can generally be symmetrical, meaning they can be evenly distributed with respect to a center line of the substrate to reduce any warping. The substrate can have a first (lower) surface and a second (upper) surface. A first heat sink can be attached to the first surface of the substrate. A heat sink is a spatially defined area or body that transfers the heat energy stored or supplied to it to an adjacent medium. Adjacent media can be solids, liquids, or gases.

[0007] The die can include a first side that includes drain and collector connections.

[0008] Furthermore, the die can include a second (upper) side, where the second upper side is a control side and includes gate and emitter connections.

[0009] The die can be completely buried and surrounded by the substrate, or it can be only partially embedded. Embedded does not necessarily mean that the die is located in a recess of the substrate; the die could also be mounted on top of the substrate and surrounded by it. Since the die is a source of heat energy that is dissipated in all directions into the surrounding substrate, the substrate becomes hot during operation. In particular, in high-voltage applications (generally above 200 V), the substrate and associated areas are subjected to thermal stress. To keep the temperature of the die below a certain threshold, it is necessary to dissipate heat away from the die and dissipate the energy. Therefore, the substrate includes a thermally conductive structure configured to conduct heat from the bottom of the die to the first heat sink on the first (bottom) side of the substrate.Since the first heat sink is located on the first surface of the substrate, the first surface may not be usable for mounting further devices on the first surface of the substrate within a footprint of the first heat sink.

[0010] Since heat is dissipated in all directions, heat is also conducted from the upper, second side of the die to the second surface of the substrate. This second surface of the substrate therefore also becomes hot. Consequently, the suitability of the upper surface of the substrate for mounting sensitive SMDs may be reduced. To reduce heat transfer from the upper side of the die to the second (upper) side of the substrate, the substrate incorporates a heat-insulating structure. This structure isolates the second side of the substrate from the heat source, the die. The heat-insulating structure is therefore positioned between the upper surface of the substrate and the heat source, i.e., the second, upper surface of the die. This reduces heat flow to the upper side of the substrate.Consequently, temperatures on the upper surface of the substrate can be reduced, and a surface area of ​​the substrate above the heat source can be better suited for SMD placement. Thus, it may be possible to place SMDs in an area above the die and / or closer to the die's base, or even in an area of ​​the substrate's secondary surface that lies within the die's base.

[0011] Since the thermally insulating structure has a thermal conductivity greater than zero, heat transfer occurs through it over time, and the upper surface of the substrate heats up as long as the heat source is in operation. To further reduce the amount of heat transferred through the thermally insulating structure to the upper surface of the substrate, a second heat sink is attached to the upper surface of the substrate. This second heat sink conducts the transferred heat energy from the upper surface of the substrate to a cooling medium. The cooling medium for both the first and second heat sinks can be ambient air, but they can also incorporate or operate with any other coolant or gas. The second heat sink further reduces the surface temperature of the upper surface of the substrate.As a result, an area on the upper surface of the substrate in which sensitive SMDs can be placed is enlarged.

[0012] The thermal conductivity of the insulating structure is in the range of 0.3 W / mK, preferably lower, while the thermally conductive structure has a thermal conductivity in the range of 3–10 W / mK, i.e., at least ten times higher than that of the insulating structure. The insulating structure can be an epoxy with reduced thermal conductivity, and the thermally conductive structure can be an epoxy with improved thermal conductivity. Both the thermally conductive structure and the insulating structure can consist of one or more layers or can be single layers.Furthermore, the heat-insulating structure can be embedded in the substrate and arranged between a metallization layer, which forms the top surface or cover layer of the substrate, and a wiring layer, the wiring layer being arranged to contact the top side of the die by means of wires, vias, or the like. The wiring layer can be electrically connected to the metallization layer, thereby forming a DC connection.

[0013] "Footprint" generally describes the area or space that an object or system occupies or requires in a particular application or environment. In this context, the term "footprint" refers to the size of an electronic component, specifically the total area that the component occupies on a PCB. A smaller footprint for a component can help achieve a higher component density on the PCB. The footprint of the first heat spreader is larger than the footprint of the die, and the footprint of the die is contained within the footprint of the first heat spreader in a top view. Heat conducted away from the first surface of the die through the thermally conductive structure is dissipated from the heat source in a circular spatial manner.Therefore, the base area of ​​the first heat distributor is larger than the base area of ​​the die, allowing the first heat distributor to collect the majority of the transferred heat. This enables higher efficiency of the first heat distributor by providing short and direct heat transfer paths from the die to the first heat sink.

[0014] In another embodiment, a base area of ​​the second heat sink overlaps a base area of ​​the die and / or the second heat sink is a device mounted on the second surface of the substrate (SMD). To implement short heat transfer paths, the second heat sink also overlaps at least partially the base area of ​​the die in a top view. In particular, a non-temperature-sensitive SMD could also act as a heat spreader, since any device attached to the top surface of the substrate increases the surface area that can be used to transfer heat from the surface to a cooling medium, e.g., ambient air. When a non-temperature-sensitive SMD is used as a heat spreader, it may be possible to mount the non-temperature-sensitive SMD directly above the die, i.e., a base area of ​​the die would be contained within a base area of ​​the second heat sink.The heat-insulating structure can be a continuous structure above the die, i.e., it can be free of vias. Electrical vias, which connect, for example, the wiring layer contacting the die and the metallization layer on the substrate surface, are preferably located outside the die's base area and outside the base area of ​​the second heat sink to prevent heat flow to the substrate's upper surface.

[0015] In a further embodiment, the substrate comprises a conductor frame, wherein the conductor frame includes a heat distribution section configured to contact the first side of the die, wherein the heat distribution section includes a via structure to contact a metal layer arranged between the heat distribution section and the first side of the substrate, the metal layer being part of the thermally conductive structure.

[0016] The substrate can include a conductor frame, such as a metal structure, on which the die or other electronic components are mounted. The conductor frame provides electrical connections between the die and the outside world by means of small wires, typically made of gold or copper, which connect the chip to the terminals of the conductor frame. In the present embodiment, the conductor frame serves as a support for the die. The die can be rigidly attached to the conductor frame. The conductor frame can include a heat distribution section that acts as a heat spreader, conducting heat away from and distributing it from the die. The die can be attached to the heat distribution section. In particular, the heat distribution section can be a cushion-shaped integral part of the conductor frame and contact the first (bottom) side of the die. The heat distribution section can be a copper cushion.

[0017] The ladder frame also provides physical support for the die and protects it from damage. It can be made of a material such as copper, a copper alloy, or an iron-nickel alloy and is designed to be compatible with the manufacturing processes used to produce the die. The heat distribution section is configured to conduct heat away from a heat-generating device such as the die.

[0018] In the case of a high-voltage semiconductor die, the heat spreader can also be a metal plate attached to the die, usually with a layer of thermal paste in between. The heat spreader helps to distribute the heat generated by the die over a larger surface area, making it easier for a cooling device, such as the first heat sink, to dissipate the heat.

[0019] The heat spreaders can be made from a variety of materials, including copper, aluminum, or a combination of both. The heat spreader section may include a via to contact an additional metal layer located between the first heat sink and the heat spreader section. This via can be a thermally conductive metal structure and can act as a path for improved heat flow from the heat spreader to the thermally conductive structure and thus to the first heat sink.

[0020] The metal layer can be part of the thermally conductive structure. The heat spreader improves heat dissipation and distribution over a larger area, allowing for better heat transfer to the primary heat sink. This enhances the overall heat dissipation and cooling of the die.

[0021] In another embodiment, the insulating structure has a heat transfer coefficient below 0.3 W / mK. Since heat transfer, and thus the surface temperature to the upper side of the substrate, depends on the heat transfer capacity of the insulating structure, i.e., the quality of the insulation, a low heat transfer coefficient for the insulating structure is desirable. In particular, if the heat transfer coefficient is below 0.3 W / mK, the surface temperature of the upper surface of the substrate is low enough to prevent damage to sensitive SMDs near the base of the die or to non-sensitive SMDs directly above the die.

[0022] In particular, the insulating structure is a honeycomb structure, a brick structure, a gas-filled honeycomb structure, or a structure comprising gas-filled cavities. Gas-filled structures exhibit particularly low heat transfer coefficients. A honeycomb structure is a type of cellular or matrix structure consisting of hexagonal cells or cavities arranged in a regular pattern. The resulting structure is lightweight yet strong and rigid, making it ideal for use in a variety of applications where strength and weight are critical factors. When the cavities of the honeycomb structure are filled with gas, the structure also acts as a very good insulator.

[0023] Since the hexagonal shape of the cells in a honeycomb structure provides a high strength-to-weight ratio, the structure is able to distribute loads and stresses evenly across the entire surface. Under thermal stress, as in the present case, the gas-filled honeycomb structure can represent a good compromise between insulation and mechanical resistance.

[0024] The same applies to a structure that includes any gas-filled cavities that contribute to good insulation properties. The structure can be a continuous structure that is free of thermally conductive vias.

[0025] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device for high-voltage applications is provided, wherein the method comprises providing a substrate, embedding a die having a first and a second surface in the substrate, arranging a first heat sink on a first surface of the substrate, and arranging a second heat sink on a second surface of the substrate, wherein the embedding comprises arranging a thermally conductive structure between the first surface of the die and the first heat sink, and arranging a thermally insulating structure between the second surface of the die and the second surface of the substrate opposite the first surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference symbols refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various examples shown may be combined, provided they are not mutually exclusive. Fig. 1 represents a semiconductor device according to the first aspect of the present disclosure. Fig. Figure 2 shows a schematic top view of the semiconductor device of Fig. 1 dar. Fig. 3 represents an embodiment of the semiconductor device of Fig. 1 dar. Fig. Figure 4 is another cross-sectional representation of the semiconductor device of the first aspect of the disclosure. Fig. 5a and Fig. Figure 5b shows schematic cross-sectional views of a layer structure of an embedding substrate according to the first aspect of the disclosure. Fig. 6 is a flowchart of the second aspect of Revelation. Fig. 7 is another flowchart of the second aspect of Revelation. DETAILED DESCRIPTION

[0027] The figures above are described below as examples.

[0028] Fig. Figure 1 represents a semiconductor device 1 according to the first aspect of the present disclosure. The semiconductor device 1 comprises a substrate 2. A semiconductor die 3 is embedded in the substrate 2. The substrate 2 completely surrounds the die 3, the die 3 being arranged in a cavity 4 within the substrate 2. The substrate 2 is a PCB and comprises several layers, as described in more detail below.

[0029] The die 3 comprises a first lower surface 5 and a second, upper surface 6. A first heat sink 7 is arranged on a first, lower surface 8 of the substrate 2. Opposite the first heat sink 7, a second heat sink 9 is arranged on a top, second surface 10 of the substrate 2.

[0030] Substrate 2 is a multilayer substrate and includes a thermally conductive structure 11. The thermally conductive structure 11 is a layered structure and is located between the die 3 and the first lower surface 8 of substrate 2. The thermally conductive structure 11 can also be a continuous monolithic structure. Therefore, the thermally conductive layer 11 transfers heat from the die 3, which is a heat source during operation, to the first heat sink 7, where the heat is to be dissipated and carried away from the semiconductor device 1, e.g., to the ambient air or any other cooling medium 12. Furthermore, a thermally insulating structure 13, which can also be a layered structure and / or a continuous monolithic structure, is arranged between the die 3, i.e., the second surface of the die 6, and the top surface of the substrate 10.The transfer of heat exiting the die 3 to the top of the substrate is impeded, resulting in a reduced heat flow to the top of the substrate and therefore lower temperatures on the top surface 10 of the substrate 2. Additional devices 14 (SMDs) are mounted on the top surface 10 of the substrate 2.

[0031] Fig. 2 shows a schematic top view of the in Fig. The semiconductor device 1 described in Section 1 represents the following. Heat emitted by the working die 3 is transferred to each side of the substrate 8, 10 and dissipated by both the heat-insulating structure 13 and the thermally conductive structure 11, as well as by any additional layers of the multilayer substrate between the die 3 and the lower and upper surfaces 8, 10 of the substrate 2. To efficiently transfer heat from the surfaces 8, 10 of the substrate to the surrounding cooling medium 12, the first heat sink 7 is mounted on the underside of the substrate 2, where a base area of ​​the substrate 2 may be larger than the base area of ​​the first heat sink 7. A base area of ​​the first heat sink 7 overlaps the base area of ​​the die 3, i.e., the die 3 is located within the base area of ​​the first heat sink 7 in a top view. The second heat sink 9 has a base area that is larger than the base area of ​​the die 3, i.e.,The die 3 is located within the base area of ​​the second heat sink 9 in a top view. In another embodiment, the base area of ​​the second heat sink 9 is smaller than the base area of ​​the die 3, i.e., the second heat sink 9 can be located within the base area of ​​the die 3. Heat reaching the first and / or second heat sinks 7, 9 through the substrate 2 from the die 3, which generally has a smaller base area, is thus absorbed more efficiently and dissipated away from the substrate 2.

[0032] Instead of the second heat sink 9, an SMD 14 is placed in an area above the die 3 on the top surface of the substrate 2. Heat generated by the die 3 is dissipated within the substrate 2 and eventually reaches the top surface. Consequently, the top surface of the substrate 2 heats up, and heat must be transferred to the surrounding medium 12 to prevent this heating. Therefore, a heat-insensitive SMD 14 is placed above the die to act as a second heat sink 9. The SMD increases the surface area above the die 3 in contact with the surrounding medium 12. The SMD 14 thus acts as a heat exchanger. The SMD 14 is located within a footprint of the die 3, meaning that a lateral surface dimension of the die 3 can be larger than a lateral surface dimension of the SMD. However, a lateral dimension of the second heat sink 9 / SMD can be smaller than a lateral dimension of the die 3.

[0033] Fig. Figure 4 is another cross-sectional representation of the semiconductor device 1 of the first aspect of the disclosure. Fig. Figure 4 shows a layered substrate 2, which is a PCB having two recesses 15. The recesses 15 form the cavity 4, which accommodates the die 3. The substrate further comprises a conductor frame 16.

[0034] In the present example, the first heat sink 7 is attached to the first side of the substrate 8, which is coated with a first metal layer 16a. The first metal layer 16a can be a copper layer and / or an electroplated copper layer with a thickness between 70 µm and 140 µm. The first metal layer 16a is followed by an epoxy layer 16b with a thickness of approximately 140 µm. The epoxy layer 16b is made of an epoxy with improved thermal conductivity or a polypropylene (PP) and can form the heat-insulating structure 11 or be part of it. A second metal layer 17 is deposited on the epoxy layer 16b.

[0035] The thermally conductive structure 11 can comprise the epoxy layer 16b and the second metal layer 17, which are arranged between the first heat sink 7 and the lower, first surface 5 of the die 3. The conductor frame 16 can be made of copper or electroplated copper, with the epoxy layer being a pre-impregnated thermoplastic or thermoset matrix (PP). The PP can typically contain flat textile semi-finished products, such as unidirectional layers of threads or woven fabrics, or grids with threads arranged at right angles.

[0036] The conductor frame 16 includes a cushion-shaped heat distribution section 18. The heat distribution section 18 is made of copper or any other suitable material. The die 3 is attached to the heat distribution section 18 by means of a thermally conductive adhesive layer 19, which is firmly bonded to the underside of the die 3 on the heat distribution section 18 of the conductor frame 16. The heat distribution section 18 includes the second metal layer 17 and is connected to it by a first via 20. The first via 20 thermally and electrically connects the cushion-shaped heat distribution section 18 to the second metal layer 17. The first via 20 can also be part of the thermally conductive structure 11, since the vias 20 can act as thermal conductors.

[0037] The conductor frame 16 is arranged on or is part of the thermally conductive structure 11, which makes it possible for heat to be efficiently transferred from the die 3 via the heat distribution section 18 through the first via structure 20 to the thermally conductive structure 11 (in this example an epoxy layer) and thus to the first heat sink 7.

[0038] Layered electrical contact surfaces 21 are arranged on the upper, first surface 5 of the die 3. Wire connections 22 are arranged on the contact surfaces 21, connecting the die 3 via the contact surfaces 21 to a second via structure 23. The second via structure 23 is connected to an upper layer structure 24. The upper layer structure 24 forms a wiring layer that electrically connects the multiple dies 3 in the parallel cavities 4 shown. The cavities 4 are filled with a molding compound 25.

[0039] The upper layer structure 24 is part of the multilayer substrate 2 and is located between the first upper surface 5 of the die 3 and the top surface 10 of the substrate 2. The thermally insulating structure 13 is located between the upper layer structure 24 and the top surface 10 of the substrate 2. The thermally insulating structure 13 is partially covered by a cover layer 26, which is a second metal layer. The thermally insulating structure 13 thermally and electrically isolates the upper layer structure from the cover layer 26 and the top surface 10 of the substrate 2. The second heat sink 9 is located above the die 3 on the cover layer 26 and is thermally connected to the cover layer 26. The second heat sink 9 enables surface temperatures of 65–90 °Celsius in the area above the die 3, while the temperature directly on the die 3 (junction temperature) is approximately 150 °Celsius during operation.The temperature of the first heat sink can reach approximately 80-90 °C during operation.

[0040] Fig. 5a and Fig. Figure 5b shows schematic cross-sectional views of a layered structure of an embedding multilayered substrate 2 according to the first aspect of the disclosure.

[0041] Fig. Figure 5a is a schematic view focusing on several embodiments of the heat-insulating structure 13. The different embodiments are shown in the same Fig. Figure 5a shows the heat-insulating structure 13, which is a brick structure 27 formed from a plurality of brick-shaped insulating elements. In general, the heat-insulating structure 13 can comprise several independent insulating elements, or the heat-insulating structure can consist of a combination of the embodiments described herein.

[0042] Furthermore, the heat-insulating structure 13 can be a honeycomb structure 28. The cavities of the honeycomb structure 28 can be filled with an insulating compound or with any suitable insulating gas. The heat-insulating structure 13 can also be a structure comprising gas-filled cavities 29. The gas-filled cavities are embedded in a matrix 30 made of any suitable heat-insulating material.

[0043] Fig. Figure 5b is a schematic cross-sectional view of the layer structure of an embedded multilayer substrate 2. An interposer layer 31 is arranged between the first heat sink 7 and the thermally conductive structure 13. The interposer layer 31 forms the lower surface 8 of the substrate 2 and may be identical to the first metal layer 16a. The second metal layer 17 is arranged on a top surface of the thermally conductive structure 13 between the thermally conductive structure 13 and the epoxy layer 16b. The epoxy layer 16b is arranged between the second metal layer 17 and another epoxy layer (not shown) and / or the heat distribution section 18. The other epoxy layer may form the core of the substrate and may have a thickness of approximately 1270 µm. The thickness of the further epoxy layer is approximately the vertical dimension of the cavity 4. The heat distribution section 18 is encapsulated by a molding compound 25, which forms a mold layer.The molding compound 25 fills the cavity 4 and encapsulates at least the second surface of the die 6. Wire connections 22 are connected to respective contact surfaces 21 on the second surface of the die 6 and connect the control side of the die 3 to the second via structure 23. The top layer structure 24 is arranged on the molding compound 25 and between the molding compound 25 and the thermally insulating structure 13. The thermally insulating structure 13 has a thickness of approximately 140 µm and is a continuous structure. In particular, the thermally insulating structure 13 has no vias from the top layer structure 24, the second via structure 23, or a cover layer 26. The top layer structure 26 is a metal layer that forms a wiring layer. The top layer structure 26 can be electrically connected to the cover layer 26 by a third via structure (not shown).The heat-insulating structure 13 is covered by the electrically conductive top layer 26, which forms the second surface 10 of the substrate 2. The SMDs 14 and / or the second heat sink 9 are arranged on the upper surface 10 of the substrate 2.

[0044] During operation of die 3, at a junction temperature, the temperature at the hottest point of die 3 will be approximately 150 °C. Subsequently, the temperature of the core material of substrate 2 in the immediate vicinity (adjacent to cavity 4) of the molding compound 25, e.g., the further epoxy layer, will be in the range of 120 °C to 130 °C. The temperature of the core material of substrate 2 in further proximity to cavity 4 will be in the range of approximately 60 °C to 80 °C. Since heat is distributed through the heat distribution section 18 and conducted from die 3 to the thermally conductive structure 11 via the first via structure 20 and the second metal layer 17, the temperature of the first via structure 20 and the second metal layer 17 will be in the range of 135 °C to 145 °C. The first heat sink 7 has a temperature in the range of 80 °C - 90 °C.The heat-insulating structure 13 allows the temperature at the top layer 26 and / or the second heat sink 9 to be reduced from a range of 130 °C - 140 °C down to 65 °C - 95 °C. Electrical connections, i.e., the third via structure for electrically connecting the upper layer structure 24 to the top layer 26, are to be spaced from the die 3 in a lateral dimension of the substrate 2.

[0045] Fig. 6 is a flowchart of the second aspect of Revelation.

[0046] According to method 32 for manufacturing the semiconductor device 1 of the first aspect of the disclosure, a substrate 2 is provided in step S1. In step S2, a die 3 with a first surface 5 and a second surface 6 opposite the first surface 5 is embedded in the substrate 2. In step S3, a first heat sink 7 is arranged on a first surface 8 of the substrate 2. In step S4, a second heat sink 9 is arranged on a second surface 10 of the substrate 2.

[0047] Fig. 7 is another flowchart of the second aspect of Revelation. The steps of Fig. 7 further specify step S2 of Fig. 6.

[0048] The embedding of a die 3 into the substrate 2 of step S2 further comprises steps S2.1 and S2.2. In step S2.1, the embedding comprises arranging a thermally conductive structure 11 between the first surface 5 of the die 3 and the first heat sink 7. Furthermore, according to step S2.2, a thermally insulating structure 13 is arranged between the second surface 6 of the die 3 and the second surface 10 of the substrate 2, which faces the first surface 8 of the substrate 2.

[0049] Although specific examples have been presented and described here, the person skilled in the art will recognize that a multitude of alternative and / or equivalent implementations can replace the specific examples shown and described without deviating from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

[0050] It should be noted that the methods and devices, including their preferred embodiments, as set forth in this document, may be used alone or in combination with the other methods and devices disclosed herein. Furthermore, features described in the context of a device are also applicable to a corresponding method, and vice versa. Moreover, all aspects of the methods and devices described in this document may be combined in any way. In particular, the features of the claims may be combined with one another in any manner. List of reference symbols 1 Semiconductor device 2 Substrat 3 The 4 cavities 5 first surface of the die 6 second surface of the die 7 first heat sink 8 first lower surface of the substrate 9 second heat sink 10 Top / second surface of the substrate 11 thermally conductive structure 12 Ambient air / cooling medium 13 heat-insulating structure 14 SMD 15 recess 16 ladder frames 16a first metal layer 16b Epoxy layer 17 second metal layer 18 Heat distribution section 19 Adhesive layer 20 first through-hole structure 21 contact pads 22 wire connections 23 second via structure 24 upper layer structure 25 molding compound 26 Top layer 27 brick structure 28 honeycomb structure 29 gas-filled cavities 30 Matrix 31 Interposer layer 32 Methods for manufacturing a semiconductor device

Claims

[1] A semiconductor device (1) comprising: a substrate (2); a die (3) having a first and a second surface (5,6), the die being embedded in the substrate; a first heat sink (7) arranged on a first surface (8) of the substrate; a second heat sink (9) arranged on a second surface (10) of the substrate opposite the first surface; wherein the substrate comprises: a thermally conductive structure (11) arranged between the first surface of the die (5) and the first heat sink (7); and a heat-insulating structure (13) arranged between the second surface of the die (6) and the second surface of the substrate (10). [2] The semiconductor device (1) according to claim 1, wherein a base surface of the first heat sink overlaps a base surface of the die (3). [3] Semiconductor device (1) according to claim 1 or 2, wherein a base area of ​​the second heat sink (9) overlaps a base area of ​​the die and / or the second heat sink (9) is a device mounted on the second surface of the substrate (SMD). [4] Semiconductor device (1) according to one of the preceding claims, wherein the substrate (2) comprises a lead frame (16), wherein the lead frame (16) comprises a heat distribution section (18) configured to contact the first side of the die (3), wherein the heat distribution section (18) comprises a via structure (20) to contact a metal layer arranged between the heat distribution section and the first side of the substrate (2), wherein the metal layer is part of the thermally conductive structure (11). [5] Semiconductor device (1) according to one of the preceding claims, wherein the heat-insulating structure (13) has a heat transfer coefficient below 0.3 W / mK. [6] The semiconductor device (1) according to claim 5, wherein the heat insulating structure (13) is one of a honeycomb structure, a brick structure, a gas-filled honeycomb structure, a structure including gas-filled cavities. [7] Semiconductor device (1) according to one of the preceding claims, wherein the thermally insulating structure (13) is a continuous structure over the die (3) and is free of vias. [8] Semiconductor device (1) according to one of the preceding claims, wherein electrical vias connecting a wiring layer contacting the die and a metallic cap layer on the surface of the substrate are arranged outside the footprint of the die and / or outside the footprint of the second heat sink. [9] A method (32) for manufacturing a semiconductor device (1) for high voltage applications, the method comprising: Providing a substrate (2); Embedding a die (3) having a first and a second surface into the substrate (2); Arranging a first heat sink on a first surface of the substrate; and disposing a second heat sink on a second surface of the substrate opposite the first surface; where embedding includes: Arranging a thermally conductive structure (11) between the first surface of the die (5) and the first heat sink (7); and Arranging a heat-insulating structure (13) between the second surface of the die (3) and the second surface of the substrate (10).

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