INTEGRATED EARTH FAULT DETECTION AND RESIDUAL CURRENT CIRCUIT WITH VARIABLE DELAY

Abstract

An integrated circuit includes a transimpedance amplifier (TIA) coupled to an outside-to-ground (A / E) sensing coil. The A / E sensing coil is coupled to an alternating current (AC) network. The TIA converts a leakage current received from the A / E sensing coil into a leakage voltage. An analog-to-digital converter (ADC) coupled to the transimpedance amplifier converts the leakage voltage into a digital signal. Control logic is coupled to the ADC and processes the digital signal to determine an average value associated with the leakage voltage over time and determines a trip delay period corresponding to the average value. The control logic, in response to the leakage voltage still meeting the average value after waiting for the trip delay period, outputs an enable signal to enable logic to cause a current being disconnected from a load by the AC network.

Description

REFERENCE TO AN EARLY FILED APPLICATION

[0001] This application claims the benefit under 35 USC § 119(e) of U.S. Provisional Patent Application No. 63 / 631,889, filed April 9, 2024, which is incorporated herein by this reference in its entirety. BACKGROUND

[0002] A ground fault circuit interrupter (GFCI) product or device works by continuously monitoring the current flow in a measuring circuit. The monitored current flow is often alternating current (AC) from the electrical grid. The GFCI device compares the current flowing into the measuring circuit (through the line conductor) with the current flowing out of the measuring circuit (through the neutral conductor). Under normal conditions, these currents are equal.

[0003] The GFCI device may contain a current transformer with two coils: one for the line conductor and one for the neutral conductor. If the current flowing out of the sensing circuit does not match the current flowing in, indicating a ground fault (e.g., a current loss to ground), a difference is detected by the current transformer. If the difference exceeds a certain threshold (typically 4-6 milliamperes), the sensing circuit triggers a response. In response to the threshold current being exceeded, the sensing circuit activates a switch that quickly disconnects the electrical supply to the sensing circuit, stopping the flow of electricity. Once activated, the GFCI device is manually reset to restore the electrical supply, ensuring that the fault is corrected before the sensing circuit can be used again. BRIEF DESCRIPTION OF THE DIFFERENT VIEWS OF THE DRAWINGS

[0004] To easily identify the discussion of a particular element or process, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced. Fig. 1 is a schematic diagram of a ground fault circuit interrupter (GFCI) system in which a sensing circuit is implemented in an integrated circuit to detect an outside-to-ground (A / E) leakage current, according to at least one embodiment. Fig. 2 is a schematic diagram illustrating a neutral / ground (N / E) leakage path detectable using a combination of an N / E sensing coil and an A / E sensing coil, according to some embodiments. Fig. 3 is a schematic diagram of a GFCI system in which a sensing circuit is implemented in an integrated circuit to detect N / E leakage current, according to at least some embodiments. Fig. 4 is a flowchart illustrating a method for operating the GFCI circuit of Fig. 1 according to some embodiments. Fig. 5 is a flowchart illustrating a method for operating the GFCI circuit of Fig. 3 according to some embodiments. DETAILED DESCRIPTION

[0005] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, and so forth, in order to provide a thorough understanding of various embodiments of an integrated circuit configured to perform the integrated ground fault detection and interruption of electricity described herein. Such integrated circuits may be implemented in GFCI products or devices in various disclosed embodiments. In other instances, well-known components, elements, or methods are not described in detail or are presented in simple block diagram format to avoid unnecessarily obscuring the subject matter described herein. Thus, the specific details set forth below are merely exemplary.Certain implementations may depart from these example details and still be considered within the spirit and scope of the present embodiments.

[0006] Reference in the specification to "one embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments" means that a particular feature, structure, step, operation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment. Furthermore, the appearances of the phrases "one embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments" in various places in the specification do not necessarily all refer to the same embodiment(s).

[0007] The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrations according to example embodiments. These embodiments, which may also be referred to herein as "examples," are described in sufficient detail to enable one skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It is to be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable one skilled in the art to make, make, and / or use the subject matter.

[0008] Some ground-fault circuit interrupter (GFCI) products on the market today are designed with a two-chip solution that includes an analog front-end providing GFCI functionality and a microcontroller that performs safety functions to meet, for example, the UL-943 specification. Thus, the GFCI products can be considered Class A devices. For example, the microcontroller is externally coupled to an analog GFCI device for the purpose of performing self-tests to comply with UL-943. This two-chip approach takes up printed circuit board (PCB) space, uses more components, and reduces reliability.

[0009] Furthermore, many existing GFCI designs use hard-coded, arbitrary thresholds to determine when the circuit breaker should be activated during a current leakage event, such as interrupting or disconnecting a load from the alternating current (AC) electrical supply. If the sensing circuit fails, existing GFCI products lack the emergency or backup circuitry to provide the protection the GFCI product is designed to provide. Furthermore, existing GFCIs regularly experience nuisance activations due to a lack of signal conditioning or filtering. In some cases, troublesome nuisance activations cause end users to replace the GFCI device with a standard receptacle, which is a less secure, certainly less than ideal, solution.

[0010] Furthermore, because existing GFCI products are implemented in application-specific integrated circuits (ASICs) or hardware, their functionality cannot be changed after manufacturing. A new revision of the entire GFCI product or device would have to be implemented, resulting in manufacturing delays.

[0011] Aspects and embodiments of the present disclosure overcome the above and other deficiencies by integrating a measurement circuit on an integrated circuit (IC) with control logic configured to analyze a digitized version of the leakage current (or voltage) and delay the output of an activation signal based on an average value associated with the leakage current / voltage. In some embodiments, the average value is a root mean square (RMS) or similarly averaged value of the digital signal over time.In this way, an on-demand delay based on an averaged current or voltage value can be used to avoid premature activation of a disconnection from the electricity based on short fluctuations in current that would otherwise cause a GFCI device employing a fixed threshold to activate.

[0012] For example, in some embodiments, a transimpedance amplifier is coupled to an outside-to-ground (A / E) sensing coil, and the A / E sensing coil is coupled to an alternating current (AC) grid. The transimpedance amplifier can convert a leakage current received from the A / E sensing coil into a leakage voltage. An analog-to-digital converter (ADC) coupled to the transimpedance amplifier converts the leakage voltage into a digital signal. Further, in some embodiments, control logic is coupled to the ADC and configured to process the digital signal to determine an average value associated with the leakage voltage over time. The control logic can then determine a trigger delay period corresponding to the average value.The trip delay period may be determined, for example, from a lookup table or the like stored in memory that indexes different trip delay periods with different average values. Further, in response to the leakage voltage still meeting the average value after waiting for the trip delay period, the control logic may output an activation signal to an activation logic that causes a disconnection of a current supplied by the AC grid, as explained. In embodiments, meeting the average value means that the leakage voltage is greater than or equal to the average value.

[0013] As another example, in additional or alternative embodiments, an oscillator is also coupled to a neutral / ground (N / E) sense coil coupled to the AC grid. In embodiments, the oscillator outputs an oscillating current to the AC grid in response to the presence of a ground loop coupling the N / E sense coil to an outside / ground (A / E) sense coil also coupled to the AC grid. The transimpedance amplifier is coupled between the A / E sense coil and the oscillator and is configured to trigger operation of the oscillator and convert the oscillating current into an oscillating voltage. In these embodiments, the ADC converts the oscillating voltage into a digital signal. Further, in embodiments, control logic coupled to the ADC processes the digital signal to determine an average value associated with the oscillating voltage over time.In embodiments, the control logic then determines a trigger delay period corresponding to the average value. The control logic may then, in response to the oscillating voltage still meeting the average value after waiting for the trigger delay period, issue an activation signal to an activation logic that causes a current supplied by the AC grid to be disconnected, as explained. For example, the average of the oscillating voltage may be compared to the previously calculated average value to make this determination.

[0014] Advantages of the present disclosure include, but are not limited to, creating a GFCI product or device that is highly programmable for system enhancements and future requirements changes, while reducing parts count and increasing system reliability. Additionally, the transimpedance amplifier and digital processing (performed by the control logic on the digitized voltage signal) can provide appropriate pre-trip filtering to avoid causing nuisance false activations. Furthermore, the ability to calculate real-time RMS current values ​​(or other types of average current values) allows for handling variable activation delays depending on the actual leakage current, which further functions to avoid nuisance false activations.Other advantages will be apparent to those skilled in the art of GFCI-based design, which is discussed below.

[0015] Fig. Figure 1 is a schematic diagram of a ground fault circuit interrupter (GFCI) system 100 in which a sensing circuit is implemented in an integrated circuit 101 (e.g., GFCI circuit) to detect outdoor-to-ground (A / E) leakage current, according to at least one embodiment. In some embodiments, the GFCI system 100 includes an AC grid 104 with a line (A) and a neutral (N) conductor, and an A / E sensing coil coupled to the AC grid to detect leakage current.

[0016] In some embodiments, the GFCI system 100 further includes a fault assembly 110 that includes a fault switch 106 coupled to a ground and a solenoid 108 (or relay) coupled between the line conductor of the AC grid 104 and the fault switch 106. The fault switch 106 can be triggered to disconnect AC electricity from a load coupled to the AC grid 104. In some embodiments, the fault switch 106 is a silicon-controlled rectifier (SCR) or other type of fault switch.

[0017] In at least some embodiments, the integrated circuit 101 includes a transimpedance amplifier 112 coupled to the A / E sensing coil 102. For example, each of two terminals of the A / E sensing coil 102 may be coupled to a respective input terminal of the transimpedance amplifier. The transimpedance amplifier 112 may include a resistor R1 coupled across a first input terminal and an output terminal, with a second input terminal receiving a voltage reference signal. In embodiments, the transimpedance amplifier 112 converts a leakage current received from the A / E sensing coil 102 into a leakage voltage. The integrated circuit 101 may further include an analog-to-digital converter, or ADC, 114 coupled to the transimpedance amplifier 112 to convert the leakage voltage into a digital signal.

[0018] In various embodiments, the integrated circuit 101 further includes control logic 116 coupled to the ADC 114 and configured to receive the digital signal. In embodiments, the control logic 116 processes the digital signal to determine an average value associated with the leakage voltage over time. In some embodiments, the average value is a root mean square (RMS) or similarly averaged value of the digital signal over time. Thus, the leakage voltage may occur over a period of time or intermittently over time. The control logic 116 may further determine a trigger delay period corresponding to the average value.Further, in response to the leakage voltage still meeting the average value after waiting for the trigger delay period, control logic 116 may output an activation signal to activation logic 130 to cause a current supplied to a load by AC grid 104 to be disconnected. By causing a delay of a certain trigger delay period, integrated circuit 101 can mitigate any noise transients or fault events within the trigger time. In other words, the leakage current must be maintained for at least the trigger delay period to trigger activation logic 130 to disconnect the load from AC grid 104.

[0019] In some embodiments, memory is coupled to control logic 116 to store a lookup table or LUT 122 (or a similar data structure capable of storing data or information) and historical RMS values ​​124 (or other average values). In embodiments, LUT 122 includes RMS values ​​and corresponding trigger delay periods, for example, indexed to the RMS values. Table 1 illustrates an example RMS voltage value (Vrms_ADC), the corresponding trigger delay (in milliseconds (ms)), and an original sensed current from AC grid 104. Table 1 is merely example, and a given LUT 122 may include more, fewer, and / or different values ​​than those displayed in Table 1. Table 1 GemessenerStrom Vrms_ADC Auslöseverzögerung(ms) 3,30E-02 2,1120 8,3333 2,90E-02 1,8480 8,3333 2,65E-02 1,6830 8,3333 2,25E-02 1,4190 16,6667 2,00E-02 1,2540 16,6667 1,75E-02 1,0890 25,0000 1,50E-02 0,9240 41,6667 1,00E-02 0,5940 58,3333 6,00E-03 0,3300 83,3333

[0020] In some embodiments, control logic 116 calculates an RMS value as the average value. Control logic 116 may access LUT 122 and, from LUT 122, determine the trigger delay period based on the RMS value. Control logic 116 may then output the enable signal after waiting for the determined trigger delay period. In some embodiments, control logic 116 may analyze the historical RMS values ​​124 stored in memory 120 to determine a historical RMS value (or average value) to compare with currently measured RMS values ​​from the recently detected leakage current.

[0021] In some embodiments, activation logic 130 is coupled to fault switch 106 and to AC grid 104. In embodiments, activation logic 130 compares the current of AC grid 104 to a minimum voltage during a positive half-cycle of current, e.g., the AC current from AC grid 104. In embodiments, the minimum voltage is required to activate solenoid 108 (or relay) coupled between AC grid 104 and fault switch 106. In embodiments, activation logic 130 causes fault switch 106 to close in response to the current exceeding the minimum threshold and in response to the activation signal. Once closed, the fault switch 106 applies a voltage to the solenoid 108 to energize the relay to disconnect the input AC line voltage (e.g., the phase-to-phase voltage of the AC mains 104) from the load.

[0022] In at least some embodiments, the integrated circuit 101 includes an optional backup circuit 135 to be deployed should the control logic 116 fail or become defective. In some embodiments, the backup circuit 135 includes a pair of comparators 140 coupled to an output of the transimpedance amplifier 112. In embodiments, the pair of comparators 140 compares the leakage voltage to a predetermined threshold (e.g., Vref) and outputs the activation signal when the leakage voltage exceeds the predetermined threshold. The backup circuit 135 may further include a delay unit 142 coupled to the pair of comparators 140 to delay the activation signal by a predetermined delay.

[0023] In some embodiments, the protection circuit 135 further includes an intelligent I / O unit 144 coupled to the delay unit 142 and to the control logic 116. In embodiments, the intelligent I / O unit 144 monitors the control logic 116 for control logic malfunctions and, in response to detecting a control logic malfunction, outputs the enable signal to the fault switch 106 and switches from a GFCI mode employing the control logic 116 to an analog-only mode employing hardware of the protection circuit 135. This can be achieved by determining whether an operating signal (such as a heartbeat signal) is present from the control logic 116.The intelligent I / O unit 144 can switch the activation signal to come from the control logic 116 or to use output signals from the pair of comparators 140 to activate the fault switch 106 depending on the comparison of the leakage current with the predetermined threshold required to trigger a disconnection from the AC grid.

[0024] In some embodiments, the integrated circuit 101 is a system-on-a-chip (SoC) with on-board computing, where the control logic 116 may be implemented, for example, with a microcontroller, a programmable processor, an ASIC, a field-programmable gate array (FPGA) device, a processing core, or the like. In embodiments, the memory 120 is volatile memory, non-volatile memory, or a combination of the volatile memory and the non-volatile memory. Thus, the memory 120 may include memory supporting a cache in which the LUT 122 and the older RMS values ​​124 are buffered, for example, to enable fast access to buffered values ​​during operation of the integrated circuit 101 (e.g., the GFCI circuit).

[0025] Fig. Figure 2 is a schematic diagram illustrating a neutral-to-ground (N / E) leakage path 200 detectable using a combination of an N / E sensing coil 202 and the A / E sensing coil 102, according to some embodiments. For example, in some embodiments, a neutral-to-ground (or N / E) leakage current 203 may occur in the presence of a ground loop coupling the N / E sensing coil 202 to the A / E sensing coil 102. As illustrated, this N / E leakage current 203 may flow from the neutral (N) conductor of the AC mains 104, passing through the coupled coils, and then through a coupled load to ground, forming the "ground loop."

[0026] In at least some embodiments, the system 100 may include an integrated circuit 201 that is similar to the integrated circuit 101 of Fig. 1, which also includes an oscillator 205. In some embodiments, the oscillator 205 includes a first input terminal coupled to an output of the transimpedance amplifier 112 (e.g., via a second resistor R2) and a second terminal receiving a reference voltage (Vref). A third resistor (R3) may be coupled between the first input terminal and an output terminal of the oscillator 205. In some embodiments, an output of the oscillator 205 is coupled to a first terminal of the N / E sense coil 202. A second terminal of the N / E sense coil 202 may be coupled to ground. In this way, when the ground loop is formed across the A / E sense coil 102 and the N / E sense coil 202, the output of the transimpedance amplifier 112 can trigger the oscillator 205 to detect a voltage that exceeds the reference voltage (Vref).Once triggered, oscillator 205 may output an oscillating current to AC grid 104, which may be used to detect a magnitude of N / E leakage current 203, as explained in more detail. In some embodiments, oscillator 205 generates the oscillating current at a frequency of at least two kilohertz.

[0027] Fig. 3 is a schematic diagram of a GFCI system 300 in which a measurement circuit is implemented in an integrated circuit 301 to detect the N / E leakage current 203, according to at least some embodiments. In some embodiments, the integrated circuit 301 may be similar to the integrated circuit 201 of Fig. 2, but now also illustrated with the components that are described with reference to the integrated circuit 101 of Fig. 1 will be discussed.

[0028] In some embodiments, the oscillator 205 is coupled to the N / E sensing coil 202, which is coupled to the AC grid 104. In embodiments, the oscillator 205 outputs an oscillating current to the AC grid 104 in response to the presence of a ground loop coupling the N / E sensing coil 202 to the A / E sensing coil 102, which is also coupled to the AC grid 104. The transimpedance amplifier 112 may be coupled between the A / E sensing coil 102 and the oscillator 205. In embodiments, the transimpedance amplifier 112 triggers the operation of the oscillator 205 and converts the oscillating current into an oscillating voltage, e.g., as described with reference to Fig. 2 discussed.

[0029] In various embodiments, as discussed, the ADC 114 is coupled to the transimpedance amplifier 112 and configured to convert the oscillating voltage into a digital signal. The control logic 116 may be coupled between the ADC and the enable logic 130. In embodiments, the control logic 116 processes the digital signal to determine an average value associated with the oscillating voltage over time. In some embodiments, the average value is a root mean square (RMS) or similarly averaged value of the digital signal over time. Thus, the leakage voltage may occur over a period of time or intermittently over time. In embodiments, the control logic 116 determines a trigger delay period corresponding to the average value.The control logic may then, in response to the oscillating voltage still meeting the average value after waiting for the trigger delay period, issue an enable signal to enable logic to cause a current supplied to a load by the AC grid 104 to be disconnected. The remainder of the functionality and description described with reference to the integrated circuit 101 (. Fig. 1) and the integrated circuit 201 ( Fig. 2) apply equally to the integrated circuit 103 ( Fig. 3) and are not repeated here.

[0030] Fig. 4 is a flowchart illustrating a method 400 for operating the GFCI circuit of Fig. 1 according to some embodiments. The method 400 may be implemented by the integrated circuit 101 described with reference to Fig. 1, may be performed to include processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions executing on a processing device), or a combination thereof. Although shown in a particular sequence or order, the order of operations may be modified unless otherwise noted. Thus, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in a different order, while some operations may be performed in parallel. Additionally, one or more operations may be omitted in some embodiments. Thus, not all illustrated operations are required in every embodiment, and other process flows are possible.

[0031] At operation 410, the method includes the transimpedance amplifier 112 receiving an A / E leakage current from the A / S sense coil.

[0032] At operation 420, method 400 includes converting, by transimpedance amplifier 112, a leakage current received from the A / E sense coil into a leakage voltage.

[0033] At operation 430, method 400 includes converting, by ADC 114, the leakage voltage into a digital signal.

[0034] At operation 440, the processing logic processes the digital signal to determine an average value associated with the leakage voltage over time.

[0035] At operation 450, the processing logic determines a trigger delay period corresponding to the average value, e.g., by performing a lookup in the LUT 122.

[0036] At operation 460, the processing logic determines whether the leakage voltage still meets the average value after waiting for the tripping delay period. If the leakage voltage does not, the method 400 may return to operation 410 and continue processing the received A / E leakage current to determine whether tripping is appropriate, e.g., by subsequently performing operations 420-460.

[0037] At operation 470, in response to the leakage voltage still meeting the average value after waiting for the trip delay period at operation 460, the processing logic issues an enable signal to enable logic 130 to cause a disconnection of a current supplied to a load by the AC mains.

[0038] Fig. 5 is a flowchart illustrating a method 500 for operating the GFCI circuit of Fig. 3 according to some embodiments. The method 500 may be implemented by the integrated circuit 301 described with reference to Fig.3, may be performed to include processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions executing on a processing device), or a combination thereof. Although shown in a particular sequence or order, the order of operations may be modified unless otherwise noted. Thus, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in a different order, while some operations may be performed in parallel. Additionally, one or more operations may be omitted in some embodiments. Thus, not all illustrated operations are required in every embodiment, and other process flows are possible.

[0039] At operation 510, method 500 includes triggering, by transimpedance amplifier 112, operation of oscillator 205 in response to the presence of a ground loop coupling N / E sense coil 202 to A / E sense coil 102.

[0040] At operation 520, method 500 includes outputting, by oscillator 205, an oscillating current in response to the presence of the ground loop.

[0041] At operation 530, method 500 includes converting, by transimpedance amplifier 112, the oscillating current into an oscillating voltage.

[0042] At operation 540, the method includes converting, by the ADC 114, the oscillating voltage into a digital signal.

[0043] At operation 550, the processing logic processes the digital signal to determine an average value associated with the oscillating voltage over time.

[0044] At operation 560, the processing logic determines a trigger delay period corresponding to the average value, e.g., by performing a lookup in the LUT 122.

[0045] At operation 570, the processing logic determines whether the oscillating voltage still meets the average value after waiting for the trigger delay period. If the oscillating voltage does not, the method 500 may return to operation 530 and continue converting the oscillating current to an oscillating voltage and then performing operations 540-570.

[0046] At operation 580, in response to the oscillating voltage still meeting the average value after waiting for the trip delay period at operation 570, the processing logic issues an enable signal to enable logic 130 to cause a disconnection of a current supplied to a load by the AC mains.

[0047] Various embodiments of the integration of ground fault detection and interruption with a variable delay for AC power shutdown described herein may include various operations. These operations may be performed and / or controlled by hardware components, digital hardware and / or firmware, and / or combinations thereof. As used herein, the term "coupled to" may mean directly connected or indirectly connected through one or more intervening components. Each of the signals provided via various on-die buses may be time-multiplexed with other signals and provided via one or more common on-die buses. Additionally, the connection between circuit components or blocks may be shown as buses or as individual signal lines.Each of the buses may alternatively be one or more individual signal lines, and each of the individual signal lines may alternatively be buses.

[0048] Certain embodiments may be implemented by firmware instructions stored on a non-transitory computer-readable medium, such as volatile memory and / or non-volatile storage. These instructions may be used to program and / or configure one or more devices including processors (e.g., CPUs) or equivalents thereof (such as processing cores, processing engines, microcontrollers, and the like) such that the instructions, when executed by the processor(s) or equivalents thereof, cause the device(s) to perform the operations described herein for GFCI-related architectures. The non-transitory computer-readable storage medium may be an electromagnetic storage medium, a read-only memory (ROM), a random access memory (RAM), an erasable programmable memory (e.g.,EPROM and EEPROM), flash memory, or any other now known or later developed non-volatile type of medium suitable for storing information.

[0049] Although the operations of the circuit(s) and block(s) are shown and described herein in a particular order, in some embodiments, the order of operations of each circuit / block may be changed so that certain operations may be performed in a reverse order, or so that certain operations may be performed at least partially concurrently and / or in parallel with other operations. In other embodiments, instructions or suboperations of various operations may be performed intermittently and / or alternately.

[0050] In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are accordingly to be considered in an illustrative rather than a restrictive sense. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 631,889

[0001]

Claims

[1] An integrated circuit that includes: a transimpedance amplifier coupled to an external / ground (A / E) sensing coil, the A / E sensing coil being coupled to an alternating current (AC) network, and the transimpedance amplifier being operable to convert a leakage current received from the A / E sensing coil into a leakage voltage; an analog-to-digital converter (ADC) coupled to the transimpedance amplifier to convert the leakage voltage into a digital signal; Control logic coupled to the ADC, where the control logic is used to: Processing the digital signal to determine an average value associated with the leakage voltage over time; Determining a trigger delay period corresponding to the average value; and Issuing, in response to the leakage voltage still meeting the average value after waiting for the trip delay period, an enable signal to an enable logic to cause a disconnection of a current supplied to a load by the AC mains. [2] The integrated circuit of claim 1, wherein each of two terminals of the A / E sense coil is coupled to a respective input terminal of the transimpedance amplifier. [3] The integrated circuit of claim 1, wherein the control logic further serves to: Calculate a root mean square (RMS) value as the average value; Accessing a lookup table (LUT) containing RMS values ​​and corresponding trigger delay periods; and Determine, from the LUT, the trigger delay period based on the RMS value. [4] The integrated circuit of claim 3, wherein the integrated circuit includes a memory coupled to the control logic, the control logic being operable to store the RMS value in the memory with older RMS values. [5] The integrated circuit of claim 1, wherein the activation logic is coupled to a fault switch and to the AC network, the activation logic being for: Comparing the AC mains current with a minimum voltage during a positive half-cycle of the current, the minimum voltage being required to activate a solenoid coupled between the AC mains and the fault breaker; and Cause the fault switch to close in response to the current exceeding the minimum threshold and in response to the enable signal. [6] The integrated circuit of claim 1, wherein the integrated circuit further comprises: a pair of comparators coupled to an output of the transimpedance amplifier, the pair of comparators serving to: Comparing the leakage voltage with a predetermined threshold; and Outputting the activation signal when the leakage voltage exceeds the predetermined threshold; and a delay unit coupled to the pair of comparators for delaying the activation signal by a predetermined delay. [7] An integrated circuit according to claim 6, further comprising: an intelligent I / O unit coupled to the delay unit, the intelligent I / O unit serving to: Monitoring the control logic for control logic malfunctions; and in response to detecting a control logic malfunction: Outputting the activation signal to a fault switch; and Switching from a GFCI mode that uses control logic to an analog-only mode. [8] An integrated circuit comprising: an oscillator coupled to a neutral / earth (N / E) sensing coil coupled to an alternating current (AC) network, the oscillator operable to output an oscillating current to the AC network in response to the presence of an earth loop coupling the N / E sensing coil to an outside / earth (A / E) sensing coil also coupled to the AC network; a transimpedance amplifier coupled between the A / E measuring coil and the oscillator, the transimpedance amplifier serving to trigger the operation of the oscillator and to convert the oscillating current into an oscillating voltage; an analog-to-digital converter (ADC) coupled to the transimpedance amplifier, the ADC serving to convert the oscillating voltage into a digital signal; Control logic coupled to the ADC, where the control logic is used to: Processing the digital signal to determine an average value associated with the oscillating voltage over time; Determining a trigger delay period corresponding to the average value; and Issuing, in response to the oscillating voltage still meeting the average value after waiting for the trip delay period, an enable signal to an enable logic to cause a disconnection of a current supplied to a load by the AC mains. [9] The integrated circuit of claim 8, wherein an output of the oscillator is coupled to a first terminal of the N / E measuring coil and wherein a second terminal of the N / E measuring coil is coupled to ground. [10] The integrated circuit of claim 8, wherein the control logic further serves to: Calculate a root mean square (RMS) value as the average value; Accessing a lookup table (LUT) containing RMS values ​​and corresponding trigger delay periods; and Determine, from the LUT, the trigger delay period based on the RMS value. [11] The integrated circuit of claim 10, wherein the integrated circuit includes a memory coupled to the control logic, the control logic for storing the RMS value in the memory with older RMS values. [12] The integrated circuit of claim 8, wherein the oscillator is arranged to generate the oscillating current at a frequency of at least two kilohertz. [13] The integrated circuit of claim 8, wherein the activation logic is coupled to a fault switch and to the AC network, the activation logic being for: Comparing the AC mains current with a minimum voltage during a positive half-cycle of the current, the minimum voltage being required to activate a solenoid coupled between the AC mains and the fault switch; and Cause the fault switch to close in response to the current exceeding the minimum threshold and in response to the enable signal. [14] The integrated circuit of claim 8, wherein the integrated circuit further comprises: a pair of comparators coupled to an output of the transimpedance amplifier, the pair of comparators serving to: Comparing the oscillating voltage with a predetermined threshold value; and Outputting an activation signal when the oscillating voltage exceeds the predetermined threshold; and a delay unit coupled to the pair of comparators for delaying the activation signal by a predetermined delay. [15] An integrated circuit according to claim 14, further comprising: an intelligent I / O unit coupled to the delay unit, the intelligent I / O unit serving to: Monitoring the control logic for control logic malfunctions; and in response to detecting a control logic malfunction: Outputting the activation signal to a fault switch; and Switching from a GFCI mode that uses control logic to an analog-only mode. [16] A method of operating a residual current device (GFCI) circuit, the GFCI circuit comprising: a transimpedance amplifier coupled to an outside-to-ground (A / E) sensing coil, the A / E sensing coil coupled to an alternating current (AC) network, an analog-to-digital converter (ADC) coupled to the transimpedance amplifier, control logic coupled to the ADC and to activation logic, the method of operating the GFCI circuit comprising: Converting, by the transimpedance amplifier, a leakage current received from the A / E measuring coil into a leakage voltage; Converting, through the ADC, the leakage voltage into a digital signal; Processing, by the control logic, the digital signal to determine an average value associated with the leakage voltage over time; Determining a trigger delay period corresponding to the average value; and Issuing, by the control logic, in response to the leakage voltage still meeting the average value after waiting for the trip delay period, an activation signal to the activation logic to cause a disconnection of a current supplied to a load by the AC mains. [17] The method of claim 16, wherein operating the GFCI circuit further includes: Calculating, by the control logic, a root mean square (RMS) value as the average value; Accessing, by the control logic, a look-up table (LUT) containing RMS values ​​and corresponding trigger delay periods; and Determine, from the LUT, the trigger delay period based on the RMS value. [18] The method of claim 16, wherein the activation logic is coupled to a fault circuit breaker and to the AC grid, and wherein operating the GFCI circuit further includes: Comparing, by the activation logic, the AC mains current with a minimum voltage during a positive half-cycle of the current, the minimum voltage being required to activate a solenoid coupled between the AC mains and the fault switch; and Cause, through the enable logic, the fault switch to close in response to the current exceeding the minimum threshold to the enable signal. [19] A method of operating a residual current device (GFCI) circuit, the GFCI circuit including: an oscillator coupled to a neutral / ground (N / E) sensing coil, the N / E sensing coil coupled to an alternating current (AC) system, an outside / ground (A / E) sensing coil coupled to the AC system, a transimpedance amplifier coupled between the oscillator and the A / E sensing coil, an analog-to-digital converter (ADC) coupled to the transimpedance amplifier, control logic coupled to the ADC, and enable logic coupled to the control logic, the method of operating the GFCI circuit including: triggering, by the transimpedance amplifier, the operation of the oscillator in response to the presence of a ground loop coupling the N / E measuring coil to the A / E measuring coil; Outputting, by the oscillator, an oscillating current in response to the presence of the ground loop; Converting, by the transimpedance amplifier, the oscillating current into an oscillating voltage; Converting, through the ADC, the oscillating voltage into a digital signal; Processing, by the control logic, the digital signal to determine an average value associated with the oscillating voltage over time; Determining a trigger delay period corresponding to the average value; and Issuing, by the control logic, in response to the oscillating voltage still meeting the average value after waiting for the trip delay period, an activation signal to an activation logic to cause a disconnection of a current supplied to a load by the AC mains. [20] A method of operating the GFCI circuit according to claim 19, wherein operating the GFCI circuit further includes: Calculating, by the control logic, a root mean square (RMS) value as the average value; Accessing, by the control logic, a look-up table (LUT) containing RMS values ​​and corresponding trigger delay periods; and Determine, from the LUT, the trigger delay period based on the RMS value.

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