METHOD FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE

Abstract

A method of manufacturing a semiconductor power device, comprising: Forming a first insulating layer (31) on an n-type substrate (20) and etching the first insulating layer (31) to form an opening (40); Forming an insulating side wall (32) in the opening (40); Etching the n-type substrate (20) using the first insulating layer (31) and the insulating sidewall (32) as a mask to form a first groove (41) in the n-type substrate (20); Forming a second insulating layer (21) and a shielding gate (22) in the first groove (41); Forming a third insulating layer (33) on a surface of the shield gate (22); Etching away the insulating sidewall (32); and etching the n-type substrate (20) using the first insulating layer (31), the second insulating layer (21), and the third insulating layer (33) as a mask to form a second groove (42) in the n-type substrate (20); Forming a fourth insulating layer (23) and a gate (24) in the second groove (42) such that the gate (24) is insulated from the shield gate (22) by the second insulating layer (21); Etching away the first insulating layer (31) and the third insulating layer (33); forming a p-type body region in the n-type substrate (20); and Forming an n-type source region in the p-type body region.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor power device technology, e.g. to a method for manufacturing a semiconductor power device. BACKGROUND

[0002] A related art method for manufacturing a semiconductor power device includes the following steps: A hard mask layer is formed on a provided silicon substrate. The position of a groove is defined by a photolithography process. Then, the hard mask layer is etched away at a groove position. The silicon substrate is etched using the etched hard mask layer as a mask to form the groove. The bottom surface of the groove and the side of the groove are covered, forming a first dielectric layer. A first polysilicon layer is deposited. The first polysilicon layer completely fills the groove formed with the first dielectric layer and extends to the outside of the groove. The polysilicon is etched back to remove the first polysilicon layer located outside the groove. The first polysilicon layer remaining after etching forms a shield gate.The first dielectric layer is self-aligned etched using the silicon on the groove side and the first polysilicon layer as a self-aligned boundary. The self-aligned etch removes the first dielectric layer at the top of the groove and retains the first dielectric layer at the bottom of the groove. Furthermore, the retained first dielectric layer is located at the bottom of a subsequently formed body region. A fourth insulating layer is formed on the inner surface of the top of the groove after the first dielectric layer has been removed. The thickness of the fourth insulating layer is less than the thickness of the first dielectric layer. A second polysilicon layer is deposited. The second polysilicon layer completely fills the top of the groove, in which the fourth insulating layer is formed after the first dielectric layer has been removed.The polysilicon is etched back to remove the second polysilicon layer located outside the groove. The second polysilicon layer remaining after etching forms a polysilicon gate. In the related art method for manufacturing a semiconductor power device, the first dielectric layer must be formed with a sufficient thickness to ensure the quality of the polysilicon gate. However, the thickness of the first dielectric layer affects the charge depletion at the bottom of the groove, thus affecting the withstand voltage of the semiconductor power device.

[0003] US 2014 / 0 134 813 A1 describes a method for manufacturing a semiconductor device, comprising the following steps: forming a gate trench on a semiconductor substrate; forming a spacer within the gate trench; forming one or more gate electrodes within the gate trench; implanting a body region; implanting a source region; forming a contact trench; disposing dielectric material within the gate trench; removing at least a portion of the dielectric material such that at least a portion of the source region extends over the dielectric material; and depositing a metal layer over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench. SUMMARY

[0004] The present application provides a method for manufacturing a semiconductor power device that can ensure the quality of the gate and does not impair the withstand voltage of the semiconductor power device.

[0005] In a first aspect, the present application provides a method of manufacturing a semiconductor power device comprising the steps described below.

[0006] A first insulating layer is formed on an n-type substrate. The first insulating layer is etched to form an opening.

[0007] An insulating side wall is formed in the opening.

[0008] The n-type substrate is etched using the first insulating layer and the insulating sidewall as a mask, so that a first groove is formed in the n-type substrate.

[0009] A second insulating layer and a shield gate are formed in the first groove.

[0010] A third insulating layer is formed on the surface of the shield gate.

[0011] The insulating sidewall is etched away. The n-type substrate is etched using the first insulating layer, the second insulating layer, and the third insulating layer as a mask, forming a second groove in the n-type substrate.

[0012] A fourth insulating layer and a gate are formed in the second groove. The gate is insulated from the shield gate by the second insulating layer.

[0013] The first insulating layer and the third insulating layer are etched away.

[0014] A p-type body region is formed in the n-type substrate.

[0015] An n-type source region is formed in the p-type body region.

[0016] In the method for manufacturing a semiconductor power device according to the present application, the first insulating layer optionally contains a silicon oxide layer.

[0017] In the method for manufacturing a semiconductor power device according to the present application, the second insulating layer is optionally the silicon oxide layer.

[0018] In the method for manufacturing a semiconductor power device according to the present application, the third insulating layer is optionally the silicon oxide layer.

[0019] In the method for manufacturing a semiconductor power device according to the present application, the insulating sidewall is optionally a silicon nitride layer.

[0020] Optionally, in the method for manufacturing a semiconductor power device according to the present application, an etching process combining anisotropic etching and isotropic etching is performed when the second groove is formed by etching.

[0021] Optionally, in the method for manufacturing a semiconductor power device according to the present application, the depth of the second groove is less than the depth of the first groove.

[0022] In the method for manufacturing a semiconductor power device according to the present application, the first groove is formed by a photolithography process, the n-type substrate is etched in a self-aligned manner using the first insulating layer, the second insulating layer, and the third insulating layer as a mask, so that the second groove is formed in the n-type substrate, and the fourth insulating layer and the gate are formed in the second groove. In the method for manufacturing a semiconductor power device according to the present application, the quality of the formed gate is not limited by the thickness of the second insulating layer. Furthermore, not only is the quality of the gate ensured, but the thickness of the second insulating layer can also be reduced. Therefore, the withstand voltage of the semiconductor power device is not affected. BRIEF DESCRIPTION OF THE DRAWINGS The Fig. 1 to 6 are sectional views illustrating the main structures in the manufacturing process of the method for manufacturing a semiconductor power device of an embodiment of the present application. DETAILED DESCRIPTION

[0023] The solutions of the present application are fully described below in conjunction with the drawings in the embodiment of the present application. It is obvious that the described embodiment represents a part and not all embodiments of the present application. To clearly illustrate the embodiment of the present application, the thicknesses of the layers and regions described in the present application are exaggerated in the views shown in the drawings of the description, and the sizes of the graphics shown in the drawings do not correspond to the actual dimensions.

[0024] The Fig. 1 to 6 are sectional views showing the main structures of the manufacturing method in the manufacturing process of a semiconductor power device of an embodiment of the present application.

[0025] First, as in Fig. 1, the first insulating layer 31 is formed on the provided n-type substrate 20. The n-type substrate 20 is typically an n-type silicon substrate. The first insulating layer 31 includes the silicon oxide layer. The first insulating layer 30 may be, for example, the silicon oxide layer or the coating of the silicon oxide layer-silicon nitride layer-silicon oxide layer. The position of the opening is defined by the photolithography process. Then, the first insulating layer 31 is etched to form at least one opening 40 in the first insulating layer 31. The number of openings 40 is determined by the specification of the designed semiconductor power device. For example, in this embodiment of the present application, only two openings 40 are shown.

[0026] Next, as in Fig. 2, the insulating sidewall 32 is formed in the opening of the first insulating layer 31. The insulating sidewall 32 can optionally be the silicon nitride layer. The process includes, for example, the following steps: First, a silicon nitride layer is deposited. Subsequently, the deposited silicon nitride layer is etched back. With this configuration, the insulating sidewall 32 is formed in a self-aligned manner at the position of the sidewall of the opening 40. After the insulating sidewall 32 has been formed, the n-type substrate 20 is etched using the first insulating layer 31 and the insulating sidewall 32 as a mask to form the first groove 41 in the n-type substrate 20.

[0027] Next, as in Fig. 3, the second insulating layer 21 and the shield gate 22 are formed in the first groove. The second insulating layer 21 may optionally be the silicon oxide layer formed by a thermal oxidation process. The shield gate 22 is generally a polysilicon gate. A forming method includes the following steps: After the second insulating layer 21 is formed, a polysilicon layer is deposited. Then, the deposited polysilicon layer is etched back. The polysilicon layer remaining after the etching forms the shield gate 22. After the shield gate 22 is formed, the third insulating layer 33 is formed on the surface of the shield gate 22. The third insulating layer 33 may optionally be the silicon oxide layer formed by the thermal oxidation process.At this time, the third insulating layer 33 and the second insulating layer 21 are connected to each other. Consequently, the shield gate 22 is surrounded by the second insulating layer 21 and the third insulating layer 33.

[0028] Next, as in Fig. 4, the insulating sidewall is etched away. The n-type substrate 20 is self-aligned etched using the first insulating layer 31, the second insulating layer 21, and the third insulating layer 33 as a mask, so that the second groove 42 is formed in the n-type substrate 20. The depth of the second groove 42 is shallower than the depth of the first groove. The etching process combining anisotropic etching and isotropic etching is performed when the second groove 42 is formed by etching. In this way, the width of the second groove 42 can be increased. As a result, the width of the second groove 42 is wider than the width of the previously formed insulating sidewall. This increases the width of the gate formed later. Therefore, the gate can be manufactured more easily.

[0029] It should be noted that the thickness of the oxidized n-type substrate 20 at the position of the sidewall of the first groove is made thinner than the thickness of the insulating sidewall when the second insulating layer 21 is formed by the thermal oxidation process. Therefore, it is ensured that the n-type substrate 20 is exposed after the insulating sidewall is etched away. In this way, the n-type substrate 20 can be etched to form the second groove 42.

[0030] Next, as in Fig. 5, the fourth insulating layer 23 is formed in the second groove. The fourth insulating layer 32 is typically the silicon oxide layer formed by the thermal oxidation process. The gate 24 is then formed in the second groove. The manufacturing process includes the following steps: A polysilicon layer is deposited. The deposited polysilicon layer is then etched back. The polysilicon layer remaining after etching forms the gate 24. The gate 24 is insulated from the shield gate 22 by the second insulating layer 21. The first insulating layer and the third insulating layer are then etched away.

[0031] Optionally, after the formation of the second groove, the first insulating layer, the third insulating layer, and a portion of the second insulating layer 21 located at the sidewall position of the second groove may be etched away. Then, the fourth insulating layer 23 is formed by the thermal oxidation process. At this time, the fourth insulating layer 23 is also formed on the exposed sidewall of the shield gate 22. As shown in Fig. As shown in Figure 6, after the gate 24 is formed, the gate 24 is insulated from the shield gate 22 by the fourth insulating layer 23. At this time, the gate 24 has a larger width. Therefore, the gate can be more easily formed by an external electrode.

[0032] Next, according to a conventional process, the p-type body region is formed in the n-type substrate. The n-type source region is formed in the p-type body region. Then, the semiconductor power device can be obtained with the arrangement in which an insulating dielectric layer, a metal layer, and the like are formed.

[0033] In the method for manufacturing a semiconductor power device according to the present application, the first groove is formed by a photolithography process, a shield gate structure is formed in the first groove, and then the n-type substrate is etched in a self-aligned manner using the first insulating layer, the second insulating layer, and the third insulating layer as a mask, so that the second groove is formed in the n-type substrate, and the fourth insulating layer and the gate are formed in the second groove. With this configuration, in the method for manufacturing a semiconductor power device according to the present application, the gates are formed in the second grooves on two sides of the first groove. The quality of the formed gate is not limited by the thickness of the second insulating layer. Furthermore, not only is the quality of the gate ensured, but the thickness of the second insulating layer can also be reduced.Therefore, the withstand voltage of the semiconductor power device is not affected.

Claims

[1] A method of manufacturing a semiconductor power device, comprising: Forming a first insulating layer (31) on an n-type substrate (20) and etching the first insulating layer (31) to form an opening (40); Forming an insulating side wall (32) in the opening (40); Etching the n-type substrate (20) using the first insulating layer (31) and the insulating sidewall (32) as a mask to form a first groove (41) in the n-type substrate (20); Forming a second insulating layer (21) and a shielding gate (22) in the first groove (41); Forming a third insulating layer (33) on a surface of the shield gate (22); Etching away the insulating sidewall (32); and etching the n-type substrate (20) using the first insulating layer (31), the second insulating layer (21), and the third insulating layer (33) as a mask to form a second groove (42) in the n-type substrate (20); Forming a fourth insulating layer (23) and a gate (24) in the second groove (42) such that the gate (24) is insulated from the shield gate (22) by the second insulating layer (21); Etching away the first insulating layer (31) and the third insulating layer (33); forming a p-type body region in the n-type substrate (20); and Forming an n-type source region in the p-type body region. [2] The method of claim 1, wherein the first insulating layer (31) comprises a silicon oxide layer. [3] Method according to one of the preceding claims, wherein the second insulating layer (21) is a silicon oxide layer. [4] A method according to any one of the preceding claims, wherein the third insulating layer (33) is a silicon oxide layer. [5] A method according to any one of the preceding claims, wherein the insulating sidewall (32) is a silicon nitride layer. [6] A method according to any one of the preceding claims, wherein an etching process combining anisotropic etching and isotropic etching is performed when the second groove (42) is formed by etching. [7] Method according to one of the preceding claims, wherein a depth of the second groove (42) is less than a depth of the first groove (41).

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