Electric switching arrangement for level conversion of digital signals

Abstract

The invention relates to an electric switching arrangement for level conversion of digital input signals of a first voltage domain into digital output signals of a second voltage domain with respect to the first voltage domain, having a first transistor which is controlled by the digital input signal and whose assigned source-drain section is connected between a ground potential and an input of a current mirror which has an output that is connected to an intermediate store via a first contact point. The invention is characterised in that the intermediate store has a second contact point which is connected to a gate terminal of a second transistor whose assigned source-drain section is arranged in series with the source-drain section of the first transistor between the input of the current mirror and the first transistor.

Description

[0001] Electrical circuit arrangement for level conversion of digital signals

[0002] Technical area

[0003] The invention relates to an electrical circuit arrangement for level conversion of digital input signals of a first voltage domain into digital output signals of a second voltage domain relative to the first voltage domain, comprising a first transistor controlled by the digital input signal, the associated source-drain path of which is connected between a ground potential and an input of a current mirror having an output connected to a buffer via a first contact point.

[0004] State of the art

[0005] Generic electrical circuit arrangements for level conversion, also referred to as level converters, level converters or “level shifters”, are used, particularly in digital technology, to transform digital signals from one voltage domain to another voltage domain in order to be able to operate digital electronic switching elements designed for higher supply and operating voltages within an electrical circuit arrangement in combination with digital switching elements designed for lower supply and operating voltages.

[0006] For example, using such level converters it is possible to transform digital signals, for example with signal levels between 0 and 1.8 V, into a higher voltage domain, so that their associated signal levels are, for example, between 10 and 11.8 V. Known, generic electrical circuit arrangements for this purpose have, for example, a current mirror whose associated input potential is used to control two transistors and whose output is connected to a buffer, a so-called latch. Such circuit arrangements can be found, for example, in the following publications: US 5,973,508 and, for example, the article by Qiang Li, et al., "A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique", Sensors 2022, 22 (5), 1774. A comparable circuit arrangement can also be found in the publication US 2013 / 0049808 A1.

[0007] When designing and constructing such electrical circuits, the goal is to achieve the shortest possible conversion or transmission times for signal level changes, even with considerable voltage swings of typically approximately ± 20 V and more. Conventional circuits use capacitors and / or pulse signal generators to control or activate the current mirror and the buffer connected to it. Their inherent time constants for executing switching processes place limits on the pursuit of the shortest possible level conversion times. In addition, the operation of such circuits involves power-consuming conduction paths that are otherwise not involved in the switching or signal level transmission process. This leads to unnecessary power consumption.

[0008] Description of the invention

[0009] The invention is based on the object of developing an electrical circuit arrangement for level conversion of digital input signals of a first voltage domain into digital output signals of a second voltage domain, which is preferably higher than the first voltage domain, with a first transistor controlled by the digital input signal, the associated source-drain path of which is connected between a ground potential and an input of a current mirror having an output connected to a buffer via a first contact point, in such a way that the disadvantages of the prior art mentioned above are to be avoided. In particular, in addition to avoiding unnecessary power consumption within the circuit arrangement, the switching or transmission times for level conversion of the digital input signals must be further shortened.

[0010] The solution to the problem underlying the invention is defined in claim 1. Features that advantageously further develop the inventive concept are the subject of the dependent claims and the further description, with reference to the drawings.

[0011] An electrical circuit arrangement according to the invention for level conversion of digital input signals according to the features of the preamble of claim 1 is characterized in that the buffer has a second contact point which is connected to a gate terminal of a second transistor, the associated source-drain path of which is arranged in series with the source-drain path of the first transistor between the input of the current mirror and the first transistor.

[0012] By providing the second transistor, preferably designed as a high-voltage transistor, along the so-called bias path between the first transistor and the input of the current mirror, as well as by directly controlling the second transistor through the buffer, it is ensured that only current that is exclusively associated with the level conversion of a digital signal can flow along the bias path. In all other operating states in which a constant current could flow along the bias path, the second transistor blocks any current flow. The second transistor is controlled in positive feedback directly from the buffer. For this purpose, the second transistor is connected to the buffer via the second contact point, which is arranged opposite the first contact point of the buffer, i.e.Components, preferably transistors, of the buffer are connected between the two contact points, which cause a system-immanent time delay (metastability) with regard to the signal transmission between the two contact points.

[0013] Preferably, a delay element is inserted between the gate terminal of the second transistor and the latch. This delay element ensures that immediately after the latch is set, the second transistor is blocked, i.e., set to "off," in order to interrupt a constant bias current when the first transistor is set to "on." By using the delay element, additional operational reliability can be generated in order to have some time reserve or time buffer for different transients, i.e., rise / fall rates of a signal, and process situations, which increases the operational robustness of the circuit arrangement.

[0014] The circuit arrangement according to the solution dispenses with the use of any capacitors and pulse generators, so that the circuit arrangement according to the solution enables significantly improved, ie very short, transmission times with which digital signals can be transmitted from a preferably lower first voltage domain to a higher second voltage domain.

[0015] A further advantage of the novel circuit arrangement is its autonomous response capability, i.e., when the latch is "set," the second transistor is blocked. Furthermore, since the circuit is not dependent on circuit-specific time constants, which may arise from, for example, existing RC elements or similar, the circuit arrangement according to the solution can be efficiently deployed and used at different levels, for example, in a range from 1.8 V to 18 V. Brief description of the invention

[0016] The invention is described below, without limiting the general inventive concept, using exemplary embodiments with reference to the drawings. They show:

[0017] Fig. 1 Circuit topology of an electrical circuit arrangement designed according to the solution for level conversion of digital input signals and

[0018] Fig. 2 Representation of the circuit arrangement of associated

[0019] Stress domains.

[0020] Ways of implementing the invention, industrial applicability

[0021] Figure 1 shows a preferred embodiment of an electrical circuit arrangement with which it is possible to transmit digital input signals from a first lower voltage domain VB to a second, higher voltage domain VD. The voltage potentials, each indicated by area arrows in Figure 2, and the lower voltage domain VB and upper voltage domain VD that can be delimited therein, mark those areas of the electrical circuit arrangement according to Figure 1 in which digital signals belonging to the first lower voltage domain VB and the second upper voltage domain VD occur or are processed.

[0022] The circuit arrangement 1 has an input “in” to which digital input signals are applied whose signal levels correspond to the first voltage domain VB, i.e. the digital signals are defined by the voltage potentials 0 V, corresponding to the ground potential GND, and +1.8 V. The maximum supply voltage VO in the illustrated embodiment is 18 V. The concrete potential specifications are to be understood as exemplary values ​​which do not further restrict the electrical circuit arrangement 1 as such. The input potential of the digital input signals applied to the input “in” controls the first transistor T1, whose associated source-drain path SD-T1 is connected to the ground potential GND on the one hand and to the input “em” of the current mirror M on the other. This connection path corresponds to the bias path B along which the bias current flows to supply the current mirror M.

[0023] The current mirror M has a known circuit configuration consisting of two transistors, a third transistor T3 and a fourth transistor T4, whose gate terminals are each connected to the input "em" of the current mirror M and whose associated drain-source paths DS-T3, DS-T4 are connected at one end to the supply voltage VO, which also corresponds to the upper potential limit of the second voltage domain VD. The two transistors T3, T4 of the current mirror M each have the same doping type, i.e., they are designed either as NMOS or PMOS transistors.

[0024] The source-drain path SD-T4 of the fourth transistor T4 forms, opposite the contact to the supply voltage VO, the output "am" of the current mirror M, which is also connected to a contact point "op" of the latch. The latch has, in a manner known per se, two pairs of series-connected transistors, (1T and 2T) and (3Z and 4T), whose gate terminals are connected to one another in the cross connection shown in Figure 1a, i.e. the gate terminals of the series-connected latch transistors 1T and 2T are connected to a second contact point "on" of the latch, and the gate terminals of the series-connected latch transistors 3T and 4T are connected to the first contact point "op" of the latch.The latch is also connected between the supply potential VO and another voltage potential VI, which corresponds to the lower limit of the second voltage domain VD.

[0025] A second transistor T2 is arranged along bias path B between the first transistor T1 and the input "em" of the current mirror M. Its source-drain path is connected in series with the source-drain path of the first transistor T1 to the input "em" of the current mirror M. The gate terminal of the second transistor T2 is connected to the second contact point "on" of the latch and is controlled by it. Preferably, a delay element "delay" is inserted between the second contact point "on" of the latch and the gate terminal of the second transistor T2, which is biased between the voltage potential VI and the supply potential VO.

[0026] The output “out” of the electrical circuit arrangement 1 is connected to the output “am” of the current mirror M.

[0027] For the purpose of resetting the voltage potential temporarily stored in the buffer "latch", a circuit arrangement with inverted controlled signals that is symmetrical to the above circuit components is arranged at the second contact point "on" of the buffer "latch", from which the second transistor T2 is controlled or switched. This circuit arrangement provides a further current mirror M', the input "em'" of which is connected to the ground potential GND via two series-connected source-drain paths of two transistors T1, T2', of which one transistor T1' is controlled by the input signal at the input "in" via a delay element "delay" that primarily serves as an inverter, and the other transistor T2' is controlled by an output signal present at the output "out" and at the output "am" of the current mirror M via a further delay element "delay'".Due to the symmetrical circuit design with inverted controlled signal, the circuit operates fully differentially, ie a differential input signal at T1 and TT could also generate a differential output signal at “op” and “on”.

[0028] Optionally, a switch SM is additionally arranged on the current mirror M, which, when closed, short-circuits the gates of the third and fourth transistors T3, T4 to the supply voltage VO. A corresponding switch SM' is preferably also arranged in the symmetrically designed current mirror M'. This switch SM or SM' can improve the efficiency of the circuit arrangement. As soon as the second transistor T2 closes, charges are retained in the current mirror M or M', ensuring that the current to the buffer "latch" is not completely switched off. The switch SM or SM' therefore enables complete switch-off and also increases the mirroring speed, since the charge can be removed more quickly from the parasitic capacitances of the current mirror.

[0029] How it works: If a digital input signal is applied to the "in" input of the electrical circuit arrangement 1, the first transistor T1 is switched "on", causing a bias current to develop along the bias path B through the second transistor T2, which is also switched on. The bias current applied to the "em" input of the current mirror M is scaled by the current mirror M and fed into the buffer "latch" via its output at the first contact point "op". The gate terminal of the second transistor T2 is controlled directly from the buffer "latch" by way of positive feedback, which puts T2 into the blocked state "off". In this way, any bias current along the bias path B is prevented.

[0030] To ensure that the latch has completely completed the storage process, especially as long as the second transistor T2 should be conductive, a delay element called "delay" is inserted directly in front of the gate terminal of the second transistor T2.

[0031] For the purpose of resetting the memory value in the buffer "latch", the blocked first further transistor T 1 ' is set to "on" so that current can flow via the conductive second transistor T 2 ' to the further current mirror M ', which can reset the buffer "latch" via the second contact point "on". In this case too, the second transistor T 2 ' is immediately blocked by positive feedback from the buffer "latch" via its first contact "op" in order to avoid unnecessary constant leakage currents along the further bias path B '. The optionally provided switches SM and SM ' are controlled by the buffer "latch" by connecting them to the contact points "op" and "on" respectively, in order to reset the bias voltage at the current mirror M or at the further current mirror M ' more quickly and thus further increase the switching speed of the electrical circuit arrangement 1.In addition, the switches SM and SM' help to save additional leakage currents that would otherwise occur.

[0032] List of reference symbols

[0033] 1 electrical circuit arrangement in input

[0034] B Bias path

[0035] M, M' current mirror, further current mirror latch buffer

[0036] SM, SM' Switch for current mirror em, em' Input current mirror, Input further

[0037] Current mirror at, at' Output Current mirror, Output further current mirror op first contact point of the buffer on second contact point of the buffer oq third contact point of the buffer delay, delay', delay" Delay element

[0038] T1, T2, T3, T4, T1', T2', T3', T4' transistors out output

[0039] VB first stress domain

[0040] VD second voltage domain

[0041] VO supply potential

[0042] VI voltage potential

[0043] HV high voltage

[0044] GND Ground

Claims

Patent claims 1 . Electrical circuit arrangement for level conversion of digital input signals of a first voltage domain (VB) into digital output signals of a second voltage domain (VD) relative to the first voltage domain, with a first transistor (T1 ) controlled by the digital input signal, the associated source-drain path of which is connected between a ground potential (GND) and an input (em) of a current mirror (M) which has an output (am) which is connected to a latch via a first contact point (op), characterized in that the latch has a second contact point (on) which is connected to a gate terminal of a second transistor (T2) whose associated source-drain path is arranged in series with the source-drain path of the first transistor (T1) between the input (em) of the current mirror (M) and the first transistor (T1 ).

2. Electrical circuit arrangement according to claim 1, characterized in that the current mirror (M) and the intermediate storage device (latch) are connected to a supply potential (VO) which corresponds to an upper limit of the second voltage domain (VD).

3. Electrical circuit arrangement according to claim 1 or 2, characterized in that the intermediate memory (latch) has a third contact point (oq) which is connected to a voltage potential (VI) corresponding to a lower limit of the second voltage domain (VD).

4. Electrical circuit arrangement according to one of claims 1 to 3, characterized in that between the gate terminal of the second A delay element (delay) is introduced between the transistor (T2) and the second contact point (on).

5. Electrical circuit arrangement according to claim 2 and 4, characterized in that the delay element (delay) is biased between the voltage potential (VI) and the supply potential (VO).

6. Electrical circuit arrangement according to one of claims 2 to 5, characterized in that the input (em) of the current mirror (M) is connected to the supply potential (VO) via a switch (SM).

7. Electrical circuit arrangement according to one of claims 2 to 6, characterized in that the second contact point (on) of the intermediate memory (latch) is connected to an output (am') of a further current mirror (M') and its input (em') is connected to the ground potential (GND) via two series-connected source-drain paths of two transistors (TT), (T2'), of which one transistor (T1') is controlled by the input signal and the other transistor (T2') is controlled via a further delay element (delay') by an output signal applied to the output.

8. Electrical circuit arrangement according to claim 7, characterized in that the further current mirror (M') is connected to the supply potential (VO).

9. Electrical circuit arrangement according to claim 7 or 8, characterized in that the input (em') of the further current mirror (M') is connected to the supply potential (VO) via a further switch (SM').

10. Electrical circuit arrangement according to one of claims 7 to 9, characterized in that a) the current mirror (M) and the further current mirror (M'), b) the first transistor (T 1 ) and the one transistor (T1 ') and c) the second transistor (T2) and the other transistor (T2') are each formed identically / symmetrically in pairs.

11. Electrical circuit arrangement according to one of claims 3 to 10, characterized in that the first voltage domain (VB) has an upper voltage limit (VBoG) which is less than, equal to or greater than the voltage potential (VI) corresponding to the lower limit of the upper voltage domain (VD).

12. Electrical circuit arrangement according to one of claims 1 to 11, characterized in that the second contact point (on) is opposite the first contact point (op) on the intermediate storage device (latch).

13. Electrical circuit arrangement according to one of claims 1 to 12, characterized in that the current mirror comprises two transistors (T3, T4) connected to one another via their gate contacts, each having the same doping type.

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