Image sensor

Abstract

Image sensor The present description relates to an image sensor comprising a plurality of pixels (100) formed in and on a semiconductor substrate (104), each pixel comprising: – a photosensitive area (102) formed in the semiconductor substrate; – a storage area (110T, 110B) formed in the semiconductor substrate; and – a first transfer transistor (112T, 112B) between the photosensitive area and the storage area, in which the first transfer transistor comprises a gate (118) extending vertically in the semiconductor substrate, from an upper face of the semiconductor substrate, inside an isolation trench (106) delimiting the storage area. Figure for abstract: Fig. 1

Description

Title of the invention: Image sensor Technical field

[0001] The present description relates generally to electronic devices and, more particularly, to image sensors. Prior art

[0002] Image sensors are known, for example of the type described in patent application US2019086519, the pixels of which comprise a photosensitive zone, or detection zone, separated from at least one storage zone by a transfer transistor. Summary of the invention

[0003] There is a need to improve existing image sensors. In particular, it would be desirable to obtain image sensors with low sensitivity to parasitic light (PLS).

[0004] One embodiment overcomes all or part of the drawbacks of known image sensors.

[0005] One embodiment provides an image sensor comprising a plurality of pixels formed in and on a semiconductor substrate, each pixel comprising: - a photosensitive zone formed in the semiconductor substrate; - a storage area formed in the semiconductor substrate; and - a first transfer transistor between the photosensitive area and the storage area, in which the first transfer transistor comprises a gate extending vertically in the semiconductor substrate, from an upper face of the semiconductor substrate, inside an isolation trench delimiting the storage area.

[0006] According to one embodiment, the isolation trench is a capacitive isolation trench comprising a metallic region electrically isolated from the semiconductor substrate.

[0007] According to one embodiment, the gate of the first transfer transistor of each pixel is electrically isolated from the semiconductor substrate and the metal region.

[0008] According to one embodiment: - the metallic region is intended to be brought to a fixed potential; and - the gate is intended to be brought to a variable potential, a first level of which controls the setting of the first transfer transistor to the on state and a second level of which controls the setting of the first transfer transistor to the off state.

[0009] According to one embodiment, the gate is made of a metal or a metal alloy.

[0010] According to one embodiment, the grid is made of polycrystalline silicon.

[0011] According to one embodiment, the sensor is configured to evaluate distances by flight time.

[0012] According to one embodiment, the storage area is separated from the first transfer transistor by a second transfer transistor.

[0013] According to one embodiment, the second transfer transistor comprises a gate extending vertically in the semiconductor substrate, from the upper face of the semiconductor substrate, inside the isolation trench delimiting the storage zone.

[0014] One embodiment provides a method of controlling a sensor as described, the method comprising, for each pixel, the following steps: a) turn on the second transfer transistor; b) turning on the first transfer transistor; c) after steps a) and b), turning the first transfer transistor off; and d) after step c), turning the second transfer transistor off.

[0015] According to one embodiment, steps a) and b) are carried out simultaneously. Brief description of the drawings

[0016] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments and modes of implementation given without limitation in relation to the attached figures among which:

[0017] [Fig-1] [Fig.l] is a top view, schematic and partial, of a pixel of a image sensor according to a first embodiment;

[0018] [Fig.2] [Fig.2] is a schematic and partial sectional view of the pixel of [Fig.l] according to plane AA of [Fig.l];

[0019] [Fig.3] [Fig.3] is a schematic and partial sectional view of a variant of the pixel of [Fig.l] according to plane AA of [Fig.l];

[0020] [Fig.4] [Fig.4] is a graph illustrating a step of a control method of a pixel according to a first mode of implementation;

[0021] [Fig.5] [Fig.5] is a graph illustrating another step of the control method of a pixel according to the first mode of implementation;

[0022] [Fig.6] [Fig.6] is a graph illustrating yet another step in the process of control of a pixel according to the first mode of implementation;

[0023] [Fig.7] [Fig.7] is a top view, schematic and partial, of another variant of the pixel of [Fig.l];

[0024] [Fig.8] [Fig.8] is a schematic and partial top view of yet another variant of the pixel in [Fig.l];

[0025] [Fig.9] [Fig.9] is a schematic and partial top view of yet another variant of the pixel in [Fig.l];

[0026] [Fig. 10] [Fig. 10] is a top view, schematic and partial, of two pixels of the type of that exhibited in relation to [Fig.9];

[0027] [Fig. 11] [Fig. 11] is a schematic and partial top view of two pixels of the type shown in relation to [Fig.7];

[0028] [Fig. 12] [Fig. 12] is a schematic and partial top view of yet another variant of the pixel of [Fig.l];

[0029] [Fig. 13] [Fig. 13] is a schematic and partial top view of yet another variant of the pixel of [Fig.l];

[0030] [Fig. 14] [Fig. 14] is a schematic and partial top view of two pixels of the type shown in relation to [Fig. 13];

[0031] [Fig. 15] [Fig. 15] is a top view, schematic and partial, of a variant of the two pixels of [Fig. 14];

[0032] [Fig. 16] [Fig. 16] is a schematic and partial top view of a pixel of an image sensor according to a second embodiment;

[0033] [Fig. 17] [Fig. 17] is a graph illustrating a step of a method of controlling a pixel according to a second embodiment;

[0034] [Fig. 18] [Fig. 18] is a graph illustrating a step of a method of controlling a pixel according to a third embodiment;

[0035] [Fig. 19] [Fig. 19] is a top view, schematic and partial, of a variant of the pixel of [Fig. 16];

[0036] [Fig.20] [Fig.20] is a top view, schematic and partial, of another variant of the pixel in [Fig. 16];

[0037] [Fig.21] [Fig.21] is a top view, schematic and partial, of yet another another variant of the pixel of [Fig. 16];

[0038] [Fig.22] [Fig.22] is a top view, schematic and partial, of yet another another variant of the pixel of [Fig. 16]; and

[0039] [Fig.23] [Fig.23] is a top view, schematic and partial, of yet another another variant of the pixel in [Fig. 16]. Description of the embodiments

[0040] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments and modes of implementation may have the same references and may have identical structural, dimensional and material properties.

[0041] For the sake of clarity, only the steps and elements useful for understanding the embodiments and modes of implementation described have been shown and are detailed. In particular, the pixel control and reading circuits will not be detailed, the embodiments and modes of implementation described being compatible with the conventional pixel control and reading circuits, or the production of these circuits being within the reach of the person skilled in the art from the indications of this description.

[0042] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0043] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0044] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0045] In the present description, the term stray light sensitivity, or PLS, refers to a characteristic of an image sensor typically linked to an absorption of stray light in memory areas or pixel storage areas of the sensor (optical PLS) or to an untimely transfer, to these memory or storage areas, of carriers generated in a photoconversion area of ​​the pixels of the sensor (electrical PLS). In the case of high stray light sensitivity, the pixels of the sensor generally have a low signal-to-noise ratio.

[0046] [Fig.l] is a schematic and partial top view of an example of a pixel 100 of an image sensor according to a first embodiment. [Fig.2] is a schematic and partial sectional view of the pixel 100 along the plane AA of [Fig.l].

[0047] In the example shown, the pixel 100 comprises a photosensitive zone 102. The photosensitive zone 102 is for example intended to collect photons during illumination phases of the image sensor of which the pixel 100 is a part, and to convert these photons into electron-hole pairs. Seen from above, the photosensitive zone 102 is located at the center of the pixel 100 and has a substantially rectangular shape.

[0048] The photosensitive zone 102 is for example formed in a substrate 104. By way of example, the substrate 104 is a wafer or a piece of wafer made of a semiconductor material doped with a first conductivity type, for example made of N-type doped silicon. The substrate 104 has for example, at the location where the photosensitive zone 102 is formed, a doping rate of between 1 x 1014 at. / cm3 and 1 x 1016 at. / cm3.

[0049] The substrate 104 may further comprise, on the surface, a region doped with a second conductivity type, i.e. P type in this example. In this case, the substrate 104 has, for example, a surface doping of between 1 x 1018 at. / cm3 and 1 x 10 20 at. / cm3. The region of the substrate 104 doped with the second type of conductivity is for example brought to a reference potential VREF.

[0050] In the example shown, the pixel 100 further comprises a peripheral isolation trench 106, for example a capacitive isolation trench. The peripheral isolation trench 106 makes it possible, for example, to electrically isolate the photosensitive area 102 of the pixel 100 from the photosensitive areas of the neighboring pixels, not shown in [Fig. 1]. The peripheral isolation trench 106 is, for example, formed in the semiconductor substrate 104. As illustrated in [Fig. 2], the peripheral isolation trench 106 extends, for example, vertically in the thickness of the substrate 104 from an upper face 104T of the substrate 104.

[0051] The peripheral isolation trench 106 has, for example, a width W of between 50 nm and 400 nm. By way of example, the peripheral isolation trench 106 has a depth of between 1 pm and 20 pm.

[0052] Viewed from above, the peripheral isolation trench 106 surrounds the photosensitive zone 102. The peripheral isolation trench 106 has, for example, when viewed from above, a periphery of substantially rectangular or square shape. In the orientation of [Fig. 1], the peripheral isolation trench 106 more particularly comprises an upper horizontal portion 106T, a lower horizontal portion 106B, a left vertical portion 106L and a right vertical portion 106R. In the example shown, the portions 106T, 106B, 106L and 106R each correspond to one of the four sides of the rectangle or square formed by the peripheral isolation trench 106. The left vertical portions 106L and right vertical portions 106R of the peripheral isolation trench 106 longitudinally delimit the photosensitive zone 102.

[0053] In the example shown, the peripheral isolation trench 106 further comprises two other horizontal portions 108T and 108B. As illustrated in [Fig.l], the portions 108T and 108B are interposed between the upper 106T and lower 106B horizontal portions. In the example shown, the portions 108T and 108B extend horizontally in the substrate 104, from the right vertical portion 106R of the trench 106, towards the left vertical portion 106L of the trench 106. The portions 108T and 108B are for example parallel to each other, and parallel to the horizontal portions 106T and 106B of the trench 106.

[0054] In the example shown, the parts 108T and 108B extend vertically in the thickness of the substrate 104 from its upper face 104T. The parts 108T and 108B have, for example, a depth similar to that of the parts 106T, 106B, 106L and 106R. In the example shown, the parts 108T and 108B of the trench 106 transversely delimit the photosensitive zone 102.

[0055] In top view, the ends of the parts 108T and 108B located opposite the part 106L are for example each separated from the part 106L by a distance LL For example, the distance L1 is between 50 nm and 400 nm, for example of the order of 260 nm. The part 108T is for example separated from the part 106T by a distance L2. For example, the distance L2 is between 50 nm and 400 nm. The part 108B is for example separated from the part 106B by the distance L2.

[0056] In the example shown, the peripheral insulation trench 106 comprises an electrically conductive region 106C. For example, the electrically conductive region 106C is made of polycrystalline silicon, a metal, for example copper, or a metal alloy.

[0057] In the example shown, the peripheral insulation trench 106 further comprises an electrically insulating layer 1061 coating the side walls and the lower face of the electrically conductive region 106C, and electrically insulating the region 106C from the substrate 104. By way of example, the electrically insulating layer 1061 is made of a dielectric material, for example silicon oxide.

[0058] In the example shown, the electrically conductive region 106C and the electrically insulating layer 1061 are common to the parts 106T, 106B, 106L, 106R, 108T and 108B of the peripheral insulation trench 106.

[0059] The electrically conductive region 106C of the trench 106 can be polarized. In the case where the substrate 104 is of type N, the region 106C is for example brought to a fixed potential V0, for example equal to approximately 3.5 V. This tends to cause an accumulation of holes along the side walls of the trench 106. This accumulation of holes makes it possible in particular to prevent photogenerated holes in the zone 102 from being trapped at the interface between the substrate 104 and the trench 106.

[0060] In the example shown, the pixel 100 further comprises a first charge storage area or memory area 110T and a second charge storage area or memory area 110B. The first storage area 110T is interposed between the parts 106T and 108T of the peripheral isolation trench 106, while the second storage area 110B is interposed between the parts 106B and 108B of the peripheral isolation trench 106.

[0061] The storage areas 110T and 110B of the pixel 100 are, for example, portions of the substrate 104 doped with the first conductivity type. For example, the storage areas 110T and 110B have a doping rate of between 1 x 1016 at. / cm3 and 1 x 1019 at. / cm3.

[0062] In the example shown, the pixel 100 further comprises first transfer transistors (which may also be called first transfer gates) 112T and 112B. The first transfer transistors 112T and 112B of the pixel 100 make it possible in particular to control lateral charge transfers from the photosensitive zone 102 to the storage zones 110T and 110B. The transfer transistor 112T comprises a portion 114T, formed at the corner of the peripheral isolation trench 106 where the parts 106L and 106T, and another part 116T, formed at the end of the part 108T located opposite the part 106L. Similarly, the transfer transistor 112B comprises a part 114B, formed at the corner of the peripheral isolation trench 106 where the parts 106L and 106B intersect, and another part 116B, formed at the end of the part 108B located opposite the part 106L.

[0063] The portions 116T and 116B extend respectively along the portions 108T and 108B over a distance L3. For example, the distance L3 is substantially equal to the width W of the peripheral isolation trench 106.

[0064] In the orientation of [Fig.l], the portion 114T of the transfer transistor 112T extends vertically, within the portion 106L, from the upper left corner of the trench 106 to the level of the lower horizontal edge of the portion 108T. Furthermore, the portion 114T of the transfer transistor 112T extends horizontally, within the portion 106T, from the upper left corner of the trench 106 to the level of the right vertical edge of the portion 116T of the transfer transistor 112T.

[0065] Similarly, portion 114B of transfer transistor 112B extends vertically, within portion 106L, from the lower left corner of trench 106 to the level of the upper horizontal edge of portion 108B. Furthermore, portion 114B of transfer transistor 112B extends horizontally, within portion 106B, from the lower left corner of trench 106 to the level of the right vertical edge of portion 116B of transfer transistor 112B.

[0066] By way of example, the transfer transistors 112T and 112B are respectively separated from the storage areas 110T and 110B by a distance of between 50 nm and 300 nm. The parts 114T and 116T of the transfer transistor 112T and the parts 114B and 116B of the transfer transistor 112B are each separated by a portion of substrate 104, called the transfer region or channel of the transistor 112T, respectively 112B, having for example an N-type doping rate of between 1 x 1016 at. / cm3 and 1 x 1019 at. / cm3.

[0067] In the example shown, the parts 114T and 116T of the transfer transistor 112T and the parts 114B and 116B of the transfer transistor 112B each comprise a region 118 formed in the peripheral isolation trench 106. The region 118 extends vertically in the thickness of the peripheral isolation trench 106 from the upper face 104T of the substrate 104. The region 118 forms a gate of each transfer transistor 112T, 112B. Seen in section, the region 118 has for example a height of between 0.2 μm and 1.5 μm. For example, the region 118 is made of a metal or a metal alloy, for example copper. Alternatively, the region 118 is made of doped polycrystalline silicon.

[0068] In the example shown, the region 118 is electrically insulated with respect to the conductive region 106C of the peripheral insulation trench 106 and with respect to the substrate 104. More precisely, the sides of the region 118 are for example bordered by the insulating layer 1061 of the peripheral insulation trench 106 and by an electrically insulating layer 120. In the example shown, the layer 120 further covers the lower face of the region 118. By way of example, the electrically insulating layer 120 is made of a dielectric material, for example silicon oxide.

[0069] The regions 118 of each part 114T, 116T, 114B, 116B of the same transfer transistor 112T, 112B are for example equivalent to plates of a metal-oxide semiconductor capacitor, or MOS capacitor.

[0070] In the example shown, the pixel 100 further comprises second transfer transistors (which may also be called second transfer gates) 122T and 122B. The transfer transistors 122T and 122B each comprise a planar conductive gate formed on the upper face 104T of the substrate 104 and insulated from the substrate 104 by a dielectric layer. In the example shown, the second transfer transistor 122T separates the first storage area 110T from a first read node 124T. Similarly, the second transfer transistor 122B separates the second storage area 110B from a second read node 124B. The transfer transistors 122T, 122B of the pixel 100 respectively allow charge transfers to be controlled from the storage areas 110T, 110B to the reading nodes 124T, 124B.

[0071] For example, the reading nodes 124T and 124B have a doping rate higher than that of the storage areas 110T and 110B.

[0072] The areas of the substrate 104 not forming part of the photosensitive area 102 may be coated with a screen layer (not shown) made of an opaque material, for example a metal. More specifically, the first transfer transistors 112T and 112B, the storage areas 110T and 110B, the second transfer transistors 122T and 122B and the reading nodes 124T and 124B may be coated with the screen layer. This limits undesirable photogeneration of charges outside the photosensitive area 102.

[0073] As illustrated in [Fig.2], electrodes 126 may be formed on the surface of each electrically conductive region 118. The electrodes 126 make it possible, for example, to bias the electrically conductive regions 118 independently of the electrically conductive region 106C. In addition, the electrodes 126 make it possible to control the bias of the gate of the transfer transistor 112T independently of that of the gate of the transfer transistor 112B.

[0074] The electrodes 126 make it possible in particular to control an on or off state of each transfer transistor 112T, 112B. The electrodes 126 make it possible, for example, to apply a variable potential to the gate of each transfer transistor 112T, 112B, a first level VOn of which controls switching to the on state. of the transfer transistor 112T, 112B and of which a second level V0Ef controls a switching towards the blocked state of the transfer transistor 112T, 112B. The potentials V on and Voff are defined with respect to the doping of the substrate 104 and with respect to the reference potential VREf applied in the surface region of the substrate 104 doped with the second type of conductivity.

[0075] When the electrodes 126 of the transfer transistor 112T, 112B are brought to the potential V0Ff, this makes it possible to create a potential barrier in the transfer region, that is to say in the part of the substrate 104 located between the two vertical gate portions of this transfer transistor. The potential barrier, which extends vertically in the thickness of the substrate 104, then tends to prevent the collection, by the storage zone 110T, 110B, of the photogenerated carriers in the photosensitive zone 102.

[0076] On the other hand, when the electrodes 126 of the transfer transistor 112T, 112B are brought to the potential V0N, this makes it possible to lower the potential barrier created in the transfer region. The carriers photogenerated in the photosensitive area 102 can then be transferred from the photosensitive area 102 in order to be collected by the storage area 110T, 110B.

[0077] In the example shown, the transfer of the photogenerated carriers into the substrate 104 via the vertical transfer transistors 112T, respectively 112B is a predominantly horizontal transfer. In other words, the transfer of the photogenerated carriers into the substrate 104 takes place at a substantially constant depth.

[0078] The pixel 100 may comprise other elements not shown in FIGS. 1 and 2. By way of example, the pixel 100 may in particular comprise a reset circuit and an anti-glare circuit.

[0079] The sensor of which the pixel 100 is a part is, for example, a sensor configured to evaluate distances by time of flight (ToF). This sensor comprises, for example, a light source, for example a laser, intended to illuminate a scene. The light source emits, for example, a periodic light signal LE, for example a sinusoidal or square wave signal, in the direction of the scene. In a case where the light signal LE is reflected in the direction of the sensor by an object in the scene, a light signal LR is, for example, received by the pixel 100. The light signal Lr has, for example, a phase shift q> relative to the light signal LE emitted by the source. The evaluation of the phase shift q> makes it possible to calculate the time of flight, which can then be converted into an estimate of the distance of the object relative to the sensor.

[0080] In order to measure the phase shift q>, it is possible, for example, to sample the LR signal by transferring, alternately and at regular intervals, photogenerated charges in the photosensitive zone 102 to the storage zones 110T and 110B. For example, it is ensured that the total duration for carrying out at least three successive transfers is equal to one period of the LE and LR signals. For this, it is possible, for example, to capture two successive images using pixel 100, or simultaneously using pixel 100 and another pixel having two storage areas, for example a pixel similar to pixel 100. These successive transfers are for example repeated a large number of times, for example at least 100,000 times. The charges accumulated in the storage area 110T are then for example read by transferring, to the node 124T, the charges from the area 110T. Similarly, the charges accumulated in the storage area 110B are for example read by transferring, to the node 124B, the charges from the area 110B.

[0081] An advantage of the pixel 100 is that the electrically conductive region 106C of the peripheral isolation trench 106 provides an optical isolation function. More specifically, the electrically conductive region 106C provides optical isolation of the photosensitive area 102 of the pixel 100 from the photosensitive areas of neighboring pixels, not shown in [Fig.l]. The electrically conductive region 106C also provides optical isolation of the photosensitive area 102 from the storage areas 110T and 110B. This prevents the appearance of photogenerated charges in the storage areas 110T and 110B of the pixel 100, which would impair the operation of the sensor.In the case where the electrically conductive region 106C is made of a metal or a metal alloy, the pixel 100 notably has a lower optical PLS than that of existing pixels which have polycrystalline silicon isolation trenches, by more effectively blocking the light reaching the pixel 100 under oblique incidence.

[0082] For example, the transfer transistors 112T and 112B are designed to have dimensions smaller than the detection wavelength by the read nodes 124T and 124B. This makes it possible to further reduce the optical PLS of the pixel 100.

[0083] Another advantage of the pixel 100 lies in the fact that the polarization of the transfer transistor 112T, 112B by the electrode 126 makes it possible to form, in the thickness of the substrate 104, an inversion layer causing a high potential barrier to appear over the entire height of the transfer transistor. The transfer transistors 112T and 112B notably allow more effective blocking of the photogenerated carriers than that which would be obtained, for example, with transfer transistors formed on the surface 104T of the substrate 104. This thus produces a pixel 100 having a lower electrical PLS than in the case of a pixel which would have transfer transistors formed on the surface of the substrate 104.

[0084] [Fig.3] is a schematic and partial sectional view of a variant of pixel 100 of [Fig.l].

[0085] The pixel of [Fig. 3] comprises elements in common with pixel 100 of Figures 1 and 2. These common elements will not be detailed again below. The pixel of [Fig. 3] differs from pixel 100 of Figures 1 and 2 mainly in that, in the pixel of [Fig.3], the electrically conductive region 118 is not flush with the upper face 104T of the substrate 104.

[0086] In the example shown, the upper face of the region 118 is coated with an electrically insulating layer 302. The layer 302 is for example made of a dielectric material, for example silicon oxide. The electrodes 126 pass through the electrically conductive layer 302 to contact the upper face of the region 118.

[0087] An advantage of this variant lies in the fact that the electrically conductive regions 118 located on either side of the transfer region have a smaller surface area than in the pixel 100 of FIGS. 1 and 2. This provides, for example, a transfer transistor having an electrical capacitance lower than that of the transfer transistor 112T of the pixel 100. This makes it possible, for example, to apply higher switching frequencies to the transfer transistor 112T than in the case of the pixel 100.

[0088] Another advantage of the variant illustrated in [Fig.3] lies in the fact that the electrically insulating layer 302 acts as a surface passivation layer. This allows in particular a reduction of dark current.

[0089] Figures 4 to 6 illustrate successive steps of an example of a first mode of implementation of a method for controlling a pixel, for example pixel 100 of [Fig.l],

[0090] [Fig.4] is a graph illustrating a step of the method for controlling the pixel 100 of [Fig.l] according to the first embodiment. The graph of [Fig.4] illustrates more particularly, by a curve 400, an example of variation of electrostatic potential V along the section plane BB of [Fig.l].

[0091] Curve 400 includes: - a portion 402 corresponding to the inversion layer formed along the walls of the peripheral isolation trench 106; - a portion 404 corresponding to the photosensitive zone 102; - portions 406, 408 and 410 corresponding to regions of an elbow-shaped channel located between the parts 114T and 116T of the transfer transistor 112T, the potential difference between the portions 406, 408 and 410 being obtained by adjusting doping profiles of these regions and / or the geometry of the transfer transistor 112T (distance between the regions 118); - a portion 412 corresponding to the storage area 110T; - a portion 414 corresponding to the planar transfer transistor 122T; and - a portion 416 corresponding to the reading node 124T.

[0092] More precisely, in the example shown: - portion 406 corresponds to an area of ​​the substrate 104 located between the end of the part 108T and the left vertical part 106L of the peripheral insulation trench 106, that is to say to a first part of the elbow-shaped channel located at the input of the transfer transistor 112T; - portion 408 corresponds to another zone of the substrate 104 located between the part 116T and the elbow located in the upper left corner of the trench 106, that is to say to a second part of the elbow-shaped channel; and - portion 410 corresponds to yet another area of ​​the substrate 104 located between the part 116T of the transfer transistor 112T and the upper horizontal part 106T of the peripheral isolation trench 106, i.e. to a third part of the elbow-shaped channel located at the output of the transfer transistor 112T.

[0093] [Fig.4] illustrates more particularly a step of the pixel control method 100 in which charges, here holes symbolized by circles, are photo-generated in the photosensitive area 102. In the example shown, the transfer transistor 112T is in the blocked state. The transfer transistor 112T forms for example a potential barrier preventing the holes from being transferred from the photosensitive area 102 to the storage area 110T of the pixel 100.

[0094] [Fig.5] is a graph illustrating another step in the control method of the pixel 100 according to the first implementation mode.

[0095] [Fig.5] illustrates more particularly a step of the pixel control method 100 in which the charges are transferred from the photosensitive area 102 towards the storage area 110T. In the example shown, the transfer transistor 112T is in the on state. The holes are then, for example, transferred from the photosensitive area 102 towards the elbow of the transfer transistor 112T, symbolized by the portion 408 of the curve 400.

[0096] [Fig.6] is a graph illustrating yet another step in the process of control of pixel 100 according to the first implementation mode.

[0097] [Fig.6] illustrates more particularly a step of the pixel control method 100 in which the charges are transferred from the transfer transistor 112T to the storage area 110T. In the example shown, the transfer transistor 112T is in the off state. The holes are then, for example, transferred from the elbow of the transfer transistor 112T to the storage area 110T.

[0098] Although not shown, other steps, for example transfer from the storage area 110T to the reading node 124T, may then take place.

[0099] [Fig.7] is a schematic and partial top view of another variant of the pixel 100 of [Fig.l].

[0100] In the variant illustrated in [Fig.7], the portion 114T of the transfer transistor 112T extends horizontally, inside the portion 106T, from the upper left corner of the trench 106 to the vertical left edge of the portion 116T of the transfer transistor 112T. Unlike the pixel 100 of [Fig.l], the portion 114T of the transfer transistor 112T of the pixel illustrated in [Fig.7] does not extend to the vertical right edge of the part 116T.

[0101] [Fig.8] is a schematic and partial top view of yet another variant of pixel 100 of [Fig.1].

[0102] In the variant illustrated in [Fig.8], the portion 114T of the transfer transistor 112T extends vertically, inside the portion 106L, from the upper left corner of the trench 106 to the level of the lower horizontal edge of the portion 108T. Unlike the pixel 100 of [Fig.l], the portion 114T of the transfer transistor 112T of the pixel illustrated in [Fig.8] does not extend horizontally inside the portion 106T.

[0103] [Fig.9] is a schematic and partial top view of yet another variant of pixel 100 of [Fig.l].

[0104] In the variant illustrated in [Fig.9], the portion 114T of the transfer transistor 112T extends horizontally, inside the portion 106T, from the upper left corner of the trench 106 to the level of the right vertical edge of the portion 116T. Unlike the pixel 100 of [Fig.l], the portion 114T of the transfer transistor 112T of the pixel illustrated in [Fig.9] does not extend vertically inside the portion 106L.

[0105] [Fig. 10] is a schematic and partial top view of two pixels of the type shown in relation to [Fig.9].

[0106] In the example shown, the two pixels are juxtaposed so that they share a common vertical portion 106V of the peripheral isolation trench 106. The left pixel is for example symmetrical to the right pixel with respect to the vertical portion 106V. This makes it possible to reduce the surface area occupied by the pixels. In the orientation of [Fig. 10], with reference to the pixel of [Fig. 9], the portion 106V corresponds to the portion 106L of the left pixel and to the portion 106L of the right pixel.

[0107] [Fig. 11] is a schematic and partial top view of two pixels of the type shown in relation to [Fig.7].

[0108] In the example shown, the two pixels are juxtaposed so that they share a common horizontal portion 106H of the peripheral isolation trench 106. This makes it possible to reduce the surface area occupied by the pixels. In the orientation of [Fig.l 1], with reference to the pixel of [Fig.7], the portion 106H corresponds to the portion 106B of the top pixel and to the portion 106T of the bottom pixel. In the example shown, the portions 114T and 114B of the transfer transistors 112T and 112B of the pixels share a common metal region 118.

[0109] [Fig. 12] is a schematic and partial top view of yet another variant of pixel 100 of [Fig.l].

[0110] In the example shown, the portion 114T of the transfer transistor 112T extends into the substrate 104 from the upper horizontal portion 106T of the trench peripheral isolation trench 106. More specifically, the portion 114T forms a protrusion penetrating for example into the substrate 104 in a manner substantially perpendicular to the upper horizontal portion 106T. In the example shown, the portion 116T of the transfer transistor 112T extends into the substrate 104 from the left vertical portion 106L of the peripheral isolation trench 106. More specifically, the portion 116T forms a protrusion penetrating for example into the substrate 104 in a manner substantially perpendicular to the left vertical portion 106L. The portions 114T and 116T of the transfer transistor 112T separate the photosensitive area 102T from the read node 124T, formed in the upper left corner of the pixel 100 in this example.

[0111] [Fig. 13] is a schematic and partial top view of yet another variant of pixel 100 of [Fig. 1].

[0112] In the example shown, the portions 114T and 116B of the transfer transistor 112T extend into the substrate 104 from the upper horizontal portion 106T of the peripheral isolation trench 106. More precisely, the portions 114T and 116B each form a protrusion penetrating for example into the substrate 104 substantially perpendicularly to the upper horizontal portion 106T. The portions 114T and 116T of the transfer transistor 112T separate the photosensitive area 102T from the read node 124T, formed in an upper central area of ​​the pixel 100 in this example.

[0113] In the examples illustrated in Figures 12 and 13, the photogenerated charges are transferred directly from the photosensitive area to the reading node 124T by the vertical transfer transistor 112T, without intermediate storage in a memory area. In other words, compared to the example of [Fig.l], the memory area 110T (respectively 110B) and the planar transfer transistor 122T (respectively 122B) are eliminated. These variants correspond for example to a case where the pixel 100 implements voltage storage. In this case, the reading node 124T corresponds to a storage area of ​​the pixel.

[0114] Although this is not shown in figures 12 and 13, an additional capacity can for example be added on each reading node 124T in order to give the pixel 100 a greater dynamic range.

[0115] [Fig. 14] is a schematic and partial top view of two pixels of the type shown in relation to [Fig. 13].

[0116] In the example shown, the two pixels are juxtaposed in a manner analogous to what was previously explained in relation to [Fig. 10], that is to say so that they share the common vertical part 106V of the peripheral isolation trench 106. In the orientation of [Fig. 14], with reference to the pixel of [Fig. 13], the part 106V corresponds to the part 106R of the left pixel and to the part 106L of the right pixel.

[0117] In the example shown, the transfer transistors 112T of the two pixels have a common part 114C. The part 114C is formed in the vertical part 106V of the peripheral isolation trench 106. In this example, the pixels share a common gate 118. On either side of the part 114C are formed parts 116L and 116R of the transfer transistors 112T, similar to the part 116T previously described in relation to [Fig. 13]. The parts 114C, 116L and 116R are for example parallel to each other. In this case, the transfer transistors 112T of the two adjacent pixels are for example driven synchronously.

[0118] In the orientation of [Fig.14], the reading node 124T of the left pixel is separated from the photosensitive area 102 by a channel delimited by the parts 116L and 114C of its transfer transistor 112T. Similarly, the reading node 124T of the right pixel is separated from the photosensitive area 102 by another channel delimited by the parts 114C and 116R of its transfer transistor 112T.

[0119] The part 114C common to the two adjacent pixels makes it possible in particular to provide a larger photosensitive zone 102 than in a case, for example, where the pixels would be juxtaposed without a common part 114C. This increases the sensitivity of the sensor.

[0120] [Fig. 15] is a schematic and partial top view of a variant of the two pixels of [Fig. 14].

[0121] Compared to the pixels of [Fig. 15], the portions 116L and 116R of the transfer transistors 112T of the two pixels penetrate further into the substrate 104 towards the center of the photosensitive area 102. This allows more efficient blocking of the carriers between the photosensitive area 102 and the read nodes 124T.

[0122] The pixels described above in relation to Figures 12 to 15 are, for example, part of a global shutter sensor or a time-of-flight distance sensor.

[0123] [Fig. 16] is a schematic and partial top view of an example of a pixel 1300 of an image sensor according to a second embodiment. The pixel 1300 of [Fig. 16] comprises elements in common with the pixel 100 of [Fig. 1]. These common elements will not be detailed again below. The pixel 1300 of [Fig. 16] differs from the pixel 100 of [Fig. 1] mainly in that the pixel 1300 comprises, in addition to the first transfer transistors 112T and 112B, third transfer transistors (which may also be called third transfer gates) 1302T and 1302B. The transfer transistors 1302T and 1302B are vertical transistors similar to the transistors 112T, respectively 112B described previously.

[0124] The third transfer transistors 1302T and 1302B of the pixel 1300 make it possible in particular to improve the control of charge transfers from the photosensitive zone 102 to the storage zones 110T and 110B. The transfer transistor 1302T comprises a portion 1304T, formed in the upper horizontal portion 106T of the peripheral isolation trench 106, and another portion 1306T, formed in the portion 108T. Similarly, the transfer transistor 1302B comprises a portion 1304B, formed in the lower horizontal portion 106B of the peripheral isolation trench 106, and another portion 1306B, formed in the portion 108B.

[0125] In the orientation of [Fig. 16], the portion 1304T of the transfer transistor 1302T extends horizontally, inside the portion 106T, from directly above the left vertical edge of the portion 116T of the first transfer transistor 112T to directly above the right vertical edge of the portion 1306T of the third transfer transistor 1302T. Similarly, the portion 1304B of the transfer transistor 1302B extends horizontally, inside the portion 106B, from directly above the left vertical edge of the portion 116B of the first transfer transistor 112B to directly above the right vertical edge of the portion 1306B of the third transfer transistor 1302B.

[0126] Furthermore, in the example shown, the portion 114T of the transfer transistor 112T extends vertically, inside the portion 106L, from the level of the upper horizontal edge of the portion 108T to the level of the lower horizontal edge of the portion 108T. Similarly, the portion 114B of the transfer transistor 112B extends vertically, inside the portion 106L, from the level of the upper horizontal edge of the portion 108B to the level of the lower horizontal edge of the portion 108B.

[0127] In the example shown, the portion 116T of the first transfer transistor 112T is separated from the portion 1306T of the third transfer transistor 1302T by a distance L4. For example, the distance L4 is between 50 nm and 300 nm. The portion 116B of the first transfer transistor 112B is for example separated from the portion 1306B of the third transfer transistor 1302B by the distance L4.

[0128] In the example shown, the first transfer transistors 112T, 112B have a smaller surface area than the third transfer transistors 1302T, 1302B. This makes it possible, for example, to switch the first transfer transistors 112T, 112B between the on state and the off state at a switching frequency higher than that of the third transfer transistors 1302T, 1302B.

[0129] [Fig. 17] is a graph illustrating a step of a method of controlling a pixel, for example pixel 1300 of [Fig. 16], according to a second embodiment.

[0130] In the example shown: - portions 402, 404, 412, 414, 416 are unchanged from what was previously explained in relation to figures 4 to 6; - portion 406 corresponds to a region of the substrate 104 located between the vertical gates 118 of the first transfer transistor 112T; - portion 408 corresponds to a region of the substrate 104 located between the vertical gates 118 of the third transfer transistor 1302T; and - portion 410 corresponds to a region of the substrate 104 located between the third transfer transistor 1302T and the storage area 110T.

[0131] During the first steps of this method, the first transfer transistor 112T and the third transfer transistor 1302T are turned on. The third transistor 1302T is for example assumed to be on at the time the first transfer transistor 112T is turned on. For example, the first and third transfer transistors 112T, 1302T are turned on simultaneously. A potential curve similar to that of [Fig. 5] is then obtained. The method then continues with the step illustrated in [Fig. 17].

[0132] [Fig. 17] illustrates more particularly a step of the control method of the pixel 1300 in which charges are transferred from the first transfer transistor 112T to the third transfer transistor 1302T. During this step, the first transfer transistor 112T is in the off state and the third transfer transistor 1302T is kept in the on state.

[0133] After this step, the transfer transistor 1302T is controlled to the blocked state (the transistor 112T being kept blocked). The photogenerated charges are thus transferred into the storage zone 110T. This gives a potential curve similar to that of [Fig.6].

[0134] The second mode of implementation corresponds to a case in which: - the first transfer transistor 112T and the third transfer transistor 1302T are driven synchronously; - the first transfer transistor 112B and the third transfer transistor 1302B are driven synchronously; and - the transfer transistors 112T and 1302T can be driven asynchronously with respect to the transfer transistors 112B and 1302B.

[0135] In this embodiment, the first transfer transistors 112T, 112B and the third transfer transistors 1302T, 1302B are turned on, for example simultaneously, during the same step.

[0136] [Fig. 18] is a graph illustrating a step of a method of controlling a pixel, for example pixel 1300 of [Fig. 16], according to a third mode of implementation.

[0137] The first step of this method is for example analogous to that previously described in relation to [Fig.4]. During this first step, the first transfer transistor 112T and the third transfer transistor 1302T are kept in the blocked state.

[0138] [Fig. 18] illustrates more particularly another step of the control method of pixel 1300, in which the third transfer transistor 1302T is in the on state (leading to lowering the potential of region 408) while the first transfer transistor 112T is kept in the off state. In the example shown, the photogenerated charges are contained in the photosensitive area 102.

[0139] After this step, the transfer transistor 112T is controlled to the on state (the transistor 1302T being kept on). A potential curve similar to that of [Fig. 5] is then obtained. Then, the process continues in a manner identical or similar to that described above in relation to [Fig. 17].

[0140] The third embodiment corresponds to a case in which the first transfer transistors 112T, 112B and the third transfer transistors 1302T, 1302B are driven asynchronously. In this embodiment, the switching on and off of the third transfer transistors 1302T, 1302B are for example out of phase with respect to the switching on and off of the first transistors 112T, 112B.

[0141] An advantage of the third embodiment lies in the fact that it makes it possible to transfer charges from the photosensitive zone 102 to one of the storage zones 110T, 110B while the transfer to the other storage zone 110B, 110T is not yet complete.

[0142] [Fig. 19] is a schematic and partial top view of a variant of pixel 1300 of [Fig. 16],

[0143] In the variant illustrated in [Fig.19], the portion 114T of the transfer transistor 112T extends horizontally, inside the portion 106T, from the upper left corner of the trench 106 to the vertical right edge of the portion 116T. In the example shown, the portion 1304T of the transfer transistor 1302T extends horizontally, inside the portion 106T, from the vertical left edge of the portion 1306T to the vertical right edge of the portion 1306T.

[0144] [Fig.20] is a schematic and partial top view of another variant of pixel 1300 of [Fig. 16].

[0145] In the variant illustrated in [Fig.20], the portion 114T of the transfer transistor 112T extends vertically, inside the portion 106L, from the level of the upper horizontal edge of the portion 108T to the level of the lower horizontal edge of the portion 108T. In the example shown, the portion 1304T of the transfer transistor 1302T extends horizontally, inside the portion 106T, from the upper left corner of the peripheral isolation trench 106 to the level of the right vertical edge of the portion 1306T.

[0146] [Fig. 21] is a schematic and partial top view of yet another variant of pixel 1300 of [Fig. 16].

[0147] In the variant illustrated in [Fig.21], the part 114T of the transfer transistor 112T extends horizontally, inside the portion 106T, from directly above the left vertical edge of the portion 116T to the level of the right vertical edge of the portion 116T. In the example shown, the portion 1304T of the transfer transistor 1302T extends horizontally, inside the portion 106T, from directly above the left vertical edge of the portion 1306T to directly above the right vertical edge of the portion 1306T.

[0148] [Fig. 22] is a schematic and partial top view of yet another variant of pixel 1300 of [Fig. 16].

[0149] In the variant illustrated in [Fig.21], the portion 114T of the transfer transistor 112T extends vertically, inside the portion 106L, from the level of the upper horizontal edge of the portion 108T to the level of the lower horizontal edge of the portion 108T. In the example shown, the portion 1304T of the transfer transistor 1302T extends horizontally, inside the portion 106T, from directly above the right vertical edge of the portion 116T to directly above the right vertical edge of the portion 1306T.

[0150] [Fig. 23] is a schematic and partial top view of yet another variant of the pixel 1300 of [Fig. 16]. The variant illustrated in [Fig. 23] corresponds, for example, to a case analogous to the variants set out in relation to [Fig. 12], in which the pixel 1300 implements voltage storage.

[0151] In the example shown, the portions 106T and 106B of the peripheral isolation trench 106 do not extend horizontally to intersect the portion 106R. The portions 106T and 106B are respectively connected to the portions 108T and 108B by vertical portions 2000T and 2000B. The portions 2000T and 2000B are for example perpendicular to the portions 108T and 108B. In this example, the memory areas 110T and 110B and the planar transfer transistors 122T and 122B are omitted.

[0152] Various embodiments, implementations, and variations have been described. Those skilled in the art will understand that certain features of these various embodiments, implementations, and variations could be combined, and other variations will occur to those skilled in the art. In particular, the variations discussed in connection with Figures 10 and 11 may be combined. Furthermore, the variations of pixel 100 discussed in connection with Figures 7 to 11 may be adapted to the embodiment of pixel 1300 of [Fig. 16] and the variations described in connection with Figures 19 to 23.

[0153] Although examples of application to a time-of-flight distance measurement sensor have been described above, the embodiments and implementations described can be transposed by a person skilled in the art to other types of sensors, for example sensors comprising a single 110T or 124T storage area, for example global shutter sensors. In addition, a person skilled in the art is able to adapt the above embodiments and implementation methods to conductivity types opposite to those described.

[0154] Finally, the practical implementation of the embodiments, implementation modes and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the person skilled in the art is capable of adapting the number, position and surface area of ​​the vertical transfer transistors according to the intended application.

Claims

Claims

1. An image sensor comprising a plurality of pixels (100; 1300) formed in and on a semiconductor substrate (104), each pixel comprising: - a photosensitive area (102) formed in the semiconductor substrate; - a storage area (110T, 110B; 124T, 124B) formed in the semiconductor substrate; and - a first transfer transistor (112T, 112B) between the photosensitive area and the storage area;and - a capacitive isolation trench (106) comprising an electrically conductive region (106C), delimiting the storage area, and a first electrically insulating layer (1061), coating the side walls and the lower face of the electrically conductive region (106C) and electrically insulating the electrically conductive region (106C) from the substrate (104), wherein the first transfer transistor comprises a gate (118) extending vertically in the semiconductor substrate, from an upper face (104T) of the semiconductor substrate, inside the capacitive isolation trench (106), the sides of the gate (118) being bordered by the first electrically insulating layer (1061) and by a second electrically insulating layer (120), the second electrically insulating layer (120) further coating the lower face of the gate (118).;

2. Sensor according to claim 1, in which: - the conductive region (106C) is intended to be brought to a fixed potential (V0); and - the gate (118) is intended to be brought to a variable potential, a first level (Von) of which controls the setting to the on state of the first transfer transistor (112T, 112B) and a second level (V0FF) of which controls the setting to the off state of the first transfer transistor.

3. A sensor according to claim 1 or 2, wherein the grid (118) is made of a metal or a metal alloy.

4. A sensor according to claim 1 or 2, wherein the grid (118) is made of polycrystalline silicon.

5. A sensor according to any one of claims 1 to 4, configured to evaluate distances by time of flight.

6. A sensor according to any one of claims 1 to 5, wherein the storage area (110T, 110B; 124T, 124B) is separated from the first transfer transistor (112T, 112B) by a second transfer transistor (1302T, 1302B).

7. Sensor according to claim 6, in which the second transfer transistor (1302T, 1302B) comprises a gate (118) extending vertically in the semiconductor substrate (104), from the upper face (104T) of the semiconductor substrate, inside the isolation trench (106) delimiting the storage zone (110T, 110B; 124T, 124B).

8. A method of controlling a sensor according to claim 6 or 7 comprising, for each pixel (1300), the following steps: a) putting the second transfer transistor (1302T, 1302B) in the on state; b) putting the first transfer transistor (112T, 112B) in the on state; c) after steps a) and b), putting the first transfer transistor (112T, 112B) in the off state; and d) after step c), putting the second transfer transistor (1302T, 1302B) in the off state.

9. A method according to claim 8, wherein steps a) and b) are carried out simultaneously.

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