Electronic device comprising two high electron mobility transistors

Abstract

The invention relates to an electronic device comprising a HEMT transistor, referred to as the main transistor, and at least one other HEMT transistor, referred to as the additional transistor, stacked one on top of the other. The main transistor and the additional transistor comprise a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged such that electrical conduction paths that can be formed by the two conduction layers are connected in parallel when both HEMT transistors are in the on state. Figure 2a

Description

Title of the invention: Electronic device comprising two high-electron-mobility transistors FIELD OF INVENTION

[0001] The invention relates to the field of electronics, and in particular to power electronics. More specifically, the present invention relates to an electronic device provided with two high electron mobility transistors.

[0002] The device according to the present invention is in particular arranged to allow better integration of the two high electronic mobility transistors.

[0003] The arrangement provided in the present invention makes it possible in this respect to obtain a compact device and to increase the current density capable of passing through said device with regard to a single high electronic mobility transistor. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0004] High electron mobility transistors (HEMTs), well known to those skilled in the art, are now widely used in the field of microwaves and in the field of switches for power electronics converters.

[0005] In this regard, these HEMT transistors are generally made from layers of IILV semiconductor materials and more particularly from IIILN semiconductor materials.

[0006] In particular, [Fig. 1] represents a HEMT transistor 10 known in the prior art. This HEMT transistor 10 is provided with a stack 13 which comprises, from a front face 11 to a rear face 12, an insulating layer 14, a barrier layer 15, and a channel layer 16 capable of forming a conduction layer 16a in the form of a two-dimensional electron gas layer. In particular, the conduction layer 16a extends into the channel layer 16 from an interface 15a, formed between the barrier layer 15 and said channel layer 16.

[0007] The IILV semiconductor materials chosen to form the barrier layer 15 and / or the channel layer 16 may include gallium nitride (GaN), aluminum nitride (Ain), AlxGabxNx ternary alloys, gallium arsenide (GaAs), AlGaAs or InGaAs ternary alloys. For example, the barrier layer 15 and the channel layer 16 may include, respectively, a compound of AlGaN and GaN. The insulating layer 14 may include a dielectric material, in particular silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0008] The HEMT transistor 10 also includes a source electrode 17 and a The drain electrode 18 is in electrical contact with the conduction layer 16a. More specifically, the source electrode 17 and the drain electrode 18 open through the front face 11 and pass through the barrier layer 15 to reach the interface 15a and electrically contact the conduction layer 16a. The source electrode 17 and the drain electrode 18 may partially or completely penetrate the conduction layer 16a. The source electrode 17 and the drain electrode 18 may contain a metallic material, for example, aluminum, filling trenches formed in the stack 13.

[0009] The HEMT transistor 10 also includes a gate electrode 19 for which a voltage V is applied, enabling control of the state of the conduction layer 16a. In particular, when the electrical potential difference between the gate electrode 19 and the source electrode 17, denoted Vg-Vs, is greater than a threshold voltage Vth characteristic of the HEMT transistor 10, the transistor is in the conducting state. Conversely, when Vg-Vs is less than Vth, the HEMT transistor 10 is in the off state and therefore behaves like an open switch.

[0010] Also, depending on the value of the threshold voltage Vth, and more particularly its sign, a HEMT transistor can be in depletion mode ("normally on" according to Anglo-Saxon terminology) if its threshold voltage Vth is negative, or in enhancement mode ("normally off" according to Anglo-Saxon terminology) if its threshold voltage Vth is positive.

[0011] Such a high electronic mobility transistor nevertheless exhibits a resistivity Ron (Ron being the drain / source resistance in the on-state) in the on-state which limits the intensity of the current likely to flow in the conduction layer.

[0012] In this regard, the main parameters influencing the resistivity Ron are:

[0013] - the surface resistance of the channel layer;

[0014] - the resistance of the contacts between the conduction layer and the source electrodes and drain;

[0015] - the electrical resistivities of the chip routing metals;

[0016] - the electrical resistances induced in the final assembly in which the high electronic mobility transistor.

[0017] To overcome this problem, it is possible to significantly reduce the resistivity Ron of a high-electron-mobility transistor by increasing its surface area. However, there are situations where the space available for integrating a high-electron-mobility transistor is so limited that such a solution cannot be considered.

[0018] Alternatively, it may be considered to optimize the parameters influencing the Ron resistivity. However, such a solution remains complex to implement, as it requires, on the one hand, a complete redesign of the high-mobility transistor electronics, and on the other hand a review of the process for manufacturing said transistor.

[0019] An object of the present invention is therefore to propose a device whose arrangement allows a higher integration density of high electronic mobility transistors without significantly increasing the space occupied by said device.

[0020] Another object of the present invention is also to provide a device enabling efficient management of inrush currents. BRIEF DESCRIPTION OF THE INVENTION

[0021] The goal is achieved by an electronic device comprising a HEMT transistor, referred to as the main transistor, and at least one other HEMT transistor, referred to as the additional transistor, the main transistor and the additional transistor being provided, respectively, with a main stack and an additional stack and between which is interposed an insulating layer, the main stack and the additional stack extending, from the insulating layer towards, respectively, a rear face and a front face of the electronic device, and each comprising, from the insulating layer, a barrier layer and a channel layer which, when the HEMT considered transitions from a non-conducting state to a conducting state, is capable of forming a conduction layer, the main transistor and the additional transistor comprising a common drain electrode and, respectively, a main source electrode and an additional source electrode,arranged so that electrical conduction paths that can be formed by the two conduction layers are connected in parallel when both HEMT transistors are in the conducting state, the transition from one of the non-conducting and conducting states to the other of these two states is controlled independently for each of the main and additional transistors via, respectively, a main gate electrode and an additional gate electrode.

[0022] Thus, according to the present invention it is possible to increase the density of high electronic mobility transistors without increasing the surface area occupied by the electronic device.

[0023] Furthermore, connecting the conduction layers of the two transistors in parallel increases the current that can flow through the electronic device, thus opening the way to higher power applications. According to the present invention, as soon as the current flowing through the main transistor exceeds a threshold value, it is possible to switch the additional transistor on.

[0024] Furthermore, the electronic device according to the present invention does not require resizing of the high electronic mobility transistors it comprises.

[0025] Moreover, the parallel connection of the conduction paths makes it possible to limit the resistivity Ron of the electronic device.

[0026] According to one embodiment, the drain electrode passes through the insulating layer, and extends on either side of said insulating layer to electrically contact the channel layer of both the main transistor and the additional transistor; advantageously, the electronic device includes a pad, called the drain pad, disposed on the rear face and allowing electrical contact of the drain electrode.

[0027] According to one embodiment, said electrical device comprises a pad, called the main grid pad, disposed on the rear face and enabling electrical contact with the main grid electrode and a pad, called the additional grid pad, disposed on the front face and enabling electrical contact with the additional grid electrode.

[0028] According to one embodiment, the main transistor and the additional transistor are HEMT transistors in enhancement mode, and in which the main source electrode and the additional source electrode form a single source electrode, advantageously, the source electrode passes through the insulating layer, and extends on both sides of said insulating layer to electrically contact the channel layer of both the main transistor and the additional transistor.

[0029] According to one embodiment, said electronic device includes a pin called source pin allowing electrical contact with the source electrode.

[0030] According to one embodiment, the source plot is arranged on the front face.

[0031] According to one embodiment, the main transistor and the additional transistor are HEMT transistors in depletion mode, and are each cascoded with a MOSFET transistor called, respectively, main MOSFET transistor and additional MOSFET transistor.

[0032] According to one embodiment, the main MOSFET transistor and the additional MOSFET transistor are arranged to impose, independently, a conducting state or a non-conducting state, respectively, on the main transistor and the additional transistor.

[0033] According to one embodiment, said electronic device further comprises two pads called main source pad and additional source pad allowing to electrically contact, respectively, the main source electrode and the additional source electrode, the main source pad and the additional source pad being disposed, respectively, on the rear face and on the front face.

[0034] According to one embodiment, the main stack and the additional stack are essentially identical.

[0035] According to one embodiment, the main transistor and the additional transistor have an identical threshold voltage.

[0036] According to one embodiment, the main transistor and the additional transistor each have, respectively, a main threshold voltage and a voltage of additional thresholds differ from one another.

[0037] According to one embodiment, the two channel layers comprise GaN and the barrier layers comprise a ternary AlGaN alloy.

[0038] According to one embodiment, the insulating layer comprises a dielectric material, advantageously silicon dioxide.

[0039] The implementation of the insulating layer is particularly advantageous, as it allows the two barrier layers to be effectively insulated.

[0040] Considering this insulating layer also simplifies the assembly of the two high-electron-mobility transistors. Indeed, it allows for assembly by molecular bonding of the two transistors.

[0041] The invention also relates to an electronic housing comprising:

[0042] - the electronic device according to the present invention;

[0043] - a means of controlling the transition from one of the non-passing states to the passing state towards the other of these two states, of the main transistor and the additional transistor, the control means being configured to make the additional transistor conductive as soon as the main transistor is itself in the conducting state and the current through it is greater than a threshold value. Brief description of the drawings

[0044] Other features and advantages of the invention will become apparent from the detailed description that follows, with reference to the accompanying figures in which:

[0045] [Fig.1] Fig.1 is a schematic representation of a known HEMT transistor from the prior art, in particular, the HEMT transistor is represented according to a cutting plane perpendicular to the front face;

[0046] [Fig.2a] Fig.2a is a schematic representation of an electronic device, according to a cutting plan, conforming to the first embodiment of the present invention;

[0047] [Fig.2b] Fig.2b is a representation illustrating the offset positioning of the main grid pad and additional grid pad allowing to electrically connect the main grid electrode and the additional grid electrode of the electronic device of the [Fig.2a];

[0048] [Fig.2c] Fig.2c is a representation illustrating the offset positioning of a additional grid stud allowing to electrically connect the additional grid electrode of the electronic device of the [Fig.2a] according to a view from the front face of said device;

[0049] [Fig.3] Fig.3 is a schematic representation of an electronic device, according to a cutting plan, conforming to the second embodiment of the present invention;

[0050] [Fig.4] The [Fig.4] is a functional representation of a housing implementing the electronic device according to the first embodiment of the present invention;

[0051] [Fig.5] The [Fig.5] is a schematic representation of a step in the formation of an additional transistor according to the terms of the present invention;

[0052] [Fig.6] The [Fig.6] is a schematic representation of a step in the formation of a main transistor according to the terms of the present invention;

[0053] [Fig. 7] [Fig. 7] is a schematic representation of a step in the formation of pads intended to electrically contact the source and grid electrodes. DETAILED DESCRIPTION OF THE INVENTION

[0054] Of course, the invention is not limited to the embodiments described and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

[0055] Furthermore, it is understood that the various figures presented in connection with this description are given for illustrative purposes only and do not limit the invention in any way. In particular, it is clear that the relative scales or dimensions may not be accurate.

[0056] Throughout this description, it is assumed that a layer or interface is generally planar and extends along a plane parallel to the (0, x, y) plane of the orthonormal (0, x, y, z) coordinate system. Furthermore, whenever reference is made to a representation along a cutting plane, this plane is perpendicular to all the planes formed by the layers, and more specifically perpendicular to the (0, x, y) plane. It is also understood that, whenever reference is made to a stacking of layers, these layers are stacked along the z-direction of the orthonormal (0, x, y, z) coordinate system.

[0057] The invention relates to an electronic device comprising a HEMT transistor, referred to as the main transistor, and at least one other HEMT transistor, referred to as the additional transistor.

[0058] The main transistor and the additional transistor are provided, respectively, with a main stack and an additional stack and between which is intercalated an insulating layer.

[0059] The main stack and the additional stack extend from the insulating layer to, respectively, a rear face and a front face of the electronic device, and each comprise, from the insulating layer, a barrier layer and a channel layer.

[0060] In particular, as soon as it transitions from a non-conducting state to a conducting state, the HEMT transistor in question is capable of forming a conduction layer in the channel layer. Specifically, this conduction layer takes the form of a two-dimensional electron gas and extends into the channel layer from the interface formed between the barrier layer and the channel layer.

[0061] The main transistor and the additional transistor comprise a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged so that electrical conduction paths that can be formed by the two conduction layers are connected in parallel when both HEMT transistors are in the on-state.

[0062] The transition from one of the non-conducting states and the conducting state to the other of these two states is controlled independently for both the main transistor and the additional transistor via, respectively, a main gate electrode and an additional gate electrode.

[0063] This configuration is advantageous in several respects. Indeed, connecting the conduction channels of the two transistors in parallel makes it possible to increase the current that can flow through the electronic device without having to increase its surface area. In particular, when the current flowing through the main transistor exceeds a threshold value, it is possible to turn on the additional transistor so as to form a conduction layer in said transistor connected in parallel with the conduction layer of the additional transistor.

[0064] Furthermore, this parallel connection also makes it possible to reduce the on-state resistivity Ron of the electronic device.

[0065] Figure 2 shows an example of an electronic device 100 according to a first embodiment of the present invention.

[0066] Thus, the electronic device 100 according to the present invention comprises high electron mobility transistors (hereinafter "HEMT transistor"). In particular, the electronic device 100 comprises, from a front face 100a to a rear face 100b, at least one additional transistor 101 and a main transistor 102 separated by an insulating layer 200. The insulating layer 200 advantageously comprises silicon dioxide or silicon nitride.

[0067] According to this first embodiment, the HEMT transistors are in enhancement mode. In other words, such a transistor has a positive threshold voltage Vth (such a transistor is therefore conducting when the potential difference Vg-VS applied between the gate electrode and the source electrode is greater than Vth).

[0068] The description of the present invention will be limited to the implementation of a single additional transistor. However, this aspect does not limit the scope of the present invention. In particular, a person skilled in the art, based on their general knowledge and the following description, is able to implement, within the framework of the present invention, a plurality of additional transistors.

[0069] The additional transistor 101 and the main transistor 102 each comprise a stack referred to respectively as the additional stack 201 and the main stack 202. Each of these stacks may include, in particular, semiconductor materials from group III-V, and more specifically semiconductor materials from group III-N. The semiconductor materials from group III-V may in particular be chosen from gallium nitride (GaN), aluminium nitride (AIN) and their ternary alloys AlxGabxN, or from gallium arsenide (GaAs) and its compounds (AlGaAs, InGaAs).

[0070] The additional stack 201 and the main stack 202 each comprise a barrier layer and a channel layer. In particular, the additional stack 201 comprises, from the insulating layer 200 to the front face 100a, an additional barrier layer 201a and an additional channel layer 201b. Equivalently, the main stack 202 comprises, from the insulating layer 200 to the rear face 100b, a main barrier layer 202a and a main channel layer 202b.

[0071] By way of example and according to the present invention, a barrier layer may comprise a ternary alloy of AlxGai_xN, while a channel layer may comprise GaN.

[0072] Furthermore, a barrier layer can have a thickness between 1 nm and 100 nm.

[0073] A channel layer can have a thickness between 10 nm and 2 pm.

[0074] A stack 201 or 202, according to the terms of the present invention, is suitable for form a two-dimensional electron gas layer (2DEG for "2-dimensional electron gas") which constitutes a conduction layer.

[0075] The conduction layer, within a stack, extends into the channel layer, from the interface formed between the barrier layer and the channel layer of the stack considered.

[0076] Thus, the additional stack 201 includes an additional conduction layer 201c which extends into the additional channel layer 201b, from an additional interface formed between the additional barrier layer 201a and the additional channel layer 201b.

[0077] Equivalently, the main stack 202 comprises a main conduction layer 202c which extends into the main channel layer 202b, from a main interface formed between the main barrier layer 202a and the main channel layer 202b.

[0078] The electronic device 100 comprises a source electrode 203 and a drain electrode 204 in electrical contact with one or the other of the additional conduction layer 201c and the main conduction layer 202c. It should be noted that various types of electrical contacts are known to electrically connect the source electrodes 203 and drain electrode 204 to a conduction layer 201c, 202c: in particular, ohmic, tunnel or Schottky contacts.

[0079] In particular, the source electrode 203 and the drain electrode 204 pass through the insulating layer 200, and extend each on either side of said insulating layer 200 to electrically contact the additional conductive layer 201c and the main conductive layer 202c.

[0080] The electrical device 100 may include a pad, called source pad 206, disposed on the front face 100a and allowing electrical contact with the source electrode 203. The source pad 206 advantageously comprises doped silicon.

[0081] The electrical device 100 may include a pad, called drain pad 207, disposed on the rear face 100b and allowing electrical contact with the drain electrode 204. The drain pad 207 may advantageously include doped silicon.

[0082] The conduction layer of a HEMT transistor, when the latter is conducting, is intended to ensure the conduction of an electric current between the source electrode and the drain electrode of the HEMT transistor in question.

[0083] The electronic device 100 according to the present invention also comprises two grid electrodes that are separate from each other (i.e., electrically isolated from each other). In particular, the electronic device 100 comprises a main grid electrode 205a and an additional grid electrode 205b.

[0084] The electrical device 100 may include a pad, called the main grid pad 208a, disposed on the rear face and allowing electrical contact with the main grid electrode.

[0085] Equivalently, the electrical device 100 may include a pad, called an additional grid pad 208b, disposed on the front face and allowing electrical contact with the additional grid electrode.

[0086] It is understood that, for each HEMT transistor, the electrical contact between a gate electrode and its associated gate pad is offset so as to avoid the risk of electrical contact with the conduction layer of the transistor in question. In particular, the main gate pad and the additional gate pad are offset from an active region of the electronic device ([Fig. 2b]). By "offset," we mean a gate pad that is located outside a contour delimiting each of the two transistors. In this respect, [Fig. 2c] is a representation of the device 100 from a front-facing view (along a plane parallel to the (0, x, y) plane). The dashed lines delimit an active section ZA of the electronic device within which any contact between the gate electrode and either of the barrier and channel layers is avoided.

[0087] Thus, the main gate electrode 205a is arranged to control the main transistor 102, and more particularly to control the transition from one of the non-conducting and conducting states to the other of these two states.

[0088] Equivalently, the additional grid electrode 205b is arranged to control the additional transistor 101, and more specifically control the transition from one of the non-conducting and conducting states to the other of these two states.

[0089] By "on-state" is meant a transistor in which a current is capable of flowing between the source electrode and the drain electrode. In particular, a HEMT transistor, when in the on-state, comprises a conduction layer as defined above.

[0090] By "non-conducting state" is meant a transistor which behaves like an open switch so that no current can flow between its source electrode and the drain electrode.

[0091] More particularly, a HEMT transistor switches from a non-conducting state to a conducting state when the potential difference Vg-Vs between the gate electrode and the source electrode is greater than the threshold voltage Vth of the transistor considered.

[0092] Thus, according to the present invention, the main transistor 102 and the additional transistor 101 can be controlled independently. More particularly, the main transistor and the additional transistor can be, depending on the voltage applied to their gate electrode, in the same state or in a different state.

[0093] For example, when it is necessary to circulate a current in the electronic device 100, it is possible to first control the transition from the non-conducting state to the conducting state of the main transistor while keeping the additional transistor in the non-conducting state. These conducting and non-conducting states, respectively, of the main transistor and the additional transistor can be maintained as long as the current remains below a threshold current value Is.

[0094] The threshold current value Is may be less than or equal to a degradation current value Id. The degradation current value Id corresponds to a current value beyond which the main transistor is likely to be degraded.

[0095] By way of example, the threshold current value Is may be less than half the degradation current value Id.

[0096] Thus, the implementation of the additional transistor 101 makes it possible to protect the main transistor, in particular when inrush currents occur.

[0097] Alternatively or complementaryly, the additional transistor 101 can be used when the main transistor presents an excessive resistance Ron to the flow of current through its conduction layer. Such an effect can occur, in particular, when the temperature of the electronic device increases.

[0098] Alternatively, the additional transistor 101 can be used to absorb a current spike that may occur in the main transistor when the latter switches from the off state to the on state. To this end, the switching of the additional transistor to the on state simultaneously with the switching of the main transistor makes it possible to mitigate the occurrence of a current spike.

[0099] Figure 3 shows an electronic device 100 according to a second embodiment of the present invention. This second embodiment incorporates the essential features described in relation to Figure 2.

[0100] According to this second embodiment, HEMT transistors are in depletion mode or normally conducting mode ("Depletion mode" according to Anglo-Saxon terminology). In other words, such a transistor has a threshold voltage Vth less than 0 (such a transistor is therefore conducting when the potential difference applied between the gate electrode and the source electrode is zero).

[0101] According to this second embodiment, the main transistor 102 and the additional transistor no longer share the same source electrode.

[0102] In particular, the main transistor 102 includes a source electrode, called the main source electrode 203a, which passes through the main stack 202 and emerges from the rear face 100b. The electronic device includes in this respect a pad, called the main source pad 206a, disposed on the rear face 100b and enabling electrical contact to be established with the main source electrode 203a.

[0103] Equivalently, the additional transistor 101 includes a source electrode, called the additional source electrode 203b, which passes through the additional stack 201 and emerges from the front face 100a. The electronic device includes in this respect a pad, called the additional source pad 206b, disposed on the front face 100b and enabling electrical contact to be established with the additional source electrode 203b.

[0104] According to this second embodiment, the main transistor and the additional transistor are each cascoded with a MOSFET transistor.

[0105] In particular, the main transistor 102 is cascoded, via its source, with a MOSFET transistor referred to as the main MOSFET. The latter comprises a source Sa connected with the main gate electrode 205a, a drain Da connected with the main source electrode 203a, and a gate Ga allowing control of the transition from a conducting state to a non-conducting state or vice versa of the main MOSFET transistor.

[0106] Equivalently, the additional transistor 101 is cascoded, via its source, with a MOSFET transistor called an additional MOSFET transistor. The latter comprises a source Sb connected with the additional gate electrode 205b, a drain Db connected with the additional source electrode 203b, and a gate Gb allowing control of the transition from a conducting state to a non-conducting state or vice versa of the additional MOSFET transistor.

[0107] Also, still according to this second embodiment, the sources Sa and Sb are also electrically connected.

[0108] According to this second embodiment, the main grid electrode and the electrode The additional grids are controlled by, respectively, the Ga grid and the Gb grid.

[0109] The operation of the electronic device according to this second embodiment is similar to that described in the first embodiment.

[0110] Regardless of the embodiment envisaged, the electronic device according to the present invention can be integrated into an electronic housing 1000 provided with a control means 600 ([Fig. 4]). The electronic housing includes in particular an input E and an output S connected, respectively, to the source electrode and the drain electrode.

[0111] The control means 600 is configured, in particular, to control the transition of the main transistor and the additional transistor from one of the non-conducting and conducting states to the other of these two states. Specifically, the control means is connected to the electronic device 100 via a Gai connection and a Ga2 connection intended to apply a voltage, respectively, to the main gate electrode and the additional gate electrode.

[0112] More particularly, the control means 600 is configured to make the additional transistor conduct when the main transistor is itself in the conducting state and the current through it is greater than the threshold value Is.

[0113] In particular, the control means 600 can be configured to synchronize the main gate electrode and the additional gate electrode in order to limit the current spikes that may appear when these two transistors switch on.

[0114] A person skilled in the art, based on their general knowledge, is able to design such a system. They may, in particular, consult the document Y. Wen, M. Rose, R. Fernandes, R. Van Otten, HJ Bergveld and O. Trescases, "A Dual-Mode Driver IC With Monolithic Negative Drive-Voltage Capability and Digital Current-Mode Controller for Depletion-Mode GaN HEMT," in IEEE Transactions on Power Electronics, vol. 32, no. 1, pp. 423-432, Jan. 2017.

[0115] The present invention also relates to a method for manufacturing the electronic device 100 described above. The manufacturing method is described only with regard to the formation of the electronic device 100 according to the first embodiment. A person skilled in the art may, based on their general knowledge and the concepts presented below, adapt the method for implementation in the second embodiment.

[0116] In particular, the process includes a step of forming an additional transistor 101 ([Fig.5]).

[0117] In particular, the formation of this additional transistor 101 includes epitaxial growth of the additional stack 201 on a first face of a first substrate 400, for example a silicon substrate. The epitaxial growth may in particular The first step is to understand the formation of the additional channel layer 201b, and secondly, the formation of the additional barrier layer 201a. Advantageously, the formation of the additional channel layer can be preceded by the formation of an additional adaptation layer (on which the additional channel layer must rest). The additional adaptation layer is specifically designed to limit the formation of dislocations in the additional channel layer.

[0118] Epitaxial growth is followed by the formation, overlying the additional barrier layer 201a, of a first insulating layer 200a, which includes, for example, silicon dioxide or silicon nitride.

[0119] The deposition of the insulating layer 200a is then followed by the formation of a first source electrode 203b, a first drain electrode 204b and a first gate electrode 205b. The two electrodes 203b and 204b extend in particular from a free surface of the first insulating layer towards or into the additional stack 201.

[0120] The manufacturing process includes a step of forming a main transistor 102 ([Fig.6]).

[0121] In particular, the formation of this main transistor 102 comprises an epitaxial growth of the main stack 202 on a first face of a second substrate 500, for example a silicon substrate. The epitaxial growth may, in particular, first comprise the formation of the main channel layer 202b, and then, secondly, the formation of the main barrier layer 202a. Advantageously, the formation of the main channel layer may be preceded by the formation of a main matching layer (on which the main channel layer is to rest). The main matching layer is specifically intended to limit the formation of dislocations in the main channel layer.

[0122] Epitaxial growth is followed by the formation, overlying the main barrier layer 202a, of a second insulating layer 200b, which includes, for example, silicon dioxide.

[0123] The deposition of the second insulating layer 200b is then followed by the formation of a second source electrode 203a, a second drain electrode 204a and a second grid electrode 205a.

[0124] The manufacturing process also includes an assembly step of the additional transistor 101 and the main transistor 102. In this regard, the assembly step is carried out by bringing the first insulating layer 200a into contact with the second insulating layer 200b, and so that the first source electrode 203b and the first drain electrode 204b are in line, respectively, with the second source electrode 203a and the second drain electrode 204a.

[0125] In other words, the assembly of the first insulating layer with the second The insulating layer forms the insulating layer 200. The assembly of the first source electrode 203b with the second source electrode 203a forms the source electrode 203. The assembly of the first drain electrode 204b with the second drain electrode 204a forms the drain electrode 204. The first grid electrode 205b and the second grid electrode 205a remain independent of each other.

[0126] It is also noteworthy that this assembly step can be carried out in a plate-by-plate manner. More specifically, the process can include the formation of a plurality of first transistors on the first substrate and a plurality of main transistors on the second substrate. These two substrates are then assembled so as to place each additional transistor opposite a main transistor.

[0127] Alternatively, the assembly may include a pick and place step. In particular, each additional transistor may be individually placed on each main transistor formed on the second substrate.

[0128] Finally, and still in an alternative manner, the main transistors and the additional transistors are all singled out, and then assembled two by two.

[0129] In a final step, the source and grid pads are formed by thinning and etching the first substrate ([Fig.7]).

[0130] The electronic device according to the present invention is advantageously implemented in an electrical energy management / consumption system.

[0131] More specifically, the management system may include a means of energy storage and a means of consuming said energy. The storage means is, for example, a battery or an accumulator.

[0132] The consumption path can be an electric motor. Thus, the electronic device 100 according to the present invention is advantageously implemented in an electric vehicle (car, truck, bicycle, train).

Claims

Claims

1. Electronic device comprising a HEMT transistor, called the main transistor, and at least one other HEMT transistor, called the additional transistor, the main transistor and the additional transistor being provided, respectively, with a main stack and an additional stack between which an insulating layer is interposed, the main stack and the additional stack extending, from the insulating layer towards, respectively, a rear face and a front face of the electronic device, and each comprising, from the insulating layer, a barrier layer and a channel layer which, when the HEMT transistor in question passes from a non-conducting state to an conducting state, is capable of forming a conduction layer, the main transistor and the additional transistor comprising a common drain electrode and, respectively, a main source electrode and an additional source electrode,arranged so that electrical conduction paths capable of being formed by the two conduction layers are connected in parallel when both of the HEMT transistors are in the on state, the transition from one of the off state and the on state to the other of these two states being controlled independently for both of the main transistor and the additional transistor via, respectively, a main gate electrode and an additional gate electrode, wherein the main transistor and the additional transistor are enhancement mode HEMT transistors, and wherein the main source electrode and the additional source electrode form a single source electrode passing through the insulating layer, and extending on either side of said insulating layer to electrically contact the channel layer of both of the main transistor and the additional transistor.,

2. Device according to claim 1 wherein said electronic device comprises a pad called a source pad allowing electrical contact with the source electrode.

3. Device according to claim 2, in which the source pad is arranged on the front face.

4. Electronic device comprising a HEMT transistor, called the main transistor, and at least one other HEMT transistor, called the additional transistor, the main transistor and the additional transistor being provided, respectively, with a main stack and an additional stack between which an insulating layer is interposed, the main stack and the additional stack extending, from the insulating layer towards, respectively, a rear face and a front face of the electronic device, and each comprising, from the insulating layer, a barrier layer and a channel layer which, when the HEMT transistor in question changes from a non-conducting state to an conducting state, is capable of forming a conduction layer, the main transistor and the additional transistor comprising a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged so that electrical conduction paths capable of being formed by the two conduction layers are connected in parallel when both of the HEMT transistors are in the conducting state,the transition from one of the off-state and the on-state to the other of these two states, being controlled independently for each of the main transistor and the additional transistor via, respectively, a main gate electrode and an additional gate electrode, in which the main transistor and the additional transistor are depletion mode HEMT transistors, and are each cascoded with a MOSFET transistor called, respectively, the main MOSFET transistor and the additional MOSFET transistor.,

5. Device according to claim 4, in which the main MOSFET transistor and the additional MOSFET transistor are arranged to impose, independently, an on state or an off state, respectively, on the main transistor and the additional transistor.

6. Device according to claim 4 or 5, wherein said electronic device further comprises two pads called main source pad and additional source pad making it possible to electrically contact, respectively, the main source electrode and the additional source electrode, the main source pad and the additional source pad being arranged, respectively, on the rear face and on the front face.

7. Device according to any one of claims 1 to 6, in which the drain electrode passes through the insulating layer, and extends on either side of said insulating layer to electrically contact the channel layer of both the main transistor and the additional transistor, advantageously, the electronic device comprises a pad, called drain pad, arranged on the rear face and allowing electrical contact to be made with the drain electrode.

8. Device according to any one of claims 1 to 7, in which said electrical device comprises a pad, called the main gate pad, arranged on the rear face and allowing electrical contact with the main gate electrode and a pad, called the additional gate pad, arranged on the front face and allowing electrical contact with the additional gate electrode.

9. Device according to one of claims 1 to 8, in which the main stack and the additional stack are essentially identical.

10. Device according to one of claims 1 to 9, in which the main transistor and the additional transistor have an identical threshold voltage.

11. Device according to one of claims 1 to 9, in which the main transistor and the additional transistor each have, respectively, a main threshold voltage and an additional threshold voltage different from each other.

12. Device according to one of claims 1 to 11, in which the two channel layers comprise GaN and the barrier layers comprise a ternary alloy of AlGaN.

13. Device according to one of claims 1 to 12, in which the insulating layer comprises a dielectric material, advantageously silicon dioxide.

14. Electronic housing comprising: - the electronic device according to one of claims 1 to 13; - a means for controlling the transition from one of the non-conducting state and the conducting state to the other of these two states, of the main transistor and of the additional transistor, the control means being configured to turn on the additional transistor as soon as the main transistor is itself in the conducting state and the current passing through it is greater than a threshold value.

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