METHOD FOR MANUFACTURING INTEGRATED CIRCUITS FROM A SEMICONDUCTOR SUBSTRATE WRAPPER

Abstract

According to one aspect, a process for manufacturing integrated circuits (ICs) from a semiconductor substrate wafer (SUB) is proposed, comprising: - formation of the integrated circuits (ICs), each IC having an electrically active area (ZA), - formation of a thermally conductive protective structure (SP) around the active areas (ZAs) of the various ICs in cutting paths (SCRBs), the protective structure (SP) being located between the electrically active areas (ZAs) of said ICs and a laser ablation zone (GRV) of the cutting paths (SCRBs), - separation of the integrated circuits (ICs) by cutting the semiconductor substrate wafer (SUB) along the cutting paths (SCRBs), the cutting comprising laser ablation in the laser ablation zone (GRV), followed by chemical etching or physical cutting. Figure for the abstract: Fig 1

Description

Title of the invention: METHOD FOR MANUFACTURED INTEGRATED CIRCUITS FROM A SEMICONDUCTOR SUBSTRATE WRAPPER

[0001] Some embodiments and implementation methods relate to the manufacture of integrated circuits on a semiconductor wafer.

[0002] Semiconductor substrate wafers are used as a substrate for manufacturing integrated circuit components. A single semiconductor wafer can support several identical integrated circuits. Once the integrated circuit components are manufactured, the integrated circuits are separated from each other by cutting pieces of the semiconductor wafer (commonly referred to as a "die") along cutting paths (usually referred to as a "scribe line") that bypass the different integrated circuits.

[0003] There are different methods for cutting the various pieces of the wafer supporting the integrated circuits. For example, it is possible to use a saw to cut the wafer along the cutting paths.

[0004] Other methods use laser ablation (also referred to by the Anglo-Saxon expression "laser grooving") followed by chemical etching or physical cutting along the cutting paths.

[0005] In these methods, laser ablation makes it possible to cut a groove in the semiconductor wafer down to the substrate, then chemical etching or physical cutting is used to finalize the cutting of the wafer to separate the integrated circuits.

[0006] The engraving can, for example, be plasma engraving (in English, "plasma dicking"). Plasma engraving has several advantages over sawing.

[0007] Indeed, plasma etching does not create vibrations during cutting and thus improves the quality of the cut. Plasma etching is a process in which the wafer is bombarded with ionized gas (plasma) to remove one or more layers. Plasma etching therefore avoids applying mechanical pressure to the semiconductor wafer.

[0008] Plasma etching also allows for finer cutting so that it is possible to form a greater number of integrated circuits on the semiconductor wafer.

[0009] However, laser ablation can induce a significant release of heat which can generate thermal stresses in the semiconductor wafer.

[0010] However, plasma etching requires directly exposing the semiconductor wafer substrate to the plasma.

[0011] Metallic structures cannot therefore be used in the center of the cutting paths to optimize laser ablation.

[0012] As a result, the integrated circuits are not protected against the thermal stresses that may result from the heat generated by laser ablation, so that deterioration of the integrated circuits is possible.

[0013] In particular, during cutting, the heat produced by the laser can cause substrate degradation. This substrate degradation can weaken the substrate. The weakening of the substrate can then generate unwanted lateral cracks in the substrate during plasma etching. These lateral cracks can propagate to the active parts of the integrated circuits and thus damage them.

[0014] There is therefore a need to propose a solution to protect integrated circuits during the cutting of the semiconductor wafer by laser ablation followed by chemical etching or physical cutting.

[0015] According to one aspect, a method for manufacturing integrated circuits from a semiconductor substrate wafer is proposed, comprising: - a training course on integrated circuits, each integrated circuit having an electrically active area, - the formation of a thermally conductive protective structure around the active areas of the various integrated circuits in the cutting paths, the protective structure being located between the electrically active areas of said integrated circuits and a laser ablation zone of the cutting paths, then - separation of integrated circuits by cutting the semiconductor substrate wafer along the cutting paths, the cutting including laser ablation, in the laser ablation zone, then chemical etching or physical cutting.

[0016] The protective structure, being thermally conductive, captures and dissipates the heat produced by the laser ablation downstream of the laser relative to the direction of laser movement. Thus, the protective structure reduces thermal stress in the wafer. Consequently, the protective structure reduces the risk of lateral cracking that could damage the active area of ​​the integrated circuit.

[0017] Preferably, the formation of the protection structure comprises a formation of a continuous or discontinuous stack of metallic elements around the active areas of the different integrated circuits.

[0018] The stack of metallic elements can be formed at least in part in a shallow trench insulation (in English “Shallow Trench Isolation”).

[0019] In an advantageous embodiment, the formation of the protective structure It also involves the formation of a semiconductor substrate shoulder. The substrate shoulder allows for a deeper trench, which provides thermal insulation deeper into the substrate and limits, or even prevents, the propagation of lateral cracks that can be generated during plasma etching due to the heat generated by laser ablation.

[0020] Alternatively, advantageously, the formation of the protection structure further comprises the formation of at least one polysilicon trench extending at least partially deep into the semiconductor substrate.

[0021] Forming a polysilicon trench allows for a trench extending deeper into the substrate. Each trench provides deeper thermal insulation and prevents the propagation of lateral cracks towards the active area of ​​the integrated circuit.

[0022] Each polysilicon trench can be formed in said shallow insulation trench.

[0023] The formation of said at least one polysilicon trench can be carried out simultaneously with the formation of polysilicon trenches for the manufacture of other integrated circuit components, such as capacitors, in the active area of ​​the integrated circuits, said at least one trench of the isolation structure being identical to the trenches used for the manufacture of said other integrated circuit components.

[0024] Preferably, the protective structure comprises several polysilicon trenches.

[0025] In an advantageous embodiment, said at least one polysilicon trench extends continuously around the active area of ​​the integrated circuits.

[0026] Preferably, when the protective structure includes several polysilicon trenches, the polysilicon trenches extend discontinuously around the active area of ​​the integrated circuits, the trenches being arranged so that at least one trench is opposite the cutting path at every point around the active area of ​​the integrated circuits.

[0027] In an advantageous embodiment, the formation of each integrated circuit comprises the formation of a chip edge ring surrounding said active area, the protection structure being formed between the laser ablation areas and the chip edge rings.

[0028] Each chip edge ring can have mechanical protection properties and can seal the integrated circuit it surrounds against moisture.

[0029] Advantageously, the engraving carried out after laser ablation is a plasma engraving.

[0030] Preferably, the formation of the protective structure is carried out simultaneously to the formation of other integrated circuit components. Thus, the formation of the protection structure does not require the use of additional masks and is therefore inexpensive.

[0031] According to another aspect, an integrated circuit formed on a semiconductor substrate is proposed, the integrated circuit comprising an electrically active area and a thermally conductive protection structure, said protection structure extending along the edge of the integrated circuit around the electrically active area.

[0032] Such an integrated circuit may be an integrated circuit that can be obtained by implementing an integrated circuit manufacturing process as described above.

[0033] Preferably, the protection structure comprises a continuous or discontinuous stack of metallic elements around the active area of ​​the integrated circuit.

[0034] The stack of metallic elements can be formed at least in part in a shallow insulation trench.

[0035] In an advantageous embodiment, the protection structure also includes a shoulder of semiconductor substrate around the active area of ​​the integrated circuit.

[0036] Alternatively, advantageously, the protection structure further comprises at least one polysilicon trench extending at least partially deep into the semiconductor substrate around the active area of ​​the integrated circuit.

[0037] Preferably, the protective structure comprises several polysilicon trenches.

[0038] In an advantageous embodiment, said at least one polysilicon trench extends continuously around the active area of ​​the integrated circuits.

[0039] Preferably, when the protective structure comprises several poly-silicon trenches, the poly-silicon trenches extend discontinuously around the active area of ​​the integrated circuit, the trenches being arranged so that at least one trench is opposite the active area at every point around the active area.

[0040] In an advantageous embodiment, the integrated circuit further comprises a chip edge ring surrounding said active area, the protection structure being formed around the chip edge ring.

[0041] Advantageously, the protection structure is composed of thermally conductive elements identical to other components of the integrated circuit.

[0042] Other advantages and features of the invention will become apparent upon examination of the detailed description of implementation and embodiments, which are by no means limiting, and the accompanying drawings in which:

[0043] [Fig.1]

[0044] [Fig.2]

[0045] [Fig.3]

[0046] [Fig.4] schematically illustrate embodiments and implementations of the invention.

[0047] Figure 1 illustrates a cross-sectional view of an embodiment of a PLQ wafer in a SUB semiconductor substrate. Several integrated circuits (ICs) are formed in wafer pieces (commonly referred to as "dies"). In Figure 1, only two integrated circuits (ICs) are partially shown.

[0048] Each integrated circuit (IC) has an electrically active area (ZA). The active area (ZA) of each IC is surrounded by a chip edge ring (SR), for example, a sealing ring. The chip edge ring (SR) may have mechanical protection properties and may seal the integrated circuit against moisture.

[0049] The semiconductor wafer is configured to be cut in order to separate the integrated circuits from one another. In particular, the semiconductor wafer can be cut by performing laser ablation followed by chemical etching or physical cutting. The etching can notably be plasma etching.

[0050] More specifically, the PLQ semiconductor wafer has spaces forming SCRB slitting paths (commonly called "scribe lines") between the different integrated circuits (ICs). The SCRB slitting paths extend around the SR chip edge rings of the ICs. Each SCRB slitting path has a GRV laser ablation zone on which laser ablation is performed. In [Fig. 1], laser ablation has already been performed to form an RNR groove extending into the SCRB slitting path.

[0051] To protect the active area of ​​the integrated circuits, the PLQ semiconductor wafer includes protective structures SP all around the active areas of the various integrated circuits. In particular, the protective structures SP extend vertically between the GRV laser ablation areas and the active areas of the integrated circuits, specifically between the GRV laser ablation areas and the SR chip edge rings. The protective structure SP extends along the GRV laser ablation areas. The protective structure therefore adjoins the GRV laser ablation area. In particular, each protective structure SP is positioned at a distance D from the chip edge ring around which it extends. This distance D can be between Opm and half the total width of the SCRB cutting paths. More specifically, it is preferable to place the protective structure as close as possible to the GRV laser ablation area.

[0052] These SP protective structures are configured to dissipate the heat produced by laser ablation downstream of the laser relative to the direction of laser movement, in order to To reduce the risk of lateral cracking that could damage the active area of ​​integrated circuits after plasma etching, SP protective structures incorporate elements made of thermally conductive materials that extend around the active areas of the integrated circuits and along the laser ablation paths. Each element captures and then dissipates the heat generated by the laser ablation downstream of the laser's direction of travel.

[0053] Fig. 2 illustrates cross-sectional views of different embodiments (A), (B), (C), (D), (E) and (F) of an SP protection structure.

[0054] In each embodiment, the SP protection structure comprises an EPL stack of metallic elements formed within intermetallic oxide (INO) layers. These metallic elements are therefore thermally conductive and thus enable the absorption and dissipation of heat produced by laser ablation. The EPL stack consists of an alternating succession of metallic P_EPL layers and V_EPL vias connecting the different metallic P_EPL layers. This EPL stack is formed in a BEOL (Back End of Line) portion of the integrated circuit fabrication process. Here, the EPL stack is vertically continuous because it includes V_EPL vias connecting the metallic P_EPL layers, as illustrated in embodiment (A).However, it is possible to design a vertically discontinuous EPL stack that could consist solely of unconnected P_EPL metallic layers or solely of unconnected V_EPL vias. It is also possible to design a discontinuous EPL stack comprising P_EPL metallic layers and V_EPL vias connecting only certain P_EPL metallic layers.

[0055] As illustrated in embodiments (B), (C), (D), (E), and (F), the SP protection structure may also include at least one CTC metal element, identical to contacts used in the active areas of the integrated circuit or to CTC_SR contacts used in the chip edge rings. The CTC metal element may extend vertically to connect the EPL stack to the SUB substrate of the PLQ semiconductor wafer. This CTC metal element may be made of tungsten. The EPL stack and the CTC metal element enable the heat generated by laser ablation to be dissipated deep into the SUB substrate. The use of a CTC metal element adds a thermally conductive element to improve the dissipation of heat generated by laser ablation.

[0056] As illustrated in each embodiment (A) to (F), the SP protection structure may also include an STP shoulder of the SUB substrate of the semiconductor wafer near the laser ablation zone. The STP shoulder of the SUB substrate allows for a deeper STI trench, which provides thermal insulation deeper into the substrate and limits, or even prevents, pro STP shoulder in the SUB substrate can cause lateral cracks that may be generated during plasma etching due to the heat generated by laser ablation. Specifically, the STP shoulder can form at the EPL stack, between the EPL stack and the laser ablation zone, or between the EPL stack and the chip edge ring. The STP shoulder can be several hundred nanometers high, for example.

[0057] Furthermore, as illustrated in embodiment (C), the CTC metal element is directly connected to the STP shoulder of the SUB substrate. The SP protective structure therefore does not include TRCH trenches between the CTC metal element and the SUB substrate.

[0058] In embodiments (D), (E) and (F), the protection structure further comprises at least one TRCH trench formed partly in the shallow insulation trench STI and extending deep into the semiconductor substrate SUB.

[0059] Each TCRH trench is filled with a thermally conductive material. For example, each TRCH trench is filled with polysilicon. The polysilicon introduces thermal resistance into the substrate. For example, the polysilicon can be doped with doping concentrations between 10¹³ atoms / cm³ and 10²⁴ atoms / cm³. Each trench extends deeper into the substrate of the semiconductor wafer. As illustrated in embodiments (D) and (E), the width of a trench can vary. Forming a TRCH trench within a shallow insulation trench (STI) results in a TRCH trench extending deeper into the substrate (SUB). Each TRCH trench provides deeper thermal insulation and prevents the propagation of lateral cracks toward the active area (ZA) of the integrated circuit.

[0060] In embodiments (D) and (E) of [Fig. 2], the protective structure comprises a single trench. Alternatively, the protective structure may comprise several different TRCH trenches. Thus, as illustrated in embodiment (F) of [Fig. 2], the EPL stack can be connected to two different TRCH trenches by two CTC metal elements, for example.

[0061] In particular, [Fig. 3] illustrates different embodiments of a TRCH trench in top view. As illustrated in embodiments (a) and (b) of [Fig. 3], each TRCH trench can be continuous around the active area of ​​the integrated circuit. In particular, embodiment (a) of [Fig. 3] has a continuous trench with a large width, as illustrated in embodiment (D) of [Fig. 2]. Embodiment (b) has two continuous trenches with a smaller width, as illustrated in embodiment (F) of [Fig. 2].

[0062] Alternatively, as illustrated in embodiment (c) of [Fig. 3], when the The structure comprises several trenches, including thin trenches as illustrated in embodiment (F) of [Fig. 2]. The trenches may be discontinuous. In the latter case, it is preferable to arrange the TRCH trenches so that there is at least one trench adjacent to the active zone at every point around the active zone. This embodiment simplifies the fabrication of the TRCH trenches because the TRCH trenches are then composed of sections of limited length.

[0063] Fig. 4 illustrates a method for manufacturing integrated circuits from a PLQ wafer in SUB semiconductor substrate.

[0064] The process comprises several steps 40, 41, and 42 performed simultaneously. In particular, the process includes manufacturing 40 the integrated circuits in the PLQ wafer on a SUB semiconductor substrate. The process also includes manufacturing 41 chip edge rings around the active areas ZA of the integrated circuits. The process also includes manufacturing 42 a protective structure SP according to one of the embodiments described above.

[0065] In particular, the formation 42 of the protective structure may include the formation of at least one TRCH trench. The formation 42 of the protective structure may also further include the formation of the EPL stack and at least one other CTC metallic element, whether or not connected to said at least one TRCH trench. As previously stated, the formation 42 of the protective structure SP is carried out in conjunction with the formation of the integrated circuits (ICs). In particular, the formation of the TRCH trenches may be carried out simultaneously with the formation of trenches for the fabrication of other components (not shown), such as capacitors in the integrated circuits (ICs), the TRCH trenches of the isolation structure being identical to the trenches used for the fabrication of said other components.Furthermore, the formation of the EPL stack and said at least one CTC metal element can be carried out simultaneously with the formation of stacks and metal elements identical to the CTC element used for the fabrication of integrated circuits or SR chip edge rings. In particular, the EPL stack and said at least one CTC metal element can be formed at the same time as the EPL-SR stack and the CTC_SR metal element of the chip edge rings illustrated in [Fig. 1].

[0066] The method then includes a cutting step 43 in which the integrated circuits (ICs) are separated from one another. In particular, the wafer is cut along the cutting paths. The wafer cutting process first involves laser ablation followed by chemical etching or physical cutting (sawing or plasma etching, for example). The protective structure SP dissipates the heat generated by the laser ablation deep into the substrate, thereby reducing the risk of cracking in the semiconductor substrate during chemical etching or physical cutting. physical cutting. After cutting, each integrated circuit has on its edge the said SP protection structure which may have been partially damaged by the cutting.

Claims

Claims

1. Method for manufacturing integrated circuits (IC) from a wafer (PLQ) made of a semiconductor substrate (SUB) comprising: - forming the integrated circuits (IC), each integrated circuit (IC) comprising an electrically active zone (ZA), - forming a thermally conductive protective structure (SP) around the active zones (ZA) of the different integrated circuits (IC) in cutting paths (SCRB), the protective structure (SP) being located between the electrically active zones (ZA) of said integrated circuits and a laser ablation zone (GRV) of the cutting paths (SCRB), then - separating the integrated circuits (IC) by cutting the wafer (PLQ) made of a semiconductor substrate (SUB) along the cutting paths (SCRB), the cutting comprising laser ablation, in the laser ablation zone (GRV), then chemical etching or physical cutting,method in which the formation of the protection structure (SP) comprises a formation of a continuous or discontinuous stack (EPL) of metallic elements (P_EPL, V_EPL) around the active zones of the different integrated circuits and: - a formation of a shoulder (STP) of the semiconductor substrate (SUB) around the active zones of the different integrated circuits, or - a formation of at least one trench (TRCH) in polysilicon extending at least partly in depth in the semiconductor substrate (SUB).,

2. Method according to claim 1, in which the protection structure (SP) comprises several polysilicon trenches (TRCH).

3. Method according to any one of claims 1 or 2, wherein said at least one polysilicon trench (TRCH) extends continuously around the active zone (ZA) of the integrated circuits (CI).

4. Method according to claim 2, in which the trenches (TRCH) extend discontinuously around the active area (ZA) of the integrated circuits (CI), the trenches being arranged so that at least one trench is opposite the cutting path (SCRB) at any point around the active area (ZA) of the integrated circuits (CI).

5. A method according to any one of claims 1 to 4, wherein the formation of each integrated circuit (IC) comprises a formation of a chip edge ring (SR) surrounding said active area (ZA), the protection structure (ZA) being formed between the laser ablation zone (GRV) and the chip edge rings (SR).

6. Method according to one of claims 1 to 5, in which the etching carried out after the laser ablation is a plasma etching.

7. Method according to one of claims 1 to 6 in which the formation of the protection structure (SP) is carried out simultaneously with a formation of other components of the integrated circuit (IC).

8. Integrated circuit formed on a semiconductor substrate (SUB), the integrated circuit comprising an electrically active area (ZA) and a thermally conductive protection structure (SP), said protection structure (SP) extending at the edge of the integrated circuit (CI) around the electrically active area (ZA), the protection structure (SP) comprises a continuous or discontinuous stack (EPL) of metallic elements (P_EPL, V_EPL) around the active area of ​​the integrated circuit and: - a shoulder (STP) of semiconductor substrate (SUB) around the active area of ​​the integrated circuit, or - at least one polysilicon trench (TRCH) extending at least partly deep into the semiconductor substrate (SUB) around the active area of ​​the integrated circuit.

9. Integrated circuit according to claim 8, in which the protection structure (SP) comprises several polysilicon trenches (TRCH).

10. Integrated circuit according to any one of claims 8 or 9, wherein said at least one polysilicon trench (TRCH) extends continuously around the active area (ZA) of the integrated circuit (CI).

11. An integrated circuit according to claim 9, wherein the polysilicon trenches (TRCH) extend discontinuously around the active area (ZA) of the integrated circuit, the trenches (TRCH) being arranged so that at least one trench faces the active area at any point around the active area.

12. Circuit according to one of claims 8 to 11, wherein the integrated circuit (CI) further comprises a chip edge ring (SR) surrounding said active area (ZA), the protection structure (SP) being formed around the chip edge ring (SR).

13. Circuit according to one of claims 8 to 12 in which the protection structure (SP) is composed of thermally conductive elements identical to other components of the integrated circuit (IC).

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