Method for filling a trench formed in a semiconductor substrate
A method for filling semiconductor trenches with controlled silicon layers addresses stress-induced deformation by balancing tensile and compressive forces, achieving effective trench filling with reduced substrate strain.
Patent Information
- Application Number
- FR2022009435
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-09-19
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2042-09-19
AI Technical Summary
Filling trenches in semiconductor substrates with polycrystalline silicon induces strong mechanical stresses, posing challenges during device manufacturing.
A method involving successive deposition of amorphous and polycrystalline silicon layers with controlled grain sizes and stresses, including an intermediate annealing step to crystallize the amorphous layer, is used to fill trenches, with each layer deposited in the same chamber to minimize substrate deformation.
The method effectively reduces substrate deformation by balancing tensile and compressive forces from the silicon layers, ensuring complete trench filling while minimizing mechanical stress.
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Abstract
Description
Title of the invention: Method for filling a trench formed in a semiconductor substrate Technical field
[0001] The present description relates generally to the field of electronic devices and their manufacturing methods. It relates more particularly to a method of filling, with polycrystalline silicon, a trench formed in a semiconductor substrate. It also relates to an electronic device comprising a trench filled by such a method. Prior art
[0002] Various electronic devices have been proposed comprising trenches extending vertically in a semiconductor substrate and partially or completely filled with polycrystalline silicon.
[0003] Such trenches are for example used to form insulating walls laterally separating different elements of an integrated circuit, for example different pixels of an image sensor or different elementary storage cells of a memory circuit, or to form vertical electronic components such as vertical transistors or vertical capacitors.
[0004] One difficulty is that filling the trenches with polycrystalline silicon can induce strong mechanical stresses on the substrate, which may pose problems during the manufacture of the devices.
[0005] It would be desirable to overcome all or part of the drawbacks of known methods of filling, with polycrystalline silicon, a trench formed in a semiconductor substrate. Summary of the invention
[0006] For this, one embodiment provides a method of filling a trench (101) formed in a semiconductor substrate (103), comprising the following successive steps: a) depositing a first layer (109) of silicon under amorphous deposition conditions on the side walls and at the bottom of the trench (101); b) depositing a second layer (111) of silicon under polycrystalline deposition conditions on and in contact with the first layer (109); and c) depositing a third layer (113) of doped silicon under amorphous deposition conditions on and in contact with the second layer (111) so as to completely fill the trench (101), in which, at the end of step b), the first layer (109) is made of poly-silicon crystalline having a grain size different from that of the second layer (111).
[0007] According to one embodiment, the silicon of the first layer (109) crystallizes and passes from an amorphous state to a polycrystalline state during the deposition of the second layer (111), under the effect of the deposition conditions of the second layer (111).
[0008] According to one embodiment, the method comprises between step a) and step b), an intermediate annealing step during which the silicon of the first layer (109) crystallizes and passes from an amorphous state to a polycrystalline state.
[0009] According to one embodiment, at the end of step c), the first layer (109) of silicon is tensile and the second layer (111) of silicon is compressive.
[0010] According to one embodiment, the second layer (111) of silicon is deposited in situ, in the same deposition chamber as the first layer (109) of silicon, without extracting the substrate (103) from the chamber between the two deposits.
[0011] According to one embodiment, the method comprises, before step a), a step of depositing a dielectric layer (107) on the side walls and at the bottom of the trench (101).
[0012] According to one embodiment, in step a), the first layer (109) of silicon is deposited on and in contact with the dielectric layer (107).
[0013] According to one embodiment, the first layer (109) of silicon is doped in situ during its deposition.
[0014] According to one embodiment, the method comprises a step of thinning the substrate (103) by its face opposite the trench (101) between step b) and step c).
[0015] According to one embodiment, the method comprises a rapid thermal annealing step between the thinning step and step c).
[0016] Another embodiment provides an electronic device comprising a trench disposed in a semiconductor substrate (103), comprising: a first layer (109) of polycrystalline silicon coating the side walls and the bottom of the trench (103); a second layer (111) of polycrystalline silicon on and in contact with the first layer (109); and a third layer (113) of doped silicon on and in contact with the second layer (111), the third layer (113) completely filling the trench, wherein the polycrystalline silicon of the first layer (109) has a different grain size than the polycrystalline silicon of the second layer (111).
[0017] According to one embodiment, the polycrystalline silicon of the first layer (109) has an average grain size of between 50 and 120 nm, and the polycrystalline silicon of the second layer (111) has an average grain size of between 10 and 30 nm. Brief description of the drawings
[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0019] [Fig.lA], [Fig.lB], [Fig.lC], [Fig.lD], [Fig.lE] and [Fig.lF] are sectional views illustrating successive steps of an example of a method of filling a trench according to one embodiment. Description of the embodiments
[0020] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0021] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, only the production of the trenches of the electronic devices has been detailed. The other elements of the electronic devices have not been detailed, the described embodiments being compatible with all or most of the known embodiments of electronic devices comprising trenches filled with polycrystalline silicon.
[0022] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0023] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0024] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0025] Figures 1A to 1F are partial and schematic sectional views illustrating successive steps of an example of a method of filling a trench according to one embodiment.
[0026] [Fig.1A] illustrates the structure obtained at the end of a step of forming a trench 101 in a semiconductor substrate 103. The trench extends vertically from one face of the substrate, the upper face in the example shown, over a depth less than the thickness of the substrate 103, for example over a depth between 1 and 50 pm, for example between 2 and 15 pm, for example of the order of 6 pm.
[0027] The width of the trench 101 is for example between 0.1 and 2 pm, for example of the order of 600 nm.
[0028] The substrate 103 is for example made of silicon, for example monocrystalline silicon. The embodiments described are however not limited to this particular case and can be applied to substrates made of other semiconductor materials, including or not including silicon.
[0029] In the example shown, the upper face of the substrate is coated with a passivation dielectric layer 105, for example made of silicon nitride. The trench 103 extends through the layer 105.
[0030] The trench 101 is for example formed by photolithography then etching, for example by a plasma etching process, for example by a DRIE type process (from the English “Deep Reactive Ion Etching”).
[0031] [Fig. 1B] illustrates the structure obtained at the end of an optional step of depositing a layer or liner 107 of a dielectric material, for example silicon oxide, on the side walls and on the bottom of the trench 101. In this example, the layer 107 serves to electrically insulate the semiconductor material of the substrate from the polycrystalline silicon subsequently deposited in the trench. In this example, the layer 107 is in contact with the material of the substrate 103 on the side walls and on the bottom of the trench 101. The layer 107 is for example deposited by a conformal deposition method over the entire upper surface of the substrate 103. Thus, in the example shown, the layer 107 also extends over the upper face of the dielectric layer 105. The thickness of the dielectric layer 107 is for example between 2 nm and 200 nm.
[0032] [Fig. 1C] illustrates the structure obtained at the end of a step of depositing an amorphous silicon layer 109 on the side walls and on the bottom of the trench 101. In this example, the layer 109 is deposited on and in contact with the upper face of the dielectric layer 107. The layer 109 is for example deposited by a conformal deposition method over the entire upper surface of the substrate 103. The thickness of the amorphous silicon layer 109 is for example between 50 and 500 nm, for example of the order of 150 nm.
[0033] Preferably, the layer 109 is doped in situ during its deposition. The doping may be of the P type or of the N type. For example, the doping is boron or phosphorus doping. The doping level of the layer 109 is for example between 1*10 18 atoms / cm3 and 1*1022 atoms / cm3.
[0034] The deposition is for example carried out at a temperature below 600°C, for example between 400 and 580°C, so as to obtain an amorphous state of the silicon of the layer 109 after deposition.
[0035] [Fig. 1D] illustrates the structure obtained at the end of a step of in-situ deposition of a layer of polycrystalline silicon 111 on the side walls and on the bottom of the trench 101 after the deposition of the layer 109. In this example, the layer 111 is deposited on and in contact with the upper face of the layer of amorphous silicon 109. The layer 111 is for example deposited by a conformal deposition method over the entire upper surface of the substrate 103. The thickness of the layer of polycrystalline silicon 111 is for example between 50 and 500 nm, for example of the order of 130 nm.
[0036] The layer 111 is for example undoped (not intentionally doped). Alternatively, the layer 111 is doped in situ during its deposition. The doping can then be of the P type or of the N type. For example, the doping is boron or phosphorus doping. The doping level of the layer 111 is for example between 1*10 18 atoms / cm3 and 1*1022 atoms / cm3.
[0037] The deposition is for example carried out at a temperature above 580°C, for example between 600 and 700°C, so as to obtain a polycrystalline state of the deposited silicon.
[0038] By in-situ deposition, it is meant here that the layer 111 is deposited in the same deposition chamber as that used to carry out the deposition of the layer 109 in the step of [Fig. 1C], without removing the structure from the chamber between the deposition of the layer 109 and the deposition of the layer 111.
[0039] In this example, no intermediate annealing is provided between the deposition of layer 109 and the deposition of layer 111, so that the silicon of layer 109 is still amorphous at the start of the deposition step of layer 111.
[0040] The temperature in the chamber during the deposition of the layer 111 induces an in-situ recrystallization of the amorphous silicon layer 109. Thus, during the deposition of the polycrystalline silicon layer 111, the amorphous silicon layer 109 is transformed into polycrystalline silicon.
[0041] The polycrystalline silicon of layer 109, obtained by in-situ recrystallization of the amorphous silicon deposited in the previous step, is tensile, that is to say that it exerts a tensile force (stretching) on the material of the substrate 103, parallel to the plane of layer 109. The polycrystalline silicon of layer 111, obtained directly by deposition under polycrystalline deposition conditions, is compressive, that is to say that it exerts a compressive force on the material of the substrate 103, parallel to the plane of layer 111. Thus, the tensile force exerted by layer 109 is at least partially compensated by the compressive force exerted by layer 111, which makes it possible to limit the deformations of the substrate 103 linked to the filling of the trenches 101. For example, the polycrystalline silicon layer of layer 109 exerts a tensile force of between 100 and 500 MPa, and the polycrystalline silicon of layer 111 exerts a compressive force of between 100 and 500 MPa. It should be noted that these values depend on the thermal budgets applied, the doping chemical elements and the doping levels, as well as the deposited thicknesses. In addition, the impact on the deformation of the plates is more or less strong depending on the density of the slices per wafer and their depth.
[0042] It will be noted that in practice, at the end of the process, due to their different formation conditions (amorphous deposition then recrystallization into polycrystalline silicon for layer 109 and polycrystalline deposition for layer 111), the polycrystalline silicon layers 109 and 111 have different grain sizes. For example, layer 109 has a larger average grain size than layer 111. For example, the polycrystalline silicon of layer 111 has an average grain size varying between 10 and 30 nm, for example with columnar growth. The recrystallized amorphous silicon of layer 109 has, for example, an average grain size varying between 50 and 120 nm, for example with a random distribution of the grains. These grain sizes and arrangements can fluctuate depending on thermal budgets, the doping chemical element and its concentration, the deposition surface, etc.
[0043] [Fig. 1E] illustrates the structure obtained at the end of a step of filling the trench 101 with a layer of doped amorphous silicon 113. In this example, the layer 113 is deposited on and in contact with the upper face of the layer of polycrystalline silicon 111. The layer 113 is for example deposited over the entire upper surface of the substrate 103. The thickness of the layer of amorphous silicon 113 is chosen to be sufficiently high to completely fill the trench 101.
[0044] Preferably, the layer 113 is doped in situ during its deposition. The doping may be of the P type or of the N type. For example, the doping is boron or phosphorus doping. The doping level of the layer 1113 is for example between 1*10 18 atoms / cm3 and 1*1022 atoms / cm3.
[0045] The deposition is for example carried out at a temperature below 600°C, for example between 400 and 580°C, so as to obtain an amorphous state of the silicon of the layer 113 at the end of the deposition.
[0046] [Fig. 1F] illustrates the structure obtained at the end of a step of planarization of its upper face, for example by chemical-mechanical polishing. During this step, the structure is thinned by its upper face so as to remove the portions of the layers 113, 111, 109 and 107 coating the upper face of the substrate 103, until the upper face of the dielectric layer 105 is exposed. The thinning is for example interrupted on the upper face of the dielectric passivation layer 105.
[0047] An advantage of the method described in relation to Figures 1A to 1F is that it allows to fill trenches formed in a substrate, while limiting deformations of the substrate under the effect of the stresses exerted by the trench filling material.
[0048] This is particularly interesting when the density of the trenches on the surface of the substrate is high, for example greater than 9%, and particularly when the trenches are deep, for example greater than 2 μm deep.
[0049] After the step of depositing the polycrystalline silicon layer 111 and before the deposition of the layer 113, a heat treatment, for example an RTP (Rapid Thermal Processing) type annealing, can advantageously be implemented, so as to relax the stresses of the layers 109 and 111 before the final filling with the layer 113. The annealing is for example implemented at a temperature between 800°C and 1200°C, for example of the order of 955°C. The duration of the annealing is for example between 2 seconds and 5 minutes.
[0050] In the example described in relation to FIGS. 1A to 1E, the amorphous silicon layer 109 deposited in the step of [Fig. 1C] is transformed into polycrystalline silicon during the step of deposition of the polycrystalline silicon layer 111.
[0051] As a variant, an intermediate step of in-situ annealing of the layer 109, leading to the transformation of the amorphous silicon of the layer 109 into polycrystalline silicon, can be implemented before the deposition of the layer 111. By in-situ annealing, it is meant here that the annealing is implemented in the chamber used to carry out the deposition in the step of [Fig. 1C], without removing the structure from the chamber between the deposition and the annealing. The annealing is for example implemented at a temperature above 560°C, for example between 580°C and 900°C.
[0052] The in-situ annealing of the amorphous silicon layer 109 again leads to the transformation of the layer 109 into a tensile polycrystalline silicon layer, i.e. exerting a tensile force (stretching) of the material of the substrate 103, parallel to the plane of the layer 109.
[0053] The polycrystalline silicon layer 11 can then be deposited in situ (in the same equipment) on the polycrystalline silicon layer 109, the rest of the process being identical to what was described previously.
[0054] The trenches produced by the methods described above form, for example, insulation walls laterally separating different elements of an integrated circuit, for example different pixels of an image sensor or different elementary storage cells of a memory circuit. As a variant, these trenches form vertical electronic components such as vertical transistors or vertical capacitors.
[0055] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and Variants could be combined, and other variants will occur to those skilled in the art. In particular, the described embodiments are not limited to the application examples mentioned above.
[0056] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Claims
1. A method of filling a trench (101) formed in a semiconductor substrate (103), comprising the following successive steps: a) depositing a first layer (109) of silicon under amorphous deposition conditions on the side walls and at the bottom of the trench (101); b) depositing a second layer (111) of silicon under polycrystalline deposition conditions on and in contact with the first layer (109); and c) depositing a third layer (113) of doped silicon under amorphous deposition conditions on and in contact with the second layer (111) so as to completely fill the trench (101), wherein, at the end of step b), the first layer (109) is made of polycrystalline silicon having a grain size different from that of the second layer (111).
2. The method of claim 1, wherein the silicon of the first layer (109) crystallizes and changes from an amorphous state to a polycrystalline state during the deposition of the second layer (111), under the effect of the deposition conditions of the second layer (111).
3. Method according to claim 1, comprising, between step a) and step b), an intermediate annealing step during which the silicon of the first layer (109) crystallizes and passes from an amorphous state to a polycrystalline state.
4. Method according to any one of claims 1 to 3, in which, at the end of step c), the first layer (109) of silicon is tensile and the second layer (111) of silicon is compressive.
5. Method according to any one of claims 1 to 4, in which the second layer (111) of silicon is deposited in-situ, in the same deposition chamber as the first layer (109) of silicon, without extracting the substrate (103) from the chamber between the two depositions.
6. Method according to any one of claims 1 to 5, comprising, before step a), a step of depositing a dielectric layer (107) on the side walls and at the bottom of the trench (101).
7. The method of claim 6, wherein, in step a), the first layer (109) of silicon is deposited on and in contact with the dielectric layer (107).
8. Method according to any one of claims 1 to 7, in which the first layer (109) of silicon is doped in situ during its deposition.
9. Method according to any one of claims 1 to 8, comprising a step of thinning the substrate (103) by its face opposite the trench (101) between step b) and step c).
10. A method according to claim 9, comprising a rapid thermal annealing step between the thinning step and step c).
11. An electronic device comprising a trench disposed in a semiconductor substrate (103), comprising: a first layer (109) of polycrystalline silicon coating the side walls and the bottom of the trench (103); a second layer (111) of polycrystalline silicon on and in contact with the first layer (109); and a third layer (113) of doped silicon on and in contact with the second layer (111), the third layer (113) completely filling the trench, wherein the polycrystalline silicon of the first layer (109) has an average grain size greater than that of the polycrystalline silicon of the second layer (111).
12. The device of claim 11, wherein the polycrystalline silicon of the first layer (109) has an average grain size of between 50 and 120 nm, and the polycrystalline silicon of the second layer (111) has an average grain size of between 10 and 30 nm.