Method for transferring control signals between a first digital domain and a second digital domain, and corresponding system-on-chip.
A conditional pulse stretching circuit in the SoC interface extends control signal duration to meet level shifting requirements, addressing data corruption issues from asynchronous resets and ensuring reliable transfer across digital domains with different supply voltages and frequencies.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- STMICROELECTRONICS INT NV
- Filing Date
- 2022-11-29
- Publication Date
- 2026-04-17
AI Technical Summary
Existing systems-on-chip (SoC) face issues with data corruption due to metastability caused by external asynchronous resets, particularly when transferring control signals between digital domains with different supply voltages and operating frequencies, as voltage level shifting circuits have limited bandwidth and can filter out pulses that are not long enough.
Implementing a conditional pulse stretching circuit in the interface circuit to lengthen the duration of control signals to ensure they meet the nominal duration required for passing through level shifting circuits, while avoiding interference from external asynchronous resets.
Ensures reliable data transfer between digital domains by preventing data corruption and ensuring control signals reach their intended destination, even during asynchronous resets, by adapting pulse duration to the bandwidth limitations of level shifting circuits.
Abstract
Description
Title of the invention: Method for transferring control signals between a first digital domain and a second digital domain, and corresponding system-on-chip.
[0001] Embodiments and implementations relate to the transfer of signals, such as control signals and data, between distinct digital domains of a system-on-chip, in particular digital domains having different supply voltages and operating frequencies.
[0002] French patent application no. 2203375 filed on April 12, 2022, describes a method, and a corresponding system-on-chip, for transferring data between a first digital domain and a second digital domain, making it possible to avoid data corruption caused by metastability in a register used for the transfer, for example metastability caused by an external asynchronous reset.
[0003] In particular, French patent application no. 2203375 filed on April 12, 2022 describes the generation of a control signal, by a pulse stretching circuit configured to generate a pulse having a duration long enough to pass through a voltage level shifting circuit, from a pulse generated in the first digital domain and having a duration corresponding for example to a clock cycle of the first digital domain.
[0004] Indeed, voltage level shifting circuits typically exhibit limited bandwidth, notably a low-pass effect (a cutoff of high frequencies), inherent to the circuit design. Thus, a pulse extending, for example, over a clock cycle of the first domain can be filtered and not pass through the voltage level shifting circuits.
[0005] That being said, the external asynchronous reset signal can cause a reset of the pulse stretching circuit interrupting the generation of this pulse, so that the pulse can have a duration long enough to be communicated to the voltage level shifting circuit but still too short to pass through the voltage level shifting circuit.
[0006] Thus, in such a situation, from the point of view of the first domain, the control signal is effectively communicated to the second domain (at least, communicated to the voltage level shifting circuit), whereas the control signal never reaches the second domain.
[0007] There is therefore a need to prevent such a situation, and more generally to ensure reliable behavior in the transfer between digital domains, regardless of when an external asynchronous reset occurs.
[0008] According to one aspect, a system on chip is proposed in this regard comprising a first digital domain, a second digital domain, and an interface circuit comprising a level shifting circuit capable of converting a signal between the first digital domain and the second digital domain, - the first digital domain comprising a control circuit configured to generate a control signal intended for the second digital domain, the control signal comprising a pulse having a nominal duration adapted to the level shifting circuit; - the interface circuit further comprising, in the first input domain of the level shifting circuit, a conditional pulse stretching circuit configured to lengthen the pulse duration of the control signal to the nominal duration if the duration of the control signal is shorter than the nominal duration and non-zero.
[0009] By "a nominal duration adapted to the level shifting circuit" it is meant for example that the nominal duration corresponds to a frequency which is not filtered in the limited bandwidth of the level shifting circuit, and which is therefore adapted so that said pulse is communicated to the second digital domain by the level shifting circuit.
[0010] Thus, the conditional pulse stretching circuit makes it possible to correct any shortening of the control signal pulse, so as to ensure that the existing control signal (because of non-zero duration) passes through the level shifting circuit and is effectively communicated to the second digital domain.
[0011] The shortening can for example be caused by a reset of the control circuit during the incomplete generation of the control signal pulse.
[0012] Furthermore, the conditional pulse stretching circuit is advantageously configured so as not to act on the control signal outside the conditions defined above, i.e. in the absence of the signal (zero-duration pulse), and if the duration of the control signal is able to pass through the level shifting circuit (i.e. if the duration is not shorter than the nominal duration).
[0013] According to one embodiment, the control circuit is configured to be reset by a first reset signal, while the conditional pulse stretching circuit is configured not to be reset by the first reset signal.
[0014] Since the conditional stretching circuit of the interface circuit is not affected by the first reset signal, the conditional stretching circuit This will effectively lengthen the pulse duration in the event of a reset by the first reset signal during pulse generation by the control circuit. Thus, this allows the interface circuit to react in a controlled manner to a reset by the first reset signal, for example, in order to complete a data transfer without data corruption, with the control signal having its nominal duration, despite a reset occurring at a moment during its incomplete generation.
[0015] For example, the first reset signal is an external asynchronous signal, while the conditional pulse stretching circuit is configured to be reset by a second internal synchronous reset signal.
[0016] According to one embodiment, the first digital domain includes a clock generator configured to generate a first clock signal, the nominal duration corresponding to a nominal number of cycles of the first clock signal, the conditional pulse stretching circuit being configured to lengthen said pulse duration, if the number of cycles of the pulse is less than the nominal number and greater than one.
[0017] In other words, the pulse duration is counted in whole numbers of cycles of the first clock signal, and the non-zero duration condition of the conditional stretching circuit corresponds to a duration of at least one cycle of the first clock signal.
[0018] According to one embodiment, the interface circuit further comprises, in the first domain, between the control circuit and the conditional pulse stretching circuit, a synchronization circuit configured to synchronize the control signal so as to align the synchronized control signal with whole cycles of the first clock signal.
[0019] Consequently, the synchronized control signal, i.e. the control signal coming out of the synchronization circuit, is communicated over durations corresponding to whole numbers of cycles of the first clock signal, in a manner adapted to take into account the conditional stretching circuit.
[0020] According to another aspect, a method for transferring a control signal between at least a first digital domain and a second digital domain of a system-on-chip is proposed, comprising a generation, in the first digital domain, of a control signal intended for the second digital domain comprising a pulse intended to have a nominal duration suitable for a level-shifting circuit capable of converting a signal between the first digital domain and the second digital domain the method further comprising, at the input of the level-shifting circuit, an extension of the pulse duration of the control signal to the nominal duration if the duration of the control signal is shorter than the nominal duration and non-zero.
[0021] According to one embodiment, a first reset signal causes a reset of the first domain but does not cause a reset of a conditional pulse stretching circuit configured to perform said pulse duration stretching.
[0022] For example, the first reset signal is an external asynchronous signal, while a second internal synchronous reset signal causes a reset of the pulse stretching conditional circuit.
[0023] According to one embodiment, the nominal duration corresponds to a nominal number of cycles of a first clock signal generated in the first domain, and the method includes said extension of the pulse duration, if the number of cycles of the control signal pulse is less than the nominal number and greater than one.
[0024] According to one embodiment, the method further includes a synchronization of the control signal aligning the synchronized control signal with whole cycles of the first clock signal.
[0025] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and implementations, which are by no means limiting, and the accompanying drawings, in which the figures:
[0026] [Fig.l] ;
[0027] [Fig.2] ; and
[0028] [Fig.3] illustrate embodiments and implementations of the invention.
[0029] Figure 1 illustrates an example of a system-on-chip (SoC) comprising at least two digital domains V1, V22 having different supply voltages and different operating frequencies.
[0030] The first digital domain Vil is powered by a first supply voltage VDD11, for example of 1.1 volts, generated by a power supply stage SUPP11. The first digital domain Vil is clocked by a first clock signal CLK11 at a first frequency, generated by a clock generation stage CLKGEN11.
[0031] The second digital domain V22 is powered by a second supply voltage VDD22, for example of 3.3 volts, generated by a SUPP22 power supply stage. The second digital domain V22 is clocked by a second clock signal CLK22 at a second frequency, generated by a CLKGEN22 clock generation stage.
[0032] For example, the second frequency is lower than the first frequency, and the second supply voltage VDD22 is higher than the first supply voltage VDD11.
[0033] In the context of this example, the first domain Vil can, for example, be intended to carry out operations with high performance and consequently high energy consumption, while the second domain V22 can, for example, be intended to be always active, so as to ensure critical operations, and with low energy consumption.
[0034] On the other hand, the first domain Vil is configured to be reset by a first PADRST reset signal, or by a second POR reset signal distinct from the first PADRST reset signal. The second domain V22 is configured to be reset by a POR_V22 reset signal specific to it, but which can also be the same signal as the second POR reset signal of the first domain Vil.
[0035] The reset signals PADRST, POR (respectively POR_V22) have the effect of placing the digital domain Vil (respectively V22) in a blank and controlled state (typically to restart the domain), and in particular in this respect of interrupting ongoing actions and erasing working data.
[0036] The first PADRST reset signal can, in particular, originate from outside the system-on-chip (SOC) asynchronously with the first CLK11 clock signal. For example, the first PADRST reset signal can be a forced reset signal activated by a user independently of the actions being performed by the first VIL domain.
[0037] The second POR reset signal can be generated during a synchronous reset process at startup of the system on chip SOC, usually referred to by the English terms "power-on reset".
[0038] It is considered that the POR_V22 reset signal of the second V22 domain is also generated internally in a synchronous manner, for example during the reset process at startup of the system on chip SOC.
[0039] Critical information to be kept in the second domain V22 can be written by initiators from the first domain VI1, and the system on chip SOC includes in this respect an INTF interface circuit configured to transfer data and signals between the two domains VI1, V22.
[0040] The INTF interface circuit makes compatible, in particular according to the respective voltage-frequency pairs for each domain, the signals and data from the first domain V11 for the second domain V22, and possibly the signals and data from the second domain V22 for the first domain V11
[0041] Furthermore, the INTF interface circuit makes it possible to protect potentially critical data against corruption caused by an asynchronous reset occurring during transfer. Indeed, an asynchronous reset can cause metastable states in registers. In the metastable state of a register, a signal The output oscillates between the high state and the low state for a certain time and then converges to a random state.
[0042] From the point of view of compatibility between the first supply voltage VDD11 and the second supply voltage VDD22, the INTF interface circuit includes LS level shifting circuits configured to convert the logic level voltages of one of the two domains V11, V22 to the corresponding voltage of the other domain V22, V11.
[0043] Level shifting circuits typically have limited bandwidth, with in particular a low-pass effect, i.e. a cutoff of high frequencies, intrinsically by construction of level shifting circuits.
[0044] Thus, for example, a pulse extending over a nominal duration is able to pass through the LS level shift circuits normally without being filtered by the frequency cutoff effect, while a pulse extending over a duration less than the nominal duration may be filtered by the frequency cutoff effect and not pass through the LS level shift circuits.
[0045] For example, the nominal duration may correspond to an integer number N of cycles of the first clock signal CLK11, whereas a pulse extending over a smaller number of cycles of the first clock signal CLK11 (for example from Nl cycles) would be filtered and would not pass through the LS level shift circuits.
[0046] By "passing through the LS level shifting circuits", it is meant that the pulse is converted and communicated to the second domain V22 (in the case of a transmission of a pulse from the first digital domain V11 to the second digital domain V22); whereas by "not passing through the LS level shifting circuits", it is meant that the pulse is not converted and is not communicated to the second domain V22, because of the limited bandwidth of the LS level shifting circuits.
[0047] From the point of view of compatibility between the first frequency CLK11 and the second frequency CLK22, the INTF interface circuit includes in particular RDEP transfer elements, ADPT1 in the first domain V1, an FFSYNC synchronization circuit in the first domain V1, a CD_STRCHR conditional stretching circuit in the first domain VI1, and an RDEST destination register in the second domain V22.
[0048] Thus, the INTF interface circuit includes circuits in the first domain V11 and circuits in the second domain V22; however, the circuits belonging to the INTF interface circuit are not necessarily all reset by the reset signal which resets the domain which contains them.
[0049] Indeed, by "a circuit in the first domain (respectively second domain)", it is meant that this circuit belongs to the first domain (respectively to the second domain), that it is powered by the first supply voltage VDD11 (resp. the second supply voltage VDD22) and that its operation is timed by the first clock signal CLK11 (resp. the second clock signal CLK22), independently of the reset signal affecting these circuits.
[0050] Corollarily, by "the first domain Vil is configured to be reset by a first reset signal PADRST" it is understood that it is the circuits intended for the primary function of the first domain Vil that are affected by the first reset signal PADRST, and not necessarily the circuits belonging to the INTF interface circuit, in particular intended for the transfer of information between the first domain Vil and the second domain V22 (which is not the primary function of the first domain Vil).
[0051] The RDEP, ADPT1 transfer elements of the INTF interface circuit allow PWDAT, PADD data to be transferred from a starting register RDEP to a destination register RDEST; or to establish a handshake procedure with a CDC22 handshake signal originating from the second domain V22 and returned to the second domain V22 after a CDC11 pass through the first domain V1.
[0052] A CMD control circuit belonging to the first domain VI1 and configured to be reset by the first reset signal PADRST, allows the generation of a Wr_i control signal to be transmitted to the destination register RDEST in order to control (W_pls_sync) an input of the transferred data PWDAT, PADD from the starting register RDEP.
[0053] The control signal Wr_i is then communicated to the level shift circuit LS via the synchronization circuit FFSYNC and via the conditional stretching circuit CD_STRCHR.
[0054] The FFSYNC synchronization circuit, for transmitting the control signal Wr_i, may include a series of D-type flip-flops, in sufficient number to guarantee a propagation risk of metastability less than a mean time between failures specification of the system on chip SOC (usually designated by the acronym "MTBF" from the English terms "Mean Time Between Failures").
[0055] Thus, it will be noted that the control signal Wr_i is resynchronized Wr_i_resync over an integer number of cycles of the first clock signal CLK11, by the synchronization circuit FFSYNC.
[0056] From the point of view of protection against corruption caused by an asynchronous reset during the transfer, the INTF interface circuit is for example configured to implement measures 100, 200, 300 to ensure an absence of risk of corruption.
[0057] In the first measure 100, the transfer elements RDEP, ADPT1, as well as the FFSYNC synchronization circuit and the CD_STRCHR conditional stretching circuit are configured not to be reset by the first PADRST reset signal, unlike the other circuits in the first domain Vil.
[0058] In the second measure 200, the starting register RDEP is configured to capture the data to be transferred PWDAT, PADD in a single cycle of the first clock signal CLK11, and then store said data accDAT, accADD, for example in a D-type flip-flop, independently of the input channels PWDAT, PADD.
[0059] In the third measure 300, the CMD control circuit is configured to generate the control signal Wr_i, intended for the destination register RDEST, one cycle of the first clock signal CLK11 after the provision of said data PWDAT, PADD.
[0060] This ensures that data stored accDAT, accADD by the starting register RDEP, possibly corrupted by a PADRST reset occurring during the first transfer cycle, are not captured by the destination register RDEST (since the PADRST reset prevents the generation and transmission of the Wr_i control signal, and furthermore without risk of metastability either due to the FFSYNC synchronization circuit).
[0061] The CMD control circuit includes a control means, for example an FSM state machine, for generating the control signal Wr_i. For example, the FSM state machine is capable of controlling the transfer actions, and in particular generating the control signal Wr_i, as a function of input signals PWRITE, PS EL, PENABLE, to be from an "APB" bus (acronym for the common English terms "Advanced Peripheral Bus").
[0062] And, for example, from an operational signal PRDY of the APB protocol, and a cumulative condition between a falling edge of the operational signal shifted by one cycle PRDY_fe_d with an access validity signal AccVld, we obtain the triggering instant of the control signal Wr_i, whose pulse is initially generated on a single cycle of the first clock signal CLK11 by a D flip-flop clocked by the first clock signal CLK11.
[0063] The control signal Wr_i is for example finally obtained by a pulse stretching circuit STRCHR, configured to lengthen the initial pulse of the control signal to a duration long enough to pass through the voltage level shifting circuit LS, for example a duration of N cycles of the first clock signal CLK11.
[0064] For all useful purposes concerning the system-on-chip (SOC) and in particular the mechanisms of the INTF interface circuit mentioned above, a person skilled in the art may refer to to French patent application no. 2203375 filed on April 12, 2022, the entire content of which is incorporated into this description.
[0065] That being said, if a PADRST reset occurs during the lengthening of the initial pulse, during one of the Nl cycles following the first cycle, then the duration of the pulse of the control signal Wr_i is truncated and may not pass through the level shift circuit LS.
[0066] In fact, it is considered that N cycles of the first clock signal CLK11 correspond to the nominal duration suitable for the LS level shift circuit, if the pulses of the control signal which have a duration less than N cycles of the first clock signal CLK11 are filtered by the LS level shift circuit, and are not communicated to the second digital domain V22.
[0067] In this respect, the INTF interface circuit further includes, in the first domain VI1, a conditional pulse-stretching circuit CD_STRCHR at the input of the level-shifting circuit LS, and in this example at the output of the synchronization circuit FFSYNC. The conditional pulse-stretching circuit CD_STRCHR is configured to lengthen the pulse duration of the control signal Wr_i_resync to the nominal duration if the following conditions are true: the effective duration of the control signal Wr_i is shorter than the nominal duration, and the effective duration of the control signal Wr_i is non-zero.
[0068] Reference is made in this regard to figures 2 and 3.
[0069] Fig. 2 illustrates an example of an implementation of the CD_STRCHR pulse stretching conditional circuit, at the output of the FFSYNC synchronization circuit.
[0070] Fig. 3 is a time diagram illustrating the shape of internal signals of the operation of the CD_STRCHR pulse stretching conditional circuit of Fig. 2.
[0071] The example of a conditional pulse-stretching circuit CD_STRCHR describes in relation to figures 2 and 3 corresponds to the particular case where N=2, in an advantageous realization with the minimum number of logic gates to ensure the aforementioned conditional function, of extending the duration of the pulse of the control signal Wr_i_resync to the nominal duration.
[0072] The operation described in relation to [Fig.3] corresponds to the case where the first asynchronous reset signal PADRST is activated after the first cycle of the first clock signal CLK11 during the generation of the pulse Wr_i, and before having completed, in the second ("Nth") cycle of the first clock signal CLK11, said generation of the pulse Wr_i.
[0073] Thus, the pulse Wr_i entering the FFSYNC synchronization circuit has a duration of one cycle and a fraction of a cycle of the first clock signal CLK11. Due to the action of at least one of the D flip-flops of the synchronization circuit In FFSYNC, the resynchronized control signal Wr_i_resync lasts only one whole cycle of the first clock signal CLK11. Moreover, the resynchronized control signal Wr_i_resync is offset from the control signal Wr_i by a number of cycles corresponding to the number of flip-flops in the FFSYNC synchronization circuit, for example two cycles.
[0074] It will be noted that in the absence of the conditional pulse stretching circuit CD_STRCHR, such a situation is not protected by the implementation of the third measure 300, since the PADRST reset occurs after the first cycle, so that the accDAT, accADD data from the starting register RDEP are supposed to be entered by the destination register RDEST, whereas the duration of the pulse Wr_i is not long enough to pass through the level shift circuit LS, and said RDEST entry will therefore not be able to be commanded.
[0075] The CD_STRCHR pulse stretching conditional circuit of this example includes a first D flip-flop clocked by the first clock signal CLK11, a two-input AND gate, one of which is inverted, a second D flip-flop clocked by the first clock signal CLK11, a third D flip-flop clocked by the inverse of the first clock signal CLK11, and a three-input OR gate.
[0076] The first flip-flop D is intended to shift by one cycle of CLK11, the pulse of the resynchronized control signal Wr_i_resync, in the first output signal Wr_i_resync_s.
[0077] The AND gate is intended to generate a pulse Wr_i_resync_re of a duration of one cycle of CLK11 from a rising edge of the resynchronized control signal Wr_i_resync, taking as inputs the resynchronized control signal Wr_i_resync and, on the inverted input, the first output signal Wr_i_resync_s.
[0078] The second flip-flop D is intended to shift by one cycle of CLK11, the rising edge pulse Wr_i_resync_re, at the output of the AND gate, into the second output signal Wr_i_resync_re_s.
[0079] Thus, in this case, the resynchronized control signal Wr_i_resync and the second outgoing signal Wr_i_resync_re_s each last one cycle and are consecutive.
[0080] The resynchronized control signal Wr_i_resync and the second output signal Wr_i_resync_re_s are provided at the input of the OR gate.
[0081] Thus, the output of the OR gate includes an output pulse Wr_Vsw on said two consecutive cycles of the resynchronized control signal Wr_i_resync and the second Wr_i_resync_re_s.
[0082] It should be noted that in the "normal" case of this example, that is, when the resynchronized control signal Wr_i_resync is not truncated and lasts two full cycles (N=2), then the second output signal Wr_i_resync_re_s is generated at the same time that the second cycle of the resynchronized control signal Wr_i_resync, and the output of the OR gate is identical to the resynchronized control signal Wr_i_resync.
[0083] In addition, the third flip-flop D advantageously allows the rising edge pulse Wr_i_resync_re at the output of the AND gate to be shifted by half a cycle of CLK11, into a third output signal Wr_i_resync_re_nCLKl 1. Indeed, the third flip-flop is clocked by the inverse of the first clock signal CLK11 and therefore on the falling edges of the first clock signal CLK11.
[0084] The third output signal Wr_i_resync_re_nCLKl 1 is supplied at the input of the OR gate, with the resynchronized control signal Wr_i_resync and the second output signal Wr_i_resync_re_s.
[0085] Therefore, if there is a misalignment, i.e. a gap, between the resynchronized control signal Wr_i_resync and the second output signal Wr_i_resync_re_s (for example caused by a slightly longer propagation time in the routing of the second output signal Wr_i_resync_re_s), then the output Wr_Vsw will not have an abrupt transition caused by the change in input conditions at said gap, due to the presence at the input of the OR gate of the third output signal Wr_i_resync_re_nCLKl 1, which is by construction constant at that instant.
[0086] Furthermore, the CD_STRCHR pulse stretching conditional circuit can advantageously implement the first measure 100, that is to say, the CD_STRCHR pulse stretching conditional circuit is configured so as not to be reset by the first PADRST reset signal, unlike the other circuits in the first domain Vil.
[0087] For example, the CD_STRCHR pulse stretching conditional circuit can be configured to be reset by the second POR reset signal.
[0088] In this regard, all the D flip-flops of the CD_STRCHR pulse stretching conditional circuit are arranged to be reset by the same POR reset signal as the FFSYNC synchronization circuit.
[0089] Thus, in summary, when the first PADRST reset signal occurs after the first cycle, and before the last ("Nth") cycle, of the generation of the control signal pulse Wr_i by the STRCHR stretching circuit of the CMD control circuit, the conditional pulse stretching circuit CD_STRCHR ensures that the pulse will safely pass through the LS level shifting circuit.
[0090] And, when the first reset signal PADRST does not occur during the generation of the control signal pulse Wr_i, the conditional pulse stretching circuit CD_STRCHR has no impact on the shape of the pulse.
Claims
Demands
1. System on chip comprising a first digital domain (V1), a second digital domain (V22), and an interface circuit (INTF) comprising a level shifter (LS) circuit capable of converting a signal between the first digital domain (V1) and the second digital domain (V22), - the first digital domain (V1) comprising a control circuit (CMD) configured to generate a control signal (Wr_i) intended for the second digital domain (V22), the control signal comprising a pulse intended to have a nominal duration suitable for the level shifter (LS) circuit;- the interface circuit further comprising, in the first domain (VI1) at the input of the level shifting circuit (LS), a conditional pulse stretching circuit (CD_STRCHR) configured to lengthen the pulse duration of the control signal (Wr_i_resync) to the nominal duration if and only if the duration of the control signal is shorter than the nominal duration and non-zero.;
2. System on chip according to claim 1, wherein the control circuit (CMD) is configured to be reset by a first reset signal (PADRST), while the conditional pulse stretching circuit (CD_STRCHR) is configured not to be reset by the first reset signal (PADRST).
3. System on chip according to claim 2, wherein the first reset signal (PADRST) is an external asynchronous signal, while the conditional pulse stretching circuit (CD_STRCHR) is configured to be reset by a second internal synchronous reset signal (POR).
4. System-on-chip according to any one of the preceding claims, wherein the first digital domain (Vil) comprises a clock generator (CLKGEN11) configured to generate a first clock signal (CLK11), the nominal duration corresponding to a nominal number of cycles of the first clock signal (CLK11), the conditional pulse stretching circuit (CD_STRCHR) being configured to lengthen said pulse duration (Wr_i_resync), if the number of pulse cycles is less than the nominal number and greater than one.
5. System on chip according to claim 4, wherein the interface circuit further comprises, in the first domain, between the control circuit (FSM) and the conditional pulse stretching circuit (CD_STRCHR), a synchronization circuit (FFSYNC) configured to synchronize the control signal (Wr_i) so as to align the synchronized control signal (Wr_i_sync) with whole cycles of the first clock signal (CLK11).
6. A method for transferring a control signal between at least a first digital domain (VI1) and a second digital domain (V22) of a system-on-chip (SOC), comprising a generation, in the first digital domain (V1), of a control signal (Wr_i) intended for the second digital domain (V22) comprising a pulse intended to have a nominal duration suitable for a level-shifting (LS) circuit capable of converting a signal between the first digital domain (VI1) and the second digital domain (V22), the method further comprising, at the input of the level-shifting circuit (V1), an extension of the pulse duration of the control signal (Wr_i_resync) to the nominal duration if and only if the duration of the control signal is shorter than the nominal duration and non-zero.
7. A method according to claim 6, wherein a first reset signal (PADRST) causes a reset of the first domain (Vil) but does not cause a reset of a conditional pulse stretching circuit (CD_STRCHR) configured to perform said pulse duration stretching.
8. A method according to claim 7, wherein the first reset signal (PADRST) is an external asynchronous signal, while a second internal synchronous reset signal (POR) causes a reset of the conditional pulse stretching circuit (CD_STRCHR).
9. A method according to any one of claims 6 to 8, wherein the nominal duration corresponds to a nominal number of cycles of a first clock signal (CLK11) generated in the first domain (Vil), and the method comprises said pulse duration extension
10. (Wr_i_resync), if the number of cycles of the control signal pulse is less than the nominal number and greater than one. Method according to claim 9, further comprising a synchronization of the control signal (Wr_i) aligning the synchronized control signal (Wr_i_sync) with whole cycles of the first clock signal (CLK11).