HEMT transistor

Abstract

HEMT Transistor The present description relates to a HEMT transistor comprising: - a first semiconductor layer (13); - a gate (15) arranged on a first face of the first semiconductor layer (13); - a first passivation layer (17) made of a first material on the sides of the gate, the first passivation layer further extending over a first part of said face of the first semiconductor layer; and - a second passivation layer (19) made of a second material different from the first material on a second part of said face of the first semiconductor layer next to the first passivation layer. Figure for abstract: Fig. 1

Description

Title of the invention: HEMT transistor Technical field

[0001] The present description relates generally to the field of transistors and more particularly to the field of high electron mobility transistors also called HEMT (from the English "High Electron Mobility Transistor"). Prior art

[0002] HEMT transistors are based on a heterojunction on the surface of which a two-dimensional gas of electrons called 2DEG is formed.

[0003] There is a need for improvement of HEMT transistors and their manufacturing processes. Summary of the invention

[0004] For this, one embodiment provides a HEMT transistor comprising: - a first semiconductor layer; - a grid arranged on a first face of the first semiconductor layer; - a first passivation layer made of a first material on the sides of the gate, the first passivation layer further extending over a first part of said face of the first semiconductor layer; and - a second passivation layer made of a second material different from the first material on a second part of said face of the first semiconductor layer next to the first passivation layer.

[0005] According to one embodiment, the first semiconductor layer is based on gallium nitride.

[0006] According to one embodiment, the first semiconductor layer is made of aluminum-gallium nitride.

[0007] According to one embodiment, the first passivation layer is made of alumina.

[0008] According to one embodiment, the second passivation layer is made of nitride of aluminum.

[0009] According to one embodiment, the transistor comprises a second semiconductor layer in contact with a second face of the first semiconductor layer, opposite the first face.

[0010] According to one embodiment, the second semiconductor layer is made of gallium nitride.

[0011] According to one embodiment, the transistor comprises a source contact metallization and a drain contact metallization, arranged respectively on either side of the gate.

[0012] According to one embodiment, the passivation layer extends laterally from the gate towards the drain contact metallization, over only a portion of the surface between the gate and the drain contact metallization.

[0013] According to one embodiment, the passivation layer extends laterally from the gate to the source contact metallization.

[0014] According to one embodiment, the second passivation layer extends laterally from an edge of the first passivation layer located between the gate and the drain contact metallization, to the drain contact metallization.

[0015] According to one embodiment, the first passivation layer is covered with an insulation layer.

[0016] According to one embodiment, the second passivation layer covers the side of the insulating layer located between the gate and the drain contact metallization and extends over a portion of the insulating layer towards the gate.

[0017] Another embodiment provides a method of forming a HEMT transistor comprising the following successive steps: a) forming a first semiconductor layer; b) forming a grid on a first face of the first semiconductor layer; c) forming a first passivation layer of a first material on the sides of the gate, the first passivation layer further extending over a first portion of said face of the first semiconductor layer; and d) forming a second passivation layer made of a second material different from the first material on a second part of said face of the first semiconductor layer next to the first passivation layer. Brief description of the drawings

[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0019] [Fig.l] is a partial and schematic sectional view of an example of a HEMT transistor according to one embodiment;

[0020] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E], [Fig.2F], [Fig.2G], [Fig.2H] and [Fig.2I] are sectional views illustrating steps of an example of a method of manufacturing the HEMT transistor illustrated in [Fig.l]. Description of the embodiments

[0021] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0022] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the applications that the described HEMT transistors may have are not detailed, the embodiments being compatible with the usual applications of HEMT transistors. Here, we are particularly interested in the field of so-called power HEMT transistors, capable of withstanding relatively high voltages in the off state, for example voltages of the order of 100 to 650 volts.

[0023] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0024] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0025] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0026] [Fig.l] is a partial, schematic sectional view of an example of a HEMT transistor 11 according to one embodiment.

[0027] The HEMT transistor 11 comprises a first semiconductor layer 13, arranged on a second conductive layer 23. The semiconductor layer 13 is for example in contact, by its lower face, with the upper face of the conductive layer 23. By way of example, the stack comprising the semiconductor layer 13 and the semiconductor layer 23 rests on a substrate 21. The semiconductor layer 23 is for example in contact, by its lower face, with the upper face of the substrate 21. The interface between the first semiconductor layer 13 and the second semiconductor layer 23 defines a heterojunction on the surface of which a two-dimensional electron gas 2DEG also called an electron channel is formed.

[0028] The semiconductor layers 13 and 23 are for example made of III-V type semiconductor materials, for example based on gallium nitride (GaN). The semiconductor layer 13 is for example made of aluminum-gallium nitride (AlGaN). The semiconductor layer 23 is for example made of gallium nitride.

[0029] For example, the substrate 21 is made of a semiconductor material. The substrate 21 is for example made of silicon, or silicon carbide. Alternatively, the substrate 21 is made of aluminum nitride. The substrate 21 comprises for example, on the side of its face su upper, a buffer layer, not detailed in the figures, for example made of gallium nitride. The buffer layer is for example in contact, by its upper face, with the lower face of the semiconductor layer 23.

[0030] The HEMT transistor 11 comprises a gate 15 on the upper face of the semiconductor layer 13. The gate 15 is for example in contact, by its lower face, with the upper face of the semiconductor layer 13.

[0031] The grid 15 is for example made of a semiconductor material, for example a III-V type semiconductor material, for example gallium nitride, for example P-type doped.

[0032] By way of example, the HEMT transistor 11 further comprises a source contact metallization 29 and a drain contact metallization 31. By way of example, the contact metallizations 29 and 31 are based on titanium, titanium nitride and / or an alloy of aluminum and copper. The source 29 and drain 31 contact metallizations each define, for example, an ohmic contact with the semiconductor layer 13. The contact metallizations 29 and 31 are, for example, located on and in contact with the semiconductor layer 13, on either side of the gate 15.

[0033] The HEMT transistor 11 further comprises a first passivation layer 17 made of a first material covering the sides of the gate 15 and extending over a portion of the upper face of the first semiconductor layer 13. For example, the passivation layer 17 is in contact, by its lower face, with the upper face of the semiconductor layer 13. In the embodiment of [Fig. 1], the passivation layer 17 covers only a portion of the upper face of the semiconductor layer 13, located next to the gate 15, for example at the periphery of the gate 15. More particularly, in this example, the passivation layer 17 extends laterally from the gate 15 in the direction of the drain contact metallization 31, over only a portion of the surface between the gate 15 and the drain contact metallization 31. In other words, the passivation layer 17 does not extend to the drain contact metallization 17.In this example, the passivation layer 17 further extends laterally from the gate 15 to the source contact metallization 29.

[0034] By way of example, the passivation layer 17 further covers a peripheral portion of the upper face of the grid 15.

[0035] The HEMT transistor 11 further comprises a second passivation layer 19 made of a second material different from the material of the layer 17. The second passivation layer 19 is arranged on another part of the upper face of the semiconductor layer 13. For example, the passivation layer 19 is in contact with the upper face of the first semiconductor layer 13. More precisely, the passivation layer 19 is formed next to the passivation layer 17 and covers a portion of the semiconductor layer 13 not covered by the passivation layer 17. The passivation layers 17 and 19 are for example in contact by their sides. In the example shown, the passivation layer 19 extends laterally from the edge of the passivation layer 17 located between the gate 15 and the drain contact metallization 31, to the drain contact metallization 31.

[0036] The passivation layers 17 and 19 each have, for example, a thickness of between 2 nm and 20 nm, for example between 5 nm and 10 nm. The passivation layers 17 and 19 have, for example, substantially the same thickness.

[0037] The passivation layer 17 is for example made of a dielectric material, for example alumina (Al2O3) or difluorooxonium (Hf2O). The passivation layer 19 is for example made of another dielectric material, for example aluminum nitride (AIN) or silicon nitride (SiN).

[0038] By way of example, the grid 15 is topped with a layer 25, optional, made of a metallic material, for example based on titanium nitride. The layer 25 is for example in contact with the grid 15. The metallic layer 25 covers for example the entire surface of the upper face of the grid 15. As a variant, the metallic layer 25 extends over only a central part of the upper surface of the grid 15, so that a peripheral part of the upper face of the grid 15 is not covered by the metallic layer 25. The passivation layer 17 extends for example laterally to the metallic layer 25.

[0039] The layer 25 is for example topped by a gate contact metallization 27 and is, for example, in contact with it. By way of example, the gate contact metallization 27 is based on titanium nitride and / or an alloy of aluminum and copper.

[0040] The HEMT transistor 11 comprises, for example, several levels of insulating layers in, and for example on, which metallizations are formed.

[0041] By way of example, the HEMT transistor 11 comprises a first insulating layer 33 on and in contact with the upper face of the passivation layer 17. By way of example, the insulating layer 33 covers the entire surface of the passivation layer 17, and does not cover the passivation layer 19. The insulating layer 33 is for example open opposite a central part of the upper face of the gate 15 so as to be crossed by the gate contact metallization 27. The insulating layer 33 is for example made of a dielectric material, for example an oxide, for example silicon dioxide (SiO2).

[0042] By way of example, the passivation layer 19 covers the flank of the insulating layer 33 located between the gate 15 and the drain contact metallization 31, and extends over a portion of the insulating layer 33 in the direction of the gate 15. Thus, starting from the drain contact metallization 31, the passivation layer 19 covers the portion of the upper face of the semiconductor layer 13 located between the drain contact metallization 31 and the passivation layer 17, then extends above the insulating layer 33, so that a part of the passivation layer 19 is located opposite the passivation layer 17 and separated from the latter by the insulating layer 33.

[0043] By way of example, the HEMT transistor 11 comprises a second insulating layer 35 on and in contact with the upper face of the passivation layer 19. By way of example, the insulating layer 35 has a flank in contact with the drain contact metallization 31 and extends towards the source contact metallization 29. By way of example, the insulating layer 35 covers, for example exclusively, the entire surface of the passivation layer 19. The insulating layer 35 thus extends for example over the part of the upper face of the semiconductor layer 13 not covered by the insulating layer 33 and over the peripheral part of the insulating layer 33. The insulating layer 35 is for example made of a dielectric material, for example silicon nitride (SiN) or an oxide, for example silicon dioxide (SiO2).

[0044] By way of example, the HEMT transistor 11 comprises a region 37 extending simultaneously over a portion of the surface of the first insulating layer 33 and over a portion of the surface of the second insulating layer 35. The metal region 37 is therefore arranged on two different levels of insulating layers. By way of example, the metal region 37 is based on titanium nitride and / or an alloy of aluminum and copper. The metal region 37 is for example made of the same material as the gate contact metallization 27.

[0045] The HEMT transistor 11 may comprise a third insulating layer 39 covering the entire structure with the exception of the source 29 and drain 31 contact metallizations. The third insulating layer 39 is, for example, made of the same material as the insulating layers 33 and 35. The HEMT transistor 11 illustrated in [Fig.l] comprises a metal region 41 formed on the insulating layer 39. For example, the metal region 41 is made of the same material as the metal region 37.

[0046] The metal regions 37 and 41 have for example the function of modifying the profile of the distribution of the electric field of the edge of the gate, located on the drain side (the right edge of the gate in [Fig.l]), and of reducing the peak of the critical electric field, thus increasing the avalanche voltage. The metal regions 37 and 41 are for example called "field plates".

[0047] In the transistor of [Fig.l], the 2DEG channel is for example normally closed ("normally-off" in English), that is to say it is interrupted under the gate 15 which prevents the circulation of a current between the source and the drain of the transistor. We then say that the transistor is in the blocked state. The channel can be reestablished (that is to say made conducting) by the polarization of the gate 15. In this case, a current can be established between the source and drain of the transistor. The transistor is then said to be in the closed or on state. The described embodiments can also be applied to normally-on transistors.

[0048] The presence of the passivation layers 17 and 19 allows the protection of the upper surface of the semiconductor layer 13 on which dangling connections may be present and likely to generate leakage currents and / or a reduction in the voltage resistance of the transistor. The passivation layers 17 and 19 fill these connections in order to make the surface of the semiconductor layer 13 electrically inactive.

[0049] The passivation layers 17 and 19 also make it possible to protect the semiconductor layer 13 against oxidation and to improve its surface state to which the 2DEG channel is sensitive.

[0050] In the embodiment of [Fig. 1], the provision of two passivation layers 17 and 19 of distinct natures between the gate and the drain of the transistor advantageously makes it possible to improve the compromise between the resistance in the on state of the transistor and the leakage currents in the off state.

[0051] The first passivation layer 17, and more particularly the part of the passivation layer 17 located on the sides of the grid 15, makes it possible to increase the resistivity of the 2DEG channel under and around the grid, which causes a reduction in the electric field formed at the corner of the grid 15, and thus a reduction in the leakage currents.

[0052] The second passivation layer 19 allows the supply of positive charges to the interface between the passivation layer and the first semiconductor layer 13, which locally increases the electronic density in the 2DEG channel, and thus locally reduces the resistivity of the 2DEG channel.

[0053] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E], [Fig.2F], [Fig.2G], [Fig.2H] and [Fig.2I] are sectional views illustrating successive steps of an example of a method for manufacturing the HEMT transistor illustrated in [Fig.l].

[0054] [Fig.2A] illustrates a starting structure comprising, in order, from the lower face of the structure, the substrate 21, the second semiconductor layer 23 and the first semiconductor layer 13. The starting structure further comprises a gate layer 15 topped by the metal layer 25. In the starting structure illustrated in [Fig.2A], the layers 23, 13, 15 and 25 each extend continuously and with a substantially uniform thickness over the entire upper surface of the substrate 21.

[0055] [Fig.2B] illustrates a structure obtained at the end of a localized etching step of the gate layer 15 and the metal layer 25 so as to retain only a portion of each layer forming the gate stack of the transistor of [Fig.1].

[0056] During this step, the metal layer 25 is etched, for example, by a plasma etching process, for example by a chlorine-based plasma etching process, for example by plasma etching in boron trichloride (BC13).

[0057] During this step, the grid 15 is further etched, for example by a plasma etching process, for example by a chlorine-based plasma etching process, for example by plasma etching in boron trichloride (BC13) and dioxygen (O2).

[0058] For example, the grid 15 and the layer 25 are etched through the same mask. At the end of this step, the grid 15 and the layer 25 are thus aligned, that is to say that their sides are aligned.

[0059] The steps of etching the grid 15 and the layer 25 are for example carried out simultaneously, that is to say they are carried out within the same etching chamber. As a variant, the steps of etching the grid 15 and the layer 25 are carried out successively one after the other.

[0060] The layer 25 may, for example, undergo another etching, for example a wet etching, so as to remove a peripheral part and thus uncover a peripheral part of the upper face of the gate 15. This etching is for example carried out through a hard mask, for example made of silicon nitride.

[0061] These etching steps are for example followed by a step of cleaning the upper face of the structure so as to remove for example the residues from the etching mask(s) and the impurities from the etching of the layer 25 and the grid 15. The cleaning of the structure comprises for example a stripping step using oxygen and nitrogen (N2) plasma. The cleaning of the structure may further comprise a step of removing organic residues using a solvent.

[0062] [Fig.2C] illustrates a structure obtained at the end of a step of forming the passivation layer 17 and the insulating layer 33 on the upper face of the structure illustrated in [Fig.2B].

[0063] During this step, the full plate passivation layer 17 is first formed, so that it covers the entire upper face of the structure illustrated in [Fig.2B].

[0064] The passivation layer 17 is, for example, formed in contact with the upper face of the semiconductor layer 13, the sides of the gate 15 and the sides and the upper face of the layer 25.

[0065] The passivation layer 17 is for example formed by a thin layer deposition process, for example an atomic layer deposition or ALD (from the English "Atomic Layer Deposition") process. For example, the deposition process of the passivation layer 17 is plasma-assisted. At the end of this step, the passivation layer 17 has a thickness for example between 1 nm and 10 nm, for example between 1.5 nm and 5 nm, for example of the order of 2.5 nm.

[0066] In a second step, in this example, the full-plate insulating layer 33 is formed so that it covers the entire upper face of the passivation layer 17. The insulating layer 33 is, for example, formed in contact with the passivation layer 17. The insulating layer 33 is, for example, formed by a plasma-enhanced chemical vapor deposition (PECVD) process. At the end of this step, the insulating layer 33 has a thickness, for example, between 150 nm and 400 nm, for example between 200 nm and 350 nm, for example of the order of 300 nm.

[0067] By way of example, the steps of depositing the passivation layer 17 and the insulating layer 33 are preceded by one or more steps of preparing the surface of the structure illustrated in [Fig.2B]. The preparation of the surface of the structure illustrated in [Fig.2B] may comprise cleaning consisting, for example, of chemical cleaning using acid, for example hydrogen chloride (HCl) and hydrogen fluoride (HF). The preparation of the surface of the structure illustrated in [Fig.2B] may, in addition, comprise cleaning consisting, for example, of surface oxidation. The passivation layer 17 will thus be formed in contact with an oxide film, itself formed in contact with the upper face of the layer 13.

[0068] [Fig.2D] illustrates a structure obtained at the end of a step of etching the passivation layer 19 and the insulating layer 33.

[0069] More particularly, during this step, the passivation layer 17 and the insulating layer 33 opposite a part of the semiconductor layer 13 are removed. For example, the layers 17 and 33 are kept next to the gate 15, and removed outside the periphery of the gate 15, here in a part located to the right of the gate 15.

[0070] For example, the removal of layers 17 and 33 is carried out by plasma etching, for example based on fluorine, for example based on carbon tetrafluoride (CF4).

[0071] The etching of layers 17 and 33 is for example selective and does not etch the gallium nitride semiconductor layer 13. The etching of layers 17 and 33 then stops with the unveiling of the upper face of layer 13.

[0072] These etching steps are for example followed by a step of cleaning the upper face of the structure for example similarly to what has been described in relation to [Fig.2B].

[0073] [Fig.2E] illustrates a structure obtained at the end of a step of forming the passivation layer 19 and the insulating layer 35 on the upper face of the structure illustrated in [Fig.2D].

[0074] During this step, the full plate passivation layer 19 is first formed, so that it covers the entire upper face of the structure illustrated in [Fig.2D].

[0075] The passivation layer 19 is, for example, formed in contact with the upper face of the insulating layer 33 and the part of the semiconductor layer 13 not covered by the passivation layer 17. By way of example, the passivation layer 19 also covers the etched flank of the layers 17 and 33.

[0076] The passivation layer 19 is for example formed by a thin layer deposition process, for example an atomic layer deposition or ALD (from the English "Atomic Layer Deposition") process. For example, the deposition process of the passivation layer 19 is plasma-assisted. At the end of this step, the passivation layer 19 has a thickness for example between 1 nm and 10 nm, for example between 2 nm and 8 nm, for example of the order of 5 nm.

[0077] In a second step, the full-plate insulating layer 35 is formed so that it covers the entire upper face of the passivation layer 19. The insulating layer 35 is, for example, formed in contact with the passivation layer 19. The insulating layer 35 is, for example, formed by a method identical to the method for forming the layer 33 described in relation to [Fig. 2C]. At the end of this step, the insulating layer 35 has a thickness, for example, between 150 nm and 400 nm, for example between 200 nm and 350 nm, for example of the order of 300 nm.

[0078] By way of example, the steps of depositing the passivation layer 19 and the insulating layer 35 are preceded by one or more steps of preparing the surface of the structure illustrated in [Fig.2D] similarly to what has been described in relation to [Fig.2C].

[0079] [Fig.2F] illustrates a structure obtained at the end of a step of etching layers 19 and 35 of the structure illustrated in [Fig.2E].

[0080] More particularly, during this step, the passivation layer 19 and the insulating layer 35 are removed opposite the gate 15 and opposite a peripheral part of the gate 15. In other words, during this step, a part of the layers 19 and 33 is removed so that, at the end of this step, the passivation layer 19 and the insulating layer 35 cover the part of the semiconductor layer 13 not covered by the passivation layer 17, the side of the insulating layer 33, here located to the right of the gate 15, and so that they extend over a part of the insulating layer 33 in the direction of the gate 15, without reaching the gate 15.

[0081] By way of example, the removal of layers 19 and 35 is carried out by a method similar to the method of etching layers 17 and 33 described in relation to [Fig.2D].

[0082] The removal of layers 19 and 33 is for example followed by a step of cleaning the upper face of the structure, for example similarly to what has been described in relation to [Fig.2B].

[0083] [Fig.2G] illustrates a structure obtained at the end of a step of opening the layers 17 and 33 opposite grid 15 of the structure illustrated in [Fig.2F].

[0084] More particularly, during this step, the passivation layer 17 and the insulating layer 33 opposite a central part of the upper face of the grid 15 are removed.

[0085] For example, the removal of layers 17 and 33 is carried out by plasma etching, for example based on fluorine, for example based on carbon tetrafluoride (CF4).

[0086] The etching of layers 17 and 33 is for example non-selective with respect to layer 25, the etching then stops with the unveiling of the upper face of layer 25. The partial removal of layers 17 and 33 is for example followed by a step of cleaning the upper face of the structure, for example similarly to what has been described in relation to [Fig.2B].

[0087] [Fig.2H] illustrates a structure obtained at the end of a step of forming the metallization 27 and the region 37 on the upper face of the structure illustrated in [Fig.2G],

[0088] During this step, for example, the gate contact metallization 27 is formed in the opening formed in the layers 17 and 33 opposite the central part of the gate 15. By way of example, the gate contact metallization 27 is formed on and in contact with the layer 25. By way of example, during this step, the region 37 is further formed simultaneously on a part of the surface of the first insulating layer 33 and on a part of the surface of the second insulating layer 35. The gate contact metallization 27 and the region 37 are, for example, formed by deposition of one or more layers of a metallic material followed by an etching step.

[0089] By way of example, the step of forming the metallization of gate contact 27 and region 37 is preceded by a step of preparing the surface of the structure illustrated in [Fig.2G], consisting for example of chemical cleaning using acid, for example hydrogen chloride (HCl).

[0090] [Fig.21] illustrates a structure obtained at the end of a step of forming the insulating layer 39 on the upper face of the structure illustrated in [Fig.2H].

[0091] During this step, for example, the full-plate insulating layer 39 is formed so that it covers the entire upper face of the structure illustrated in [Fig.2H], i.e. the upper face and the sides of the gate contact metallization 27 and of the region 37, a portion of the layer 33 and a portion of the layer 35. The insulating layer 39 is for example formed by a method identical to the method for forming the layer 33 described in relation to [Fig.2C]. At the end of this step, the insulating layer 39 has a thickness for example between 150 nm and 400 nm, for example between 200 nm and 350 nm, for example of the order of 300 nm.

[0092] At the end of this step, the ohmic contacts and more particularly the source 29 and drain 31 contact metallizations are, for example, formed so as to form the structure illustrated in [Fig.l].

[0093] For this, openings intended to receive the source 29 and drain 31 contact metallizations are, in a first step, created in the layers 33 and 35. The openings are for example formed by a plasma etching process, for example based on fluorine, for example based on carbon tetrafluoride (CF4). The aforementioned etching is for example selective and does not etch the gallium nitride semiconductor layer 13. The etching of the layers 33 and 35 thus stops when the upper face of the layer 13 is revealed. The step of forming the openings intended to receive the contact metallizations 29 and 31 is for example followed by a step of cleaning the upper face of the structure, for example similarly to what has been described in relation to [Fig.2B].

[0094] By way of example, a step of preparing the surface of the upper face of the layer 13 in the openings may be provided. This step consists, for example, of chemical cleaning using acid, for example hydrogen chloride (HCl).

[0095] In a second step, the source 29 and drain 31 contact metallizations are, for example, formed in the previously made openings and the region 41 is, for example, formed on the upper face of the layer 39. The metallizations 29, 31 and the region 41 are, for example, formed by deposition of one or more layers of a metallic material followed by an etching step.

[0096] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0097] In particular, it may be provided that the ohmic contact metallizations, for example the source and drain contact metallizations, are formed before the formation of the gate contact metallization.

[0098] Furthermore, although the embodiments and implementations have been described with a passivation layer 19 made of aluminum nitride, they are not limited to this particular example, the passivation layer 19 being able to be made of another dielectric material carrying positive charges.

[0099] Furthermore, although an exemplary embodiment has been described above in which the gate 15 of the transistor is in contact with the upper face of the upper semiconductor layer 13, as a variant, the gate 15 may be separated from the semiconductor layer 13 by a gate insulator layer.

[0100] Finally, the embodiments are not limited to the examples of numerical values ​​or to the examples of materials mentioned in the present description.

[0101] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given below. above.

Claims

Claims

1. HEMT transistor comprising: - a first semiconductor layer (13); - a gate (15) arranged on a first face of the first semiconductor layer (13); - a first passivation layer (17) made of a first material on the sides of the gate, the first passivation layer further extending over a first part of said face of the first semiconductor layer; and - a second passivation layer (19) made of a second material different from the first material on a second part of said face of the first semiconductor layer next to the first passivation layer, wherein the first passivation layer (17) has a thickness of between 1 and 10 nm, and the second passivation layer (19) has a thickness of between 1 and 10 nm.

2. A transistor according to claim 1, wherein the first semiconductor layer (13) is based on gallium nitride.

3. A transistor according to claim 2, wherein the first semiconductor layer (13) is aluminum gallium nitride.

4. A transistor according to any one of claims 1 to 3, wherein the first passivation layer (17) is made of alumina.

5. A transistor according to any one of claims 1 to 4, wherein the second passivation layer (19) is made of aluminum nitride.

6. Transistor according to any one of claims 1 to 5, comprising a second semiconductor layer (23) in contact with a second face of the first semiconductor layer (13), opposite the first face.

7. A transistor according to claim 6, wherein the second semiconductor layer (23) is gallium nitride.

8. Transistor according to any one of claims 1 to 7, comprising a source contact metallization (29) and a drain contact metallization (31), arranged respectively on either side of the gate (15).

9. A transistor according to claim 8, wherein the passivation layer (17) extends laterally from the gate (15) towards the drain contact metallization (31), over only a portion of the surface between the grid (15) and the drain contact metallization (31).

10. A transistor according to claim 8 or 9, wherein the passivation layer (17) extends laterally from the gate (15) to the source contact metallization (29).

11. A transistor according to any one of claims 8 to 10, wherein the second passivation layer (19) extends laterally from an edge of the first passivation layer (17) located between the gate (15) and the drain contact metallization (31), to the drain contact metallization (31).

12. A transistor according to any one of claims 1 to 11, wherein the first passivation layer (17) is covered with an insulation layer (33).

13. A transistor according to claim 12, wherein the second passivation layer (19) covers the flank of the insulating layer (33) located between the gate (15) and the drain contact metallization (31) and extends over a portion of the insulating layer (33) towards the gate (15).

14. A method of forming a HEMT transistor comprising the following successive steps: a) forming a first semiconductor layer (13); b) forming a gate (15) on a first face of the first semiconductor layer (13); c) forming, by ALD deposition, a first passivation layer (17) made of a first material on the sides of the gate, the first passivation layer further extending over a first portion of said face of the first semiconductor layer; and d) forming, by ALD deposition, a second passivation layer (19) made of a second material different from the first material on a second portion of said face of the first semiconductor layer next to the first passivation layer.

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