Device for measuring the power current delivered by a power FET transistor

Abstract

Device for measuring power current delivered by a power FET. This description relates to a device (100) for measuring power current delivered by a main power FET (102), comprising: a current-measuring power FET (110) coupled to the main FET; first and second FETs (114, 116) whose gates are coupled together, the first FET being coupled to the current-measuring FET, wherein a source / drain electrode (122) of the second FET is coupled to a source / drain electrode (118) of the first FET, or a source / drain electrode (122) of the second FET is coupled to a source / drain electrode (108) of the main FET or to a voltage source or load external to the device, and source / drain electrodes (124, 126) of the first and second FETs are coupled together. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Device for measuring the power current delivered by a power FET transistor. Technical field

[0001] The present description relates in general to a device for measuring a power current delivered by a power FET transistor. Previous technique

[0002] A measurement of the current delivered by a power FET transistor driving an electrical load can be implemented in particular to efficiently control the electrical load, diagnose a problem on the load, or even to protect the load and the circuit to which it belongs.

[0003] To measure the current delivered by a power FET transistor driving an electric load, it is possible to use another power FET transistor dedicated to this measurement, and coupled in a branch of the circuit parallel to that comprising the main power FET transistor.

[0004] In order to ensure that the current delivered by the measurement FET is very low compared to the current delivered by the main power FET, the measurement FET is constructed with a semiconductor surface area much smaller than that of the main power FET. The ratio of the semiconductor surface area of ​​the main power FET to that of the measurement FET can be chosen, in particular, according to the functions to be performed by the power circuit in which the main power transistor is located and the desired power current values.

[0005] The characteristics of the measurement FET transistor, in particular the form factor, can be optimized at the level of each of its regions in order to avoid the problems encountered with power transistors of too small dimensions (difference in dynamic behavior compared to that expected, modification of the response of the transistor as a function of the operating temperature) and which are due in particular to edge effects and variations in the form factor of the edge and corner cells of the transistor. Summary of the invention

[0006] There is a need to propose a device for measuring a power current delivered by a main power FET transistor that does not have the disadvantages of existing solutions.

[0007] A particular embodiment addresses at least some of these problems and provides a device for measuring a power current intended to be delivered by a main power FET transistor, comprising at least:

[0008] - a current-measuring power FET transistor comprising a first source or drain electrode configured to be coupled to a first source or drain electrode of the main power FET transistor;

[0009] - of the first and second FET transistors whose gates are electrically coupled three-fold between them, a first source or drain electrode of the first FET transistor being coupled to a second source or drain electrode of the current-measuring power FET transistor,

[0010] wherein a first source or drain electrode of the second FET transistor is coupled to the first source or drain electrode of the first FET transistor, or

[0011] wherein the first source or drain electrode of the second FET transistor is configured to be coupled to a second source or drain electrode of the primary power FET transistor or to a voltage source or load external to the device, and the second source or drain electrodes of the first and second FET transistors are electrically coupled to each other.

[0012] According to a particular embodiment, a semiconductor area of ​​the current-measuring power FET transistor and channel widths of the first and second FET transistors are such that the value of a ratio between a load current intended to be delivered on the second source or drain electrode of the main power FET transistor and an output current intended to be delivered on the second source or drain electrode of the first FET transistor is different from that of a ratio between a semiconductor area of ​​the main power FET transistor and the semiconductor area of ​​the current-measuring power FET transistor.

[0013] According to a particular embodiment, the current measurement power FET transistor is of the VDMOSFET type, and the first and second FET transistors are of the MOSFET type.

[0014] According to a particular embodiment, the first and second FET transistors have different channel widths from each other.

[0015] According to a particular embodiment, the device further comprises a comparator having a first input configured to be coupled to the second source or drain electrode of the main power FET transistor, a second input coupled to the second source or drain electrode of the current measurement power FET transistor, and an output coupled to the gates of the first and second FET transistors.

[0016] According to a particular embodiment, the device further comprises at least one third FET transistor whose gate is coupled to the gates of the first and second FET transistors and whose first source or drain electrode is coupled to the first source or drain electrode of the first FET transistor or to the second source or drain electrode of the main power FET transistor.

[0017] According to a particular embodiment, the device further comprises:

[0018] - a fourth FET transistor of which a first source or drain electrode is coupled to the second source or drain electrode of the current-measuring power FET transistor, and of which a second source or drain electrode is coupled to the first source or drain electrode of the first FET transistor;

[0019] - a comparator having a first input coupled to the second electrode of source or drain of the current-measuring power FET transistor, a second input configured to be coupled to the second source or drain electrode of the main power FET transistor, and an output coupled to the gate of the fourth FET transistor.

[0020] In a particular embodiment, the first and second FET transistors are mounted in current mirror.

[0021] According to a particular embodiment:

[0022] - the first and second FET transistors are of type P;

[0023] - the gates of the first and second FET transistors are coupled to the second source and drain electrode of the first FET transistor;

[0024] - the first source or drain electrode of the second FET transistor is coupled to the first source or drain electrode of the first FET transistor.

[0025] In a particular embodiment:

[0026] - the first and second FET transistors are of type N;

[0027] - the gates of the first and second FET transistors are coupled to the first source and drain electrode of the first FET transistor;

[0028] - the second source or drain electrodes of the first and second transistors FETs are electrically coupled to each other.

[0029] According to a particular embodiment, a power control circuit for an electric load is proposed, comprising at least:

[0030] - a main power FET transistor comprising a first electrode of source or drain configured to be coupled to an electrical power source and a second source or drain electrode configured to be coupled to an electrical load terminal;

[0031] - a device for measuring a power current delivered by the FET transistor of main power as described above.

[0032] In a particular embodiment, the main power FET transistor and the current measurement power FET transistor are of the same type of conductivity.

[0033] According to a particular embodiment, a method for making a power control circuit of an electric load, comprising at least one embodiment of a main power FET transistor including a first source or drain electrode configured to be coupled to an electric power source and a second source or drain electrode configured to be coupled to a terminal of the electric load, and a device for measuring a power current delivered by the main power FET transistor as described above.

[0034] According to a particular embodiment, the method further comprises, prior to the realization of the main power FET transistor and the device for measuring the power current delivered by the main power FET transistor,a step of determining the semiconductor area of ​​the current-measuring power FET and the channel widths of the first and second FETs of the power current-measuring device delivered by the main power FET such that the value of a ratio between a load current intended to be delivered to the second source or drain electrode of the main power FET and an output current intended to be delivered to the second source or drain electrode of the first FET is different from that of a ratio between a semiconductor area of ​​the main power FET and the semiconductor area of ​​the current-measuring power FET;

[0035] and at least the current-measuring power FET and the first and second FETs of the device are then made according to the semiconductor surface area of ​​the current-measuring power FET and the channel widths of the first and second FETs previously determined. Brief description of the drawings

[0036] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0037] - Figure 1 schematically represents an example of the embodiment of a device measurement of a power current delivered by a main power FET transistor, according to a first embodiment;

[0038] - Figure 2 schematically represents a variant embodiment of the device measurement of a power current delivered by a main power FET transistor, according to the first embodiment;

[0039] - Figure 3 schematically represents an example of the embodiment of a device measurement of a power current delivered by a main power FET transistor, according to a second embodiment;

[0040] - Figure 4 schematically represents an example of an embodiment of the device measurement of a power current delivered by a main power FET transistor, according to a third embodiment;

[0041] - Figure 5 schematically represents an example of the embodiment of a device measurement of a power current delivered by a main power FET transistor, according to a fourth embodiment;

[0042] - Figure 6 schematically represents a variant embodiment of the device measurement of a power current delivered by a main power FET transistor, according to the fourth embodiment;

[0043] - Figure 7 schematically represents the steps in a process for producing a device for measuring a power current delivered by a main power FET transistor. Description of the implementation methods

[0044] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0045] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the various transistors and the comparator of the power current measurement device are not detailed. A person skilled in the art will be able to implement these elements in detail from the functional description given here.

[0046] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements linked or coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0047] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0048] In all the embodiments described, for each transistor, the first and second source or drain electrodes correspond to two different electrodes of the same transistor, one of them corresponding to the source electrode and the other to the drain electrode.

[0049] A first example of a device 100 for measuring a power current delivered by a main power FET transistor 102 according to a first embodiment is described below in relation to [Fig.1].

[0050] In this first embodiment, transistor 102 supplies an electrical load 104 by delivering a charging current called "I_load". For example, The electrical load 104 corresponds to a motor, lamp, or any other electrical component intended to be powered by a high-power electric current. The term "high-power electric current," which applies to the charging current delivered by transistor 102, refers, for example, to an electric current with an intensity ranging from a few milliamperes to several tens of amperes, this value depending on the size of transistor 102.

[0051] Transistor 102 and device 100 are, for example, part of a power control circuit 1000, the other components of which (converter, regulator, etc.) are not visible in [Fig. 1]. In the example of [Fig. 1], the power control circuit 1000 is of the "High Side" type, that is, it corresponds to a power control circuit interposed between the electrical load 104 and the positive supply electrical potential of this electrical load 104. Thus, transistor 102 has a first source or drain electrode 106 coupled to a supply electrical potential "+V", and a second source or drain electrode 108 coupled to a terminal of the electrical load 104 and to which the current I_load is delivered. Transistor 102 is intended to receive on its gate a signal controlling the electrical supply of the load 104.

[0052] In the first embodiment of [Fig.1], the transistor 102 is of type N. The first electrode 106 therefore corresponds to the drain of the transistor 102 and the second electrode 108 corresponds to the source of the transistor 102.

[0053] The device 100 includes a current-measuring power FET 110 comprising a first source or drain electrode 112 coupled to the first electrode 106 of transistor 102, and therefore to the supply electrical potential +V. Transistor 110 is intended to receive on its gate the same signal as that applied to the gate of transistor 102. Transistors 102 and 110 are therefore switched on or off simultaneously.

[0054] In the embodiment shown in [Fig.1], transistor 110 is of type N, and therefore of the same type as transistor 102. The first electrode 112 therefore corresponds to the drain of transistor 110.

[0055] The device 100 also includes first and second FET transistors, respectively referenced 114 and 116, which, unlike transistors 102 and 110, are not power transistors. A first source or drain electrode 118 of transistor 114 is coupled to a second source or drain electrode 120 of transistor 110, i.e., the source of transistor 110 in the embodiment described here.

[0056] In the embodiment shown in [Fig. 1], a first source or drain electrode 122 of transistor 116 is coupled to the first electrode 118 of transistor 114. Transistor 114 also includes a second source or drain electrode 124, on which a measurement current called "Isense" is intended to be delivered. The transistor 116 also includes a second source or drain electrode 126, on which a current is intended to be delivered, the characteristics of which are detailed later.

[0057] In the embodiment example of [Fig. 1], the transistors 114, 116 are of type P, and therefore the first electrodes 118, 122 correspond to the sources of these transistors 114, 116 and the second electrodes 124, 126 correspond to the drains of these transistors 114, 116.

[0058] In this first embodiment, the device 100 also includes a comparator 128 with a first input 130 coupled to the second electrode 108 of transistor 102, a second input 132 coupled to the second electrode 120 of transistor 110, and an output 134 coupled to the gates of transistors 114 and 116, which are therefore electrically coupled to each other. In this configuration, the VGs voltages of transistors 114 and 116 are thus identical.

[0059] The transistors 110, 114, 116 of the device 100 are made with a semiconductor surface of the transistor 110 and channel widths of the transistors 114, 116 which are such that the value of a ratio K_target = I_load / Isense is different from that of a ratio Kref between a semiconductor surface of the transistor 102 and the semiconductor surface of the transistor 110.

[0060] In the embodiment example of [Fig.1], transistors 110, 114, 116 are dimensioned such that the value of the ratio K_target is greater than that of the ratio Kref between the semiconductor surfaces of transistors 102 and 110. Transistor 110 therefore delivers, on its second electrode 120, a current Isense_ref = I_load / Kref of a value greater than that of the current Isense.

[0061] Obtaining the Isense current from the Isense_ref current is possible because transistors 114 and 116 both receive the Isense_ref current as input on their first electrode 118, 122 and deliver a portion of this Isense_ref current on their second electrode 124, 126. Transistor 114 has a channel width called "W1" and transistor 116 has a channel width called "W2," which are such that W2 = K * W1, with K a real number greater than 0. In the embodiment shown in [Fig. 1], K corresponds to an integer greater than or equal to 1. According to a particular embodiment, transistors 114 and 116 may have different channel widths, meaning that the value of K is not equal to 1, and for example, greater than 1.

[0062] The current Isense delivered to the second electrode 124 of transistor 114 is therefore such that Isense = I_load / K_target with K_target = Kref*(l+K), and the current delivered to the second electrode 126 of transistor 116 is therefore equal to K*Isense. These currents satisfy the relation Isense_ref = (l+K)*Isense.

[0063] From the measurement current Isense obtained, and knowing the values ​​of the ratios Kref and K, it is therefore possible to determine the value of the current I_load. The measurement of the current Isense and the calculation of the current I_load can be carried out by elements of the device 100 not visible in [Fig. 1].

[0064] Thus, transistor 110 is made with a larger semiconductor surface than would allow transistor 110 alone, without the presence of transistors 114, 116, to deliver the Isense current.

[0065] In a particular embodiment, the K*Isense current delivered to the second electrode 126 of the transistor 116 can be reused for an application other than the measurement of the I_load current.

[0066] A variant of device 100 according to the first embodiment is described below in relation to [Fig.2].

[0067] The device 100 according to this variant comprises all the elements and components of the device 100 previously described in connection with [Fig.1].

[0068] In addition, the device 100 visible in [Fig.2] includes at least one third FET transistor 136 whose gate is coupled to the output 134 of the comparator 128 and therefore also to the gates of transistors 114, 116. A first source or drain electrode 138 of transistor 136 is coupled to the first electrode 118 of transistor 114 (which is itself coupled to the first electrode 122 of transistor 116 and to the second electrode 120 of transistor 110).

[0069] In the embodiment described here, transistor 136 is of the same type as transistors 114, 116, i.e. type P. Thus, the first electrode 138 corresponds to the source of transistor 136, and the second electrode 140 corresponds to the drain of transistor 136.

[0070] In the embodiment shown in [Fig.2], transistors 114, 116, 136 are such that:

[0071] - the transistor 114 has a channel width W1 and delivers on its second electrode 124 a currentIsense1;

[0072] - the transistor 116 has a channel width W2 and delivers on its second electrode 126 an Isense2 current;

[0073] - the transistor 136 has a channel width W3 and delivers on its second electrode source or drain 140 an Isense3 current.

[0074] Thus, in the example of [Fig. 2], transistors 114, 116, 136 receive the current Isense_ref as input on their first electrode 118, 122, 138 and deliver a portion of this current Isense_ref on their second electrode 124, 126, 140. The currents Isense1, Isense2, and Isense3 delivered on the second electrodes 124, 126, 140 of these transistors 114, 116, 136 therefore satisfy the following relationships:

[0075] Isense_ref = Isensel + Isense2 + Isense3

[0076] Isensel = (W1 / (W1+W2+W3)) * Isense_ref

[0077] Isense2 = (W2 / (W1+W2+W3)) * Isense_ref

[0078] Isense3 = (W3 / (W1+W2+W3)) * Isense_ref

[0079] The different currents Isensel, Isense2, Isense3 can for example be used for distinct functions: diagnosis of the load 104, protection of the electrical beam coupled to the transistor 102, protection against current spikes, etc.

[0080] According to another variant, the device 100 could comprise a larger number of FET transistors including their first source or drain electrode coupled to the second electrode 120 of the transistor 110 and their second source or drain electrode on which a measurement current is obtained.

[0081] An example of a device 100 for measuring a power current delivered by the main power FET transistor 102 according to a second embodiment is described below in relation to [Fig.3].

[0082] The device 100 according to this second embodiment comprises all the elements and components of the device 100 previously described in connection with [Fig.1].

[0083] Unlike device 100 according to the first embodiment, the first electrode 122 of transistor 116 is not coupled to the first electrode 118 of transistor 114, but to the second electrode 108 of transistor 102. In addition, the second electrodes 124, 126 of transistors 114, 116 are electrically coupled to each other.

[0084] Thus, unlike the first embodiment in which the current Isense delivered by the second transistor 114 is lower than the current Isense_ref delivered by the transistor 110, the current delivered by the second transistor 114 is equal to Isense_ref, to which is added, at the junction of the second electrodes 124, 126, the current delivered on the second electrode 126 of the transistor 116. The device 100 according to the second embodiment therefore makes it possible to obtain, at the junction of the second electrodes 124, 126 of the transistors 114, 116, a current Isense_target greater than the current Isense_ref delivered by the transistor 110.

[0085] In this second embodiment, the comparator 128 regulates the current flowing through the transistor 110 so that the potential on the second electrode 120 of the transistor 110 is similar to, or substantially equal to, that on the second electrode 108 of the transistor 102. The potential on the first electrode 118 of the transistor 114 (which is equal to that on the second electrode 120 of the transistor 110) is therefore similar to, or substantially equal to, that on the first electrode 122 of the transistor 116 (which is equal to that on the second electrode 108 of the transistor 102). Since the Vgs voltages of the transistors 114 and 116 are similar to, or substantially equal to, those of the comparator 128, the current values ​​supplied by the transistors 114 and 116 are proportional to their respective sizes.

[0086] Thus, considering the channel width W1 of transistor 114 and the channel width W2 of transistor 116 which are such that W2 = K * Wl, the current Isense_target delivered at the junction of the second electrodes 124, 126 of transistors 114, 116 is therefore such that Isense_target = I_sense_ref * (1+K), because the current delivered on the second electrode 124 of transistor 114 is equal to Isense_ref and the current delivered on the second electrode 126 of transistor 116 is equal to K * Isense_ref.

[0087] In this second embodiment, because the second electrodes 118, 122 of the transistors 114, 116 are not electrically coupled to each other, the potentials applied to the second electrodes 118, 122 may not be perfectly equal. A potential difference, for example of a few mV, may therefore appear on the inputs 130, 132 of the comparator 128, resulting in a variation in the current delivered by the transistor 116 relative to the current delivered by the transistor 114. However, the various components of the device 100 are dimensioned and optimized (in particular the offset of the comparator 128 and the ratio of the dimensions of the transistors 114 and 116) in order to minimize this potential potential difference as much as possible.

[0088] An example of a device 100 for measuring a power current delivered by the main power FET transistor 102 according to a third embodiment is described below in relation to [Fig.4].

[0089] The device 100 according to this third embodiment comprises all the elements and components of the device 100 previously described in connection with [Fig.1].

[0090] In addition, the device 100 visible in [Fig.4] includes the third FET transistor 136 whose gate is coupled to the output 134 of the comparator 128 and therefore also to the gates of transistors 114, 116. The first source or drain electrode 138 of transistor 136 is coupled to the second electrode 108 of transistor 102.

[0091] As in the first embodiment, transistors 114, 116 both receive the Isense_ref current as input on their first electrode 118, 122 and deliver a portion of this Isense_ref current on their second electrode 124, 126. The Isensel and Isense2 currents delivered on the second electrodes 124, 126 of these transistors 114, 116 therefore satisfy the following relationships:

[0092] Isense_ref = Isensel + Isense2

[0093] Isensel = (W1 / (W1+W2)) * Isense_ref

[0094] Isense2 = (W2 / (W1+W2)) * Isense_ref

[0095] with W1 corresponding to the channel width of transistor 114 and W2 corresponding to the channel width of transistor 116.

[0096] The transistor 136 also allows to deliver, on its second electrode 140, a current Isense3 proportional to the current I_load.

[0097] Alternatively, it is possible that the second electrode 140 of the transistor 136 is coupled to the second electrode 124, 126 of one of the transistors 114, 116 in order to obtain at Injunction of the two second electrodes coupled to each other, a current corresponding to the sum of the current Isense3 with one of the currents Isensel or Isense2.

[0098] Alternatively, the device 100 may include one or more other FET transistors of which a first source or drain electrode is coupled to the first electrode 118 of the first transistor 114.

[0099] An example of a device 100 for measuring a power current delivered by the main power FET transistor 102 according to a fourth embodiment is described below in relation to [Fig.5].

[0100] The device 100 according to this fourth embodiment comprises all the elements and components of the device 100 previously described in connection with [Fig.1].

[0101] The device 100 according to this fourth embodiment also includes another FET transistor 142, a first source or drain electrode 144 of which is coupled to the second electrode of transistor 110, and a second source or drain electrode 146 of which is coupled to the first electrodes 118, 122 of transistors 114, 116, which are electrically coupled to each other. In the embodiment shown in [Fig. 5], transistor 142 is of type P, the first electrode 144 corresponding to the source of transistor 142 and the second electrode 146 corresponding to the drain of transistor 142.

[0102] Contrary to the modes and embodiments previously described, the output 134 of the comparator 128 is not electrically coupled to the gates of transistors 114, 116 but to the gate of transistor 142.

[0103] Transistors 114 and 116 are connected in a current mirror configuration. Thus, the gates of transistors 114 and 116 are electrically coupled to each other and to the second electrode 124 of transistor 114. A current Isense1 is delivered to the second electrode 124 of transistor 114, and a current Isense2 is delivered to the second electrode 126 of transistor 116.

[0104] As in the first embodiment, transistor 114 has a channel width W1 and transistor 116 has a channel width W2 such that W2 = K * W1, with K a real number greater than 0. In the embodiment shown in [Fig. 1], K is an integer greater than or equal to 1. According to a particular embodiment, transistors 114 and 116 may have different channel widths, meaning that the value of K is not equal to 1, and for example greater than 1.

[0105] As in the first embodiment, the transistors 114, 116 both receive the Isense_ref current as input on their first electrode 118, 122 and deliver a portion of this Isense_ref current on their second electrode 124, 126. The currents Isensel and Isense2 delivered on the second electrodes 124, 126 of these transistors 114, 116 mounted in current mirror therefore satisfy the following relationships:

[0106] Isense_ref = Isensel + Isense2

[0107] Isensel = (W1 / (W1+W2)) * Isense_ref

[0108] Isense2 = (W2 / (W1+W2)) * Isense_ref

[0109] A variant of device 100 according to the fourth embodiment is described below in relation to [Fig.6].

[0110] Device 100 according to this variant includes all the elements and components of device 100 previously described in connection with [Fig.5].

[0111] However, in device 100 according to the variant shown in [Fig. 6], the transistors 114, 116 (connected in current mirror) are of type N, their first electrode 118, 122 corresponding to the drain and their second electrode 124, 126 corresponding to the source of these transistors 114, 116. The gates of the transistors 114, 116 are electrically coupled to each other and to the first electrode 118 of the transistor 114. The first electrode 122 of the transistor 116 is coupled to a voltage source or a load (not visible in [Fig. 6]) capable of delivering a current K*Isense_ref to the first electrode 122 of the transistor 116. The second electrodes 124, 126 of the transistors 114, 116 are electrically coupled to each other.

[0112] In this variant, the current Isense_target is equal to the current K * Isense_ref flowing in the first electrode 122 of transistor 116, and the current Isensel flowing in the first electrode 118 of transistor 114 is equal to the current Isense_ref. As in the previous examples, transistor 114 has a channel width W1 and transistor 116 has a channel width W2 such that W2 = K * W1.

[0113] In all embodiments, examples and variants described above, the current measurement accuracy obtained with the device 100 is, for example, less than or equal to 5% of the nominal value of the current I_load, throughout the entire operating temperature range of the device 100.

[0114] The proposed circuit allows the use of a larger current-measuring power FET compared to existing solutions, thus avoiding the problems encountered with an undersized transistor, such as differences in dynamic behavior compared to that expected, or a change in the response of the measuring transistor as a function of operating temperature, the effects of which would be similar to a change in the K_target ratio as a function of operating temperature. The behavior of the current-measuring power FET is also closer to that of the main power FET, regardless of the values ​​of external parameters such as temperature or the VGs applied to it. transistors.

[0115] In all embodiments, examples, and variants, the transistors are sized according to the desired values ​​of the various ratios K_target, Kref, and K, which themselves depend on the characteristics and functionalities of the electrical environment in which the device 100 and the circuit 1000 are used. For example, the value of the K_target ratio (which can be fixed according to the application of the device 100) can be greater than or equal to 1000, or, for example, to one of the following values: 1000, 2000, 10000, 40000. For example, the value of the K_target ratio can be 4 to 10 times greater than that of the Kref ratio.

[0116] In all embodiments, examples and variants, the main power FET 102 and the current measurement power FET can be, for example, VDMOSFET type transistors (“Vertical Double diffused Metal-Oxide-Semiconductor Field-Effect Transistor”).

[0117] In all embodiments, examples and variants, the FET transistors 114, 116, 136, 142 can, for example, be MOSFET-type transistors. Furthermore, these FET transistors 114, 116, 136, 142 can be of N-type or P-type.

[0118] In all embodiments, examples and variants, the FET transistors 114, 116, 136, 142 form an output stage enabling the measurement current to be obtained at the output having, with respect to the load current, the desired ratio.

[0119] In all embodiments and variants, the main power FET transistor 102 and / or the current measurement power FET transistor 110 are of the same type, N or P.

[0120] As an alternative to the embodiments described above, the transistor 102 and the device 100 can be part of a "Low Side" type power control circuit 1000, i.e. corresponding to a control circuit interposed between the electrical load 104 and the electrical reference potential of this electrical load 104. In this case, the first electrodes of the power transistors 102, 110 are not coupled to the supply electrode potential but to one of the terminals of the electrical load 104, and the second electrode 108 of the transistor 102 is coupled to the electrical reference potential.

[0121] The measuring device 100 and the control circuit 1000 can be made in the form of independent modules or integrated into chips or integrated circuits including other functions and for example made in technology integrating power components and CMOS components, and / or bipolar (analog), CMOS (digital) and DMOS (“Double-Diffused MOS” in English, or double diffusion MOS, which are power components).

[0122] Figure 7 schematically represents the steps of an example of a re- ization of circuit 1000 for power control of the electrical load 104.

[0123] In a first step 200, the semiconductor area of ​​transistor 110 and the channel widths of transistors 114, 116 are determined such that the value of the ratio K_target between the load current I_load and the output current Isense is different from that of the ratio Kref between the semiconductor area of ​​transistor 102 and the semiconductor area of ​​transistor 110. In this step, any other elements or components of the device 100 are also dimensioned according to the desired characteristics for the device 100.

[0124] In a step 300, the main power FET transistor 102 and the various components of the device 100 are then fabricated. In particular, transistors 110, 114 and 116 are fabricated according to the previously determined surface areas and channel widths.

[0125] The measuring device 100 and the control circuit 1000 can be advantageously applied in the automotive field, for example in an electrical power distribution and management circuit of a vehicle. The measuring device 100 and the control circuit 1000 can also be used in other fields, for example in the industrial field.

[0126] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0127] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. Device (100) for measuring a power current intended to be delivered by a main power FET transistor (102), comprising at least: - a current measuring power FET transistor (110) comprising a first source or drain electrode (112) configured to be coupled to a first source or drain electrode (106) of the main power FET transistor (102); - first and second FET transistors (114, 116) whose gates are electrically coupled to each other, a first source or drain electrode (118) of the first FET transistor (114) being coupled to a second source or drain electrode (120) of the current measuring power FET transistor (110), wherein a first source or drain electrode (122) of the second FET transistor (116) is coupled to the first source or drain electrode (118) of the first FET transistor (114), or wherein the first source or drain electrode (122) of the second FET transistor (116) is configured to be coupled to a second source or drain electrode (108) of the main power FET transistor (102) or to a voltage source or load external to the device (100), and second source or drain electrodes (124, 126) of the first and second FET transistors (114, 116) are electrically coupled to each other.

2. The device (100) of claim 1, wherein a semiconductor area of the current measuring power FET transistor (110) and channel widths of the first and second FET transistors (114, 116) are such that the value of a ratio between a load current to be supplied to the second source or drain electrode (108) of the main power FET transistor (102) and an output current to be supplied to the second source or drain electrode (124) of the first FET transistor (114) is different from that of a ratio between a semiconductor area of the main power FET transistor (102) and the semiconductor area of the transistor Current measuring power FET (110).

3. Device (100) according to one of the preceding claims, in which the current measuring power FET transistor (110) is of the VDMOSFET type, and in which the first and second FET transistors (114, 116) are of the MOSFET type.

4. Device (100) according to one of the preceding claims, wherein the first and second FET transistors (114, 116) have channel widths different from each other.

5. The device (100) of one of the preceding claims, further comprising a comparator (128) having a first input (130) configured to be coupled to the second source or drain electrode (108) of the main power FET transistor (102), a second input (132) coupled to the second source or drain electrode (120) of the current-sensing power FET transistor (110), and an output coupled to the gates of the first and second FET transistors (114, 116).

6. Device (100) according to one of the preceding claims, further comprising at least one third FET transistor (136) whose gate is coupled to the gates of the first and second FET transistors (114, 116) and whose first source or drain electrode (138) is coupled to the first source or drain electrode (118) of the first FET transistor (114) or to the second source or drain electrode (108) of the main power FET transistor (102).

7. Device (100) according to one of claims 1 to 4, further comprising: - a fourth FET transistor (142) having a first source or drain electrode (144) coupled to the second source or drain electrode (120) of the current measuring power FET transistor (110), and having a second source or drain electrode (146) coupled to the first source or drain electrode (118) of the first FET transistor (114); - a comparator (128) having a first input (130) coupled to the second source or drain electrode (120) of the current measuring power FET transistor (110), a second input (132) configured to be coupled to the second source or drain electrode (108) of the transistor main power FET (102), and an output (134) coupled to the gate of the fourth FET transistor (142).

8. The device (100) of claim 7, wherein the first and second FET transistors (114, 116) are connected in a current mirror.

9. Device (100) according to claim 8, wherein: - the first and second FET transistors (114, 116) are P-type; - the gates of the first and second FET transistors (114, 116) are coupled to the second source or drain electrode (124) of the first FET transistor (114); - the first source or drain electrode (122) of the second FET transistor (116) is coupled to the first source or drain electrode (118) of the first FET transistor (114).

10. The device (100) of claim 8, wherein: - the first and second FET transistors (114, 116) are N-type; - the gates of the first and second FET transistors (114, 116) are coupled to the first source or drain electrode (118) of the first FET transistor (114); - the second source or drain electrodes (124, 126) of the first and second FET transistors (114, 116) are electrically coupled to each other.

11. Circuit (1000) for controlling the power of an electrical load (104), comprising at least: - a main power FET transistor (102) comprising a first source or drain electrode (106) configured to be coupled to a source of electrical energy and a second source or drain electrode (108) configured to be coupled to a terminal of the electrical load (104); - a device (100) for measuring a power current delivered by the main power FET transistor (102), according to one of the preceding claims.

12. The circuit (1000) of claim 11, wherein the main power FET transistor (102) and the current measuring power FET transistor (110) are of the same conductivity type.

13. Method for producing a circuit (1000) for controlling the power of an electrical load (104), comprising at least one embodiment (200) of a main power FET transistor (102) comprising a first source or drain electrode (106) configured to be coupled to a source of electrical energy and a second source or drain electrode (108) configured to be coupled to a terminal of the electrical load (104), and a device (100) for measuring a power current delivered by the main power FET transistor (102), according to one of claims 1 to 10.

14. The method of claim 13, further comprising, prior to the production (200) of the main power FET transistor (102) and the device (100) for measuring the power current delivered by the main power FET transistor (102), a step of determining (300) a semiconductor surface area of the current measuring power FET transistor (110) and channel widths of the first and second FET transistors (114,116) of the device (100) for measuring the power current delivered by the main power FET transistor (102) such that the value of a ratio between a load current intended to be delivered on the second source or drain electrode (108) of the main power FET transistor (102) and an output current intended to be delivered on the second source or drain electrode (124) of the first FET transistor (114) is different from that of a ratio between a semiconductor surface of the main power FET transistor (102) and the semiconductor surface of the current measuring power FET transistor (110); and wherein at least the current measuring power FET transistor (110) and the first and second FET transistors (114,116) of the device (100) are then made in accordance with the semiconductor surface area of the current measuring power FET transistor (110) and the channel widths of the first and second FET transistors (114, 116) previously determined.

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