Clock generator and clock generation method

Abstract

Clock Generator and Clock Generation Method This description relates to a clock generator comprising: a ring oscillator (202) configured to generate an output frequency signal (F_RO); a frequency detector (204) configured to compare a frequency of the output frequency signal with r times a frequency of a reference frequency signal (f_REF) and to generate a feedback signal (a, a'); and a control circuit (210) configured to: control a loop delay parameter () of the ring oscillator and a supply voltage (Vdd) of the ring oscillator based on the feedback signal; reduce the frequency of the output frequency signal when its frequency is greater than r times the frequency of the reference frequency signal by reducing the supply voltage;and increase the output frequency signal frequency when its frequency is less than r times the reference frequency signal frequency by reducing the loop delay parameter. Figure for the abbreviation: Fig. 2;

Description

Title of the invention: Clock generator and clock generation method Technical field

[0001] The present description relates generally to electronic circuits, and in particular to a clock generator and a clock generation method. Prior art

[0002] There is a growing demand for low-power solutions for electronic circuits, particularly for battery-powered devices, such as loT (Internet of Things) devices, where it is desirable to increase battery life between charges.

[0003] Low-power clock generators can be part of the solution to reducing the power consumption of electronic circuits. For example, one of the parts of an integrated circuit that is particularly power-hungry is the system clock, which is usually at a relatively high frequency. One mechanism for reducing the power consumption of an integrated circuit is to use low-power or sleep modes when the circuit is inactive, and to disable the system clock during these periods. A low-power local clock generator can then be used to drive the wake-up circuit that will wake the integrated circuit at the appropriate time, without the need for a central processing unit (CPU).

[0004] Such a clock generator must be capable of generating a clock signal at a relatively stable frequency as a function of PVT (Process, Voltage, Temperature) variations and which, in some cases, is a variable frequency. This involves the use of a control loop to regulate the clock frequency. However, implementing such a control loop capable of converging quickly to the frequency and voltage state in which the power consumption is relatively low faces technical difficulties. Summary of the invention

[0005] One of the objectives of embodiments of the present description is to at least partially meet one or more needs of the prior art.

[0006] According to one aspect, there is provided a clock generator comprising: a ring oscillator configured to generate an output frequency signal; a frequency detector configured to compare a frequency of the output frequency signal with r times a frequency of a reference frequency signal and to generate a feedback signal based on the comparison; and a control circuit configured to control a loop delay parameter of the ring oscillator and a supply voltage of the ring oscillator based on the feedback signal, wherein the control circuit is configured to: reduce the frequency of the output frequency signal when its frequency is greater than r times the frequency of the reference frequency signal by reducing the supply voltage, unless the supply voltage has reached a minimum level, in which case the loop delay parameter is then increased; and increase the frequency of the output frequency signal when its frequency is less than r times the frequency of the reference frequency signal by reducing the loop delay parameter, unless the loop delay parameter has reached a minimum level, in which case the supply voltage is then increased.

[0007] According to one embodiment, the control circuit is configured to prevent changes to the supply voltage once the control circuit has detected that the loop delay parameter has reached its minimum level.

[0008] According to one embodiment, the control circuit is configured to iteratively reduce and / or increase the delay parameter of the loop, the reduction or increase at each iteration being equal to a step size.

[0009] According to one embodiment, the step size is variable as a function of a frequency difference between the frequency of the output frequency signal and the frequency of the reference frequency signal.

[0010] According to one embodiment, the step size is equal to a first size until the loop delay parameter reaches the minimum level, and to a second size, less than the first size, after the loop delay parameter reaches the minimum level.

[0011] According to one embodiment, the clock generator further comprises a sigma-delta converter configured to convert the loop delay parameter into a plurality of control signals configured to control the ring oscillator.

[0012] According to one embodiment, the frequency detector is configured to compare the frequency of the output frequency signal to r times the frequency of the reference frequency signal by comparing the output frequency signal to r times the frequency of the reference frequency signal.

[0013] According to one embodiment, the ring oscillator comprises a plurality of delay stages, each delay stage comprising: a multiplexer; a delay element connected to a first input of the multiplexer, the first input being selected by a first state of a control signal of the multiplexer; a bypass path connected to a second input of the multiplexer, the second input being selected by a second state of the multiplexer control signal; and a logic gate connecting the output of a previous stage to an input of the delay element, the logic gate receiving the multiplexer control signal and being configured to provide a constant signal to the delay element while the control signal is in the second state.

[0014] According to one embodiment, r is a real number greater than 1.

[0015] According to another aspect, there is provided an integrated circuit comprising: an electronic circuit electronic circuit controlled by a clock signal; and the above clock generator configured to provide the clock signal to the electronic circuit.

[0016] According to one embodiment, the integrated circuit further comprises: a voltage regulator configured to generate said supply voltage; and an additional electronic circuit powered by said supply voltage.

[0017] According to yet another aspect, there is provided a method of generating a clock comprising: generating, by a ring oscillator, an output frequency signal; comparing, by a frequency detector, a frequency of the output frequency signal with r times a frequency of a reference frequency signal to generate a feedback signal based on the comparison; and controlling, by a control circuit based on the feedback signal, a loop delay parameter of the ring oscillator and a supply voltage of the ring oscillator, by: reducing the frequency of the output frequency signal when its frequency is greater than r times the frequency of the reference frequency signal by reducing the supply voltage, unless the supply voltage has reached a minimum level, in which case the loop delay parameter is then increased;and increasing the frequency of the output frequency signal when its frequency is less than r times the frequency of the reference frequency signal by reducing the loop delay parameter, unless the loop delay parameter has reached a minimum level, in which case the supply voltage is then increased. ; Brief description of the drawings

[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0019] [Fig.l] schematically represents an integrated circuit comprising a clock generator according to an exemplary embodiment of the present description;

[0020] [Fig.2] schematically represents the clock generator of [Fig.l] in such a way more detailed according to an exemplary embodiment of the present description;

[0021] [Fig.3] is a graph illustrating an example of valid ranges of a voltage power supply and a delay parameter of a ring oscillator of the generator clock of [Fig.2], according to an exemplary embodiment of the present description;

[0022] [Fig.4] is a flowchart illustrating steps of a clock generation method according to an exemplary embodiment of the present disclosure;

[0023] [Fig.5] schematically represents a ring oscillator according to an exemplary embodiment of the present description;

[0024] Figure 6 is a graph showing frequency as a function of a loop delay parameter r for a range of voltage settings;

[0025] [Fig.7] is a flowchart illustrating steps of a clock generation method according to another exemplary embodiment of the present disclosure;

[0026] Figure 8 is a graph showing frequency as a function of loop delay parameter T for a range of voltage settings;

[0027] [Fig.9] is a decision tree illustrating the selection of a step size according to an exemplary embodiment of the present disclosure;

[0028] [Fig. 10] is a flowchart illustrating steps of a clock generation method according to another exemplary embodiment of the present disclosure; and

[0029] [Fig. 11] schematically illustrates an alternative implementation of a ring oscillator according to an exemplary embodiment of the present description. Description of the embodiments

[0030] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0032] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0033] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0035] [Fig.l] schematically represents an integrated circuit 100 comprising a circuit (CIRCUIT) 102 powered by a supply voltage Vdd_c generated by a voltage regulator (V_REG) 104, and controlled by a clock signal M_CLK generated by a clock generator (CLK GENERATOR) 106. In certain embodiments, the circuit 100 is configured to implement a wake-up function in order to wake up the integrated circuit 100 at an appropriate time. According to a variant, the circuit 100 has other functions which can be implemented under the control of the clock signal M_CLK.

[0036] The clock generator 106 receives for example an input frequency signal f_EXT and a supply voltage Vdd.

[0037] The input frequency signal f_EXT is, for example, an external signal generated by an off-chip circuit, such as a phase-locked loop. The input frequency signal f_EXT has, for example, a relatively stable frequency depending on PVT (Process, Voltage, Temperature) variations.

[0038] The supply voltage Vdd is for example generated by an additional voltage regulator (V_REG) 108. In some embodiments, the clock generator 106 is configured to control the supply voltage Vdd provided by the voltage regulator 108, for example by transmitting a control signal V_CTRL to the voltage regulator 108 on a control line 110. In some embodiments, the voltage regulator 108 is also configured to supply another circuit (CIRCUIT2) 112 with the supply voltage Vdd, the other circuit 112 being for example external to the integrated circuit 100.

[0039] [Fig.2] schematically represents the clock generator 106 of [Fig.l] in more detail according to an exemplary embodiment of the present description.

[0040] The clock generator 106 comprises for example a ring oscillator (RO) 202 configured to generate an output frequency signal F_RO.

[0041] The clock generator 106 also comprises, for example, a frequency detector (FD) 204, configured to receive the output frequency signal F_RO from the ring oscillator 202 and to compare the frequency of the signal F_RO to the frequency of a reference frequency signal f_REF. For example, the reference frequency signal f_REF is generated by a frequency divider ( ~ P) 206, based on the input frequency signal f_EXT. For example, the frequency divider 206 is configured to divide the frequency of the input frequency signal f_EXT by a division coefficient P to generate the reference frequency signal f_REF, where P is for example equal to one or more.

[0042] The frequency detector 204 is for example configured to generate an output signal a' equal to freq_RO / freq_REF-r, where freq_RO is the frequency of the signal F_RO, freq_REF is the frequency of the signal f_REF, and r is a desired ratio between the frequencies of the signals F_RO and f_REF. In some embodiments, r is a real number equal to or greater than 1. The output signal a' is, for example, a digital signal. The output signal a' is for example processed by a low-pass filter (LPF) 208 in order to generate a feedback signal a, which is supplied to a control circuit (CTRL) 210. The control circuit (CTRL) 210 is configured to apply a control algorithm based on the feedback signal a, in order to adjust the supply voltage Vdd and / or the loop delay parameter T of the ring oscillator 202. For example, the control circuit 210 provides, as output, the control signal V_CTRL to the voltage regulator 108, which in turn generates the corresponding supply voltage Vdd, which is supplied to the ring oscillator 202.The control circuit 210 also provides, as output, for example, the control signal T indicating the delay to be applied by the ring oscillator 202. In some embodiments, the control signal ' is provided to a sigma-delta converter 212, which is configured to generate, based on the control signal T, an additional control signal rCTRL, which is used to control the ring oscillator. For example, the control signal T is an n-bit signal and the control signal r_CTRL is an n'-bit signal, where n' <n. Dans un mode de réalisation, le signal de commande T est un signal à 8 bits et le signal de commande T _CTRL est un signal à 4 bits. .

[0043] The output frequency signal F_RO is for example supplied to a frequency divider (“m) 214, which is configured to divide the frequency of the signal F_RO by a division coefficient m in order to generate the output clock signal M_CLK, where m is for example equal to one or more.

[0044] In alternative embodiments of clock generator 106, frequency divider 206 and / or frequency divider 214 may be omitted.

[0045] Figure 3 is a graph illustrating an example of valid ranges of the supply voltage Vdd and the delay ' of the ring oscillator 202 of the clock generator 106 of [Fig.2] according to an exemplary embodiment of the present disclosure.

[0046] As shown, the supply voltage Vdd has for example a maximum level Vdd_max and a minimum level Vdd_min, such that: V dd_min< V dd< V dd_max.

[0047] Similarly, the delay of the ring oscillator 7 has a maximum level Tmax and a minimum level Tmin such that: Tmin <T<Tmia_

[0048] An error is for example generated when the supply voltage is at Vdd_max while the ring oscillator delay is at Tmm or when the supply voltage is at Vdd_min while the ring oscillator delay is at because the system is not able to generate the expected frequency.

[0049] Referring again to Figure 2, the control circuit 210 is configured to control the loop delay parameter T of the ring oscillator 202 and the supply voltage Vdd of the ring oscillator 202 as a function of the feedback signal a. In particular, the control circuit 210 is configured to reduce the frequency of the output frequency signal F_RO when its frequency is greater than r times the frequency of the reference frequency signal f_REF by reducing the supply voltage, unless the supply voltage has reached the minimum level Vdd_min, in which case the loop delay parameter T is then increased.The control circuit 210 is also configured to increase the frequency of the output frequency signal F_RO when its frequency is less than r times the frequency of the reference frequency signal f_REF by reducing the loop delay parameter T unless the loop delay parameter T has reached the minimum level in which case the supply voltage Vdd is then increased.

[0050] [Fig.4] is a flowchart illustrating in more detail the steps implemented by the control circuit 210 of [Fig.2] according to an exemplary embodiment of the present description.

[0051] In a step 402, it is determined whether the feedback signal a is greater than 0. Indeed, in certain embodiments, a positive value of the signal a indicates that the frequency of the signal F_RO is greater than r times the frequency of the reference signal f_REF, while a negative value of the signal a indicates that the frequency of the signal F_RO is less than r times the frequency of the reference signal f_REF. In alternative embodiments, the feedback signal a could have other values ​​to indicate the relative frequencies of the signals F_RO and f_REF.

[0052] In the case where the feedback signal a is positive (Y branch), the frequency of F_RO is for example reduced. This involves for example a step 404, during which it is determined whether the supply voltage Vdd is greater than Vdd_min. If so (Y branch), the supply voltage Vdd is for example reduced during a step 406. If not (N branch), the delay of the ring oscillator T is for example increased during a step 408.

[0053] In the case where the feedback signal a is negative (branch N), the frequency of F_RO is for example increased. This involves for example a step 410, during which it is determined whether the delay of the ring oscillator T is greater than the minimum level rmin. If so (branch Y), the delay of the ring oscillator r is for example reduced during a step 412. If not (branch N), the supply voltage Vdd is for example increased during a step 414.

[0054] After step 406, 408, 412 or 414, the method is for example repeated for the new value of the target signal F_RO on the basis of the updated supply voltage Vdd or the updated ring oscillator delay r.

[0055] An advantage of favoring a reduction in the supply voltage to decrease the frequency and a reduction in the delay of the ring oscillator T to increase the frequency is that this algorithm converges to a relatively low supply voltage Vdd, and therefore to a state in which the power consumption is relatively low.

[0056] [Fig.5] schematically represents the ring oscillator 202 of [Fig.2] in more detail according to an exemplary embodiment of the present description.

[0057] In the example of Figure 5, the ring oscillator comprises a series of delay elements 502, 504, 506 and 508. In some embodiments, the delay elements have a binary weighting, element 502 introducing for example a delay of 8*T, element 504 introducing for example a delay of 4*T, element 506 introducing for example a delay of 2*T and element 508 introducing for example a delay of T, where T is a unit delay, equal for example to a value between 1 and 100 ns.

[0058] The delay element 502 is for example connected between the output of a logic gate 510, which is for example an AND gate, and an input of a multiplexer 512. A second input of the multiplexer 512 is for example connected directly to the output of the logic gate 510.

[0059] The delay element 504 is for example connected between the output of the multiplexer 512 and an input of a multiplexer 514. A second input of the multiplexer 514 is for example connected directly to the output of the multiplexer 512.

[0060] The delay element 506 is for example connected between the output of the multiplexer 514 and an input of a multiplexer 516. A second input of the multiplexer 516 is for example connected directly to the output of the multiplexer 514.

[0061] The delay element 508 is for example connected between the output of the multiplexer 516 and an input of a multiplexer 518. A second input of the multiplexer 518 is for example connected directly to the output of the multiplexer 516.

[0062] The multiplexers 512, 514, 516 and 518 are for example controlled by control signals S1, S2, S3 and S4 respectively, these control signals forming for example the control signal rCTRL generated by the sigma-delta converter 212 of [Fig.2]. In one example, a logic low, or zero, state of any of the control signals S1 to S4 causes the output signal of the logic gate 510 or the preceding multiplexer 512, 514, 516 to be selected by the corresponding multiplexer 512, 514, 516, 518, while a logic high, or one, state of any of the control signals S1 to S4 causes the output of the corresponding delay element 502, 504, 506 or 508 to be selected by the corresponding multiplexer 512, 514, 516, 518.

[0063] The output of the multiplexer 518 is for example connected to an input of the logic gate 510 via an additional delay element 520, which is for example configured to introduce a delay of h*T, where n is for example equal to a value between 1 and 50. The other input of the logic gate 510 receives for example an enable signal EN, the ring oscillator 202 being for example operational when the enable signal EN is at a high logic level.

[0064] Thus, in the example of Figure 5, the ring oscillator 202 can be controlled to have a loop delay between n*T and n*T + 15T.

[0065] Figure 6 is a graph representing frequency (FREQ) as a function of the T parameter (TAU) for a range of voltage settings, and illustrates examples of the control algorithm of [Fig.4].

[0066] In the example of Figure 6, the parameter T is between -128 and +127 (Figure 6 only illustrates values ​​up to +112). Such a range of values ​​is for example obtained by using the ring oscillator of Figure 5 and controlling the four control bits S1 to S4 to have one of their 16 corresponding settings, and by using the sigma-delta converter 212 of Figure 2 to provide four additional control bits, which leads to a total of 8 control bits, or 256 values ​​of the parameter. T.

[0067] Furthermore, the 17 curves in [Fig.6] represent the output frequency for supply voltages in the range from 0.6 V to 1.4 V.

[0068] According to a first example EX1 of the control algorithm, the supply voltage starts at its highest level of 1.4 V, and the parameter T starts at its highest level allowed by the clock generator 106, for example equal to 112. The parameter T is then reduced by the steps 402, 410 and 412 of FIG. 4, until the frequency of F_RO exceeds a target frequency freq_TARGET equal to r times the frequency of the reference frequency signal f_REF. The supply voltage is then iteratively reduced by steps 402, 404 and 406 of Figure 4, each iteration causing the frequency of F_RO to fall below the target frequency freq_TARGET, and causing the parameter T to be further reduced until the parameter T reaches its minimum level rmin of -128, at which point the supply voltage and parameter T are each increased to reach a convergence point CP.The supply voltage and parameter T then enter, for example, a permanent hysteresis loop in which they oscillate between their values ​​at the point of convergence and the following lower levels.

[0069] According to example EX2 of Figure 6, the supply voltage stabilizes at the lowest value Vdd_min, resulting in a frequency of F_RO lower than the target frequency freq_TARGET equal to r times the frequency of the signal f_REF, and therefore steps 402, 410 and 412 of Figure 4 result in the reduction of the parameter r until the parameter T reaches its minimum level Tmm of -128. The supply voltage is then increased until the signal frequency F_RO exceeds the target frequency freq_TARGET, at which point the parameter T is increased to reach a convergence point CP. The supply voltage and parameter T then enter, for example, a permanent hysteresis loop in which they oscillate between their values ​​at the convergence point and the following lower levels.

[0070] In order to avoid variations in the supply voltage during the hysteresis loop, which may lead to additional power consumption, a modified algorithm is for example used, as will be described in more detail with reference to [Fig.7].

[0071] [Fig. 7] is a flowchart illustrating steps of a clock generation method according to another exemplary embodiment of the present description. This method is for example implemented by the control circuit 210 of [Fig. 2].

[0072] Certain steps of [Fig.7] are identical to those of [Fig.4] and these steps have been designated by similar reference numerals and will not be described again in detail.

[0073] The algorithm of Figure 7 starts, for example, with step 402 and, if the feedback signal a is less than 0 (branch N), step 410 is implemented and, if the parameter T is greater than its minimum level Tmtn (branch Y), step 412 is performed as in Figure 4. However, if the parameter T is not greater than its minimum level Tmm (branch N), then in a step 710, the supply voltage is increased and a variable R is set to 1. The variable R is for example an information bit which is initialized to zero at the beginning of the algorithm.

[0074] If, in step 402, the feedback signal a is less than 0 (Y branch), a step 702 is performed, in which it is determined whether the variable R is equal to 1. If not (N branch), then step 404, followed by step 406 or 408, are performed, as in Figure 4. On the other hand, if R is equal to 1 (Y branch), then in a step 704, it is determined whether the parameter T is greater than or equal to its maximum level rmax which is for example a threshold value used to trigger a modification of the variable R. For example, Tmax is equal to 112 in one example, while the maximum theoretical level that the parameter T can reach is greater than Tmax and is for example equal to 127. If the parameter 1 is greater than or equal to its maximum level Tmax (Y branch), in a step 706, the parameter T is incremented and the variable R is set to zero.If, on the other hand, the parameter r is less than Tmax then, in a step 708, the parameter T is increased without setting the variable R to zero. In this way, once the parameter T has reached its minimum value rmm once, it will oscillate between this value and the level Tmin + 1 without variation of the supply voltage.

[0075] The algorithms of Figures 4 and 7 are based on incrementing or decrementing- mentation of the parameter T by a step size of one. In other embodiments, faster convergence may be achieved by using a variable step size, as will be described in more detail in connection with Figures 8, 9 and 10.

[0076] Figure 8 is a graph representing the frequency (FREQ) as a function of the parameter T (TAU) for a range of voltage settings. Two examples EX1 and EX2 are illustrated, showing the convergence of the parameter T towards the convergence point CP, the example EX1 being based on an initial supply voltage equal to Vdd_max, and the example EX2 being based on an initial supply voltage equal to Vdd_min. In both examples, the parameter T is decremented until it reaches the minimum level 1 mm and the step size depends for example on whether the frequency of the signal F_RO has exceeded the target frequency freq_TARGET, on whether the hysteresis loop has been introduced and / or on the proximity of the frequency of the signal F_RO to r times the frequency of the reference frequency signal f_REF.

[0077] For example, until the frequency of the signal F_RO has exceeded r times the frequency of the reference frequency signal f_REF, the supply voltage is constant and the step size is for example equal to a relatively large step size, equal for example to 16 according to one example.

[0078] Once the frequency of the signal F_RO has exceeded r times the frequency freq_REF and if the hysteresis loop has not been introduced (case occurring in EX1 but not in EX2), the step size depends for example on the proximity of the frequency of the signal F_RO to r times the frequency freq_REF. For example, as shown on the right side of [Fig.8], if r times the frequency of the target signal F_RO is: - in a frequency interval II, equal for example to freq_REF plus or minus j Hz, the step size is equal to 1 (STP=1); - in a frequency interval 12, equal for example to freq_REF plus or minus k Hz, where k>j, the step size is equal to 2 (STP=2); - in a frequency interval 13, equal for example to freq_REF plus or minus 1 Hz, where l>k, the step size is equal to 4 (STP=4); - in a frequency interval 14, equal for example to freq_REF plus or minus s Hz, where s>l, the step size is equal to 8 (STP=8); and - in a frequency interval 15, equal for example to freq_REF plus or minus q Hz, where q>p, the step size is equal to 16 (STP=16).

[0079] Once entered into the hysteresis cycle, the step size is for example reduced to a relatively small value, equal for example to one.

[0080] [Fig. 9] is a decision tree illustrating the selection of the step size according to an exemplary embodiment of the present description. This method is for example implemented by the control circuit 210 of [Fig. 2].

[0081] In a step 902, it is determined for example whether a variable SS is set to 1. If so (branch Y), in a step 904, the step size is for example set to 1 (STP=1). On the other hand, if, during step 902, the variable SS is not set to 1 (branch N), a step 906 is carried out.

[0082] In step 906, it is determined for example whether a variable BS is set to 1. If so (branch Y), in a step 904, the step size is for example set to 16 (STP=16). On the other hand, if in step 906 the variable BS is not set to 1 (branch N), a step 910 is carried out.

[0083] In step 910, it is determined, for example, whether the magnitude of a difference between the frequency of the signal F_RO and the frequency freq_REF is less than a first threshold. For example, as mentioned above, the frequency detector 204 of FIG. 2 is configured to provide, as output, the value a' indicating the difference between the frequency of the signal F_RO and r times the frequency freq_REF. In the example of FIG. 9, each period of the reference frequency is assumed to correspond to r=610 periods of the ring oscillator clock and the value a' indicates the number of ring oscillator periods during one period of the reference frequency minus 610. Thus, a value of a'=0 indicates, for example, that the frequency of the signal F_RO matches the target and a value of a'=610 indicates, for example, that the frequency of the signal F_RO is 2 times higher than expected. For example, in the example in Figure 9, the first threshold is equal to 76.If <76 (Y branch), in a step 912, the step size is for example set to 1 (STP=1). On the other hand, if in step 910 |a 'j £ 76 (N branch), a step 914 is carried out.

[0084] In step 914, it is determined for example whether a' is between the first threshold and a second threshold greater than the first threshold. For example, in the example of Figure 9, the second threshold is equal to 122. If 76 < | a' | <122 (Y branch), in a step 916, the step size is for example set to 2 (STP=2). On the other hand, if in step 914 |#'| > 122 (N branch), a step 918 is performed.

[0085] In step 918, it is determined for example whether a' is between the second threshold and a third threshold greater than the second threshold. For example, in the example of FIG. 9, the third threshold is equal to 244. If 122 < [a'| < 244 (Y branch), in a step 920, the step size is for example set to 4 (STP=4). On the other hand, if in step 918 > 244 (N branch), a step 922 is performed.

[0086] In step 922, it is determined for example whether a' is between the third threshold and a fourth threshold greater than the third threshold. For example, in the example of Figure 9, the fourth threshold is equal to 427. If 244 < |a'| < 427 (Y branch), in a step 924, the step size is for example set to 8 (STP=8). On the other hand, if in step 922 ja'] > 427 (N branch), a step 926 is performed.

[0087] In step 926, it is determined for example whether a' is between the fourth threshold and a fifth threshold greater than the fourth threshold. For example, in the example of FIG. 9, the fifth threshold is equal to 458. If 427 < < 458 (Y branch), in a step 928, the step size is for example set to 16 (STP=16). On the other hand, if in step 926 |a'\ > 458 (N branch), a step 930 is carried out, in which the step size is for example set to 32 (STP=32).

[0088] Of course, the above values ​​of the first, second, third, fourth and fifth thresholds are only examples and other values ​​are possible. Furthermore, there could be a different number of thresholds, such as only one, two, three or four thresholds, or more than five thresholds.

[0089] [Fig. 10] is a flowchart illustrating steps of a clock generation method according to another exemplary embodiment of the present description. This method is for example implemented by the control circuit 210 of [Fig. 2].

[0090] Certain steps of [Fig. 10] are identical to the steps of [Fig. 7], and these steps have been designated by the same numerical references and will not be described again in detail.

[0091] Compared to the algorithm of [Fig.7], in the algorithm of [Fig. 10], some steps have been replaced as follows.

[0092] Step 704 of Figure 7 is replaced in Figure 10 by a step 1004 in which it is determined whether T + Step > Tmax. If so (branch Y), in a step 1006 replacing step 706 of Figure 7, the parameter T is increased by the current step size, determined for example by the method of Figure 9, the variable R is set to zero and the variable BS is for example set to 1. If, in step 1004, it is determined that T + Step < Tmax then, in a step 1008 replacing step 708 of Figure 7, the parameter T is increased by the current step size, determined for example by the method of [Fig.9], and the variable BS is for example set to 0.

[0093] Step 408 of Figure 7 is replaced in Figure 10 by a step 1009 in which the parameter T is increased by the current step size, determined for example by the method of [Fig.9], and the variable BS is set to zero.

[0094] Step 410 of Figure 7 is replaced in Figure 10 by a step 1010 in which it is determined whether t - step £ Tmjn. If so (branch Y), in a step 1012 replacing step 412 of Figure 7, the parameter T is decreased by the current step size, determined for example by the method of Figure 9. If, during step 1010, it is determined that T - step < Tmin, then in a step 1013 replacing step 710 of [Fig.7], the supply voltage Vdd is increased, the variable R is set to 1 and the variable SS is for example set to 1.

[0095] [Fig. 11] schematically illustrates a variant implementation of an oscillator in ring 202 of [Fig.2] according to another embodiment example than that of [Fig.5]. In [Fig.11], certain elements are identical to those of [Fig.5], and these elements have been designated with the same numerical references and will not be described again in detail.

[0096] Compared to the implementation example of [Fig. 5], the implementation of [Fig. 1 1] further comprises, for example, a logic gate 1102, which is for example an OR gate, connecting the output of the AND gate 510 to the input of the delay element 502. In particular, the OR gate 1102 has for example one of its inputs connected to the output of the AND gate 510, its other input connected to receive the control signal SI via an inverter 1104, and its output connected to the input of the delay element 502.

[0097] Similarly, with respect to the implementation example of [Fig.5], the implementation of [Fig.11] further comprises, for example, a logic gate 1106, which is for example an OR gate, connecting the output of the multiplexer 512 to the input of the delay element 504. In particular, the OR gate 1106 has for example one of its inputs connected to the output of the multiplexer 512, its other input connected to receive the control signal S2 via an inverter 1108, and its output connected to the input of the delay element 504.

[0098] Again likewise, with respect to the implementation example of [Fig.5], the implementation of [Fig.11] further comprises, for example, a logic gate 1110, which is for example an OR gate, connecting the output of the multiplexer 514 to the input of the delay element 506. In particular, the OR gate 1110 has for example one of its inputs connected to the output of the multiplexer 514, its other input connected to receive the control signal S3 via an inverter 1112, and its output connected to the input of the delay element 506.

[0099] Likewise again, compared to the implementation example of [Fig. 5], the implementation of [Fig. 11] further comprises, for example, a logic gate 1114, which is for example an OR gate, connecting the output of the multiplexer 516 to the input of the delay element 508. In particular, the OR gate 1114 has for example one of its inputs connected to the output of the multiplexer 516, its other input connected to receive the control signal S4 via an inverter 1116, and its output connected to the input of the delay element 508.

[0100] The addition of logic gates 1102, 1106, 1110 and 1114 makes it possible, for example, to reduce the risk of transient disturbances at the time of transitions of the control signals S1 to S4. In particular, when any of the control signals is at zero, the corresponding logic gate 1102, 1106, 1110, 1114 is configured to emit a constant high logic state, rather than oscillating according to the signal propagated around the ring. This means that, when any of the control signals command goes from zero to a high logic state, a stable signal is present at input "1" of the corresponding 512 to 518 multiplexer.

[0101] An advantage of the embodiments described herein is that a clock generator with a ring oscillator can converge quickly to a target frequency while selecting a relatively low supply voltage, thereby reducing the power consumption of the ring oscillator. Furthermore, the embodiment of Figure 7 allows for a stable supply voltage after the clock generator reaches the target frequency, and the embodiment of Figure 10 allows for faster convergence through the use of variable steps of the loop delay parameter r.

[0102] An advantage of using the supply voltage Vdd to power additional circuitry, such as circuit 112, in addition to the clock generator 106, is that this voltage will be regulated to a relatively low level, and therefore at relatively low power consumption, while still achieving the targeted performance of the clock generator 106, meaning that this voltage can also allow the additional circuitry to achieve its desired performance with relatively low power consumption.

[0103] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. For example, it will be obvious to those skilled in the art that the described implementations of the ring oscillators are only examples and that other architectures are possible. Furthermore, it would be possible to combine features of the algorithms of Figures 4, 7 and 10 in various ways. For example, the variable step size of the algorithm of [Fig. 10] could be implemented in the algorithm of [Fig. 4], in other words without using the variable R.

[0104] Furthermore, although an embodiment involving a Sigma-delta controller has been described, it would be possible, in other embodiments, not to use such a controller. The use of a Sigma-delta controller has the advantage of allowing more precise control of the loop delay of the ring oscillator without the addition of additional multiplexers in the ring oscillator, which would degrade its performance.

[0105] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A clock generator comprising: - a ring oscillator (202) configured to generate an output frequency signal (F_RO); - a frequency detector (204) configured to compare a frequency of the output frequency signal (F_RO) with r times a frequency of a reference frequency signal (f_REF) and to generate a feedback signal (a, a') based on the comparison;and - a control circuit (210) configured to control a loop delay parameter (r) of the ring oscillator and a supply voltage (Vdd) of the ring oscillator based on the feedback signal (a, a'), wherein the control circuit is configured to: reduce the frequency of the output frequency signal (F_RO) when its frequency is greater than r times the frequency of the reference frequency signal (f_REF) by reducing the supply voltage (Vdd), unless the supply voltage has reached a minimum level (Vdd_min), in which case the loop delay parameter (r) is then increased; and increase the frequency of the output frequency signal (F_RO) when its frequency is less than r times the frequency of the reference frequency signal (f_REF) by reducing the loop delay parameter (r), unless the loop delay parameter (r) has reached a minimum level (in which case the supply voltage (Vdd) is increased.;

2. The clock generator of claim 1, wherein the control circuit (210) is configured to prevent changes in the supply voltage (Vdd) once the control circuit (210) has detected that the loop delay parameter (' ) has reached its minimum level (7^).

3. A clock generator according to claim 1 or 2, wherein the control circuit (210) is configured to iteratively reduce and / or increase the loop delay parameter (r), the reduction or increase at each iteration being equal to a step size.

4. A clock generator according to claim 3, wherein the step size is variable depending on a frequency difference between the frequency of the output frequency signal (F_RO) and the frequency of the reference frequency signal (f_REF).

5. A clock generator according to claim 3 or 4, wherein the size of the step is equal to a first size until the loop delay parameter (r) reaches the minimum level and to a second size, smaller than the first size, after the loop delay parameter (T) reaches the minimum level (^w)-

6. The clock generator of any one of claims 1 to 5, further comprising a sigma-delta converter (212) configured to convert the loop delay parameter (r) into a plurality of control signals (S1, S2, S3, S4) configured to control the ring oscillator.

7. A clock generator according to any one of claims 1 to 6, wherein the frequency detector (204) is configured to compare the frequency of the output frequency signal (F_RO) to r times the frequency of the reference frequency signal (f_REF) by comparing the output frequency signal (F_RO) to r times the frequency of the reference frequency signal (f_REF).

8. A clock generator according to any one of claims 1 to 7, wherein the ring oscillator comprises a plurality of delay stages, each delay stage comprising: - a multiplexer (512, 514, 516, 518); - a delay element (502, 504, 506, 508) connected to a first input of the multiplexer (512, 514, 516, 518), the first input being selected by a first state of a control signal (SI, S2, S3, S4) of the multiplexer; - a bypass path connected to a second input of the multiplexer (512, 514, 516, 518), the second input being selected by a second state of the control signal (SI, S2, S3, S4) of the multiplexer;and - a logic gate (1102, 1106, 1110, 1114) connecting the output of a previous stage to an input of the delay element (502, 504, 506, 508), the logic gate receiving the control signal (SI, S2, S3, S4) from the multiplexer and being configured to provide a constant signal to the delay element when the control signal is in the second state.;

9. A clock generator according to any one of claims 1 to 8, wherein r is a real number greater than 1.

10. Integrated circuit (100) comprising: - an electronic circuit (102) controlled by a clock signal (M_CLK); and - the clock generator (106) according to any one of the claims- indications 1 to 9 configured to provide the clock signal (M_CLK) to the electronic circuit (102).

11. An integrated circuit according to claim 10, further comprising: - a voltage regulator (V_REG, 108) configured to generate said supply voltage (Vdd); and - an additional electronic circuit (112) powered by said supply voltage (Vdd).

12. A method of generating a clock comprising: - the generation, by a ring oscillator (202), of an output frequency signal (F_RO); - comparing, by a frequency detector (204), a frequency of the output frequency signal (F_RO) with r times a frequency of a reference frequency signal (f_REF) in order to generate a feedback signal (a, a') on the basis of the comparison; and - controlling, by a control circuit (210) on the basis of the feedback signal (a, a'), a loop delay parameter (r) of the ring oscillator and a supply voltage (Vdd) of the ring oscillator, by: reducing the frequency of the output frequency signal (F_RO) when its frequency is greater than r times the frequency of the reference frequency signal (f_REF) by reducing the supply voltage (Vdd), unless the supply voltage has reached a minimum level (Vdd_min), in which case the loop delay parameter (r) is then increased; and increasing the frequency of the output frequency signal (F_RO) when its frequency is less than r times the frequency of the reference frequency signal (f_REF) by reducing the loop delay parameter (r), unless the loop delay parameter (r) has reached a minimum level in which case the supply voltage (Vdd) is increased.

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