Device for a particle counting detector
The particle counting detector uses digitization channels and a digital pulse reset circuit to accurately count and evaluate particle number and energy, addressing overlap issues by resetting signals, ensuring reliable operation at high flux rates.
Patent Information
- Application Number
- FR2023011202
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2023-10-17
- Publication Date
- 2025-08-29
- Estimated Expiration
- 2043-10-17
AI Technical Summary
Existing particle counting detectors struggle to accurately assess the number and energy of particles when the probability of receiving two particles close together in time increases, often requiring intervention in the analog part of the detector.
A particle counting detector is designed with digitization channels and a digital pulse reset circuit that generates a second pulsed digital signal based on a threshold, resetting signals after a fixed time period to maintain accurate counting, even when particles are received closely in time.
The detector maintains accurate counting of particle number and energy by resetting signals appropriately, preventing overlap errors and ensuring consistent operation even at high flux rates.
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Abstract
Description
Title of the invention: Device for a particle counting detector Technical field
[0001] The present description relates generally to electronic circuits, and, more particularly, to devices (or circuits) for particle counting detectors. Prior art
[0002] Known electronic systems comprise one or more particle counting detectors. Each detector comprises a photodetector configured to receive incident particles and to provide a pulsed analog current determined by the received particles. Each detector further comprises a current-voltage conversion circuit configured to receive the pulsed analog current and to provide a corresponding pulsed analog voltage. Each detector further comprises a device configured to allow the number and energy of the particles received by the photodetector to be evaluated from the pulsed analog voltage.
[0003] Photon counting spectral scanners are an example of such a known electronic system, for example used for medical imaging. In a photon counting spectral scanner, the particles are for example photons of X-ray radiation, i.e. radiation in the wavelength range from about 0.01 nm to about 10 nm. For example, each photodetector then comprises cadmium telluride.
[0004] Known particle counting detectors have drawbacks. Summary of the invention
[0005] There is a need to overcome all or part of the disadvantages of known particle counting detectors, for example known devices allowing the evaluation of the number and energy of the particles received by these known detectors.
[0006] For example, it would be desirable to have a particle counting detector that can correctly assess the number and energy of the particles it receives when the probability of receiving two particles close together in time increases.
[0007] For example, it would be desirable to have a device for a particle counting detector which allows the particle counting detector to correctly evaluate the number and energy of the particles it receives when the probability of receiving two particles close together in time increases, preferably without intervening upstream of the analog-to-digital conversion circuit of the detector, that is to say without intervening on the purely analog part of the detector.
[0008] One embodiment overcomes all or part of the drawbacks of known particle counting detectors.
[0009] One embodiment overcomes all or part of the drawbacks of known devices for a particle counting detector allowing the evaluation of the number and energy of the particles received by the detector.
[0010] One embodiment provides a device for a particle counting detector, the device comprising: digitization channels each configured to receive a pulsed analog voltage and to provide a first pulsed digital signal in an active state if said voltage is greater than a threshold of the channel, and in an inactive state otherwise; and a digital pulse reset circuit configured to: - for each channel, receiving the first signal from said channel, generating a second pulsed digital signal, and switching the second signal into an active state when the first signal is in the active state; and - generating a reset signal forcing, at each switching to the active state of the second signal of the lowest threshold channel, a switching to the inactive state of the first signals and / or the second signals at the end of a first time period starting with the switching to the active state of the second signal of the lowest threshold channel.
[0011] According to one embodiment, the reset circuit is configured to: - for each channel and after each switching to the active state of the second signal of the channel, to maintain the second signal in the active state until the reset signal forces the second signal to the inactive state; or - for each channel and after each switching to the active state of the second signal of the channel, to maintain the second signal in the active state until the first signal of the channel switches to the inactive state or the reset signal forces the second signal to the inactive state.
[0012] According to one embodiment, the device further comprises a digital counting circuit configured to count, for each channel, a number of switchings to the active state of the second signal of said channel.
[0013] According to one embodiment, a duration of the first time period is fixed.
[0014] According to one embodiment, after each switching to the active state of the second signal of the lowest threshold channel, the first time period ends if the first or second signal of a given channel with a threshold higher than the lowest threshold switches to the inactive state before the end of a second time period of fixed duration and starting with the first time period, and at the end of the second period temporal otherwise.
[0015] According to one embodiment, the reset circuit is configured so that the reset signal maintains the inactive state of the first and / or second signals for a constant duration each time that said reset signal forces a switching to the inactive state of these signals.
[0016] According to one embodiment, each digitization channel comprises a comparator configured to receive the pulsed analog voltage and compare it to the threshold of the channel, and to provide the first digital signal of the channel.
[0017] According to one embodiment, each comparator receives the reset signal.
[0018] According to one embodiment, the reset circuit comprises, for each track, a first circuit configured to receive the reset signal and the first signal from the track, and to provide the corresponding second signal.
[0019] According to one embodiment, each first circuit comprises an RS type flip-flop having an initialization input configured to receive the first signal received by said first circuit, a reset input configured to receive a signal at least partly determined by the reset signal, and an output configured to provide the corresponding second signal.
[0020] According to one embodiment, the reset circuit comprises a second circuit configured to receive the second signal from the lowest threshold channel, and to generate the reset signal from this second signal.
[0021] According to one embodiment, the second circuit comprises: a first monostable circuit configured to receive the second signal from the lowest threshold channel, and to provide a first pulse each time said second signal switches to the active state; and a second monostable circuit configured to receive the first pulses and to provide a second pulse at the end of each first pulse.
[0022] According to one embodiment, the reset signal is determined from the second pulses.
[0023] Another embodiment provides a particle counting detector comprising: a photodetector adapted to receive particles, for example photons of X-ray radiation, and to provide a pulsed analog current determined by the particles received; a current-to-voltage conversion circuit configured to receive the pulsed analog current and to provide a corresponding pulsed analog voltage; and a device as above, configured to receive the pulsed analog voltage.
[0024] Another embodiment provides a photon counting scanner comprising a plurality of particle counting detectors as above, wherein the particles are photons of X-ray radiation, and each photodetector comprises, for example, cadmium telluride. Brief description of the drawings
[0025] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0026] [Fig.l] schematically represents in block form an example of a known particle counting detector;
[0027] [Fig.2] illustrates by means of timing diagrams an example of operation of the detector of [Fig.l];
[0028] [Fig.3] illustrates by means of timing diagrams another example of operation of the detector of [Fig.l];
[0029] [Fig.4] schematically represents in the form of blocks an embodiment of a particle counting detector;
[0030] [Fig.5] illustrates by means of timing diagrams an example of operation of the detector of [Fig.4] according to one embodiment;
[0031] [Fig.6] illustrates by means of timing diagrams another example of operation of the detector of [Fig.4] according to one embodiment; and
[0032] [Fig.7] schematically represents in block form an example of a detailed embodiment of a digital pulse reset circuit of the detector of [Fig.4]. Description of the embodiments
[0033] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0034] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.
[0035] Unless otherwise specified, when referring to two elements connected between them, it means directly connected without intermediate elements other than conductors, and when we refer to two elements connected (in English "coupled") between them, it means that these two elements can be connected or be linked by means of one or more other elements.
[0036] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0037] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0038] [Fig.l] schematically represents in block form an example of a known particle counting detector.
[0039] The DET detector comprises a PD photodetector, a FRONT-END current-voltage conversion circuit and an EVAL-NUM device.
[0040] The photodetector PD is configured to receive the particles to which the detector DET is sensitive, for example photons of X-ray radiation also called X-photons.
[0041] The photodetector PD is further configured to provide a pulsed analog current Idet determined by the X photons it receives. For example, for each X photon that the photodetector PD receives, the current Idet has a current pulse having a shape (width, amplitude, rise and fall slope, etc.) determined by the energy of the received X photon.
[0042] The FRONT-END circuit is configured to receive the current Idet, and to provide a corresponding pulsed analog voltage outFE. For example, at each current pulse of the current Idet, the voltage outFE has a voltage pulse having a shape (width, amplitude, rise and fall slope, etc.) determined by the shape of the current pulse of the current Idet. For example, the FRONT-END circuit is configured so that the voltage outFE has a direct current (DC) component ref, and an alternating current (AC) component having pulses determined by the pulses of the current Idet.
[0043] The EVAL-NUM device or circuit is configured to receive the outFE voltage and to evaluate the number and energy of the X-ray photons received by the PD photodetector from the outFE voltage, or at least provide signals allowing the evaluation of the number and energy of the received X-ray photons.
[0044] More particularly, the EVAL-NUM circuit comprises a NUM circuit and an EVAL circuit.
[0045] The NUM circuit is an analog-to-digital conversion circuit configured to evaluate the amplitude of each voltage pulse of the received outFE voltage. The NUM circuit receives the outFE voltage and provides several digital signals, for example several one-bit signals or binary signals, representative, for each pulse of the outFE voltage, of the amplitude of this pulse.
[0046] The EVAL circuit is configured to count, from the binary signals provided by the NUM circuit and for at least one given X-ray photon energy value, the number of detected X-ray photons having an energy greater than or equal to this given energy value. In other words, the EVAL circuit is configured to provide the spectrum of the X-ray photons detected by the PD photodetector, or at least to provide signals allowing the reconstruction of the spectrum of the detected X-ray photons.
[0047] More particularly, the NUM circuit comprises N digitization channels CHi, with i an index ranging from 1 to N and N a positive integer greater than or equal to 1, preferably 2. For example, in [Fig.l], N is equal to 8, and the NUM circuit comprises 8 channels CHi (CHI, CH2, ..., CHi, ..., CH7 and CH8 in [Fig.l]). Each channel CHi is configured to receive the analog voltage outFE and to provide a pulsed digital signal outi (outl, out2, ..., outi, ..., out7 and out8 in [Fig.l]) in an active state when the voltage outFE is greater than a threshold Thi of the channel (Thl, Th2, ..., Thi, Th7 and Th8 in [Fig.l]), and in an inactive state when the voltage outFE is less than this threshold Thi. Each active state of the signal outi corresponds to a pulse of the signal outi.
[0048] For example, each channel CHi comprises a circuit or comparator COMPi (COMP1, COMP2, ..., COMPi, ..., COMP7 and COMP8 in [Fig.l]) configured to receive the voltage outFE and compare it to the threshold Thi of the channel, and to provide the signal outi of the channel. For example, each comparator COMPi receives the threshold Thi, that is to say a threshold voltage Thi.
[0049] For each channel CHi, the circuit EVAL, in practice a digital counting circuit, is configured in the example of [Fig.l] to count the number of pulses of the signal outi, that is to say the number of switchings to the active state of this signal outi. For example, the circuit EVAL comprises, for each channel CHi, a counter COUNTi (COUNT1, COUNT2, ..., COUNTi, ..., COUNT7 and COUNT8 in [Fig.l]) configured to receive the signal outi and to provide a digital output signal ci (cl, c2, ..., ci, ..., c7 and c8 in [Fig.l]) incremented by one unit for each pulse of the signal outi received.
[0050] [Fig.2] illustrates by timing diagrams an example of operation of the DET detector of [Fig.l]. More particularly, [Fig.2] represents the evolution of the outFE voltage as a function of time t, the thresholds Thi and the evolution of the outi signals as a function of time t in a case where the DET circuit comprises N=4 CHi channels. The thresholds Thi (Thl, Th2, Th3, Th4 in [Fig.2]) are increasing with the index i, the threshold Thl then being the lowest of the Thi thresholds. In this example, the inactive state of the outi signals is the low state, and the active state (pulse) of the outi signals is the high state. In the example of [Fig.2], the outFE voltage has two successive pulses PI and P2.
[0051] In [Fig.2], during the PI pulse, the outFE voltage increases from its resting value, i.e. from the ref value, up to a maximum value determined by the energy of the corresponding X photon received by the PD photodetector ([Fig.l]). During this increase, the outFE voltage successively crosses the thresholds Thl, Th2, Th3 and Th4, which causes the signals outl, out2, out3 and out4 to switch to the active state successively. Then, the outFE voltage decreases from the maximum value of the PI pulse. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the signals out4, out3, out2 and outl to switch to the inactive state successively.
[0052] Similarly, during pulse P2, the outFE voltage increases from its minimum value previously reached to a maximum value determined by the energy of the corresponding X photon received by the photodetector PD. During this increase, the outFE voltage successively crosses the thresholds Thl, Th2, Th3 and Th4, which causes the signals outl, out2, out3 and out4 to switch to the active state successively. Then, the outFE voltage decreases from the maximum value of the pulse PL. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the signals out4, out3, out2 and outl to switch to the inactive state successively.
[0053] In [Fig.2], the two X photons corresponding to the two pulses PI and P2 are received one after the other with a duration between the reception of the first X photon and that of the second X photon which is sufficiently large so that the two corresponding pulses of the current Idet do not overlap or overlap little, from which it results that the voltage outFE falls back below the threshold Thl between the two pulses PI and P2.
[0054] The signals outl to out4 are then such that, in this example, each of the corresponding signals cl to c4 is incremented twice.
[0055] It is then possible, from the signals c1 to c4, to determine that two X photons having an energy greater than a value E4 have been received by the photodetector PD of the detector DET, the energy value E4 determining, with the FRONT-END circuit, the value of the threshold Th4.
[0056] As an example, to reconstruct a histogram of the spectrum of X photons received by the photodetector PD of the detector DET: - for each channel CHi of index i strictly less than N, the value indicated by the signal ci+1 of the channel CHi+1 is subtracted from that indicated by the signal ci of the channel CHi, and the result of this subtraction indicates the number of X photons received with an energy between an energy value Ei and an energy value Ei+1, the value Ei determining with the FRONT-END circuit the value of the threshold Thi of the channel CHi and the value Ei+1 determining with the FRONT-END circuit the value of the threshold Thi+1 of the channel CHi+1; and - for the CHi channel of index N, the value indicated by the signal ci indicates the number of X photons received with an energy greater than the energy value Ei.
[0057] [Fig. 3] illustrates by timing diagrams an example of operation of the DET detector of [Fig. 1]. More particularly, [Fig. 3] represents the evolution of the voltage outFE as a function of time t, the thresholds Thi and the evolution of the signals outi as a function of time t in a case where the DET circuit comprises N=4 channels CHi. The thresholds Thi (Thl, Th2, Th3, Th4 in [Fig. 2]) are increasing with the index i. In this example, the inactive state of the signals outi is the low state, and the active state (pulse) of the signals outi is the high state.
[0058] In the example of [Fig. 3], the outFE voltage has two successive pulses PI and P2. However, compared to [Fig. 2], in the example of [Fig. 3], the two X photons corresponding to the two pulses PI and P2 are received one after the other with a duration between the reception of the first X photon and that of the second X photon which is such that the two corresponding pulses of the current Idet overlap and, between the two pulses PI and P2, the outFE voltage does not fall below the threshold Thl, and more particularly the thresholds Thl and Th2 in this example.
[0059] More particularly, in [Fig.3], during the PI pulse, the voltage outFE increases from its resting value ref up to a maximum value, and successively crosses the thresholds Thl, Th2, Th3 and Th4, which causes the signals outi, out2, out3 and out4 to switch to the active state successively.
[0060] Then, the voltage outFE decreases from the maximum value of the pulse PI to a minimum value reached at the start of the following pulse P2 and between the thresholds Th2 and Th3. During this decrease, the voltage outFE successively crosses the thresholds Th4 and Th3 but does not fall below the thresholds Th2 and Th1, from which it follows that the signals out4 and out3 successively switch to the inactive state while the signals out2 and outi remain in the active state.
[0061] Then, during pulse P2, the outFE voltage increases from the minimum value reached previously, up to a maximum value. During this increase, the outFE voltage successively crosses the thresholds Th4 and Th3, which causes the signals out3 and out4 to switch to the active state successively, the other signals out2 and out3 still being in the active state. Then, the outFE voltage decreases from the maximum value of pulse P2. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Th1, which causes the signals out4, out3, out2 and out1 to switch to the inactive state successively.
[0062] The signals outi to out4 obtained in the example of [Fig.3] do not allow the number and energy of the X photons received to be correctly evaluated.
[0063] As an example, taking the histogram reconstruction example given above, the corresponding signals c1 to c4 would indicate that: 2 X-ray photons with energy greater than E4 were received; 0 X-ray photons with energy between E4 and E3 were received; -1 X-ray photon with energy between E2 and E3 was received; and 0 X-ray photons with energy between E1 and E2 were received.
[0064] [Fig.4] schematically represents in the form of blocks an embodiment of a particle counting detector.
[0065] The DET1 detector includes many elements in common with the DET detector of [Fig.l] and only the differences between these two detectors DET and DET1 are highlighted here. In other words, unless otherwise indicated, everything that has been described for the DET detector of [Fig.l] applies to the DET1 detector of [Fig.4].
[0066] Thus, the detector DET1 comprises the photodetector PD supplying the current Idet, and the FRONT-END circuit receiving the current Idet and supplying the voltage outFE.
[0067] The detector DET1 comprises a device or circuit EVAL-NUM1 similar to the circuit EVAL-NUM of the detector DET of [Fig.l] in that it comprises the circuit NUM and the circuit EVAL. However, the circuit EVAL-NUM1 differs from the circuit NUM-EVAL in that it further comprises a device or circuit PULSE-RESET.
[0068] The circuit EVAL-NUM1 is, like the circuit EVAL-NUM, configured to receive the outFE voltage and to evaluate the number and energy of the X photons received by the photodetector PD from the outFE voltage, or at least provide signals allowing the evaluation of the number and energy of the received X photons.
[0069] In the device EVAL-NUM1, as in [Fig.l], the circuit NUM is an analog-digital conversion circuit configured to evaluate the amplitude of each voltage pulse of the received outFE voltage, the circuit NUM providing several digital signals outi, for example several binary signals, representative, for each pulse of the outFE voltage, of the amplitude of this pulse. In the example of [Fig.4], the circuit NUM comprises N=4 digitization channels CHi, and the thresholds Thi are increasing with the index i.
[0070] Compared to the EVAL-NUM device, in the EVAL-NUM 1 device, the outi signals are not directly supplied to the EVAL circuit. Indeed, in the EVAL-NUM 1 circuit, the PULSE-RESET circuit, which is a digital pulse reset circuit, is configured to receive the outi signals and to supply corresponding outci signals. It is these outci signals which are supplied to the EVAL circuit.
[0071] More particularly, for each channel CHi, the PULSE-RESET circuit is configured to receive the signal outi from this channel, and to generate the corresponding signal outci so that the signal outci is in the active state when the signal outi is in the active state and is in the inactive state when the signal outi is in the inactive state.
[0072] Furthermore, the PULSE-RESET circuit is configured to provide a digital pulse reset signal rst. More particularly, the signal rst is configured to force, each time the outci signal switches to the active state, the outci signals switch to the inactive state, at the end of a time period tmpl starting when the switching to the active state of the outcl signal. Thus, although the rst signal is illustrated in [Fig.4] as an output of the PULSE-RESET circuit, in practice, in the embodiment of [Fig.4] where the rst signal resets the digital pulses of the outci signals, this rst signal is an internal signal of the PULSE-RESET circuit.
[0073] According to one embodiment, the value of the period tmpl is fixed, or, in other words, constant. For example, the duration tmpl is determined empirically, by tests or simulations, and depends on (or is determined by) the FRONT-END circuit and the average energy of the detected particles.
[0074] Preferably, the PULSE-RESET circuit is configured so that the signal rst maintains the inactive state of the outci signals for a constant duration tmp2 each time the signal rst switches these outci signals to the inactive state at the end of a corresponding period tmpl. For example, the duration tmp2 is constant. For example, the duration tmp2 is determined empirically, by tests or simulations. For example, the duration tmp2 is chosen to be as short as possible but large enough to be able to be taken into account by the EVAL circuit, for example by the counters COUNTi of the EVAL circuit (see [Fig.l]). For example, the duration tmp2 is at least ten times shorter than the average width of the voltage pulses of the outFE voltage, the width of an outFE voltage pulse being for example the duration separating the instant when the pulse exceeds the lowest threshold Thi and the instant when the pulse falls back below this threshold Thi.For example, for a given FRONT-END circuit and for particles corresponding to X-ray photons, the average width of the outFE pulses is about 20 ns, and, for example, the duration tmp2 is then about 2 ns.
[0075] The outci signals (outcl, ..., outci, ..., outc4 in [Fig.4]) are supplied to the EVAL circuit of the detector DET1, instead of the outi signals which were supplied to the EVAL circuit of the detector DET of [Fig.l]. Thus, the EVAL circuit here is configured to count, for each channel CHi, the number of pulses of the outci signal, that is to say the number of switchings to the active state of this outci signal. For example, the EVAL circuit provides, for each channel CHi, a digital output signal ci (cl, ..., ci, ..., c4 in [Fig.4]) incremented by one unit for each pulse of the outci signal received.
[0076] As an example, as illustrated in [Fig. 4] for the circuit COMP4 of the circuit NUM, each comparator COMPi of the circuit NUM comprises an open-loop amplifier OTA, the amplifier receiving the voltage outFE on a first input, and the only corresponding Thi on a second input, and providing the corresponding signal outi. As an example, this signal outi can be directly provided at the output of the circuit NUM. As an alternative example, as illustrated in [Fig. 4], the output signal outi of the amplifier is shaped before being transmitted to the corresponding output of the circuit NUM, for example by a buffer circuit BUFF consisting for example of two inverters INV in series. As another alternative example, the output of the OTA amplifier can be coupled to the corresponding output of the NUM circuit by a single inverter INV.
[0077] [Fig.5] illustrates by means of timing diagrams an example of operation of the detector DET1 of [Fig.4] according to an embodiment in which the signal rst is a signal for resetting the signals (or pulses) outci. More particularly, [Fig.5] illustrates: the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the corresponding signals outi as a function of time t, and the evolution of the corresponding signals outci as a function of time t.
[0078] In this example, N is equal to 4, the thresholds Thi have the same values as in [Fig.2] and 3, and the outFE voltage has the same shape as the outFE voltage of [Fig.2] and includes in particular the two successive pulses PI and P2. In this example, it is the high state of the signal rst which forces the outci signals to the inactive state, the other state of the signal rst having no influence on the outci signals.
[0079] During the PI pulse, the outFE voltage increases from its resting value ref, up to a maximum value. During this increase, the outFE voltage successively crosses the thresholds Thi, Th2, Th3 and Th4, which causes the signals outl, out2, out3 and out4 to switch to the active state successively. The PULSE-RESET circuit ( [Fig.4]) then switches the corresponding signals outci, outc2, outc3 and outc4 to the active state at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals outl, out2, out3 and out4 respectively. Furthermore, the switching of the signal outci to the active state marks the beginning of a period tmpl.
[0080] Then, while the period tmpl has not yet expired in this example, the voltage outFE decreases from the maximum value of the pulse PI, and successively crosses the thresholds Th4, Th3, Th2 and Thi, causing the signals out4, out3, out2 and outl to switch to the inactive state successively. The PULSE-RESET circuit ([Fig.4]) then successively switches the corresponding signals outc4, outc3, outc2 and outci to the inactive state, at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2 and outl respectively.
[0081] Between the two pulses PI and P2, while the voltage outFE is below the threshold Thi, the duration tmpl expires, which causes the signal rst to change to a state (the high state in this example) suitable for forcing the signals outci to the inactive state. Since the signals outci are already in the inactive state, the signal rst has no influence here on the operation of the detector DET1. The signal rst is then switched to its other state (the low state in this example), for example at the end of the duration tmp2.
[0082] Then the pulse P2 starts and the voltage outFE increases from a value in lower than the threshold Thl up to a maximum value. During this increase, the voltage outFE successively crosses the thresholds Thl, Th2, Th3 and Th4, which causes the switching to the active state of the signals outl, out2, out3 and out4 successively, and therefore the switching to the active state of the signals outl, out2, out3 and out4 successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals outl, out2, out3 and out4 respectively. In addition, although it is not illustrated in [Fig.5], the switching of the signal outcl to the active state during the second pulse P2 marks the beginning of a new period tmpl.
[0083] Then, the outFE voltage decreases from the maximum value of the pulse P2. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the switching to the inactive state of the signals out4, out3, out2 and outl successively, and the switching to the inactive state of the signals outc4, outc3, outc2 and outcl successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2 and outl respectively.
[0084] The example in [Fig.5] shows that, when the time separating the reception of two successive X photons is long enough for the voltage outFE to fall below the threshold Thl between the pulses PI and P2, the PULSE-RESET circuit, and in particular the signal rst that it generates, does not modify the correct operation of the detector DET1 with respect to the detector DET, the signals outci then being identical to the signals outi.
[0085] [Fig.6] illustrates by means of timing diagrams an example of operation of the detector DET1 of [Fig.4] according to an embodiment in which the signal rst is a signal for resetting the signals (or pulses) outci. More particularly, [Fig.6] illustrates: the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the corresponding signals outi as a function of time t, and the evolution of the corresponding signals outci as a function of time t.
[0086] In this example, N is equal to 4, the thresholds Thi have the same values as in [Fig.2] and 3, and the outFE voltage has the same shape as the outFE voltage of [Fig.3] and includes in particular the two successive pulses PI and P2. In this example, it is the high state of the signal rst which forces the signals outci to the inactive state, the other state of the signal rst having no influence on the signals outci.
[0087] During the PI pulse, the outFE voltage increases from its resting value ref, up to a maximum value. During this increase, the outFE voltage successively crosses the thresholds Thl, Th2, Th3 and Th4, which causes the signals outl, out2, out3 and out4 to switch to the active state successively. The PULSE-RESET circuit ( [Fig.4]) then switches the corresponding signals outcl, outc2, outc3 and outc4 to the active state at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals outl, out2, out3 and out4 respectively. Furthermore, the switching of the signal outcl to the active state marks the beginning of a period tmpl.
[0088] Then, while the period tmpl has not yet expired in this example, the voltage outFE decreases from the maximum value of the pulse PI, and successively crosses the thresholds Th4 and Th3, but does not fall below the thresholds Th2 and Thl. As a result, the signals out4 and out3 successively switch to the inactive state, but the signals out2 and outl remain in the active state. In addition, the corresponding signals outc4 and outc3 successively switch to the inactive state at the same times (neglecting the propagation delays) as the respective signals out4 and out3, the signals outc2 and outcl remaining, like the signals out2 and outl, in the active state.
[0089] Between the two pulses PI and P2, while the voltage outFE is at a value between the thresholds Th3 and Th2, the duration tmpl expires, which causes the signal rst to switch to a state (the high state in this example) suitable for forcing the signals outci to the inactive state. Since the signals outc4 and outc3 are already in the inactive state, the signal rst has no influence on these signals here. On the other hand, the signal rst forces the switching to the inactive state of the signals outc2 and outcl although the signals out2 and outl are in the active state. The signal rst is then switched to its other state (the low state in this example), for example at the end of the duration tmp2. Once the rst signal is switched back to its low state, since the out2 and outl signals are still in the active state, the PULSE-RESET circuit switches the corresponding outc2 and outcl signals to the active state. Although this is not illustrated in [Fig.6], this switching of the outcl signal to the active state at the end of the high state of the rst signal marks the beginning of a new tmpl period.
[0090] Then the pulse P2 begins and the voltage outFE increases to a maximum value. During this increase, the voltage outFE successively crosses the thresholds Th3 and Th4, which causes the signals out3 and out4 to switch to the active state successively, and therefore the signals outc3 and out4 to switch to the active state successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out3 and out4 respectively.
[0091] Then, the voltage outFE decreases from the maximum value of the pulse P2. During this decrease, the voltage outFE successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the switching to the inactive state of the signals out4, out3, out2 and outl successively, and the switching to the inactive state of the signals outc4, outc3, outc2 and outcl successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2 and outl respectively.
[0092] The example in [Fig.6] shows that, when the time separating the reception of two successive X-ray photons is too weak for the outFE voltage to fall below the Thl threshold between the PI and P2 pulses, the PULSE-RESET circuit, and in particular the rst signal that it generates, makes it possible to force the reinitialization of the outci signals which have not returned to the inactive state between the two PI and P2 pulses.
[0093] Thus, since it is the signals outci which are supplied to the circuit EVAL, each of the signals ci is indeed incremented twice in this example. It is then possible, from the signals cl to c4, to determine that two X photons having an energy greater than a value E4 were received by the photodetector PD of the detector DET1, the energy value E4 determining, with the FRONT-END circuit, the value of the threshold Th4, whereas this was not the case with the signals ci of the detector DET.
[0094] In particular, in very high flux applications, when the photodetector PD ( [Fig.4]) receives so many X photons that at least some of the signals outi remain permanently in the active state, where the detector DET of [Fig.l] would be paralyzed and would not generate any incrementation of the corresponding signals ci, the detector DET1 is not paralyzed and will continue to increment the corresponding signals ci thanks to the reinitializations of the signals outci by the signal rst. In this case, the detector DET1 will have a counting frequency which does not decrease at very high flux but which will reach a maximum value equal to l / (tmpl + tmp2).
[0095] [Fig.7] schematically represents in the form of blocks, an example of a detailed embodiment of the PULSE-RESET circuit of the DET1 detector of [Fig.4]
[0096] In this embodiment, the rst signal is configured to reset the outci signals.
[0097] In this example, N is equal to 4.
[0098] The PULSE-RESET circuit comprises, for each channel CHi, a circuit GENi (GEN1, ..., GENi, ..., GEN4 in [Fig.7]) configured to receive the signal outi from the channel CHi, receive the signal rst and generate the corresponding signal outci.
[0099] According to one embodiment, as illustrated in [Fig.7], each GENi circuit comprises an RS flip-flop 700 and an OR combinational logic gate. The OR logic gate is configured to receive the outi signal and the rst signal, and to provide a binary output in the active state, for example the high state, if the outi signal is in the inactive state or the rst signal is in the active state, and in the inactive state, for example the low state, otherwise. The RS flip-flop comprises, in the usual manner, an initialization input S, a reset input R and an output Q. The input S is controlled, for example receives, the corresponding outi signal, the input R being controlled, for example receiving, the output signal of the OR gate. The output Q determines, for example provides, the corresponding outci signal. More particularly, in each GENi circuit, the flip-flop 700 is configured to: - switching the outci signal to the active state when the outi signal (input S) switches to the active state while its input R receives a signal in the inactive state; and - switch the outci signal to the inactive state when its R input receives a signal in the active state.
[0100] The person skilled in the art will be able to foresee other implementations of the GENi circuits.
[0101] For example, the person skilled in the art will be able to implement each GENi circuit using a combinational circuit taking as input the signal outi and the signal rst, and providing the corresponding signal outci. For example, in the case where the signals outi, rst and outci are active in the high state, and inactive in the low state, the GENi circuit can be implemented with an AND gate having an input receiving the signal outi, another input receiving a binary signal in the high state when the signal rst is in the low state, and in the low state when the signal rst is in the high state, and an output providing the corresponding signal outci.
[0102] As another example, the person skilled in the art will be able to implement each GENi circuit using a multiplexer taking the signal outi and a signal at a level corresponding to the inactive state of the signals outi and outci on two respective data inputs, and the signal rst on a control input, and providing as output the corresponding signal outci. For example, when the signal rst is active, the multiplexer couples its output to the data input receiving the signal outi when the signal rst is inactive, and couples its output to the other data input when the signal rst is active.
[0103] Furthermore, in the embodiment of [Fig.7], the PULSE-RESET circuit comprises a GEN-RST circuit configured to provide the rst signal, from at least the outci signal. The GEN-RST circuit is therefore configured to receive the outci signal and to provide the rst signal from the outci signal.
[0104] According to one embodiment, the GEN-RST circuit comprises a first monostable circuit M0N01 and a second monostable circuit M0N02. The circuit M0N01 is configured to receive the signal outci from the channel CH1 with the lowest threshold Thl, and to provide a pulse P3 each time the signal outci switches to the active state. In other words, each switching of the signal outci to the active state causes the circuit M0N01 to provide a pulse P3. In other words, each switching of the signal outci to the active state triggers the monostable circuit M0N01. The circuit M0N02 is configured to receive the pulses P3, and to provide, for each pulse P3 received, for example at the end of each pulse P3 received, a pulse P4. The rst signal is determined by the P4 pulses, for example is identical to the output signal of the M0N02 circuit having the P4 pulses.For example, the rst signal is configured to force the outci signals to the inactive state on each P4 pulse, and for the duration of that P4 pulse.
[0105] For example, the duration of each pulse P3 is equal to the duration tmpl, and the duration of each pulse P4 is equal to the duration tmp2.
[0106] According to one embodiment, the monostable circuits MONO1 and MONO2 each comprise one or more resistive components and one or more capacitive components whose resistance values and capacitance values determine the duration of the pulses P3 and P4. Preferably, these resistance values and / or these capacitance values are adjustable so that the durations tmpl and tmp2 can be adapted according to the application in which the device EVAL-NUM1 is implemented, for example according to the characteristics of the FRONT-END circuit and / or the particles detected.
[0107] In the embodiments described above in relation to Figures 4, 5, 6 and 7, the signal rst is configured to force the outci signals to the inactive state upon expiration of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi.
[0108] In alternative embodiments, in addition to forcing the outci signals to the inactive state at the expiration of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi, the signal rst is further configured to force the reinitialization of other circuits, in particular the comparators COMPi. For example, according to an alternative embodiment, the signal rst is configured to force the outci signals and the outi signals to the inactive state at the expiration of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi. In such an alternative, each comparator COMPi receives the signal rst, for example on a reset input of the comparator COMPi. For example, each time the signal rst forces the outci signals to the inactive state, this signal also forces the outi signals to the inactive state.The person skilled in the art will be able to adapt the description given above in relation to figures 4, 5, 6 and 7 to such a variant.
[0109] In other alternative embodiments, rather than forcing the outci signals to the inactive state at the end of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi, the signal rst is configured to force the reinitialization of other circuits, in particular the comparators COMPi, at the end of the time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi. For example, according to an alternative embodiment, the signal rst is configured to force only the outi signals to the inactive state at the end of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi. In such an alternative, each comparator COMPi receives the signal rst, for example on a reset input of the comparator COMPi. For example, in such an alternatively, each GENi circuit is configured to copy the outi signal that it receives onto the outci signal that it provides. For example, each GENi circuit then comprises a simple connection or a buffer circuit or a delay circuit or an inverter between its input receiving the outi signal and its output providing the corresponding outci signal. The person skilled in the art will be able to adapt the description given above in relation to figures 4, 5, 6 and 7 to such a variant.
[0110] In the embodiments described above in relation to figures 4, 5, 6 and 7, each time period tmpl has the same constant duration.
[0111] In alternative embodiments, a time period tmpl is triggered, by the PULSE-RESET circuit, each time the signal outci of the channel CHi with the lowest threshold Thi switches to the active state, but this period tmpl ends: if the signal outi or outci of a given CHi channel, preferably the CHN channel, having a threshold Thi greater than the lowest threshold Thl switches to the inactive state before the end of a time period tmplmax of fixed duration which begins at the same time as the period tmpl, and at the end of the time period tmplmax otherwise.
[0112] The implementation of such variant embodiments is within the reach of those skilled in the art from the present description.
[0113] Furthermore, alternative embodiments as described above where the duration tmpl is not fixed are combinable with the alternative embodiments in which the signal rst is configured to force the reset of only the outi signals, and with the alternative embodiments in which the signal rst is configured to force the reset of the outi signals and the outci signals. The implementation of such combinations is within the scope of the person skilled in the art from the present description.
[0114] In the embodiments and variants described above, the PULSE-RESET circuit is configured to switch, for each channel CHi, the signal outci to the active state when the signal outi switches to the active state, to switch the signal outci to the inactive state when the signal outi switches to the inactive state and to generate the signal rst configured to force the signals outci and / or the signals outi to the inactive state. In the case where the signal rst is configured to force at least the signals outci to the inactive state, in variant embodiments, the PULSE-RESET circuit is configured, for each channel CHi, to switch the signal outci to the active state when the signal outi switches to the active state, and to maintain this signal outci in the active state as long as the signal rst does not force the switching of this signal outci to the inactive state. Such a variant is compatible with a fixed duration tmpl and with a variable duration tmpl but limited by a duration tmpmaxl.As an example of the implementation of such a variant, taking the example of the PUSLE-RESET circuit in [Fig.7], this amounts, for each GENi circuit, to removing the OR gates so that the R input of the flip-flop is controlled. for example receives the rst signal. In such an example, the RS flip-flop is then configured to: - switch the outci signal (output Q) to the active state when the outi signal (input S) switches to the active state while the rst signal is in the inactive state (input R); - switch the outci signal (output Q) to the inactive state when the rst signal (input R) switches to the active state, whether the outi signal is in the active state or not; and - keep the outci signal (output Q) in the inactive state as long as the rst signal (input R) and the outi signal (input S) are simultaneously in the inactive state.
[0115] Although embodiments and variants of a detector DET1 comprising a device EVAL-NUM1 have been described, one embodiment provides the device EVAL-NUM1 alone, i.e. without the FRONT-END circuit and the photodetector PD. Indeed, it may be desirable for a set of a photodetector PD and a FRONT-END circuit to be developed and produced by one entity (legal or natural person), and for the circuit EVAL-NUM1 to be developed and produced by another entity (legal or natural person) and to be compatible with this set of a photodetector PD and a FRONT-END circuit, for example by adjusting the values of the thresholds Thi and / or the durations tmpl (or tmplmax) and / or tmp2 accordingly.
[0116] Similarly, one embodiment provides the PULSE-RESET circuit alone, i.e. without the NUM, EVAL and FRONT-END circuits and without the PD photodetector.
[0117] Furthermore, one embodiment provides a particle counting scanner, for example X-ray photons, comprising a plurality of photon counting detectors DET1. In the case where the particles detected by each detector DET1 of the scanner, each photodetector PD comprises, for example, cadmium telluride. For example, according to a particular embodiment, all the photodetectors PD of a set of several detectors DET1 are arranged in a first level of a stack, the first level comprising, for example, a layer or a substrate of cadmium telluride, and all the FRONT-END and EVAL-NUM1 circuits of this set of detectors DET1 are arranged in a second level of the stack, the first level comprising, for example, a silicon substrate or a silicon layer, for example of the SOI type.The first level is then mounted on the second level, and is electrically connected to it, for example, by conductive balls or pads.
[0118] Of course, the embodiments and variants described above are not limited to implementation in an X-ray photon counting scanner, and, more generally, are not limited to implementation in a particle counting scanner.
[0119] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art.
[0120] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Claims
1. Device (EVAL-NUM1) for a particle counting detector (DET1), the device comprising: digitization channels (CHi) each configured to receive a pulsed analog voltage (outFE) and to provide a first pulsed digital signal (outi) in an active state if said voltage is greater than a threshold (Thi) of the channel, and in an inactive state otherwise; and a digital pulse reset circuit (PULSE-RESET) configured to: - for each channel (CHi), receive the first signal (outi) of said channel, generate a second pulsed digital signal (outci), and switch the second signal into an active state when the first signal is in the active state;and - generating a reset signal (rst) forcing, at each switching to the active state of the second signal (outci) of the channel (CHI) with the lowest threshold (THI), a switching to the inactive state of the first signals (outi) and / or of the second signals (outci) at the end of a first time period (tmpl) starting with the switching to the active state of the second signal of the channel with the lowest threshold.;
2. Device according to claim 1, in which the reset circuit (PULSE-RESET) is configured to: - for each channel (CHi) and after each switching to the active state of the second signal (outci) of the channel, to maintain the second signal in the active state until the reset signal (rst) forces the second signal to the inactive state; or - for each channel (CHi) and after each switching to the active state of the second signal (outci) of the channel, to maintain the second signal in the active state until the first signal (outi) of the channel switches to the inactive state or the reset signal (rst) forces the second signal to the inactive state.
3. Device according to claim 1 or 2, wherein the device further comprises a digital counting circuit (EVAL) configured to count, for each channel (CHi), a number of switchings to the active state of the second signal (outci) of said channel.
4. Device according to any one of claims 1 to 3, wherein a duration of the first time period (tmpl) is fixed.
5. A device according to any one of claims 1 to 3, wherein, after each switching to the active state of the second signal (outcl) of the channel (CH1) with the lowest threshold (Thl), the first time period (tmpl) ends if the first or second signal (outi; oucti) of a given channel (CHi) with a threshold (Thi) higher than the lowest threshold (Thl) switches to the inactive state before the end of a second time period of fixed duration and starting with the first time period (tmpl), and at the end of the second time period otherwise.
6. Device according to any one of claims 1 to 5, in which the reset circuit (PULSE-RESET) is configured so that the reset signal (rst) maintains the inactive state of the first and / or second signals (outi; outci) for a constant duration (tmp2) each time that said reset signal (rst) forces a switching to the inactive state of these signals.
7. Device according to any one of claims 1 to 6, wherein: each digitization channel (CHi) comprises a comparator (COMPi, OTA) configured to receive the pulsed analog voltage (outFE) and compare it to the threshold (Thi) of the channel, and to provide the first digital signal (outi) of the channel.
8. Device according to claim 7, in which each comparator (COMPi, OTA) receives the reset signal (rst).
9. Device according to any one of claims 1 to 8, in which the reset circuit (PULSE-RESET) comprises, for each channel (CHi), a first circuit (GENi) configured to receive the reset signal (rst) and the first signal (outi) of the channel, and to provide the corresponding second signal (outci).
10. Device according to claim 9, wherein each first circuit (GENi) comprises an RS type flip-flop (700) having an initialization input (S) configured to receive the first signal (out) received by said first circuit, a reset input (R) configured to receive a signal at least partly determined by the reset signal, and an output (Q) configured to provide the corresponding second signal (outci).
11. Device according to any one of claims 1 to 10, in which the reset circuit (PULSE-RESET) comprises a second circuit (GEN-RST) configured to receive the second signal (outcl) from the lowest threshold channel (THI), and to generate the reset signal (rst) from this second signal (outcl).
12. A device according to claim 11, wherein the second circuit (GEN-RST) comprises: a first monostable circuit (M0N01) configured to receive the second signal (outl) from the lowest threshold (TH1) channel (CH1), and to provide a first pulse (P3) each time said second signal switches to the active state; and a second monostable circuit (M0N02) configured to receive the first pulses (P3) and to provide a second pulse (P4) at the end of each first pulse (P3).
13. Device according to claim 12, wherein the reset signal (rst) is determined from the second pulses (P4).
14. Particle counting detector (DET1) comprising: a photodetector (PD) adapted to receive particles, for example photons of X-ray radiation, and to provide a pulsed analog current (Idet) determined by the received particles; a current-voltage conversion circuit (FRONT-END) configured to receive the pulsed analog current (Idet) and to provide a corresponding pulsed analog voltage (outFE); and a device (EVAL-NUM1) according to any one of claims 1 to 13, configured to receive the pulsed analog voltage.
15. A photon counting scanner comprising a plurality of particle counting detectors (DET1) according to claim 14, wherein the particles are photons of X-ray radiation, and each photodetector (PD) comprises, for example, cadmium telluride.