Device for a particle counting detector

Abstract

Device for a particle counting detector This description relates to a device (EVAL-NUM2) for a particle counting detector (DET2), in which: the device comprises N digitizing channels, CHi, with N an integer strictly greater than 1 and i an index from 1 to N; each channel CHi comprises a comparator, COMPi, associated with a threshold, Thi, of the channel and providing a first digital pulse signal, outi, active if a pulse voltage (outFE) is greater than the threshold of the channel, and inactive otherwise; the thresholds Thi are increasing with the index i; for i from 2 to N, each comparator COMPi operates selectively in a low-power mode and a high-power mode; and the device comprises a circuit (BOOST) controlling, for i from 2 to N, each comparator COMPi in the low-power mode or in the high-power mode as a function of at least the first signal outi of at least one of the channels CHi.Figure for the summary: Fig. 3.

Description

Title of the invention: Device for a particle counting detector Technical field

[0001] The present description relates generally to electronic circuits, and, more particularly, to devices (or circuits) for particle counting detectors. Prior art

[0002] Known electronic systems comprise one or more particle counting detectors. Each detector comprises a photodetector configured to receive incident particles and to provide a pulsed analog current determined by the received particles. Each detector further comprises a current-voltage conversion circuit configured to receive the pulsed analog current and to provide a corresponding pulsed analog voltage. Each detector further comprises a device configured to allow the number and energy of the particles received by the photodetector to be evaluated from the pulsed analog voltage.

[0003] Photon counting spectral scanners are an example of such a known electronic system, for example used for medical imaging. In a photon counting spectral scanner, the particles are for example photons of X-ray radiation, i.e. radiation in the wavelength range from about 0.01 nm to about 10 nm. For example, each photodetector then comprises cadmium telluride.

[0004] Known particle counting detectors have drawbacks. Summary of the invention

[0005] There is a need to overcome all or part of the disadvantages of known particle counting detectors, for example known devices allowing the evaluation of the number and energy of the particles received by these known detectors.

[0006] For example, it would be desirable to have a particle counting detector that has reduced power consumption compared to known particle counting detectors.

[0007] For example, it would be desirable to have a device for a particle counting detector which makes it possible to reduce the consumption of the particle counting detector compared to known particle counting detectors.

[0008] For example, it would be desirable to have a particle counting detector that can correctly assess the number and energy of the particles it receives. when the probability of receiving two particles close together in time increases.

[0009] For example, it would be desirable to have a device for a particle counting detector which allows the particle counting detector to correctly evaluate the number and energy of the particles it receives when the probability of receiving two particles close together in time increases, preferably without intervening upstream of the analog-digital conversion circuit of the detector, i.e. without intervening on the purely analog part of the detector.

[0010] One embodiment overcomes all or part of the drawbacks of known particle counting detectors.

[0011] One embodiment overcomes all or part of the drawbacks of known devices for a particle counting detector allowing the evaluation of the number and energy of the particles received by the detector.

[0012] One embodiment provides a device for a particle counting detector, wherein: the device comprises N digitization channels, CHi, with N an integer strictly greater than 1 and i an index ranging from 1 to N, each channel CHi comprises a comparator, COMPi, associated with a threshold, Thi, of the channel and configured to provide a first pulsed digital signal, outi, in an active state if a pulsed analog voltage supplied to said channels is greater than the threshold of the channel, and in an inactive state otherwise; the thresholds Thi are increasing with the index i; for i ranging from 2 to N, each comparator COMPi is configured to selectively operate in a low power mode and a high power mode; and the device comprises a control circuit for the comparators COMPi configured, for i ranging from 2 to N, to control each comparator COMPi in the low consumption mode or in the high consumption mode as a function of at least the first signal outi of at least one of the channels CHi.

[0013] According to one embodiment, the control circuit is configured, during a rising edge of each pulse of said voltage and for i ranging from 2 to N, to switch each comparator COMPi into the high consumption mode in response to a switching to the active state of the first signal outi of the channel CHI or of the first signal outi-1 of the channel CHi-1.

[0014] According to one embodiment, the control circuit is further configured, following the rising edge of the pulse of said voltage and for i ranging from 2 to N, to switch each comparator COMPi into the low consumption mode at the earliest in response to a switching to the active state of the first signal outi of the channel CHi, and at the latest in response to a switching to the inactive state of the first signal outi of the channel CHI.

[0015] According to one embodiment, the control circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high consumption mode if the first signal outi-1 of channel CHi-1 is in the active state, and in low consumption mode otherwise.

[0016] According to one embodiment, N is strictly greater than 2 and the control circuit is configured, for i ranging from 2 to N-1, for: - control each COMPi comparator in high consumption mode if the first signal outi-1 of channel CHi-1 is in the active state while the first signal outi+1 of channel CHi+1 is in the inactive state, and in low consumption mode otherwise; and - control the comparator COMPN in high consumption mode if the first signal outN-1 of channel CHN-1 is active and in low consumption mode otherwise.

[0017] According to one embodiment, the control circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in the high consumption mode if the first signal outl of the channel CH1 is in the active state, and in the low consumption mode otherwise.

[0018] According to one embodiment: - the COMPI comparator is configured to operate only in high power mode; or - the COMPI comparator is configured to operate selectively in high consumption mode or in low consumption mode, and the control circuit is configured to control the COMPI comparator in high consumption mode if the first signal out2 is in the inactive state, and in low consumption mode otherwise.

[0019] According to one embodiment, the device further comprises a digital counting circuit configured to count, for each channel CHi, a number of switchings to the active state of the first signal outi of said channel.

[0020] According to one embodiment: the device further comprises a digital pulse reset circuit configured to: - for each channel CHi, receive the first signal outi of said channel, generate a second pulsed digital signal outci, and switch the second signal outci into an active state when the first signal outi is in the active state; and - generate a reset signal forcing, at each switching to the active state of the second outci signal of the CHI channel, a switching to the inactive state of the first outi signals and / or the second outci signals at the end of a first time period starting with the switching to the active state of the second outci signal of the CHI channel.

[0021] According to one embodiment, the reset signal is configured to force, at each switching to the active state of the second outcl signal of the CH1 channel, at least the switching to the inactive state of the first outi signals at the end of the first time period starting with the switching to the active state of the second outcl signal of the CH1 channel.

[0022] According to one embodiment: the device further comprises a digital pulse reset circuit configured to: - for each channel CHi, receive the first signal outi of said channel, generate a second pulsed digital signal outci, and switch the second signal outci into an active state when the first signal outi is in the active state; and - generate a reset signal forcing, at each switching to the active state of the second outcl signal of the CHI channel, a switching to the inactive state of the first outi signals at the end of a first time period starting with the switching to the active state of the second outcl signal of the CHI channel, and the control circuit is configured to, for i ranging from 2 to N, control each comparator COMPi in the high consumption mode if the first signal outi of the channel CHi is in the inactive state while the first signal outi of the channel CHI is in the active state, and in the low consumption mode otherwise.

[0023] According to one embodiment: the device further comprises a digital pulse reset circuit configured to: - for each channel CHi, receive the first signal outi of said channel, generate a second pulsed digital signal outci, and switch the second signal outci into an active state when the first signal outi is in the active state; and - generate a reset signal forcing, at each switching to the active state of the second outcl signal of the CHI channel, a switching to the inactive state of the first outi signals at the end of a first time period starting with the switching to the active state of the second outcl signal of the CHI channel, and the control circuit is configured to, for i ranging from 2 to N, control each comparator COMPi in the high consumption mode if the first signal outi of the channel CHi is in the inactive state while the first signal outi-1 of the channel CHi-1 is in the active state, and in the low consumption mode otherwise.

[0024] According to one embodiment, the device further comprises a digital counting circuit configured to count, for each channel CHi, a number of switchings to the active state of the second signal outci of said channel.

[0025] One embodiment provides a particle counting detector comprising: a photodetector adapted to receive particles, for example photons of X-ray radiation, and to provide a pulsed analog current determined by the particles received; a current-to-voltage conversion circuit configured to receive the pulsed analog current and to provide a corresponding pulsed analog voltage; and a device as above, configured to receive the pulsed analog voltage.

[0026] One embodiment provides a photon counting scanner comprising a plurality of particle counting detectors as above, wherein the particles are photons of X-ray radiation, and each photodetector comprises, for example, cadmium telluride.

[0027] Another embodiment provides a device for a particle counting detector, the device comprising: digitization channels each configured to receive a pulsed analog voltage and to provide a first pulsed digital signal in an active state if said voltage is greater than a threshold of the channel, and in an inactive state otherwise; and a digital pulse reset circuit configured to: - for each channel, receiving the first signal from said channel, generating a second pulsed digital signal, and switching the second signal into an active state when the first signal is in the active state; and - generating a reset signal forcing, at each switching to the active state of the second signal of the lowest threshold channel, a switching to the inactive state of the first signals and / or the second signals at the end of a first time period starting with the switching to the active state of the second signal of the lowest threshold channel.

[0028] According to one embodiment, the reset circuit is configured to: - for each channel and after each switching to the active state of the second signal of the channel, to maintain the second signal in the active state until the reset signal forces the second signal to the inactive state; or - for each channel and after each switching to the active state of the second signal of the channel, to maintain the second signal in the active state until the first signal of the channel switches to the inactive state or the reset signal forces the second signal to the inactive state.

[0029] According to one embodiment, the device further comprises a digital counting circuit configured to count, for each channel, a number of switchings to the active state of the second signal of said channel.

[0030] According to one embodiment, a duration of the first time period is fixed.

[0031] According to one embodiment, after each switching to the active state of the second signal from the lowest threshold channel, the first time period ends if the first or second signal of a given channel with a threshold higher than the lowest threshold switches to the inactive state before the end of a second time period of fixed duration and starting with the first time period, and at the end of the second time period otherwise.

[0032] According to one embodiment, the reset circuit is configured so that the reset signal maintains the inactive state of the first and / or second signals for a constant duration each time that said reset signal forces a switching to the inactive state of these signals.

[0033] According to one embodiment, each digitization channel comprises a comparator configured to receive the pulsed analog voltage and compare it to the threshold of the channel, and to provide the first digital signal of the channel.

[0034] According to one embodiment, each comparator receives the reset signal.

[0035] According to one embodiment, the reset circuit comprises, for each track, a first circuit configured to receive the reset signal and the first signal from the track, and to provide the corresponding second signal.

[0036] According to one embodiment, each first circuit comprises an RS type flip-flop having an initialization input configured to receive the first signal received by said first circuit, a reset input configured to receive a signal at least partly determined by the reset signal, and an output configured to provide the corresponding second signal.

[0037] According to one embodiment, the reset circuit comprises a second circuit configured to receive the second signal from the lowest threshold channel, and to generate the reset signal from this second signal.

[0038] According to one embodiment, the second circuit comprises: a first monostable circuit configured to receive the second signal from the lowest threshold channel, and to provide a first pulse each time said second signal switches to the active state; and a second monostable circuit configured to receive the first pulses and to provide a second pulse at the end of each first pulse.

[0039] According to one embodiment, the reset signal is determined from the second pulses.

[0040] Another embodiment provides a particle counting detector comprising: a photodetector adapted to receive particles, for example photons of X-ray radiation, and to provide a pulsed analog current determined by the particles received; a current-to-voltage conversion circuit configured to receive the pulsed analog current and to provide a corresponding pulsed analog voltage laying; and a device as above, configured to receive the pulsed analog voltage.

[0041] Another embodiment provides a photon counting scanner comprising a plurality of particle counting detectors as above, wherein the particles are photons of X-ray radiation, and each photodetector comprises, for example, cadmium telluride. Brief description of the drawings

[0042] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0043] [Fig.l] schematically represents in block form an example of a known particle counting detector;

[0044] [Fig.2] illustrates by means of timing diagrams an example of operation of the detector of [Fig.l];

[0045] [Fig.3] schematically represents in the form of blocks an embodiment of a particle counting detector;

[0046] [Fig.4] illustrates by means of timing diagrams an example of operation of the detector of [Fig.3];

[0047] [Fig.5] schematically represents in the form of blocks another embodiment of a particle counting detector;

[0048] [Fig.6] illustrates by means of timing diagrams an example of operation of the detector of [Fig.5];

[0049] [Fig.7] schematically represents in the form of blocks another embodiment of a particle counting detector;

[0050] [Fig.8] illustrates by means of timing diagrams an example of operation of the detector of [Fig.5];

[0051] [Fig.9] illustrates by means of timing diagrams another example of operation of the detector of [Fig.1];

[0052] [Fig. 10] schematically represents in block form another embodiment of a particle counting detector;

[0053] [Fig. 1 1] illustrates by means of timing diagrams an example of operation of the detector of [Fig. 10] according to one embodiment;

[0054] [Fig. 12] illustrates by means of timing diagrams another example of operation of the detector of [Fig. 10] according to one embodiment;

[0055] [Fig. 13] schematically represents in block form an example of a detailed embodiment of a digital pulse reset circuit of the detector of [Fig. 10];

[0056] [Fig. 14] schematically represents in block form another embodiment of a particle counting detector;

[0057] [Fig. 15] illustrates by means of timing diagrams an example of operation of the detector of [Fig. 14] according to one embodiment; and

[0058] [Fig. 16] illustrates by means of timing diagrams an example of operation of the detector of [Fig. 14] according to another embodiment. Description of the embodiments

[0059] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0060] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0061] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0062] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0063] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0064] [Fig.l] schematically represents in block form an example of a known particle counting detector.

[0065] The DET detector comprises a PD photodetector, a FRONT-END current-voltage conversion circuit and an EVAL-NUM device.

[0066] The photodetector PD is configured to receive the particles to which the detector DET is sensitive, for example photons of X-ray radiation also called X-photons.

[0067] The photodetector PD is further configured to provide a pulsed analog current Idet determined by the X photons it receives. For example, for each X photon that the photodetector PD receives, the current Idet has a current pulse having a shape (width, amplitude, rise and fall slope, etc.) determined by the energy of the received X-ray photon.

[0068] The FRONT-END circuit is configured to receive the current Idet, and to provide a corresponding pulsed analog voltage outFE. For example, at each current pulse of the current Idet, the voltage outFE has a voltage pulse having a shape (width, amplitude, rise and fall slope, etc.) determined by the shape of the current pulse of the current Idet. For example, the FRONT-END circuit is configured so that the voltage outFE has a direct current (DC) component ref, and an alternating current (AC) component having pulses determined by the pulses of the current Idet.

[0069] The EVAL-NUM device or circuit is configured to receive the outFE voltage and to evaluate the number and energy of the X-ray photons received by the PD photodetector from the outFE voltage, or at least provide signals allowing the evaluation of the number and energy of the received X-ray photons.

[0070] More particularly, the EVAL-NUM circuit comprises a NUM circuit and an EVAL circuit.

[0071] The NUM circuit is an analog-to-digital conversion circuit configured to evaluate the amplitude of each voltage pulse of the received outFE voltage. The NUM circuit receives the outFE voltage and provides several digital signals, for example several one-bit signals or binary signals, representative, for each pulse of the outFE voltage, of the amplitude of this pulse.

[0072] The EVAL circuit is configured to count, from the binary signals provided by the NUM circuit and for at least one given X-photon energy value, the number of detected X-photons having an energy greater than or equal to this given energy value. In other words, the EVAL circuit is configured to provide the spectrum of the X-photons detected by the PD photodetector, or at least to provide signals making it possible to reconstruct the spectrum of the detected X-photons.

[0073] More particularly, the NUM circuit comprises N digitization channels CHi, with i an index ranging from 1 to N and N a positive integer greater than or equal to 1, preferably 2. For example, in [Fig.l], N is equal to 8, and the NUM circuit comprises 8 channels CHi (CHI, CH2, ..., CHi, ..., CH7 and CH8 in [Fig.l]). Each channel CHi is configured to receive the analog voltage outFE and to provide a pulsed digital signal outi (outl, out2, ..., outi, ..., out7 and out8 in [Fig.l]) in an active state when the voltage outFE is greater than a threshold Thi of the channel (Thl, Th2, ..., Thi, Th7 and Th8 in [Fig.l]), and in an inactive state when the voltage outFE is less than this threshold Thi. Each active state of the signal outi corresponds to a pulse of the signal outi.

[0074] For example, each channel CHi comprises a circuit or comparator COMPi (COMP1, COMP2, ..., COMPi, ..., COMP7 and COMP8 in [Fig.l]) configured to receive the outFE voltage and compare it to the channel threshold Thi, and to provide the channel signal outi. For example, each comparator COMPi receives the threshold Thi, i.e. a threshold voltage Thi.

[0075] For each channel CHi, the circuit EVAL, in practice a digital counting circuit, is configured in the example of [Fig.l] to count the number of pulses of the signal outi, that is to say the number of switchings to the active state of this signal outi. For example, the circuit EVAL comprises, for each channel CHi, a counter COUNTi (COUNT1, COUNT2, ..., COUNTi, ..., COUNT7 and COUNT8 in [Fig.l]) configured to receive the signal outi and to provide a digital output signal ci (cl, c2, ..., ci, ..., c7 and c8 in [Fig.l]) incremented by one unit for each pulse of the signal outi received.

[0076] [Fig.2] illustrates by timing diagrams an example of operation of the DET detector of [Fig.l]. More particularly, [Fig.2] represents the evolution of the outFE voltage as a function of time t, the thresholds Thi and the evolution of the outi signals as a function of time t in a case where the DET circuit comprises N=4 channels CHi. The thresholds Thi (Thi, Th2, Th3, Th4 in [Fig.2]) are increasing with the index i, the threshold Thi then being the lowest of the thresholds Thi. In this example, the inactive state of the outi signals is the low state, and the active state (pulse) of the outi signals is the high state. In the example of [Fig.2], the outFE voltage has two successive pulses PI and P2.

[0077] In [Fig.2], during the PI pulse, the outFE voltage increases from its resting value, i.e. from the ref value, up to a maximum value determined by the energy of the corresponding X photon received by the PD photodetector ([Fig.l]). During this increase, the outFE voltage successively crosses the thresholds Thi, Th2, Th3 and Th4, which causes the signals outi, out2, out3 and out4 to switch to the active state successively. Then, the outFE voltage decreases from the maximum value of the PL pulse. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Thi, which causes the signals out4, out3, out2 and outi to switch to the inactive state successively.

[0078] Similarly, during pulse P2, voltage outFE increases from its minimum value previously reached to a maximum value determined by the energy of the corresponding X photon received by photodetector PD. During this increase, voltage outFE successively crosses thresholds Thi, Th2, Th3 and Th4, which causes signals outi, out2, out3 and out4 to switch to the active state successively. Then, voltage outFE decreases from the maximum value of pulse PL. During this decrease, voltage outFE successively crosses thresholds Th4, Th3, Th2 and Thi, which causes signals out4, out3, out2 and outi to switch to the inactive state successively.

[0079] In [Fig.2], the two X photons corresponding to the two pulses PI and P2 are received one after the other with a duration between the reception of the first X-ray photon and that of the second X-ray photon which is sufficiently large so that the two corresponding pulses of the current Idet do not overlap or overlap little, from which it results that the voltage outFE falls below the threshold Thl between the two pulses PI and P2.

[0080] The signals outl to out4 are then such that, in this example, each of the corresponding signals cl to c4 is incremented twice.

[0081] It is then possible, from the signals c1 to c4, to determine that two X photons having an energy greater than a value E4 have been received by the photodetector PD of the detector DET, the energy value E4 determining, with the FRONT-END circuit, the value of the threshold Th4.

[0082] As an example, to reconstruct a histogram of the spectrum of X photons received by the photodetector PD of the detector DET: - for each channel CHi of index i strictly less than N, the value indicated by the signal ci+1 of the channel CHi+1 is subtracted from that indicated by the signal ci of the channel CHi, and the result of this subtraction indicates the number of X photons received with an energy between an energy value Ei and an energy value Ei+1, the value Ei determining with the FRONT-END circuit the value of the threshold Thi of the channel CHi, and the value Ei+1 determining with the FRONT-END circuit the value of the threshold Thi+1 of the channel CHi+1; and - for the CHi channel of index N, the value indicated by the signal ci indicates the number of X photons received with an energy greater than the energy value Ei.

[0083] In the DET detector described above, it is desirable for the COMPi comparators to switch their output signals as quickly as possible, or, in other words, for these COMPi comparators to be as fast as possible. Thus, at least during detection and counting phases, these COMPi comparators operate permanently in a high-consumption mode, i.e. in a higher-consumption mode than in a low-consumption mode where the COMPi comparators would be slower. For example, a detection and counting phase corresponds to a time window during which the detector is used to detect and count particles that it receives.

[0084] It would be desirable to reduce the consumption in the DET detector, without the COMPi converters being, at least when switching their output signals outi to the active state, slower than if they were operating in high consumption mode.

[0085] According to a first aspect, it is proposed here to take advantage of the particularities of the outFE voltage, or, in other words, of the fact that during a pulse of the outFE voltage, the outi signals successively switch to their active states starting from the index i equal to 1.

[0086] First aspect

[0087] To reduce the consumption of a particle counting detector of the type described in relation to figures 1 and 2, a NUM2 device similar to the NUM device is proposed here but in which: - for i ranging from 2 to N, with N strictly greater than 1, the COMPi comparators are configured to operate selectively according to a low consumption mode and a high consumption mode, and - a BOOST control circuit configured to control, for i ranging from 2 to N, each comparator COMPi in the low consumption mode or in the high consumption mode as a function of at least the signal outi of at least one of the channels CH1 to CHN, the BOOST circuit preferably being a purely combinational circuit without a storage function.

[0088] More particularly, the BOOST circuit controls the high and low consumption modes of the COMPi comparators for i ranging from 2 to N so that each of these COMPi comparators is in high consumption mode when the outFE voltage reaches and then exceeds the threshold Thi of the COMPi comparator and the consumption of the NUM1 device is lower than that of the NUM device in which the COMPi comparators are kept permanently, at least during detection and counting phases, in high consumption mode.

[0089] According to one embodiment, the BOOST circuit is configured, at each outFE pulse, to switch, for i ranging from 2 to N, each comparator COMPi from the low consumption mode to the high consumption mode in response to a switching to the active state of the signal outi of a channel CHi of index i lower than that of this comparator COMPi. Preferably, the BOOST circuit is configured, at each outFE pulse, to switch, for i ranging from 2 to N, each comparator COMPi into the high consumption mode in response to a switching to the active state of the signal outi-1 of the channel CHi-1, or, alternatively, in response to a switching to the active state of the signal outi of the channel CHI.

[0090] Thus, for i ranging from 2 to N, each comparator COMPi is in high consumption mode when the voltage outFE reaches and then exceeds the threshold Thi of this comparator COMPi.

[0091] According to one embodiment, the BOOST circuit is further configured, for each pulse and for each comparator COMPi that the BOOST circuit has switched to high consumption mode during the rising edge of the pulse, to switch this comparator COMPi to low consumption mode at the latest in response to a switching to the inactive state of the signal outi of the channel CHI, and, for example, at the earliest in response to a switching to the active state of the output signal outi of this comparator COMPi.

[0092] Thus, at each pulse, after having switched to high consumption mode on the rising edge of the pulse a comparator COMPi of index i included in the range from 2 to N, the BOOST circuit switches this comparator COMPi to low consumption mode at the latest at the end of the outFE pulse.

[0093] With regard to the comparator COMPI of channel CH1, according to one embodiment, this only operates in high consumption mode and is therefore not controlled by the BOOST circuit.

[0094] According to an alternative embodiment concerning the COMPI comparator, the latter is also configured to operate selectively according to a low consumption mode and a high consumption mode, and the BOOST circuit is then configured to control the COMPI comparator in low consumption mode if the out2 signal is in the active state, and in high consumption mode otherwise.

[0095] Examples of embodiments of such a circuit NUM1 will now be described in relation to FIGS. 3 to 8.

[0096] [Fig.3] schematically represents in the form of blocks an embodiment of a DET2 particle counting detector.

[0097] The DET2 detector includes many elements in common with the DET detector of [Fig.l] and only the differences between these two detectors DET and DET2 are highlighted here. In other words, unless otherwise indicated, everything that has been described for the DET detector of [Fig.l] applies to the DET2 detector of [Fig.3].

[0098] Thus, the detector DET2 comprises the photodetector PD providing the current Idet, and the FRONT-END circuit receiving the current Idet and providing the voltage outFE.

[0099] The DET2 detector comprises a device or circuit EVAL-NUM2 similar to the circuit EVAL-NUM of the DET detector of [Fig.l] in that it comprises the circuit EVAL and a circuit NUM2 similar to the circuit NUM. However, the circuit or device NUM2 differs from the circuit NUM in that: for i ranging from 2 to N, each comparator COMPi is configured to operate selectively in a high consumption mode and in a low consumption mode; and the NUM2 circuit also includes a BOOST circuit for controlling the comparators.

[0100] In the example of [Fig.3], the circuit NUM2 comprises N=4 digitization channels CHi, and the thresholds Thi increase with the index i.

[0101] As an example, each comparator COMPi which is configured to operate selectively according to the low consumption mode and according to the high consumption mode receives a binary signal bi (b2, ..., bi, ..., bN in [Fig.3]) of which a first binary state controls the comparator COMPi in low consumption mode, and of which a second binary state controls the comparator in high consumption mode. The bi signals are provided by the BOOST circuit from at least one of the outi signals.

[0102] In this embodiment, the BOOST circuit is more particularly configured to control, for i ranging from 2 to N, each comparator COMPi in high consumption mode, for example by providing the signal bi corresponding to its second binary state, if the signal outi-1 of the channel CHi-1 is in the active state, and in low consumption mode otherwise, for example by providing the signal bi corresponding to its first binary state.

[0103] In other words, in this embodiment, the BOOST circuit controls the high or low consumption mode of each of the comparators COMPi with i ranging from 2 to N, solely from the state of the signal outi-1 of the channel CHi-1.

[0104] In other words, for each comparator COMPi with i ranging from 2 to N, the comparator COMPi is in low consumption mode (bi in its first binary state) if the signal outi-1 is inactive, and is in high consumption mode (bi in its second binary state) if the signal outi-1 is active.

[0105] Thus, in this embodiment, the BOOST circuit receives the signals outi for i ranging from 1 to N.

[0106] In this example, the COMPI comparator operates only in high consumption mode and therefore does not receive any bl signal from the BOOST circuit.

[0107] However, in another example not shown, the comparator COMPI is configured to operate selectively in high consumption mode or in low consumption mode, and the BOOST circuit is configured to control the comparator COMPI in high consumption mode if the signal out2 is in the inactive state, and in low consumption mode otherwise. As an example, the BOOST circuit then provides a binary signal bl to the comparator COMPI, a first binary state of the signal bl controlling the comparator COMPI in low consumption mode, and a second binary state of the signal bl controlling the comparator COMPI in high consumption mode.

[0108] As an example, as illustrated in [Fig.3] for circuit COMP4 of circuit NUM2, each comparator COMPi of circuit NUM2 comprises an open-loop amplifier OTA, the amplifier receiving the voltage outFE on a first input, and the only corresponding Thi on a second input, and providing the corresponding signal outi. As an example, this signal outi can be directly provided at the output of comparator COMPi. As an alternative example, as illustrated in [Fig.3], the output signal outi of the OTA amplifier is shaped before being transmitted to the corresponding output of comparator COMPi, for example by a buffer circuit BUFF consisting for example of two inverters INV in series. As another alternative example, the output of the OTA amplifier can be coupled to the corresponding output of the COMPi comparator by a single inverter INV.

[0109] [Fig.4] illustrates by means of timing diagrams an example of operation of the detector DET2 of [Fig.3]. More specifically, [Fig.4] represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the outi signals as a function of time t, and the evolution of the bi signals as a function of time t in a case where the DET circuit comprises N=4 CHi channels. The thresholds Thi (Thl, Th2, Th3, Th4 in [Fig.4]) increase with the index i, the threshold Thl then being the lowest of the Thi thresholds. In this example, the inactive state of the outi signals is the low state, and the active state (pulse) of the outi signals is the high state. In this example, each signal bi controls the comparator COMPi in low consumption mode when it is in the low state, and in high consumption mode when it is in the high state. In the example of [Fig.4], the outFE voltage has a single PL pulse

[0110] At a time t0 before the start of the PI pulse, the voltage outFE is lower than the threshold Thl, the signals outi are therefore all in the inactive state (low state in [Fig.4]). Furthermore, as all the signals outi are in the inactive state, all the signals bi for i ranging from 2 to N are all in their first binary states (the low state in [Fig.4]). As a result, the comparators COMPi for i ranging from 2 to N are all controlled in low-power mode.

[0111] The PI pulse begins after the instant t0, and, at an instant t1 after the instant t0, the voltage outFE becomes greater than the threshold Thl. As a result, the signal outi switches to the active state (high state in [Fig.4]). In particular, in this example where the comparator COMPI still operates in high consumption mode, this switching of the signal outi is faster than if the comparator COMPI operated in low consumption mode.

[0112] Switching the signal outi to the active state causes the comparator COMP2 to switch to high consumption mode via the BOOST circuit ([Fig.3]), or, in other words, the signal b2 to switch to its second binary state (high state in [Fig.4]).

[0113] At a time t2 after time tl, the voltage outFE becomes higher than the threshold Th2. As a result, the signal out2 switches to the active state (high state in [Fig.4]). Since the comparator COMP2 has been switched to high consumption mode at time tl, this switching of the signal out2 is faster than if the comparator COMP2 operated in low consumption mode.

[0114] Switching the signal out2 to the active state causes the comparator COMP3 to switch to high consumption mode via the BOOST circuit ([Fig.3]), or, in other words, the signal b3 to switch to its second binary state (high state in [Fig.4]).

[0115] At a time t3 after time t2, the voltage outFE becomes greater than the threshold Th3 and the signal out3 switches to the active state (high state in [Fig.4]) while the comparator C0MP3 is controlled in high consumption mode since the instant t2. The switching of the signal out3 to the active state causes the switching, by the BOOST circuit ([Fig.3]), of the comparator COMP4 to high consumption mode, or, in other words, the switching of the signal b4 to its second binary state (high state in [Fig.4]).

[0116] At a time t4 after time t3, the voltage outFE becomes higher than the threshold Th4 and the signal out4 switches to the active state (high state in [Fig.4]) while the comparator COMP4 is controlled in high consumption mode since time t3.

[0117] At a time t5 after time t4, during the falling edge of the outFE pulse, the outFE voltage becomes lower than the threshold Th4 and the out4 signal switches to the inactive state (low state in [Fig.4]). During this switching of the out4 signal, the COMP4 comparator is still controlled in high consumption mode and this switching is then faster than if the COMP4 comparator had been controlled in low consumption mode.

[0118] At a time t6 after time t5, during the falling edge of the outFE pulse, the outFE voltage becomes lower than the threshold Th3 and the out3 signal switches to the inactive state (low state in [Fig.4]) while the COMP3 comparator is still controlled in high consumption mode. The switching of the out3 signal to the inactive state causes the switching, by the BOOST circuit ([Fig.3]), of the COMP4 comparator to low consumption mode, or, in other words, the switching of the b4 signal to its first binary state (low state in [Fig.4]).

[0119] At a time t7 after time t6, during the falling edge of the outFE pulse, the outFE voltage becomes lower than the threshold Th2 and the out2 signal switches to the inactive state (low state in [Fig.4]) while the COMP2 comparator is still controlled in high consumption mode. The switching of the out2 signal to the inactive state causes the switching, by the BOOST circuit ([Fig.3]), of the COMP3 comparator to low consumption mode, or, in other words, the switching of the b3 signal to its first binary state (low state in [Fig.4]).

[0120] At a time t8 after time t7, during the falling edge of the outFE pulse, the outFE voltage becomes lower than the threshold Thl and the outl signal switches to the inactive state (low state in [Fig.4]) while the comparator COMP1 is still controlled in high consumption mode. The switching of the outl signal to the inactive state causes the switching, by the BOOST circuit ([Fig.3]), of the COMP2 comparator to low consumption mode, or, in other words, the switching of the b2 signal to its first binary state (low state in [Fig.4]).

[0121] After time t8, the situation is the same as at time t0.

[0122] Although an example has been described here in the case where the comparator COMP1 is still in high consumption mode, the person skilled in the art is able to adapt the description of this example to the case where the comparator C0MP1 is controlled in high consumption mode when the signal out2 is in the inactive state, and in low consumption mode otherwise. Taking the example of [Fig.4], the comparator C0MP1 would then be in high consumption mode until time t2, in low consumption mode from time t2 to time t7, and in high consumption mode after time t7.

[0123] [Fig.5] schematically represents in block form another embodiment of a DET2 detector with particle counting. In [Fig.5], only the NUM2 circuit of the DET2 detector is shown, the rest of the DET2 detector in [Fig.5] being identical to that in [Fig.3]. Furthermore, the NUM2 circuit in [Fig.5] is similar to that in [Fig.3] and only the differences between these two circuits are highlighted here.

[0124] In this embodiment, the BOOST circuit is more particularly configured to control, for i ranging from 2 to N, each comparator COMPi in high consumption mode, for example by providing the signal bi corresponding to its second binary state, if the signal outl of the channel CH1 is in the active state, and in low consumption mode otherwise, for example by providing the signal bi corresponding to its first binary state.

[0125] In other words, in this embodiment, the BOOST circuit controls the high or low consumption mode of each of the comparators COMPi with i ranging from 2 to N, solely from the state of the signal outl of the channel CH1.

[0126] In other words, for each comparator COMPi with i ranging from 2 to N, the comparator COMPi is in low consumption mode (bi in its first binary state) if the signal outl is inactive, and is in high consumption mode (bi in its second binary state) if the signal outl is active.

[0127] Thus, in this embodiment, the BOOST circuit receives the signal outl, but does not receive the signals outi from the channels CHi of index i strictly greater than 2.

[0128] In this example, the COMPI comparator operates only in high-power mode and therefore does not receive any bl signal from the BOOST circuit. In addition, the BOOST circuit does not receive the out2 signal.

[0129] However, in another example not shown, the comparator COMPI is configured to operate selectively in high consumption mode or in low consumption mode, and the BOOST circuit is configured to control the comparator COMPI in high consumption mode if the signal out2 is in the inactive state, and in low consumption mode otherwise. As an example, the BOOST circuit then provides a binary signal bl to the comparator COMPI, a first binary state of the signal bl controlling the comparator COMPI in low consumption mode, and a second binary state of the signal bl controlling the comparator COMP1 in high consumption mode. In addition, the BOOST circuit then receives, for example, the signal out2.

[0130] [Fig.6] illustrates by timing diagrams an example of operation of the detector DET2 of [Fig.5]. More particularly, [Fig.6] represents the evolution of the voltage outFE as a function of time t, the thresholds Thi, the evolution of the signals outi as a function of time t, and the evolution of the signals bi as a function of time t in a case where the circuit DET comprises N=4 channels CHi. The thresholds Thi (Thl, Th2, Th3, Th4 in [Fig.6]) are increasing with the index i. In this example, the inactive state of the signals outi is the low state, and the active state (pulse) of the signals outi is the high state. In this example, each bi signal controls the COMPi comparator in low power mode when it is low, and in high power mode when it is high. In the example of [Fig.6], the outFE voltage has a single PL pulse.

[0131] At a time t0 before the start of the PI pulse, the voltage outFE is lower than the threshold Thl, the signals outi are therefore all in the inactive state (low state in [Fig.6]). Furthermore, as all the signals outi are in the inactive state, all the signals bi for i ranging from 2 to N are all in their first binary states (the low state in [Fig.6]). As a result, the comparators COMPi for i ranging from 2 to N are all controlled in low-power mode.

[0132] The PI pulse begins after the instant t0, and, at an instant t1 after the instant t0, the voltage outFE becomes greater than the threshold Thl. As a result, the signal outi switches to the active state (high state in [Fig.6]). In particular, in this example where the comparator COMPI is still operating in high consumption mode, this switching of the signal outi occurs while the comparator COMPI is in high consumption mode.

[0133] The switching of the signal outi to the active state causes the switching, by the BOOST circuit ([Fig.5]), of the comparators COMPi, for i going from 2 to N=4, in high consumption mode, or, in other words, the switching of the signals bi, for i going from 2 to N=4, to the second binary state (high state in [Fig.6]).

[0134] After time t1, the voltage outFE increases and successively exceeds the thresholds Th2, Th3 and Th4 before reaching a maximum value (peak of the PI pulse), from which it follows that the signals out2, out3 and out4 successively switch to the active state. These switchings of the signals out2, out3 and out4 occur while the corresponding comparators COMP2, COMP3 and COMP4 are controlled in high consumption mode.

[0135] Then the voltage outFE decreases and becomes successively lower than the thresholds Th4, Th3 and Th2, from which it follows that the signals out4, out3 and out2 successively switch to the inactive state. These switchings of the signals out4, out3 and out2 occur while the corresponding comparators C0MP4, C0MP3 and C0MP2 are controlled in high consumption mode.

[0136] The voltage outFE continues to decrease until it becomes lower than the threshold Thl at a time t2. As a result, the signal outl switches to the inactive state, while the comparator COMP1 is in high consumption mode. The switching of the signal outl to the inactive state causes the switching, by the BOOST circuit ([Fig.5]), of the comparators COMPi, for i ranging from 2 to N=4, to low consumption mode, or, in other words, the switching of the signals bi, for i ranging from 2 to N=4, to the first binary state (low state in [Fig.6]).

[0137] Although an example has been described here in the case where the comparator COMPI is always in high consumption mode, the person skilled in the art is able to adapt the description of this example to the case where the comparator COMPI is controlled in high consumption mode when the signal out2 is in the inactive state, and in low consumption mode otherwise. Using the example of [Fig. 6], the comparator COMPI would then be in high consumption mode until the signal out2 switches to the active state on the rising edge of the pulse PI, in low consumption mode as long as the signal out2 remains in the active state, and in high consumption mode after the signal out2 switches to the inactive state on the falling edge of the pulse PL.

[0138] [Fig.7] schematically represents in block form another embodiment of a DET2 detector with particle counting. In [Fig.7], only the NUM2 circuit of the DET2 detector is shown, the rest of the DET2 detector in [Fig.7] being identical to that in [Fig.3]. Furthermore, the NUM2 circuit in [Fig.7] is similar to that in [Fig.3] and only the differences between these two circuits are highlighted here.

[0139] In this embodiment, the BOOST circuit is more particularly configured to: - for i ranging from 2 to N-1 and N strictly greater than 2, control each comparator COMPi in high consumption mode if the signal outi-1 of channel CHi-1 is in the active state while the signal outi+1 of channel CHi+1 is in the inactive state, and in low consumption mode otherwise; and - control the comparator COMPN in high consumption mode if the outN-1 signal of the CHN-1 channel is active, and in low consumption mode otherwise.

[0140] In other words, in this embodiment, the BOOST circuit controls the high or low consumption mode of each of the comparators COMPi with i ranging from 2 to Nl, solely from the state of the signals outi-1 and outi+1 of the channels with indices immediately lower and immediately higher relative to the channel CHi of the comparator COMPi.

[0141] In other words, for each comparator COMPi with i ranging from 2 to Nl, the comparator COMPi is in high consumption mode (bi in its second binary state) if the out-1 signal is active while the out+1 signal is inactive, and is in low consumption mode (bi in its first binary state) otherwise.

[0142] Said again in another way, for each comparator COMPi with i ranging from 2 to Nl: - upon a rising edge of the outFE voltage, switching to the active state of the outi-1 signal of the channel with the immediately lower index causes the comparator COMPi to switch to high consumption mode, then switching to the active state of the outi+1 signal of the channel with the immediately higher index causes the comparator COMPi to switch to low consumption mode; and - during a falling edge of the outFE voltage, switching to the inactive state of the outi+1 signal of the channel with the immediately higher index causes the COMPi comparator to switch to high consumption mode, then switching to the inactive state of the outi-1 signal of the channel with the immediately lower index causes the COMPi comparator to switch to low consumption mode.

[0143] Thus, in this embodiment, the BOOST circuit receives the signals outi for i ranging from 1 to N. In addition, the BOOST circuit provides the signals bi, at least for i ranging from 2 to N.

[0144] In this example, the comparator COMPI is configured to operate selectively in high power mode or in low power mode, and the BOOST circuit is configured to control the comparator COMPI in high power mode if the signal out2 is in the inactive state, and in low power mode otherwise. For example, the BOOST circuit then provides the binary signal bl to the comparator COMPI.

[0145] In another example not shown, the COMPI comparator operates only in high consumption mode and therefore does not receive any bl signal from the BOOST circuit.

[0146] [Fig.8] illustrates by timing diagrams an example of operation of the detector DET2 of [Fig.7]. More particularly, [Fig.8] represents the evolution of the voltage outFE as a function of time t, the thresholds Thi, the evolution of the signals outi as a function of time t, and the evolution of the signals bi as a function of time t in a case where the circuit DET comprises N=4 channels CHi. The thresholds Thi (Thl, Th2, Th3, Th4 in [Fig.4]) are increasing with the index i, the threshold Thl then being the lowest of the thresholds Thi. In this example, the inactive state of the signals outi is the low state, and the active state (pulse) of the signals outi is the high state. In this example, each signal bi controls the comparator COMPi in low consumption mode when it is in the low state, and in high consumption mode when it is in the high state. In the example of [Fig.8], the outFE voltage has a single PL pulse

[0147] At a time t0 before the start of the PI pulse, the voltage outFE is lower than the threshold Thl, the signals outi are therefore all in the inactive state (low state in [Fig.8]). Furthermore, since all the signals outi are in the inactive state, all the signals bi for i ranging from 2 to N are all in their first binary states (the low state in [Fig.8]), and the signal bl is in its second binary state (the high state in [Fig.8]) because the signal out2 is in the inactive state. As a result, the comparators COMPi for i ranging from 2 to N are all controlled in low consumption mode, and the comparator COMPI is controlled in high consumption mode.

[0148] The PI pulse begins after the instant t0, and, at an instant t1 subsequent to the instant t0, the voltage outFE becomes greater than the threshold Thl. As a result, the signal outi switches to the active state while the comparator COMP1 operates in high consumption mode. Furthermore, the switching of the signal outi to the active state causes the BOOST circuit to switch the comparator COMP2 to high consumption mode, or, in other words, the switching of the signal b2 to its second binary state.

[0149] At a time t2 subsequent to time t1, the voltage outFE becomes greater than the threshold Th2 and the signal out2 switches to the active state while the comparator COMP2 is controlled in high consumption mode. The switching of the signal out2 to the active state causes the switching, by the BOOST circuit, of the comparator COMP3 in high consumption mode (switching of the signal b3 to its second binary state) and of the comparator COMP1 in low consumption mode (switching of the signal b1 to its first binary state).

[0150] At a time t3 after time t2, the voltage outFE becomes greater than the threshold Th3 and the signal out3 switches to the active state while the comparator COMP3 is controlled in high consumption mode. The switching of the signal out3 to the active state causes the switching, by the BOOST circuit, of the comparator COMP4 in high consumption mode (switching of the signal b4 to its second binary state) and of the comparator COMP2 in low consumption mode (switching of the signal b2 to its first binary state).

[0151] At a time t4 after time t3, the voltage outFE becomes greater than the threshold Th4 and the signal out4 switches to the active state while the comparator COMP4 is controlled in high consumption mode. The switching of the signal out4 to the active state causes the switching, by the BOOST circuit, of the comparator COMP3 to low consumption mode (switching of the signal b3 to its first binary state).

[0152] At a time t5 after time t4, during the falling edge of the outFE pulse, the outFE voltage becomes lower than the threshold Th4 and the out4 signal switches to the inactive state while the comparator COMP4 is still controlled in high consumption mode. In addition, the switching of the out4 signal to the inactive state causes the com mutation, by the BOOST circuit, of the C0MP3 comparator in high consumption mode (switching of the b3 signal to its second binary state)

[0153] At a time t6 after time t5, during the falling edge of the outFE pulse, the outFE voltage becomes lower than the threshold Th3 and the out3 signal switches to the inactive state while the COMP3 comparator is still controlled in high consumption mode. The switching of the out3 signal to the inactive state causes the BOOST circuit to switch the COMP4 comparator to low consumption mode (switching the b4 signal to its first binary state) and the COMP2 comparator to high consumption mode (switching the b2 signal to its second binary state).

[0154] At a time t7 after time t6, during the falling edge of the pulse outFE, the voltage outFE becomes lower than the threshold Th2 and the signal out2 switches to the inactive state while the comparator COMP2 is still controlled in high consumption mode. The switching of the signal out2 to the inactive state causes the switching, by the BOOST circuit, of the comparator COMP3 in low consumption mode (switching of the signal b3 to its first binary state) and of the comparator COMP1 in high consumption mode (switching of the signal bl to its second binary state).

[0155] At a time t8 after time t7, during the falling edge of the outFE pulse, the outFE voltage becomes lower than the threshold Thl and the outl signal switches to the inactive state while the comparator COMP1 is controlled in high consumption mode. The switching of the outl signal to the inactive state causes the BOOST circuit to switch the COMP2 comparator to low consumption mode (switching of the b2 signal to its first binary state).

[0156] After time t8, the situation is the same as at time t0.

[0157] Although an example has been described here in the case where the comparator COMP1 is controlled in high consumption mode when the signal out2 is in the inactive state, and in low consumption mode otherwise, the person skilled in the art is able to adapt the description of this example to the case where the comparator COMP1 is always in high consumption mode.

[0158] Several embodiments and variants have been described in relation to Figures 3 to 8. The person skilled in the art will be able to combine aspects of these embodiments and variants with each other. For example, the person skilled in the art will be able to provide, in an N-channel NUM2 device, that comparators of the higher index channels are selectively controlled in high or low consumption mode in the manner described in relation to Figures 3 and 4, that is to say, for each of these comparators, only from the output signal of the comparator of the immediately lower index, and that the other comparators other than that of the index channel are selectively controlled in high or low consumption mode in the manner described in relation to Figures 7 and 8. More generally, in a N-channel NUM2 circuit, the person skilled in the art is able to provide that, for i ranging from 2 to N, a portion of the COMPi comparators are selectively in high or low consumption mode according to one of the ways described in relation to figures 3 to 8, and that another portion of these COMPi comparators are controlled according to another of the ways described in relation to figures 3 to 8.

[0159] A first aspect of a NUM2 circuit has been described above, which makes it possible to reduce the consumption compared to the NUM circuit while maintaining the same switching speed of the COMPi comparators. Said in a complementary manner, the first aspect of the NUM2 circuit makes it possible to increase the switching speed of the COMPi comparators at the time of switching compared to the NUM circuit, while maintaining the same average consumption.

[0160] Referring again to the DET detector of [Fig.l], [Fig.9] illustrates by timing diagrams an example of operation of this DET detector. More particularly, [Fig.9] represents the evolution of the voltage outFE as a function of time t, the thresholds Thi and the evolution of the signals outi as a function of time t in a case where the DET circuit comprises N=4 channels CHi. The thresholds Thi (Thl, Th2, Th3, Th4 in [Fig.2]) are increasing with the index i. In this example, the inactive state of the signals outi is the low state, and the active state (pulse) of the signals outi is the high state.

[0161] In the example of [Fig.9], the outFE voltage has two successive pulses PI and P2. However, compared to [Fig.2], in the example of [Fig.9], the two X photons corresponding to the two pulses PI and P2 are received one after the other with a duration between the reception of the first X photon and that of the second X photon which is such that the two corresponding pulses of the current Idet overlap and, between the two pulses PI and P2, the outFE voltage does not fall below the threshold Thl, and more particularly the thresholds Thl and Th2 in this example.

[0162] More particularly, in [Fig.9], during the PI pulse, the voltage outFE increases from its resting value ref to a maximum value, and successively crosses the thresholds Thl, Th2, Th3 and Th4, which causes the signals outi, out2, out3 and out4 to switch to the active state successively.

[0163] Then, the outFE voltage decreases from the maximum value of the PI pulse to a minimum value reached at the start of the following P2 pulse and between the thresholds Th2 and Th3. During this decrease, the outFE voltage successively crosses the thresholds Th4 and Th3 but does not fall below the thresholds Th2 and Th1, from which it follows that the signals out4 and out3 successively switch to the inactive state while the signals out2 and outi remain in the active state.

[0164] Then, during pulse P2, the outFE voltage increases from the minimum value reached previously, up to a maximum value. During this increase, the outFE voltage successively crosses the thresholds Th4 and Th3, which causes the com mutation to the active state of the signals out3 and out4 successively, the other signals out2 and out3 being still in the active state. Then, the voltage outFE decreases from the maximum value of the pulse P2. During this decrease, the voltage outFE successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the signals out4, out3, out2 and outl to switch to the inactive state successively.

[0165] The signals outl to out4 obtained in the example of [Fig.9] do not allow the number and energy of the X photons received to be correctly evaluated.

[0166] As an example, taking the example of histogram reconstruction given in relation to [Fig.2], the corresponding signals cl to c4 would indicate that: 2 X-ray photons with energy greater than E4 were received; 0 X-ray photons with energy between E4 and E3 were received; -1 X-ray photon with an energy between E2 and E3 was received; and 0 X-ray photons with energy between E1 and E2 were received.

[0167] It would be desirable to have a particle counting detector that allows the number and energy of the particles it receives to be correctly evaluated when the probability of receiving two particles close together in time increases, so as to avoid the counting errors and / or inconsistencies illustrated in relation to [Fig.9].

[0168] A second aspect provides an EVAL-NUM1 circuit similar to the EVAL-NUM circuit, but which makes it possible to achieve this objective.

[0169] Second aspect

[0170] [Fig. 10] schematically represents in block form an embodiment of a particle counting detector DET1.

[0171] The DET1 detector includes many elements in common with the DET detector of [Fig.l] and only the differences between these two detectors DET and DET1 are highlighted here. In other words, unless otherwise indicated, everything that has been described for the DET detector of [Fig.l] applies to the DET1 detector of [Fig.10].

[0172] Thus, the detector DET1 comprises the photodetector PD providing the current Idet, and the FRONT-END circuit receiving the current Idet and providing the voltage outFE.

[0173] The detector DET1 comprises a device or circuit EVAL-NUM1 similar to the circuit EVAL-NUM of the detector DET of [Fig.l] in that it comprises the circuit NUM and the circuit EVAL. However, the circuit EVAL-NUM1 differs from the circuit NUM-EVAL in that it further comprises a device or circuit PULSE-RESET.

[0174] The EVAL-NUM circuit 1 is, like the EVAL-NUM circuit, configured to receive the outFE voltage and to evaluate the number and energy of the X photons received by the PD photodetector from the outFE voltage, or at least provide signals allowing the evaluation of the number and energy of the received X photons.

[0175] In the EVAL-NUM1 device, as in [Fig.l], the NUM circuit is a circuit of analog-digital conversion configured to evaluate the amplitude of each voltage pulse of the received outFE voltage, the NUM circuit providing several digital signals outi, for example several binary signals, representative, for each pulse of the outFE voltage, of the amplitude of this pulse. In the example of [Fig. 10], the NUM circuit comprises N=4 digitization channels CHi, and the thresholds Thi are increasing with the index i.

[0176] Compared to the EVAL-NUM device, in the EVAL-NUM1 device, the outi signals are not directly supplied to the EVAL circuit. Indeed, in the EVAL-NUM 1 circuit, the PULSE-RESET circuit, which is a digital pulse reset circuit, is configured to receive the outi signals and to supply corresponding outci signals. It is these outci signals which are supplied to the EVAL circuit.

[0177] More particularly, for each channel CHi, the PULSE-RESET circuit is configured to receive the signal outi from this channel, and to generate the corresponding signal outci so that the signal outci is in the active state when the signal outi is in the active state and is in the inactive state when the signal outi is in the inactive state.

[0178] Furthermore, the PULSE-RESET circuit is configured to provide a signal rst for resetting digital pulses. More particularly, the signal rst is configured to force, each time the outci signal switches to the active state, the switching to the inactive state of the outci signals, at the end of a time period tmpl starting when the outci signal switches to the active state. Thus, although the signal rst is illustrated in [Fig. 10] as an output of the PULSE-RESET circuit, in practice, in the embodiment of [Fig. 10] where the signal rst resets the digital pulses of the outci signals, this signal rst is an internal signal of the PULSE-RESET circuit.

[0179] According to one embodiment, the value of the period tmpl is fixed, or, in other words, constant. For example, the duration tmpl is determined empirically, by tests or simulations, and depends on (or is determined by) the FRONT-END circuit and the average energy of the detected particles.

[0180] Preferably, the PULSE-RESET circuit is configured so that the signal rst maintains the inactive state of the outci signals for a constant duration tmp2 each time the signal rst switches these outci signals to the inactive state at the end of a corresponding period tmpl. For example, the duration tmp2 is constant. For example, the duration tmp2 is determined empirically, by tests or simulations. For example, the duration tmp2 is chosen to be as short as possible but large enough to be taken into account by the EVAL circuit, for example by the counters COUNTi of the EVAL circuit (see [Fig.l]). For example, the duration tmp2 is at least ten times shorter than the average width of the voltage pulses of the outFE voltage, the width of an outFE voltage pulse being for example the duration separating the instant when the pulse exceeds the lowest threshold Thi and the instant when the pulse falls below this threshold Thi. For example, for a given FRONT-END circuit and for particles corresponding to X photons, the average width of the outFE pulses is approximately 20 ns, and, for example, the duration tmp2 is then approximately 2 ns.

[0181] The outci signals (outcl, ..., outci, ..., outc4 in [Fig. 10]) are supplied to the EVAL circuit of the detector DET1, instead of the outi signals which were supplied to the EVAL circuit of the detector DET of [Fig. 1]. Thus, the EVAL circuit here is configured to count, for each channel CHi, the number of pulses of the outci signal, that is to say the number of switchings to the active state of this outci signal. For example, the EVAL circuit provides, for each channel CHi, a digital output signal ci (cl, ..., ci, ..., c4 in [Fig. 10]) incremented by one unit for each pulse of the outci signal received.

[0182] As an example, as illustrated in [Fig. 10] for the circuit COMP4 of the circuit NUM, each comparator COMPi of the circuit NUM comprises an open-loop OTA amplifier, the amplifier receiving the voltage outFE on a first input, and the only corresponding Thi on a second input, and providing the corresponding signal outi. As an example, this signal outi can be directly provided at the output of the circuit NUM. As an alternative example, as illustrated in [Fig. 10], the output signal outi of the amplifier is shaped before being transmitted to the corresponding output of the circuit NUM, for example by a buffer circuit BUFF consisting for example of two inverters INV in series. As another alternative example, the output of the OTA amplifier can be coupled to the corresponding output of the circuit NUM by a single inverter INV.

[0183] [Fig. 11] illustrates by means of timing diagrams an example of operation of the detector DET1 of [Fig. 10] according to an embodiment in which the signal rst is a signal for resetting the signals (or pulses) outci. More particularly, [Fig.5] illustrates: the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the corresponding signals outi as a function of time t, and the evolution of the corresponding signals outci as a function of time t.

[0184] In this example, N is equal to 4, the thresholds Thi have the same values ​​as in [Fig.2] and 3, and the outFE voltage has the same shape as the outFE voltage of [Fig.2] and includes in particular the two successive pulses PI and P2. In this example, it is the high state of the signal rst which forces the outci signals to the inactive state, the other state of the signal rst having no influence on the outci signals.

[0185] During the PI pulse, the outFE voltage increases from its resting value ref, up to a maximum value. During this increase, the outFE voltage successively crosses the thresholds Thi, Th2, Th3 and Th4, which causes the signals outi, out2, out3 and out4 to switch to the active state successively. The PULSE-RESET circuit ( [Fig.10]) then switches the corresponding signals outcl, outc2, outc3 and outc4 to the active state at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals outl, out2, out3 and out4 respectively. Furthermore, the switching of the signal outcl to the active state marks the beginning of a period tmpl.

[0186] Then, while the period tmpl has not yet expired in this example, the voltage outFE decreases from the maximum value of the pulse PI, and successively crosses the thresholds Th4, Th3, Th2 and Thl, causing the signals out4, out3, out2 and outl to switch to the inactive state successively. The PULSE-RESET circuit ([Fig. 10]) then successively switches the corresponding signals outc4, outc3, outc2 and outcl to the inactive state, at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2 and outl respectively.

[0187] Between the two pulses PI and P2, while the voltage outFE is below the threshold Thl, the duration tmpl expires, which causes the signal rst to switch to a state (the high state in this example) suitable for forcing the signals outci to the inactive state. Since the signals outci are already in the inactive state, the signal rst has no influence here on the operation of the detector DET1. The signal rst is then switched to its other state (the low state in this example), for example at the end of the duration tmp2.

[0188] Then the pulse P2 starts and the voltage outFE increases from a value lower than the threshold Thl up to a maximum value. During this increase, the voltage outFE successively crosses the thresholds Thl, Th2, Th3 and Th4, which causes the switching to the active state of the signals outl, out2, out3 and out4 successively, and therefore the switching to the active state of the signals outl, out2, out3 and out4 successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals outl, out2, out3 and out4 respectively. Moreover, although this is not illustrated in [Fig.5], the switching of the signal outcl to the active state during the second pulse P2 marks the beginning of a new period tmpl.

[0189] Then, the outFE voltage decreases from the maximum value of the pulse P2. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the switching to the inactive state of the signals out4, out3, out2 and outl successively, and the switching to the inactive state of the signals outc4, outc3, outc2 and outcl successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2 and outl respectively.

[0190] The example in [Fig.5] shows that, when the time separating the reception of two successive X photons is long enough for the outFE voltage to fall below the threshold Thl between the pulses PI and P2, the PULSE-RESET circuit, and in particular the signal rst that it generates, does not modify the correct operation of the detector. DET1 with respect to the DET detector, the outci signals then being identical to the outi signals.

[0191] [Fig. 12] illustrates by means of timing diagrams an example of operation of the detector DET1 of [Fig. 10] according to an embodiment in which the signal rst is a signal for resetting the signals (or pulses) outci. More particularly, [Fig. 12] illustrates: the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the corresponding signals outi as a function of time t, and the evolution of the corresponding signals outci as a function of time t.

[0192] In this example, N is equal to 4, the thresholds Thi have the same values ​​as in [Fig.2] and 3, and the outFE voltage has the same shape as the outFE voltage of [Fig.3] and includes in particular the two successive pulses PI and P2. In this example, it is the high state of the signal rst which forces the outci signals to the inactive state, the other state of the signal rst having no influence on the outci signals.

[0193] During the PI pulse, the outFE voltage increases from its resting value ref, up to a maximum value. During this increase, the outFE voltage successively crosses the thresholds Thi, Th2, Th3 and Th4, which causes the signals outi, out2, out3 and out4 to switch to the active state successively. The PULSE-RESET circuit ( [Fig.10]) then switches the corresponding signals outci, outc2, outc3 and outc4 to the active state at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals outi, out2, out3 and out4 respectively. Furthermore, the switching of the signal outci to the active state marks the beginning of a period tmpl.

[0194] Then, while the period tmpl has not yet expired in this example, the voltage outFE decreases from the maximum value of the pulse PI, and successively crosses the thresholds Th4 and Th3, but does not fall below the thresholds Th2 and Thi. As a result, the signals out4 and out3 successively switch to the inactive state, but the signals out2 and outi remain in the active state. In addition, the corresponding signals outc4 and outc3 successively switch to the inactive state at the same times (neglecting the propagation delays) as the respective signals out4 and out3, the signals outc2 and outci remaining, like the signals out2 and outi, in the active state.

[0195] Between the two pulses PI and P2, while the voltage outFE is at a value between the thresholds Th3 and Th2, the duration tmpl expires, which causes the signal rst to switch to a state (the high state in this example) suitable for forcing the signals outci to the inactive state. As the signals outc4 and outc3 are already in the inactive state, the signal rst has no influence on these signals here. On the other hand, the signal rst forces the switching to the inactive state of the signals outc2 and outci although the signals out2 and outi are in the active state. The signal rst is then switched to its other state (the state low in this example), for example at the end of the tmp2 duration. Once the rst signal has been switched back to its low state, since the out2 and outl signals are still in the active state, the PULSE-RESET circuit switches the corresponding outc2 and outcl signals to the active state. Although not illustrated in [Fig. 12], this switching of the outcl signal to the active state at the end of the high state of the rst signal marks the beginning of a new tmpl period.

[0196] Then the pulse P2 begins and the voltage outFE increases to a maximum value. During this increase, the voltage outFE successively crosses the thresholds Th3 and Th4, which causes the signals out3 and out4 to switch to the active state successively, and therefore the signals outc3 and out4 to switch to the active state successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out3 and out4 respectively.

[0197] Then, the outFE voltage decreases from the maximum value of the pulse P2. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the switching to the inactive state of the signals out4, out3, out2 and outl successively, and the switching to the inactive state of the signals outc4, outc3, outc2 and outcl successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2 and outl respectively.

[0198] The example in [Fig. 12] shows that, when the time separating the reception of two successive X photons is too short for the voltage outFE to fall below the threshold Thl between the pulses PI and P2, the PULSE-RESET circuit, and in particular the signal rst that it generates, makes it possible to force the reinitialization of the signals outci which have not returned to the inactive state between the two pulses PI and P2.

[0199] Thus, since it is the signals outci which are supplied to the circuit EVAL, each of the signals ci is indeed incremented twice in this example. It is then possible, from the signals cl to c4, to determine that two X photons having an energy greater than a value E4 were received by the photodetector PD of the detector DET1, the energy value E4 determining, with the FRONT-END circuit, the value of the threshold Th4, whereas this was not the case with the signals ci of the detector DET.

[0200] In particular, in very high flux applications, when the photodetector PD ( [Fig. 10]) receives so many X photons that at least some of the signals outi remain permanently in the active state, where the detector DET of [Fig.l] would be paralyzed and would not generate any incrementation of the corresponding signals ci, the detector DET1 is not paralyzed and will continue to increment the corresponding signals ci thanks to the reinitializations of the signals outci by the signal rst. In this case, the detector DET1 will have a counting frequency which does not decrease at very high flux but which will reach a maximum value equal to l / (tmpl + tmp2).

[0201] [Fig. 13] represents schematically and in the form of blocks, an example of detailed embodiment of the PULSE-RESET circuit of the DET1 detector of [Fig.10].

[0202] In this embodiment, the rst signal is configured to reset the outci signals.

[0203] In this example, N is equal to 4.

[0204] The PULSE-RESET circuit comprises, for each channel CHi, a circuit GENi (GEN1, ..., GENi, ..., GEN4 in [Fig.7]) configured to receive the signal outi from the channel CHi, receive the signal rst and generate the corresponding signal outci.

[0205] According to one embodiment, as illustrated in [Fig. 13], each GENi circuit comprises an RS flip-flop 700 and an OR combinational logic gate. The OR logic gate is configured to receive the outi signal and the rst signal, and to provide a binary output in the active state, for example the high state, if the outi signal is in the inactive state or the rst signal is in the active state, and in the inactive state, for example the low state, otherwise. The RS flip-flop comprises, in the usual manner, an initialization input S, a reset input R and an output Q. The input S is controlled, for example receives, the corresponding outi signal, the input R being controlled, for example receiving, the output signal of the OR gate. The output Q determines, for example provides, the corresponding outci signal. More particularly, in each GENi circuit, the flip-flop 700 is configured to: - switching the outci signal to the active state when the outi signal (input S) switches to the active state while its input R receives a signal in the inactive state; and - switch the outci signal to the inactive state when its R input receives a signal in the active state.

[0206] The person skilled in the art will be able to foresee other implementations of the GENi circuits.

[0207] For example, the person skilled in the art will be able to implement each GENi circuit using a combinational circuit taking as input the signal outi and the signal rst, and providing the corresponding signal outci. For example, in the case where the signals outi, rst and outci are active in the high state, and inactive in the low state, the GENi circuit can be implemented with an AND gate having an input receiving the signal outi, another input receiving a binary signal in the high state when the signal rst is in the low state, and in the low state when the signal rst is in the high state, and an output providing the corresponding signal outci.

[0208] As another example, the person skilled in the art will be able to implement each GENi circuit using a multiplexer taking the outi signal and a signal at a level corresponding to the inactive state of the outi and outci signals on two respective data inputs, and the rst signal on a control input, and providing the corresponding outci signal as output. For example, when the rst signal is active, the mul The triplexer couples its output to the data input receiving the outi signal when the rst signal is inactive, and couples its output to the other data input when the rst signal is active.

[0209] Furthermore, in the embodiment of [Fig. 13], the PULSE-RESET circuit comprises a GEN-RST circuit configured to provide the rst signal, from at least the outcl signal. The GEN-RST circuit is therefore configured to receive the outcl signal and to provide the rst signal from the outcl signal.

[0210] According to one embodiment, the circuit GEN-RST comprises a first monostable circuit M0N01 and a second monostable circuit M0N02. The circuit M0N01 is configured to receive the signal outcl from the channel CH1 with the lowest threshold Thl, and to provide a pulse P3 each time the signal outcl switches to the active state. In other words, each switching of the signal outcl to the active state causes the circuit M0N01 to provide a pulse P3. In other words, each switching of the signal outcl to the active state triggers the monostable circuit M0N01. The circuit M0N02 is configured to receive the pulses P3, and to provide, for each pulse P3 received, for example at the end of each pulse P3 received, a pulse P4. The rst signal is determined by the P4 pulses, for example is identical to the output signal of the M0N02 circuit having the P4 pulses.For example, the rst signal is configured to force the outci signals to the inactive state on each P4 pulse, and for the duration of that P4 pulse.

[0211] For example, the duration of each pulse P3 is equal to the duration tmpl, and the duration of each pulse P4 is equal to the duration tmp2.

[0212] According to one embodiment, the monostable circuits M0N01 and M0N02 each comprise one or more resistive components and one or more capacitive components whose resistance values ​​and capacitance values ​​determine the duration of the pulses P3 and P4. Preferably, these resistance values ​​and / or these capacitance values ​​are adjustable so that the durations tmpl and tmp2 can be adapted according to the application in which the device EVAL-NUM1 is implemented, for example according to the characteristics of the FRONT-END circuit and / or the particles detected.

[0213] In the embodiments described above in relation to Figures 11, 12, 13 and 14, the signal rst is configured to force the outci signals to the inactive state upon expiration of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi.

[0214] In alternative embodiments, in addition to forcing the outci signals to the inactive state upon expiration of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi, the signal rst is further configured to force the reinitialization of other circuits, in particular the comparators COMPi. For example, according to an alternative embodiment, the signal rst is configured to force the signals outci and the signals outi to the inactive state at the end of a time period tmpl starting with each switching to the active state of the signal outci of the channel CHi with the lowest threshold. In such a variant, each comparator COMPi receives the signal rst, for example on a reset input of the comparator COMPi. For example, each time the signal rst forces the signals outci to the inactive state, this signal also forces the signals outi to the inactive state. The person skilled in the art will be able to adapt the description given above in relation to figures 11, 12, 13 and 14 to such a variant.

[0215] In other embodiment variants, rather than forcing the outci signals to the inactive state at the end of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi, the signal rst is configured to force the reinitialization of other circuits, in particular the comparators COMPi, at the end of the time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi. For example, according to an embodiment variant, the signal rst is configured to force only the outi signals to the inactive state at the end of a time period tmpl starting with each switching to the active state of the outci signal of the lowest threshold channel CHi. In such an embodiment, each comparator COMPi receives the signal rst, for example on a reset input of the comparator COMPi.For example, in such a variant, each GENi circuit is configured to copy the outi signal that it receives onto the outci signal that it provides. For example, each GENi circuit then comprises a simple connection or a buffer circuit or a delay circuit or an inverter between its input receiving the outi signal and its output providing the corresponding outci signal. The person skilled in the art will be able to adapt the description given above in relation to figures 11, 12, 13 and 14 to such a variant.

[0216] In the embodiments described above in relation to figures 11, 12, 13 and 14, each time period tmpl has the same constant duration.

[0217] In alternative embodiments, a time period tmpl is triggered, by the PULSE-RESET circuit, each time the signal outci of the channel CHi with the lowest threshold Thi switches to the active state, but this period tmpl ends: if the signal outi or outci of a given CHi channel, preferably the CHN channel, having a threshold Thi greater than the lowest threshold Thl switches to the inactive state before the end of a minimum time period tmplmax of fixed duration which begins at the same time as the period tmpl, and at the end of the time period tmplmax otherwise.

[0218] The implementation of such variant embodiments is within the reach of those skilled in the art from the present description.

[0219] Furthermore, alternative embodiments as described above where the duration tmpl is not fixed are combinable with the embodiment variants in which the rst signal is configured to force the reset of only the outi signals, and with the embodiment variants in which the rst signal is configured to force the reset of the outi signals and the outci signals. The implementation of such combinations is within the scope of the person skilled in the art from the present description.

[0220] In the embodiments and variants described above, the PULSE-RESET circuit is configured to switch, for each channel CHi, the signal outci to the active state when the signal outi switches to the active state, to switch the signal outci to the inactive state when the signal outi switches to the inactive state and to generate the signal rst configured to force the signals outci and / or the signals outi to the inactive state. In the case where the signal rst is configured to force at least the signals outci to the inactive state, in variant embodiments, the PULSE-RESET circuit is configured, for each channel CHi, to switch the signal outci to the active state when the signal outi switches to the active state, and to maintain this signal outci in the active state as long as the signal rst does not force the switching of this signal outci to the inactive state. Such a variant is compatible with a fixed tmpl duration and with a variable tmpl duration but limited by a tmpmaxl duration.As an example of implementing such a variant, taking the example of the PUSLE-RESET circuit in [Fig.7], this amounts, for each GENi circuit, to removing the OR gates so that the R input of the flip-flop is controlled, for example receives, the rst signal. In such an example, the RS flip-flop is then configured to: . - switch the outci signal (output Q) to the active state when the outi signal (input S) switches to the active state while the rst signal is in the inactive state (input R); - switch the outci signal (output Q) to the inactive state when the rst signal (input R) switches to the active state, whether the outi signal is in the active state or not; and - keep the outci signal (output Q) in the inactive state as long as the rst signal (input R) and the outi signal (input S) are simultaneously in the inactive state.

[0221] The embodiments and variants of the second aspect described above may be combined with the embodiments and variants of the first aspect described previously. In this case, the NUM1 circuit is associated with a PUSLE-RESET circuit, or, in other words, the NUM circuit of the EVAL-NUM1 circuit is replaced by the NUM1 circuit of the first aspect.

[0222] A third aspect provides for taking advantage of the embodiments and variants of the second aspect described above, in cases where the PULSE-RESET circuit forces the resetting of the outi signals, when these embodiments and variants are combined with the first aspect. In other words, a third aspect provides a NUM-EVAL3 circuit comprising not only the NUM1 circuit (first aspect), and in particular its BOOST circuit, but also the PUSLE-RESET circuit (second aspect) configured to force outi signals to the inactive state upon expiration of the tmpl period starting with each switch to the active state of the outcl signal.

[0223] Third aspect

[0224] [Fig. 14] schematically represents in block form an embodiment of a DET3 particle counting detector.

[0225] The DET3 detector includes many elements in common with the DET1 detector of [Fig. 10] and only the differences between these two detectors DET3 and DET1 are highlighted here. In other words, unless otherwise indicated, everything that has been described for the DET1 detector of [Fig. 10] applies to the DET3 detector of [Fig.14],

[0226] The DET3 detector differs from the DET1 detector in that the EVAL-NUM1 circuit is replaced by an EVAL-NUM3 circuit. The EVAL-NUM3 circuit is similar to the EVAL-NUM1 circuit and differs from the latter only in that the NUM circuit is replaced by the NUM2 circuit.

[0227] Furthermore, in this third aspect, the PULSE-RESET circuit is configured to force the reset of the outi signals, and, optionally, that of the outci signals, at the end of the period tmpl starting with each switching to the active state of the outcl signal. Thus, the circuit NUM2 receives the signal rst. For example, each circuit COMPi receives the signal rst and is configured to force the corresponding outi signal to the inactive state when it receives the active state of the signal rst.

[0228] According to one embodiment, in a manner similar to what has been described in relation to figures 5 and 6, the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high consumption mode if the signal outi is in the active state, and in low consumption mode otherwise.

[0229] According to another embodiment, in a manner similar to what has been described in relation to figures 3 and 4, the BOOST circuit is configured to control, for i ranging from 2 to N, each comparator COMPi in high consumption mode if the signal outi-1 of the channel CHi-1 is in the active state, and in low consumption mode otherwise.

[0230] According to yet another embodiment, similarly to what has been described in relation to Figures 7 and 8, the BOOST circuit is configured to: - for i ranging from 2 to N-1 and N strictly greater than 2, control each comparator COMPi in high consumption mode if the signal outi-1 of channel CHi-1 is in the active state while the signal outi+1 of channel CHi+1 is in the inactive state, and in low consumption mode otherwise; and - control the comparator COMPN in high consumption mode if the outN-1 signal of the CHN-1 channel is active, and in low consumption mode otherwise.

[0231] According to another embodiment, the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in the high mode. consumption if the outi signal of the CHi channel is in the inactive state while the outl signal of the CHI channel is in the active state, and in the low consumption mode otherwise. In this case, as shown in [Fig. 14], the BOOST circuit provides the signals b2 to BN only from the outl signal.

[0232] According to another embodiment, the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in the high consumption mode if the signal outi of the channel CHi is in the inactive state while the signal outi-1 of the channel CHi-1 is in the active state, and in the low consumption mode otherwise.

[0233] More generally, the person skilled in the art will be able to implement the other embodiments and variants of the BOOST circuit mentioned at the end of the description of the first aspect, in the NUM2 circuit of the EVAL-NUM3 circuit.

[0234] Furthermore, in the circuit NUM2 of the circuit EVAL-NUM3, according to embodiments, the comparator COMPI is configured to operate permanently in high consumption mode, the BOOST circuit then not providing a signal bl, and, according to other embodiments, the comparator COMPI is configured to operate selectively in high consumption mode or in low consumption mode, and the BOOST circuit is then configured to control the comparator COMPI in high consumption mode, for example by means of the signal bl in its second binary state, if the signal out2 is in the inactive state, and in low consumption mode, for example by means of the signal bl in its first binary state, otherwise.

[0235] [Fig. 15] illustrates by timing diagrams an example of operation of the DET3 detector of [Fig.14]. More particularly, [Fig.15] represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, and the evolution of the signals outi, rst, outcl and bi as a function of time t in a case where the DET3 circuit comprises N=4 CHi channels. The thresholds Thi (Thl, Th2, Th3, Th4 in [Fig.15]) are increasing with the index i. In this example, the inactive state of the signals outi and of the signal outc 1 is the low state, and the active state (pulse) of the signals outi and of the signal outcl is the high state. In this example, each signal bi (b2, b3 and b4 in [Fig. 15]) controls the comparator COMPi in low power mode when it is in the low state, and in high power mode when it is in the high state. In the example in [Fig. 15], the outFE voltage has a single PL pulse. In the example in [Fig. 15], the comparator COMPI is permanently in high power mode.

[0236] In the example of [Fig. 15], the timing diagrams take into account the delay introduced by each comparator COMPi between the moment when the voltage outFE crosses the threshold Thi associated with this comparator and the corresponding switching of the output signal outi of the comparator.

[0237] In the embodiment illustrated by [Fig.15], the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high mode consumption if the signal outl is in the active state, and in low consumption mode otherwise.

[0238] At a time t0 before the start of the PI pulse, the voltage outFE is lower than the threshold Thl, the signals outi are therefore all in the inactive state (low state in [Fig. 15]). Furthermore, as all the signals outi are in the inactive state, all the signals bi for i ranging from 2 to N are all in their first binary states (the low state in [Fig. 15]). As a result, the comparators COMPi for i ranging from 2 to N are all controlled in low consumption mode. The signal outi being in the inactive state, the signal outcl is also in the inactive state.

[0239] The PI pulse begins after time t0, and, at a time tl after time t0, the voltage outFE becomes greater than the threshold Thl. As a result, at a time tl' after time tl, the signal outi switches to the active state (high state in [Fig. 15]). In this example where the comparator COMPI is still operating in high consumption mode, this switching of the signal outi occurs while the comparator COMPI is in high consumption mode.

[0240] The switching of the signal outi to the active state causes the switching, by the BOOST circuit, of the comparators COMPi, for i ranging from 2 to N=4, in high consumption mode, or, in other words, the switching of the signals bi, for i ranging from 2 to N=4, to the second binary state (high state in [Fig. 15]).

[0241] Switching the signal outi to the active state also causes the signal outcl to switch to the active state (high state in [Fig. 15]) via the PULSE-RESET circuit. This results in the start of a corresponding duration tmpl.

[0242] After time tl, at a time t2 subsequent to time tl' in this example, the voltage outFE increases and exceeds the threshold Th2, from which it follows that, at a time t2' subsequent to time t2, the signal out2 switches to the active state while the corresponding comparator COMP2 is controlled in high consumption mode.

[0243] After time t2, at a time t3 between times t2 and t2' in this example, the voltage outFE increases and exceeds the threshold Th3, from which it follows that, at a time t3' after times t3 and t2', the signal out3 switches to the active state while the corresponding comparator COMP3 is controlled in high consumption mode.

[0244] After time t3, at a time t4 between times t2' and t3' in this example, the voltage outFE increases and exceeds the threshold Th4, from which it follows that, at a time t4' after times t4 and t3', the signal out4 switches to the active state while the corresponding comparator COMP4 is controlled in high consumption mode.

[0245] At successive times t5, t6, t7 and t8 subsequent to time t4, and subsequent to time t4' in this example, the voltage outFE successively becomes lower than the thresholds Th4, Th3, Th2 and Thl.

[0246] Dotted lines illustrate in [Fig. 15] the corresponding appearance that the corresponding signals out4, out3, out2 and outi should have, and, in particular, that the signals out4, out3, out2 and outl, should successively switch to the inactive state at times later than time t8.

[0247] However, substantially at time t8 in this example, the duration tmpl expires and the signal rst switches to the active state. This causes the outi outputs of the COMPi comparators to be reset, or, in other words, this forces the outi signals to switch to the inactive state.

[0248] Switching the signal outi to the inactive state causes the BOOST circuit to switch the comparators COMPi, for i ranging from 2 to N=4, to low consumption mode, or, in other words, the switching of the signals bi, for i ranging from 2 to N=4, to the first binary state (low state in [Fig. 15]).

[0249] Switching the outi signal to the inactive state also causes the outcl signal to switch to the inactive state (low state in [Fig. 15]).

[0250] The PUSLE-RESET circuit therefore makes it possible to assist the return of the outi signals to the inactive state, and, more particularly, to switch them to the inactive state in advance compared to the case where these signals would be switched to the inactive state by the COMPi comparators solely on the basis of the comparison made, by each COMPi comparator, between the outFE voltage and the associated Thi threshold.

[0251] As a result, the COMPi comparators for i ranging from 2 to N switch back to low-power mode more quickly than in the example in [Fig.6].

[0252] Although an example has been described here in the case where the comparator COMPI is always in high consumption mode, the person skilled in the art is able to adapt the description of this example to the case where the comparator COMPI is controlled in high consumption mode when the signal out2 is in the inactive state, and in low consumption mode otherwise.

[0253] [Fig. 16] illustrates by timing diagrams another example of operation of the DET3 detector of [Fig.14]. More particularly, [Fig.16] represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, and the evolution of the signals outi, rst, outcl and bi as a function of time t in a case where the DET3 circuit comprises N=4 CHi channels. The thresholds Thi (Thi, Th2, Th3, Th4 in [Fig.15]) are increasing with the index i. In this example, the inactive state of the signals outi and of the signal outc 1 is the low state, and the active state (pulse) of the signals outi and of the signal outcl is the high state. In this example, each signal bi (bl, b2, b3 and b4 in [Fig. 16]) controls the comparator COMPi in low power mode when it is in the low state, and in high power mode when it is in the high state. In the example of [Fig. 16], the outFE voltage has a single PL pulse. In the example of [Fig.16], the COMPI comparator is controlled in high consumption mode if the out2 signal is inactive, and in low consumption mode otherwise.

[0254] In the example of [Fig. 16], the timing diagrams take into account the delay introduced by each comparator COMPi between the moment when the voltage outFE crosses the threshold Thi associated with this comparator and the corresponding switching of the output signal outi of the comparator.

[0255] In the embodiment illustrated by [Fig.16], the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high consumption mode if the signal outi is in the inactive state while the signal outl is in the active state, and in low consumption mode otherwise.

[0256] In this example, the comparator COMPI is controlled in high consumption mode when the signal out2 is in the inactive state, and in low consumption mode otherwise.

[0257] At a time t0 before the start of the PI pulse, the voltage outFE is lower than the threshold Thl, the signals outi are therefore all in the inactive state (low state in [Fig. 16]). Furthermore, since all the signals outi are in the inactive state, all the signals bi for i ranging from 2 to N are all in their first binary states (the low state in [Fig. 16]), and the signal bl is in the active state (the high state in [Fig. 16]). As a result, the comparators COMPi for i ranging from 2 to N are all controlled in low-power mode, and the comparator COMPI is controlled in high-power mode. The signal outi being in the inactive state, the signal outc 1 is also in the inactive state.

[0258] The PI pulse begins after time t0, and, at a time t1 after time t0, the voltage outFE becomes greater than the threshold Thl. As a result, at a time t1' after time t1, the signal outi switches to the active state (high state in [Fig. 16]) while the comparator COMPI is in high consumption mode.

[0259] The switching of the signal outi to the active state causes the switching, by the BOOST circuit, of the comparators COMPi, for i ranging from 2 to N=4, in high consumption mode, or, in other words, the switching of the signals bi, for i ranging from 2 to N=4, to the second binary state (high state in [Fig. 16]).

[0260] Switching the outi signal to the active state also causes the PULSE-RESET circuit to switch the outcl signal to the active state (high state in [Fig. 16]). This results in the start of a corresponding duration tmpl.

[0261] After time tl, at a time t2 subsequent to time tl' in this example, the voltage outFE increases and exceeds the threshold Th2, from which it follows that, at a time t2' subsequent to time t2, the signal out2 switches to the active state while the corresponding comparator COMP2 is controlled in high consumption mode. The switching of the signal out2 to the active state causes the switching of the comparators COMP1 and COMP2 to low consumption mode, that is to say the switching of the signals bl and b2 to their first binary states (the low state in [Fig. 16]).

[0262] After time t2, at a time t3 between times t2 and t2' in this example, the voltage outFE increases and exceeds the threshold Th3, from which it follows that, at a time t3' after times t3 and t2', the signal out3 switches to the active state while the corresponding comparator C0MP3 is controlled in high consumption mode. This switching of the signal out3 to the active state causes the comparator C0MP3 to switch to low consumption mode, i.e. the switching of the signal b3 to its first binary state (low state in [Fig. 16]).

[0263] After time t3, at a time t4 between times t2' and t3' in this example, the voltage outFE increases and exceeds the threshold Th4, from which it follows that, at a time t4' after times t4 and t3', the signal out4 switches to the active state while the corresponding comparator COMP4 is controlled in high consumption mode. This switching of the signal out4 to the active state causes the comparator COMP4 to switch to low consumption mode, that is to say the switching of the signal b4 to its first binary state (low state in [Fig. 16]).

[0264] At successive times t5, t6, t7 and t8 subsequent to time t4, and subsequent to time t4' in this example, the voltage outFE successively becomes lower than the thresholds Th4, Th3, Th2 and Thl.

[0265] Dotted lines illustrate in [Fig. 16] the appearance that the corresponding signals out4, out3, out2 and outl should have, and, in particular, that the signals out4, out3, out2 and outl should successively switch to the inactive state at times subsequent to time t8.

[0266] However, substantially at time t8 in this example, the duration tmpl expires and the signal rst switches to the active state. This causes the outi outputs of the COMPi comparators to be reset, or, in other words, this forces the outi signals to switch to the inactive state.

[0267] The switching of the signal outl to the inactive state causes the switching, by the BOOST circuit, of the comparators COMPi, for i going from 2 to N=4, in low consumption mode, or, in other words, the switching of the signals bi, for i going from 2 to N=4, to the first binary state (low state in [Fig. 16]).

[0268] Switching the outl signal to the inactive state also causes the outcl signal to switch to the inactive state (low state in [Fig. 16]).

[0269] Switching the signal out2 to the inactive state causes the comparator COMPI to switch to high consumption mode by the BOOST circuit, or, in other words, the signal bl to switch to the second binary state (high state in [Fig. 16])

[0270] The PULSE-RESET circuit therefore makes it possible to assist the return of the outi signals to the inactive state, and, more particularly, to switch them to the inactive state in advance compared to the case where these signals would be switched to the inactive state by the COMPi comparators solely on the basis of the comparison made, by each COMPi comparator, between the outFE voltage and the associated Thi threshold. This also makes it possible to condition the high consumption mode of each COMPi comparator for i ranging from 2 to N to the inactive state of the output signal outi of this comparator. As a result, the comparators COMPi for i ranging from 2 to N switch back to low-power mode more quickly than in the example in [Fig. 15].

[0271] Although an example has been described here in the case where the comparator COMPI is controlled in high consumption mode when the signal out2 is in the inactive state, and in low consumption mode otherwise, the person skilled in the art is able to adapt the description of this example to the case where the comparator COMPI is always in high consumption mode.

[0272] In the example of [Fig.16], the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high consumption mode if the signal outi is in the inactive state while the signal outl is in the active state, and in low consumption mode otherwise. As a result, the transition of these comparators COMPi to high consumption mode occurs when the signal outi is switched to the active state.

[0273] In another example not illustrated, to further reduce the time that each comparator COMPi, for i ranging from 2 to N, is controlled in high consumption mode if the signal outi of the channel CHi is in the inactive state while the signal outi-1 of the channel CHi-1 is in the active state, and in the low consumption mode otherwise. Taking the example of [Fig. 16], the signals b2, b3 and b4 would then switch to the high state at the respective times t1', t2' and t3'.

[0274] Although embodiments and variants of detectors DET1, DET2 and DET3 comprising devices EVAL-NUM1, EVAL-NUM2 and EVAL-NUM3 respectively have been described, embodiments provide the devices EVAL-NUM1, EVAL-NUM2 and EVAL-NUM3 alone, i.e. without the FRONT-END circuit and the PD photodetector. Indeed, it may be desirable for a set of a PD photodetector and a FRONT-END circuit to be developed and produced by one entity (legal or natural person), and for the circuit EVAL-NUM1, EVAL-NUM2, EVAL-NUM3 to be developed and produced by another entity (legal or natural person) and to be compatible with this set of a PD photodetector and a FRONT-END circuit, for example by adjusting the values ​​of the thresholds Thi and / or the durations tmpl (or tmplmax) and / or tmp2 accordingly.

[0275] Similarly, one embodiment provides the PULSE-RESET circuit alone, i.e. without the NUM and NUM2, EVAL and FRONT-END circuits and without the PD photodetector.

[0276] Furthermore, one embodiment provides a particle counting scanner, for example X-ray photons, comprising a plurality of photon counting detectors DET1, DET2 or DET3. In the case where the particles detected by each detector DET1, DET2, DET3 of the scanner are X-ray photons, each photodetector PD comprises, for example, cadmium telluride. For example, according to one embodiment In a particular embodiment, all the PD photodetectors of a set of several detectors DET1, DET2 or DET3 are arranged in a first level of a stack, the first level comprising for example a cadmium telluride layer or substrate, and all the FRONT-END and respectively EVAL-NUM1, EVAL-NUM2 or EVAL-NUM3 circuits of this set of detectors are arranged in a second level of the stack, the first level comprising for example a silicon substrate or a silicon layer, for example of the SOI type. The first level is then mounted on the second level, and is electrically connected to it, for example, by conductive balls or pads.

[0277] Of course, the embodiments and variants described above are not limited to implementation in an X-ray photon counting scanner, and, more generally, are not limited to implementation in a particle counting scanner.

[0278] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0279] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Device (EVAL-NUM2, EVAL-NUM3, NUM2) for a particle counting detector (DET2, DET3), in which: the device comprises N digitization channels, CHi, with N an integer strictly greater than 1 and i an index ranging from 1 to N, each channel CHi comprises a comparator, COMPi, associated with a threshold, Thi, of the channel and configured to provide a first pulsed digital signal, outi, in an active state if a pulsed analog voltage (outFE) supplied to said channels is greater than the threshold of the channel, and in an inactive state otherwise; the thresholds Thi are increasing with the index i; for i ranging from 2 to N, each comparator COMPi is configured to selectively operate according to a low consumption mode and a high consumption mode;and the device comprises a control circuit (BOOST) of the comparators COMPi configured, for i ranging from 2 to N, to control each comparator COMPi in the low consumption mode or in the high consumption mode as a function of at least the first signal outi of at least one of the channels CHi.;

2. Device according to claim 1, in which the control circuit (BOOST) is configured, during a rising edge of each pulse of said voltage (outFE) and for i ranging from 2 to N, to switch each comparator COMPi into the high consumption mode in response to a switching to the active state of the first signal outi of the channel CHI or of the first signal outi-1 of the channel CHi-1.

3. Device according to claim 2, in which the control circuit (BOOST) is further configured, following the rising edge of the pulse of said voltage and for i ranging from 2 to N, to switch each comparator COMPi into the low consumption mode at the earliest in response to a switching to the active state of the first signal outi of the channel CHi, and at the latest in response to a switching to the inactive state of the first signal outi of the channel CHI.

4. Device according to any one of claims 1 to 3, in which the control circuit (BOOST) is configured, for i ranging from 2 to N, to control each comparator COMPi in the high consumption mode if the first signal outi-1 of the channel CHi-1 is in the active state, and in the low consumption mode otherwise.

5. Device according to any one of claims 1 to 3, in which N is strictly greater than 2 and the control circuit (BOOST) is configured, for i ranging from 2 to N-1, to: - control each comparator COMPi in the high consumption mode if the first signal outi-1 of the channel CHi-1 is in the active state while the first signal outi+1 of the channel CHi+1 is in the inactive state, and in the low consumption mode otherwise; and - control the comparator COMPN in the high consumption mode if the first signal outN-1 of the channel CHN-1 is active and in the low consumption mode otherwise.

6. Device according to any one of claims 1 to 3, in which the control circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in the high consumption mode if the first signal outl of the channel CHI is in the active state, and in the low consumption mode otherwise.

7. Device according to any one of claims 4 to 6, wherein: - the comparator COMPI is configured to operate only in high consumption mode; or - the comparator COMPI is configured to operate selectively in high consumption mode or in low consumption mode, and the control circuit (BOOST) is configured to control the comparator COMPI in high consumption mode if the first signal out2 is in the inactive state, and in low consumption mode otherwise.

8. Device according to any one of claims 1 to 7, in which the device (EVAL-NUM2) further comprises a digital counting circuit (EVAL) configured to count, for each channel CHi, a number of switchings to the active state of the first signal outi of said channel.

9. Device according to any one of claims 1 to 7, wherein: the device (EVAL-NUM3) further comprises a digital pulse reset circuit (PULSE-RESET) configured to: - for each channel CHi, receive the first signal outi of said channel, generate a second pulse digital signal outci, and switch the second signal outci into an active state when the first signal outi is in the active state; and - generate a reset signal (rst) forcing, each time the second signal outci of the channel CHI switches to the active state, a switching to the inactive state of the first outi signals and / or the second outci signals at the end of a first time period (tmpl) starting with the switching to the active state of the second outci signal of channel CH1.

10. Device according to claim 9 wherein the reset signal (rst) is configured to force, at each switching to the active state of the second outci signal of the channel CH1, at least the switching to the inactive state of the first outi signals at the end of the first time period (tmpl) starting with the switching to the active state of the second outci signal of the channel CH1.

11. Device according to any one of claims 1 to 3, wherein: the device (EVAL-NUM3) further comprises a digital pulse reset circuit (PULSE-RESET) configured to: - for each channel CHi, receive the first signal outi of said channel, generate a second pulse digital signal outci, and switch the second signal outci into an active state when the first signal outi is in the active state;and - generate a reset signal (rst) forcing, at each switching to the active state of the second outci signal of the CHI channel, a switching to the inactive state of the first outi signals at the end of a first time period (tmpl) starting with the switching to the active state of the second outci signal of the CHI channel, and the control circuit (BOOST) is configured to, for i ranging from 2 to N, to control each comparator COMPi in the high consumption mode if the first outi signal of the CHi channel is in the inactive state while the first outi signal of the CHI channel is in the active state, and in the low consumption mode otherwise.;

12. Device according to any one of claims 1 to 3, wherein: the device (EVAL-NUM3) further comprises a digital pulse reset circuit (PULSE-RESET) configured to: - for each channel CHi, receive the first signal outi of said channel, generate a second pulse digital signal outci, and switch the second signal outci into an active state when the first signal outi is in the active state; and - generate a reset signal (rst) forcing, each time the second signal outci of the channel CHI switches to the active state, a switching to the inactive state of the first outi signals at the end of a first time period (tmpl) starting with the switching to the active state of the second outcl signal of the channel CH1, and the control circuit (BOOST) is configured to, for i ranging from 2 to N, to control each comparator COMPi in the high consumption mode if the first outi signal of the channel CHi is in the inactive state while the first outi-1 signal of the channel CHi-1 is in the active state, and in the low consumption mode otherwise.

13. Device according to any one of claims 9 to 12, in which the device (EVAL-NUM3) further comprises a digital counting circuit (EVAL) configured to count, for each channel CHi, a number of switchings to the active state of the second signal outci of said channel.

14. Particle counting detector (DET2, DET3) comprising: a photodetector (PD) adapted to receive particles, for example photons of X-ray radiation, and to provide a pulsed analog current (Idet) determined by the received particles; a current-voltage conversion circuit (FRONT-END) configured to receive the pulsed analog current (Idet) and to provide a corresponding pulsed analog voltage (outFE); and a device (EVAL-NUM2, EVAL-NUM3, NUM2) according to any one of claims 1 to 13, configured to receive the pulsed analog voltage.

15. A photon counting scanner comprising a plurality of particle counting detectors (DET2, DET3) according to claim 14, wherein the particles are photons of X-ray radiation, and each photodetector (PD) comprises, for example, cadmium telluride.

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