Programming the high resistance (HRS) state of a resistive memory element

Abstract

Method (100) for programming a high resistivity state of a memory element (Stck) forming part of a resistive random access memory (MEM), the method (100) comprising: an initial step (S110) of writing the high resistivity state of the memory element (Stck); and a reconditioning step (S140) following the initial step (S110) of writing the high resistivity state (HRS), the reconditioning step (S140) comprising at least one cycle of operations including, in this order: a reconditioning write operation (SETrec) which consists of circulating a reconditioning write current (Irec) in the memory element (Stck), the reconditioning current (Irec) having an absolute value less than the nominal programming current (Iset); and a reset operation (RESET) which consists of circulating a reset current (Ireset) through the memory element (Stck). Fig.5.

Description

Title of the invention: Programming the high resistance state (HRS) of a resistive memory element FIELD OF INVENTION

[0001] The technical field of the invention is that of resistive random access memories, or Resistive Random Access Memory (ReRAM), each of which comprises a memory element whose resistive state defines a bit of information. More specifically, the invention relates to a method for programming ReRAM. CONTEXT OF THE INVENTION

[0002] A non-volatile memory (NVM) is a type of computer memory capable of retaining information even when its power source is turned off. Examples of non-volatile memories include read-only memories (ROM), erasable read-only memories (EPROM), flash memories, ferroelectric random-access memories (FRAM), magnetoresistive random-access memories (MRAM), phase-change memories (PCM), and resistive random-access memories (ReRAM).

[0003] This latter type of memory, ReRAM, is generally formed from an array of stacks Stck consisting of a Diel layer made of a solid-state dielectric material and two electrodes E1 and E12 between which the Diel layer is interposed, as illustrated in [Fig. 1]. Such a structure constitutes a binary memory element, or memory element, and typically functions by modifying the electrical resistance of the Diel layer through the formation and dissolution of a conductive filament in the otherwise non-conductive dielectric layer. The dielectric layer can be formed, for example, from a chalcogenide, a perovskite, or an oxide of a transition metal such as hafnium oxide (HfOx).

[0004] A memory is formed from an array of such memory elements, each forming the core of a bit cell. The present description takes as an example a ReRAM using transition metal oxides to form the dielectric material in the solid state, i.e., an OxRAM.

[0005] As illustrated in [Fig. 1], during a SET writing operation, the application of a given voltage between the two electrodes generates an electric current Ip.set as well as an associated electric field in a first direction dl, from electrode E12 to electrode Eli. This current can lead to the formation of an electrically conductive filament Fil in the electrically insulating layer Diel, due to the formation and diffusion of oxygen ion pairs Oxy and oxygen vacancies VOxy in the The volume of the Diel dielectric layer. The binary element is then placed in a low resistance state, or LRS (Low Resistive State). The higher the writing current, the thicker the filament and the lower the resistance of the binary element.

[0006] Conversely, during a RESET operation, an opposing voltage is applied to generate a reset current Ip res flowing between the two electrodes Eli and E12 in a second direction d2, opposite to the first direction. The reset current can dissolve the electrically conductive filament Fil created during the Set operation, thus forming a dissolved filament DisFil and increasing the electrical resistance of the binary element. The binary element is then placed in a high resistance state, or HRS (High Resistive State).

[0007] Each of the LRS and HRS states can be associated with a bit value in a digital memory. During a read operation, a read current flows between the two electrodes to evaluate the resistive state of the binary element, and thus the associated binary value. The absolute value of the read current is lower than the write and reset currents so as not to alter the state of the dielectric layer.

[0008] The filament formation process and its final configuration, which determines the resistance of the memory element in the LRS, are stochastic in nature. Consequently, the characteristics of the bit cells extend over ranges. In this context, [Fig. 2] illustrates the resistances of a collection of bit cells from the same matrix.

[0009] Figures 2(A) and (B) illustrate the probability Pr for each bit cell of a matrix of taking a given resistance value R(Q), in an ideal case and in a more realistic case, respectively. In the ideal case, only two values ​​are possible: a first unique value for the resistance of the low resistance state LRS and a second unique value for the resistance of the high resistance state HRS.

[0010] In the ideal model, only these two states are accessible to the bit cells and each has a unique and well-defined resistance value. However, in practice, the resistance values ​​extend over ranges which can each be described as a probability density having the shape of a peak centered on a given value (Ro.lrs and Rq_hrs for the two states LRS and HRS, respectively) and having a standard deviation of 0 (similar distributions for LRS and HRS in this example, for the sake of simplicity of explanation), as illustrated by [Fig.2](B).

[0011] As illustrated in [Fig. 2](B), two states, LRS and HRS, can in fact be very close to each other. The distributions of these two states can even overlap. This can lead to confusion between an LRS state and an HRS state and to errors when reading data stored in ReRAM.

[0012] Depending on the absolute value Ip rog of the programming current defining the write current and the reset current, the resistance values ​​of the HRS and the LRS vary.

[0013] As illustrated in [Fig. 3], for a given memory element, a write operation with a first programming current 1^1 will result in a first filament Fill of a given width, and therefore in an LRS with a first resistive value R1lrs. With the same programming current IProgl, a reset operation RESET will dissolve the filament to a certain extent, and therefore an HRS with a first resistive value R1Hrs. These results are illustrated in the left part of [Fig. 3].

[0014] The right-hand side of [Fig. 3] illustrates the results of the same write and reset operations as the left-hand side, except that a stronger programming current IProg2 is used. The filament Fil2 formed by the write operation is thicker than the filament Fill and more difficult to dissolve by the reset operation RESET, which leads to an LRS with a second resistive value R2lrs lower than the first resistive value R1lrs, and an HRS with a second resistive value R2hrs lower than the first resistive value R1Hrs-

[0015] Thus, programming the LRS of a memory element with a higher write current can contribute to the formation of a thicker filament. The advantage of this method is that it allows the formation of LRSs with lower resistance values. However, thicker filaments are more difficult to dissolve, resulting in a relatively low resistance value for the HRS, which defeats the overall objective of increasing the resistance gap between LRS and HRS states. Furthermore, the memory's HRS retention capacity degrades because the thicker filaments reform more easily over time.

[0016] We find that it is necessary to improve the writing method used in OxRAM, and more generally in ReRAM. SUBJECT OF THE INVENTION

[0017] In the context described above, the inventors propose a method for programming a ReRAM memory element that allows a high resistance value to be set for the HRS while maintaining a low resistance value for the LRS, and thus improves the resistance gap between the LRS and the HRS. Summary of the invention

[0018] To this end, a first aspect of the invention relates to a method for programming a high-resistivity state of a memory element forming part of a random-access resistive memory, the random-access memory being configured to program a low-resistivity state of the memory element by passing a nominal programming current in a first direction through the memory element, the method comprising: an initial step of writing the high resistivity state of the memory element, consisting of passing a reset current through the memory element in a second direction, opposite to the first direction; and a reconditioning step following the initial step of writing the high resistivity state, the reconditioning step comprising at least one cycle of operations including, in this order: a reconditioning write operation which consists of passing a reconditioning write current in the first direction through the memory element, the reconditioning write current having an absolute value less than the nominal programming current;and a reconditioning operation which consists of passing a reconditioning current in the second direction through the memory element.

[0019] By applying a reconditioning operation, which includes at least one write operation followed by a reset operation, the write operation using a programming current lower than the nominal current used in the normal write operation of an LRS, the programming method according to the invention makes it possible to achieve a resistive value for the HRS which is greater than that which could be obtained by conventional HRS writing methods.

[0020] Advantageously, the resistance gap between the LRS and the HRS is widened, which facilitates the reading operation and generally improves the reliability of a ReRAM using this programming method.

[0021] According to other non-limiting features of the first aspect of the invention, whether taken individually or in any technically feasible combination:

[0022] - the method may also include: a first reading operation measuring a resistive value of the resistive element after the initial step of executing the reset operation; and a test step in which the measured resistive value is compared to a threshold value, the reconditioning step being executed when the measured resistive value is less than the threshold value;

[0023] - the reconditioning step can increase the resistive value of the element of memory obtained by the initial step of writing the high resistivity state;

[0024] - the method may further comprise: a second reading operation measuring a reconditioned resistive value of the resistive element after execution of the reconditioning step; and a second test step in which the measured reconditioned resistive value is compared to the threshold value, the reconditioning step being executed again when the measured reconditioned resistive value is less than the threshold value;

[0025] - the reconditioning step may include exactly one occurrence of the cycle of operations;

[0026] - the reconditioning step may include more than one occurrence of the cycle of operations;

[0027] - the reconditioning step may include more than one and less than 20 occurrences of the cycle of operations;

[0028] - the nominal programming current can have an absolute value between 175 pA and 225 pA, and the reconditioning write current can have an absolute value between 75 pA and 125 pA;

[0029] - the initial step of writing the high-resistivity state of the memory element can dissolve an electrically conductive filament formed in the memory element; the reconditioning write operation can reform the dissolved filament; and the reconditioning reset operation can dissolve the reformed filament.

[0030] A second aspect of the invention relates to a ReRAM memory device comprising a bit cell array controlled by a column multiplexer circuit and a row driver circuit configured to write a high-resistance state of a bit cell memory element according to the method of the first aspect of the invention. The ReRAM may be an OxRAM.

[0031] A third aspect of the invention relates to an embedded system comprising a microprocessor and the memory device according to the second aspect of the invention arranged to be in communication with the microprocessor. Brief description of the drawings

[0032] Many other features and advantages of the present invention will become apparent from the following detailed description, considered together with the accompanying drawings, in which:

[0033] [Fig-1] - The [Fig.1] illustrates the operating principle of a ReRAM;

[0034] [Fig.2] - Fig.2 illustrates the distribution of resistivities of the bit cells of a resistive memory;

[0035] [Fig.3] - The [Fig.3] illustrates the influence of the programming current intensity on the resistive values ​​of the LRS and HRS of a memory element;

[0036] [Fig.4] - The [Fig.4] illustrates the effects of the method according to the invention;

[0037] [Fig.5] - The [Fig.5] is a diagram of an HRS writing method;

[0038] [Fig.6] - The [Fig.6] represents the currents applied to a memory element according to the method of the [Fig.5];

[0039] [Fig.7] - Fig.7 phenomenologically illustrates the functioning of the method of figures 5 and 6;

[0040] [Fig-8] - The [Fig.8] presents graphs explaining the operation of the method of the [Fig.5];

[0041] [Fig.9] - Fig.9 is a graph justifying the specific values ​​of the intensity of the current used in the method of [Fig.5];

[0042] [Fig. 10] - [Fig. 10] illustrates a ReRAM memory incorporating the memory element illustrated by [Fig. 4]; and

[0043] [Fig. 11] - The [Fig. 11] illustrates an embedded system incorporating the memory illustrated by the [Fig. 10].

[0044] DETAILED DESCRIPTION OF A GENERIC EMBODIMENT OF THE INVENTION

[0045] A generic embodiment of the invention will be described below, with reference to Figures 4 to 11.

[0046] Fig. 4 represents the cumulative probabilities Cum.Pr for the memory elements of a ReRAM to exhibit a given resistance R, expressed in ohms, for their respective low resistance state LRS and high resistance state HRS.

[0047] In (A), [Fig. 4] represents a situation in which there is an overlap, indicated by Over, between the resistances of the low-resistivity state LRS and the high-resistivity state HRSConv obtained with conventional writing methods. This overlap is a source of difficulty for the use of ReRAM.

[0048] At point (B), [Fig. 4] represents the objective and function of the programming method described below. The objective is to use a programming method that allows the HRS profile to transition from the conventional high resistivity state HRSConv to a high resistivity state HRSinv, obtained using the method according to the invention, to high R values. Then, a Marg gap is introduced, or widened if it already existed, between the low and high resistivity states of the ReRAM.

[0049] In other words, it is necessary to obtain a higher resistive value for the HRS state of a memory element in a ReRAM than is usually obtained. The method developed by the inventors is based on the principle of better dissolution of a filament formed in the memory element than is usually obtained. This principle is implemented by method 100 of [Fig. 5], applied to a Stck memory element of a ReRAM such as that illustrated in [Fig. 1].

[0050] In order to place the memory element in a state in which the method is applicable, a preliminary step of programming the low resistivity state LRSprog of the memory element is performed. This programming forms an electrically conductive filament within the dielectric layer Diel, which is otherwise electrically insulating.

[0051] In the present embodiment, the LRSprog programming step consists of programming the memory element in LRS by means of a SETprog programming operation in a step S90. The SETprog operation is performed by applying a voltage to the electrodes Eli and E12 of the memory element so as to cause a nominal programming current Ip.set, having an absolute current value Inom, to flow in the first direction dl through the Stck stack. The absolute value of the current and the direction of current flow are chosen to form the filament Fil.

[0052] Next, at step S105, a programming command for the Stck memory element in HRS is received, and a programming step for the high resistance state HRSprog of the memory element is then carried out in accordance with the following steps SI 10 to S140.

[0053] In a first step SI 10 of programming the memory element in HRS, a programming reset operation RESETprog is performed by applying a constant voltage to the electrodes Eli and E12 of the memory element so as to cause a programming reset current Ip res to flow. This current will initially be approximately of the same absolute value Inom as Ip set, but in the second direction d2 in the stack-up Stck, opposite to the first direction, before decreasing and converging towards the current flowing in the HRS state of the memory element. The initial reset current may have an absolute value different from T J-nom*.

[0054] At step S120, a first READ operation is performed on the resistive element Stck in order to measure its resistive value R after the first step SI 10 of programming the memory element in HRS.

[0055] After the first read operation of step S120, a test step S130 is carried out during which the read value R is compared to a threshold value RTh which is considered to be the lowest acceptable resistive value for the high resistivity state HRS of the memory element.

[0056] If the read value R is greater than or equal to the threshold value RTh, then the process is allowed to stop at an S150 end-of-process step END. In this situation, the resistive value is considered sufficient to ensure proper memory operation, with a margin between LRS and HRS that meets the predetermined specifications for this memory.

[0057] If, however, the read value R is less than the threshold value RTh, the process proceeds to a reconditioning step S140, which constitutes the core of the process for increasing the resistive value R of the memory element above the threshold value Rïh-

[0058] The S140 reconditioning step comprises n cycles, each consisting of a SETrec reconditioning write operation followed by a RESETrec reconditioning reset operation. The number n is an integer that can be between 1 and 30, preferably between 1 and 20.

[0059] The RESETrec reconditioning reset operation is performed by applying a voltage to the electrodes Eli and E12 of the memory element so as to cause a reconditioning reset current Irec.res to flow in the second direction d2, through the Stck memory element.

[0060] The reconditioning reset current Irec res may optionally be identical to the programming reset current Ipres of the programming reset operation RESETprog of step SI 10, i.e. that the characteristics of the current (direction, intensity, duration of the applied voltage) used to dissolve the Fil filament may be the same as those of the current Ipres used to normally write the HRS in step SI 10.

[0061] In contrast, the SETrec write operations of the S140 reconditioning step differ from the SETprog write operation of the ReRAM; that is, the Irec Set current used to form the Fil filament in the S140 reconditioning step is different from the Ip Set current used to normally write the LRS in the S90 step. The intensity of the reconditioning Irec Set current is lower in absolute value than the Ip Set current used in regular ReRAM write operations: Urec.seJ < Hp.seJ*

[0062] Figures 7 and 8 explain the principle of the S140 reconditioning step.

[0063] Fig. 7 shows in (A) the resistive values ​​plotted for the low and high resistive states RLHS and Rhrs of a memory element as a function of the absolute value of the programming current Iprog used to write these states with conventional write and reset operations.

[0064] If we start from a low resistivity state STARTlrs written by a relatively high value IStart of the programming current, a reset operation using the same value Iprog will write a high resistivity state STARThrs which still has a resistivity value much lower than a resistivity value of a target low resistivity state TARGHRs • This is due to the phenomenon illustrated by [Fig.3] and discussed previously.

[0065] To write the high resistivity state TARGhrs, one can consider starting from the high resistivity state STARThrs, then reducing the programming current to the ITaig current corresponding to that of the high resistivity state TARGhrs on the graph to write the corresponding low resistivity state TARGhrs, and then applying an operation reset to reach the target state TARGhrs- However, this scheme is not feasible because, in the scenario of [Fig.7](A), the resistive value of the initial high resistivity state STARTHrs is less than the resistive value of the target low resistivity state TARGhrs.

[0066] To circumvent this limitation, the method consists of employing, if necessary, a succession of cycles, each comprising a write operation followed by a reset operation, which allows the high resistive state TARGhrs to be reached progressively, even starting from the low resistive state STARTlrs, as illustrated in [Fig. 7](B). For the reasons explained below in relation to [Fig. 8], the current used must be lower than the current initially used to write the STARTlrs state.

[0067] In the scenario illustrated by [Fig. 7](B), 9 steps are required to write the TARGhrs state from the STARTlrs state, and there is no situation in which the transition from an HRS to an LRS would involve increasing the resistive value, which was the impossibility mentioned in the scenario of [Fig. 7](A). These 9 steps are distributed among 5 pairs of LRS and HRS identified as (1) to (5).

[0068] In a conventional writing method, the resistance of the memory element switches between two resistance states in a one-dimensional manner, along the Y-axis of the graphs in [Fig. 7]. In contrast, the programming method 100 of [Fig. 4] advantageously allows the resistive value to be moved along both the X-axis and the Y-axis of the graphs, thus enabling greater flexibility in programming a ReRAM memory. In this example, we can see that the achievable resistive value has gained a resistance Rgain, which represents the difference between the resistive values ​​of the Rhrs and TARGhrs states.

[0069] [Fig.8] explains in a phenomenological way the response of the dielectric layer of the Stck memory element to the successions of steps illustrated by [Fig.7](B).

[0070] The left side of [Fig.8] represents the Fil filaments formed by the successive setup operations and the right side of [Fig.8] represents the dissolved filament DisFil obtained by the successive reset operations, for each of the 5 pairs of LRS and HRS identified as (1) to (5) in [Fig.7](B).

[0071] The principle is to start with a thick filament, necessary to obtain a low resistive value, and to reduce the filament's thickness by repeatedly dissolving and reforming it thinner than before, in successive cycles carried out according to step S140. In this way, the filament obtained at the last pair of states (5) is thin and can be easily dissolved to obtain an HRS state with a high resistive value. Generally, the number of pairs of states is equal to the number of repetitions n of the SETrec / RESETrec cycles. Figure 8 represents The first reset operation corresponds to the programming reset operation of step SI 10, which uses the Ipres current, and subsequent reset operations use the Irec.res current. Write operations are performed with the Irecset current. In this example, four cycles, each comprising a SETrec operation and a RESETrec operation, are performed.

[0072] Step S140 changes the resistive value R of the memory element to a value Rrec which must be read during a new step S120, considered as the new value R and compared to the threshold value RTh during a new test step S130.

[0073] If the threshold value RTh is still greater than the value R read, steps S140, S120 and S130 are executed again, until the resistive value R becomes greater than or equal to the threshold value R^, in which case the method ends at step S150.

[0074] As illustrated in [Fig. 6], the method of [Fig. 5] can be implemented by any conventional ReRAM memory programmed to execute the steps of Method 100 described above. More specifically, the write, reset, and read operations can consist of applying control voltages to electrodes E1 and E12 in the form of pulses (applying voltages for finite periods of time), which has the effect of generating current pulses flowing through a memory element, as is traditionally well known. [Fig. 6] is a graph representing the applied currents of intensity I as a function of time t. [Fig. 6] is only a schematic illustration, and the intensities, lengths, and profiles of the pulses shown are not limited to this figure.

[0075] During a write operation, a voltage is applied, generating a circulating current in the memory element, which must be limited in order to avoid damaging the memory, because the formation of the filament and therefore the reduction of the resistance of the current leads to an increase in the current, which must be capped in order to avoid damaging the memory.

[0076] During a reset operation, a voltage of the same order of magnitude but opposite sign to the voltage used during the write operation can be used, generating a current initially substantially identical to the current flowing through the memory element at the end of the write operation. As the filament dissolves, this current decreases with increasing resistance.

[0077] The voltages required to generate the currents suitable for write, reset and read operations may vary depending on the ReRAM technology and the electronic configuration of a memory cell, a memory element array or, more generally, the electronic circuits used to control the ReRAM.

[0078] In contrast, the current values ​​are better defined. Figure 9 shows a graph that can be used to determine a suitable current value for implementing the SETprog programming operation and the SETrec reconditioning operation. The nominal programming current is determined by the retention requirements: the current must be strong enough to form a filament thick enough to provide a sufficiently high retention capacity. The current for the reconditioning operation must be low enough so that the filament it forms can be effectively dissolved by a reset operation, ensuring that the resistive value of the high resistive state is above a given threshold, defined by the ReRAM specifications.

[0079] Write tests of the LRS and HRS were performed for four values ​​(408 pA, 307 pA, 208 pA, 119 pA) of the programming current for the SETprog and SETrec write and recondition operations. In this example, it is observed that the higher the current, the lower the resistive value of the LRS, and conversely, the lower the current, the higher the resistive value of the LRS. Here, the current must be as low as 119 pA for the resistive value of the HRS state to reach a threshold value RTh and be considered acceptable. As illustrated, a gain in the resistive value of the high-resistivity state can be estimated by comparing the resistive value for two distinct programming currents, the 408 pA current and the 119 pA current in [Fig. 9].

[0080] In practice, by proceeding as illustrated above, favorable values ​​for the SETprog operation current can be defined as being between 175 pA and 225 pA. A current of the same absolute value can be used for the RESETprog and RESETrec reset operations. Conversely, favorable values ​​for the SETrec reconditioning operation current are lower than the values ​​for the SETprog write operation current and can be defined as being between 75 pA and 125 pA.

[0081] The number n of cycles required to reach an acceptable resistive value for the HRS can be determined empirically by experience.

[0082] Alternatively, as illustrated by method 100 of [Fig.5], reconditioning can be used only when necessary, after the reading and testing operations.

[0083] The read and test operation could be performed between each cycle, which would correspond to n = 1 in the diagram in [Fig. 5]. This specific variant has the disadvantage of a speed loss when several cycles are required. On the other hand, it limits the number of write and reset operations, which reduces wear on the memory element and therefore improves retention capacity and reliability.

[0084] Alternatively, a fixed number n of cycles, with n > 1, can be performed between two test operations. This specific variant can be advantageous in terms of speed when a large number of cycles are required to reach the threshold value RTh, as it allows limiting the number of reset and test operations.

[0085] The Stck stack described above can constitute the active elements of a ReRAM MEM memory. The setup, reset, and read operations can be applied to bit cells integrated into an ARR network, each bit cell comprising a Stck stack.

[0086] Figure 10 illustrates a conventional basic structure of a resistive memory EMM. Such a memory is described, for example, in US patent 11735260B2.

[0087] Typically, as illustrated in [Fig. 10](C), each bit cell BC of the ARR network comprises (i) a stack Stck which forms a variable resistance VarR (see [Fig. 10](B)) and fulfills the function of binary memory element for each bit cell, and (ii) a SelTr selection transistor having a source and a drain connected in series with the variable resistance.

[0088] An ARR bit cell network generally comprises columns and rows of bit cells, as illustrated in [Fig. 10](A). Each column comprises (i) a bit line BL connected to a source and drain of the SelTr transistor through the variable resistor VarR for each of the bit cells in the column, and (ii) a source line SL connected to the bit line BL through the source and drain of the SelTr transistor and the variable resistor VarR. Each row of bit cells comprises a word line WL connected to the gate of the SelTr selector transistor for each of the bit cells in the row. The bit lines BL and the source lines SL are each connected to and controlled by a column multiplexer circuit SL / BL-Mux. The word lines WL are each connected to and controlled by a line driver circuit WL-Drv.

[0089] Figure 11 illustrates an EmbSys embedded system integrating OxRAM in communication with a CPU microprocessor. Such a system can be a portable semiconductor device configured to process digital data. Generally speaking, any embedded device conventionally using flash memory can use resistive memory instead. OxRAM can benefit from the improved retention capacity of the Stck stacking described above, making it particularly suitable for high-temperature applications such as transportation applications.

[0090] Other variants of the disclosed embodiments can be understood and carried out by persons competent in the practice of the claimed invention, from the study of the drawings, the disclosure and the attached claims.

Claims

Demands

1. Method (100) of programming a high resistivity state (HRS) of a memory element (Stck) forming part of a random access memory (MEM), the random access memory being configured to program a low resistivity state (LRS) of the memory element by circulating a nominal programming current (Ip .set) in a first direction (dl) through the memory element (Stck), the method (100) comprising: - a first step (SI 10) of writing the high resistance state (HRS) of the memory element (Stck), consisting of circulating a reset current (Ireset) through the memory element in a second direction (d2), opposite to the first direction (dl);and - a reconditioning step (S 140) following the initial step (SI 10) of writing the high resistivity state (HRS), the reconditioning step (S 140) comprising at least one cycle of operations including, in this order: - a reconditioning write operation (SETrec) which consists of passing a reconditioning write current (Irec,set) in the first direction (d1) through the memory element (Stck), the reconditioning write current (Irec set) having an absolute value less than the nominal programming current (Ip set); and - a reconditioning reset operation (RESET) which consists of passing a reconditioning reset current (Ireset) in the second direction (d2) through the memory element (Stck).

2. A method according to claim 1, further comprising: - a first read operation (S 120) measuring a resistive value (R) of the memory element after the initial step (SI 10) of executing the reset (RESET) operation; and - a test step (S 130) during which the measured resistive value (R) is compared to a threshold value (RTh), in the reconditioning step (S 140) is carried out when the measured resistive value (R) is less than the threshold value (RTh).

3. A method according to any one of claims 1 and 2, wherein the reconditioning step (S 140) increases the resistive value (R) of the memory element obtained by the initial step (SI 10) of writing the high resistivity state (HRS).

4. A method according to any one of claims 1 to 3, further comprising: - a second read operation (S 120) measuring a reconditioned resistive value (Rrec) of the memory element after execution of the reconditioning step (S 140); and - a second test step (S 130) in which the measured reconditioned resistive value (R) is compared to the threshold value (Rn), in which the reconditioning step (S 140) is executed again when the measured reconditioned resistive value (Rrec) is less than the threshold value (RTh).

5. A method according to any one of claims 1 to 4, wherein the reconditioning step (S 140) comprises exactly one occurrence of the cycle of operations.

6. A method according to any one of claims 1 to 4, wherein the reconditioning step (S 140) comprises more than one occurrence of the cycle of operations.

7. A method according to claim 6, wherein the reconditioning step (S 140) comprises more than one and less than 20 occurrences of the cycle of operations.

8. A method according to any one of claims 1 to 7, wherein: - the nominal programming current (Ip set) has an absolute value (Lom) between 175 pA and 225 pA, and - the reconditioning write current (Irec set) has an absolute value between 75 pA and 125 pA.

9. A method according to any one of claims 1 to 8, wherein: - the initial step (SI 10) of writing the high resistivity state (HRS) of the memory element (Stck) dissolves an electrically conductive filament (Wire) formed in the memory element (Stck); - the write reconditioning operation (SETrec) reforms the dissolved filament (DisWire); and - the reset reconditioning operation (RESET) dissolves the reformed filament (Wire).

10. ReRAM (MEM) memory device comprising an array (ARR) of bit cells (BCs) controlled by a column multiplexer circuit (SL / BL-Mux) and a row driver circuit (WL-Drv) configured to write a high resistance state (HRS) of an element

11.

12. of memory (Stck) of the bit cell (BC) according to the method of any one of claims 1 to 9. ReRAM memory device according to claim 10, the ReRAM being an OxRAM. Embedded system (EmbSys) comprising a microprocessor (CPU) and the memory device (MEM) according to claim 10 or 11 arranged to be in communication with the microprocessor (CPU).

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