A substrate for the CVD growth of graphene, a graphene laminate and a method of manufacture thereof

Abstract

A substrate for the CVD growth of graphene comprises a support 205 and a first layer 210 provided thereon, the first layer having a growth surface distal from the support, the growth surface being for

Description

The present invention relates to a substrate suitable for the CVD growth of graphene, in particular to a substrate having a growth surface formed of scandium-aluminium oxide. The present invention also relates to a graphene laminate and a method for the manufacture of a graphene laminate, in particular a method comprising forming graphene by CVD. Graphene has received much attention as a two-dimensional material in view of its unique electronic properties and its applications in electronic devices. It is common in the art for graphene to be manufactured by techniques such as exfoliation or by CVD on catalytic metal substrates such as copper. The graphene produced by such methods is then transferred to electronic devices having compatible, insulative or semiconducting substrates. It is also known in the art that graphene may be synthesised, manufactured or formed, directly on non-metallic surfaces of substrates. These include silicon, sapphire and lll-V semiconductor substrates. The present inventors have found that the most effective method for manufacturing high quality graphene, especially directly on such non-metallic surfaces, is that disclosed in WO 2017 / 029470. This publication discloses methods for manufacturing graphene; principally these rely on heating a substrate held within a reaction chamber to a temperature that is within a decomposition range of a carbon based precursor for graphene growth, introducing the precursor into the reaction chamber through a relatively cool inlet so as to establish a sufficiently steep thermal gradient that extends away from the substrate surface towards the point at which the precursor enters the reaction chamber such that the fraction of precursor that reacts in the gas phase is low enough to allow the formation of graphene from carbon released from the decomposed precursor. Preferably the apparatus comprises a showerhead having a plurality of precursor entry points or inlets, the separation of which from the substrate surface may be varied and is preferably less than 100 mm. The method of WO 2017 / 029470 is ideally performed using an MOCVD reactor. Whilst the method of WO 2017 / 029470 enables the production of high quality graphene with excellent uniformity and a constant number of layers (as desired) across its whole area on the substrate without additional carbon fragments or islands, the strict requirements in the art of electronic device manufacture means that there remains a need to further improve the electronic properties of the graphene and to provide methods that are more reliable and more efficient for the industrial manufacture of graphene, particularly large area graphene on non-metallic substrates. WO 2022 / 200351 is a publication originating from the present inventors which also aims to address this problem and discloses forming a graphene layer structure on a growth surface of a substrate by CVD, wherein the growth surface is formed of a material selected from the group consisting of: YSZ, MgAl2O4, YAIO3, CaF2, and LaFs. WO 2022 / 175273 is a publication originating from the present inventors which relates to the formation of a thin graphene-containing conductive substrate obtainable by etching a sacrificial silicon wafer away from a graphene layer structure formed on an insulative layer that is itself formed on the silicon wafer. However, there remains a need in the art for methods which provide yet further higher quality graphene so as to provide improved electronic properties characteristic of those which are envisaged as theoretically possible for graphene. Moreover, there is a need in the art for ever more reliable methods which allow for the integration of graphene into conventional silicon-based semiconductor manufacturing processes and the growth of graphene onto silicon-based wafers / substrates. The present inventors developed the present invention with the aim of addressing these problems in the art, or to at least provide a commercially useful alternative thereto. In a first aspect, the present invention provides a substrate for the CVD growth of graphene, the substrate comprising a support and a first layer provided thereon, the first layer having a growth surface distal from the support, the growth surface being formed of scandium-aluminium oxide having a <111 >crystallographic orientation, wherein an atomic ratio of scandium to aluminium is from 1:24 to 1:4. The present disclosure will now be described further. In the following passages, different aspects / embodiments of the disclosure are defined in more detail. Each aspect / embodiment so defined may be combined with any other aspect / embodiment or aspects / embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous. The present invention relates to a substrate which is suitable for the CVD growth of graphene. As used herein, the term substrate may be used to refer to a material suitable for the deposition of another layer thereon as is customary in the art of electronic device fabrication. The term substrate is typically synonymous with a wafer which may consist of a single material or layers of multiple materials. As will be appreciated, a substrate, and a substantially flat upper growth surface thereof, is formed of crystalline material as is known in the art. Accordingly, substrates and wafers provide a planar growth surface, preferably formed of a single crystal, and do not include powders or nanocrystalline materials. Preferably, the substrate has a diameter of at least 1 inch (25 mm), preferably at least 2 inches (51 mm). In the present invention, the substrate comprises a support and a first layer is provided thereon. As used herein, a support may itself be considered synonymous with a substrate or wafer upon which there is provided the first layer which itself provides an exposed surface for subsequent growth of further layers (i.e. the growth surface). The growth surface is therefore the surface of the first layer which is distal from the underlying support, the opposite surface of the first layer being that which interfaces an upper surface of the support. As described in greater detail herein, the support preferably comprises silicon, germanium and / or sapphire, in particular silicon (i.e. elemental silicon). It is preferred that the support consists essentially of silicon and / or sapphire, and optionally germanium. Such supports may be referred to as a silicon wafer, a sapphire wafer, or silicon on sapphire (SOS) wafer. In some embodiments, it is preferred that the upper surface of the support is formed of silicon (such that the interface with the first layer is silicon). As will be appreciated, a silicon support layer, for example, includes a “pure” silicon wafer (essentially consisting of silicon, doped or undoped) or what may be referred to as a CMOS wafer which includes additional associated circuitry. As such, the present invention allows for the integration of graphene into conventional silicon-based electronic device fabrication processes. Preferably, the thickness of the support is at least 250 pm, preferably at least 400 pm. Generally the support thickness is no more than about 2 mm, preferably no more than about 1.5 mm, as is conventional for large-area wafers. The first layer is generally provided as a crystalline “thin film”. Though there is no specific upper limit of the thickness, thin films are generally those which are less than 10 pm thick, such as less than 5 pm, or even less than 1 pm. Preferably, the thickness of the first layer is at least 5 nm, preferably at least 10 nm. As such, the thickness of the first layer may range from 5 nm to 5 pm, such as from 10 nm to 1 pm. The growth surface of the substrate is formed of scandium-aluminium oxide (i.e. ternary oxide of scandium and aluminium). Scandium-aluminium oxide may be represented by the chemical formula ScxAlyO3, wherein x + y = 2 (equivalent to ScxAh-xOs), wherein x and y are greater than 0. As will be appreciated, the oxygen stoichiometry may be about 3 as it is known that oxygen stoichiometry in metal oxides may be subject to minor variations from an idealised stoichiometry. The present inventors have used sapphire (i.e. aluminium oxide - AI2O3) extensively as a non-metallic surface upon which to manufacture graphene layer structures using CVD techniques. Sapphire is a readily commercially available substrate with desirable properties which have allowed the inventors to manufacture high quality graphene. As is known in the art, sapphire is a material which adopts a hexagonal crystal structure which is believed to accommodate the growth of graphene as a hexagonal two-dimensional material. Without wishing to be bound by theory, the inventors believe that a <111 >crystallographic orientation of a cubic material can improve the quality of graphene deposited thereon by CVD as a result of the threefold rotational symmetry associated with such an orientation. Again, without wishing to be bound by theory, the inventors believe that that the addition of a small amount of scandium to aluminium oxide provides and stabilises a cubic phase. By way of comparison, it is known in the art that yttria (Y2O3) may be used to stabilise the cubic phase of zirconia (ZrOs) to provide yttria-stabilised zirconia (YSZ) such that the growth surface of the substrate of the present invention may be viewed as “scandia-stabilised alumina”. The present inventors have determined that the atomic ratio of scandium to aluminium of from 1:24 to 1:4 can provide an improved growth surface for the formation of a graphene layer structure. Preferably, the atomic ratio of scandium to aluminium is from 1:16 to 1:5, more preferably from 1:12 to 1:7, with the ideal ratio being about 1:9. In other words, x in ScxAh-xOi.5 is preferably about 0.1 though the inventors have determined that an improved growth surface may be achieved where x is at most 0.2 (for example, when compared to aluminium oxide). Generally, a minimum amount of scandium may be at least 0.04, preferably at least 0.06, more preferably at least 0.08. Preferably, a maximum amount of scandium is at most 0.17, more preferably at most 0.13. These values of x may equally provide the atomic amount of scandium with respect to the amount of scandium and aluminium when multiplied by 100. For example, the most preferred range for x of from 0.08 to 0.13 may alternatively refer to a range of from 8 to 13 at.% scandium, with about 10 at.% scandium being preferred. The inventors believe that scandium-aluminium oxide has a beneficially low carbon solubility at high temperatures (relative to known growth substrate materials), similar to other rare earth oxides with which the inventors have grown graphene on, such that during the high temperatures of CVD, high-quality uniform graphene may be grown without the defects which can be present when grown directly on such other known growth surfaces. For example, it is known that growth surfaces formed of materials such as silicon or 11 l-V semiconductors can give rise to covalent bonding to the carbon atoms during CVD growth resulting in graphene defects. The inventors were surprised to find that the resulting graphene was yet further improved over aluminium oxide or rare earths such as scandium oxide alone as binary oxides since it is believed that the ternary structure of scandium-aluminium oxide having the atomic ratio of scandium to aluminium described herein minimises the lattice mismatch with graphene providing a more stable configuration of carbon atoms during and after growth, minimising defect formation and promoting single crystal graphene formation. Accordingly, the use of scandium-aluminium oxide as a material of the growth surface of a substrate provides advantages for CVD grown graphene in terms of the resulting electronic properties, i.e. improved mobility, sheet resistance and / or Hall sensitivity. In some embodiments, the first layer may simply consist of the scandium-aluminium oxide having the atomic ratio. In other preferred embodiments, the first layer comprises a first sub-layer as a buffer layer between the support and the growth surface. The first layer may therefore comprise a second sub-layer consisting of the scandium-aluminium oxide which provides the growth surface. As such, the buffer layer (i.e. the first sub-layer) is provided between the support and the second sub-layer. More preferably, the first layer consists of the first and second sub-layers such that the lower surface of the buffer layer is on an upper surface of the support, the lower surface of the second sub-layer is on the upper surface of the buffer layer. A buffer layer is particularly suitable for embodiments wherein the support has a silicon upper surface. The inventors have found that there are notable differences in the lattice parameters of scandiumaluminium oxide and silicon such that these differences can result in strain and stresses being present at the interface of the two layers. There is a risk that this then leads to defects occurring in the scandium-aluminium oxide layer. This is a particular problem where the substrate is used to form graphene by CVD thereon since the temperatures required for CVD are typically in excess of 750°C as described herein. A buffer layer may help to mitigate the differences in lattice parameters and reduce the risk of forming defects in the second sub-layer. A buffer layer is an inorganic cubic material, generally a metal oxide, though CaFs and MgFa may also be preferred. Suitable metal oxides include zirconium, yttrium, hafnium, cerium, erbium, gadolinium, dysprosium, praseodymium and / or magnesium oxide, strontium titanate (STO) and / or yttria-stabilised zirconia (YSZ). Particularly preferred oxides for forming the buffer oxide layer are scandium oxide, erbium oxide, yttrium oxide, zirconium oxide and / or yttria-stabilised zirconia, preferably scandium oxide, yttrium oxide and / or erbium oxide, due to their thermodynamic stability during subsequent CVD growth of graphene. Scandium oxide and yttrium oxide are diamagnetic which can avoid any complications with subsequent use in electronic devices whereas erbium oxide is paramagnetic. However, erbium oxide has greater thermodynamic stability on silicon which is advantageous. Combinations of such materials in a buffer layer may be used to alleviate lattice mismatch and may be formed of buffer sub-layers. For example, the buffer layer may comprise a layer of scandium oxide on a layer of erbium oxide as the inventors have found this to work better for graphene growth than just scandium oxide. That is, particularly on silicon, erbium oxide may be used between the silicon surface of the support and scandium oxide to alleviate the mismatch between the two materials. In some preferred embodiments, the buffer layer comprises scandium-aluminium oxide having a different atomic ratio from the growth surface. The buffer layer may consist of such scandium-aluminium oxide, though may optionally include one or more sub-layers of the materials described above. When present, such a (first) “buffer sub-layer” is preferably provided on the support, and the scandium-aluminium oxide (second) “buffer sub-layer” is provided on the first buffer sub-layer such that the growth surface is provided on the second buffer sub-layer of scandium-aluminium oxide having a different atomic ratio of scandium to aluminium. In some embodiments, the buffer layer comprises scandium-aluminium oxide having a greater atomic ratio of scandium to aluminium than the growth surface, i.e. greater relative amount of scandium. The ratio may therefore be greater than 1:4 (e.g. greater than 1:3, or greater than 2:4). In other embodiments, the ratio of scandium may be lesser. The buffer layer may comprise two or more layers of scandium-aluminium oxide with progressively increasing or decreasing amounts of scandium to aluminium with respect to the growth surface. For example, the amount of scandium in the scandium-aluminium oxide buffer (sub-)layer(s) may increase away from the growth surface. Increasing amounts of scandium may be preferred in embodiments wherein the buffer layer comprises a first buffer sub-layer of scandium oxide on the support such that the amount of scandium progressively increases from the growth surface to the layer of scandium oxide. In other exemplary embodiments, the amount of scandium in the scandium-aluminium oxide buffer (sub-)layer(s) may decrease away from the growth surface. This may be preferred in embodiments wherein the buffer layer consists of scandium-aluminium oxide and the support is sapphire such that the amount of aluminium progressively increases from the growth surface to the aluminium oxide support (i.e. the amount of scandium progressively decreases from the growth surface to the support). As will be appreciated, the buffer layer may be formed of discrete sub-layers as described above. In other preferred embodiments, the buffer layer may comprise an essentially continuously graded composition. For example, a continuously graded composition of scandium-aluminium oxide may be used in, or as, a buffer layer. The graded composition may be linear across its thickness though other profiles may also be formed, e.g. exponential. Generally in such embodiments, the first layer will comprise what may be referred to as a second sub-layer with a thickness of at least 2 nm, consisting of the scandium-aluminium oxide (i.e. of uniform composition) which provides the growth surface. Where other buffer sub-layers are present, discrete or continuous grading of compositions may also be used. For example, based on the exemplary combination of scandium oxide on erbium oxide described above, the buffer layer may comprise a sub-layer of a continuously graded composition of scandium-erbium oxide formed essentially of erbium oxide at one surface (e.g. that on a silicon support) and essentially of scandium oxide at the opposite surface (e.g. that interfacing either a further buffer sub-layer of continuously graded scandium-aluminium oxide, or the second sub-layer providing the growth surface). Such grading of metals in semiconductors and dielectrics is well-known in the art of LED manufacture based on materials such as GaN and AIGaN on silicon wafers and equivalent techniques known in the art may be used to manufacture graded compositions of buffer layers suitable for use in the present invention. A buffer (sub-)layer having a continuously graded composition may at its opposing surfaces have a composition which is essentially identical to the layer with which the surface interfaces. In some embodiments, there may be a step in the composition at the interface of the continuously graded layer with one or both of the adjacent layers (i.e. at one or both interfaces). A step may be a difference of at least 5 at.% of the amount of the common metal of the material across the interface, preferably at least 10 at.%. Such a step may be used as an etch stop layer in subsequent device fabrication. A step change in the composition may also help to reduce propagation of dislocations during growth (i.e. as a dislocation blocking layer during fabrication of the substrate). The total thickness of a buffer layer is not particularly limited, though it is preferred for the buffer layer to be as thin as possible. For example, the buffer layer may have a thickness of up to 100 nm, preferably up to 10 nm, preferably up to 5 nm. Accordingly, the thickness of the buffer layer may range from 1 nm to 100 nm. In some embodiments, for example with a single composition of buffer layer, the thickness may be generally thinner (e.g. from 1 nm to 10 nm), whereas multiple buffer sublayers and graded compositions may require greater total thicknesses (e.g. from 10 nm to 100 nm). Thinner buffer layers are preferred since the inventors have found that such layers are typically smoother with lower surface roughness which may otherwise template into other layers growth thereon, and ultimately any graphene. Thinner layers may also be preferred where the buffer layer is formed of erbium oxide as this minimises the volume of the paramagnetic material interacting with a magnetic field which is useful for final device applications, in particular sensors. The substrate of the present invention is preferably manufactured by forming the first layer by epitaxy directly on the support. Suitable methods for epitaxy are well-known to those skilled in the art. Preferred methods of epitaxy include molecular beam epitaxy (MBE) and high temperature sputtering. Such methods typically employ high temperatures, for example, from about 500°C to about 1000°C. Epitaxy may be used to deposit any buffer layer(s) where used, and a layer of scandium-aluminium oxide. Graded (discrete and continuous) compositions may be formed by epitaxy using conventional techniques known to those skilled in the art. For example, a graded composition of scandiumaluminium oxide may be formed by epitaxy directly on a support, or a buffer sub-layer as described herein, by gradually increasing or decreasing the scandium / aluminium content during the growth process. The crystallographic orientation of the growth surface depends on how the first layer orients on the support as is known in the art. For example, the <111 >growth surface of scandium-aluminium oxide may be achieved through epitaxial growth on a <111 >surface of a silicon wafer (or a <111 >surface of a buffer layer grown thereon), or on a c-plane surface of a sapphire wafer. In a second aspect, the present invention provides a graphene laminate comprising the substrate of the first aspect of the present invention, the graphene laminate further comprising a CVD-grown graphene layer structure grown directly on the growth surface of the substrate. In a further aspect, the present invention also provides a method for the manufacture of a graphene laminate, the method comprising: (i) providing a substrate in accordance with the first aspect described herein; and (ii) forming a graphene layer structure on the growth surface of the substrate by CVD. As will be appreciated, the method of this further aspect may equally be described as a method for the manufacture of a graphene laminate in accordance with the second aspect. These further aspects of the present invention relate to CVD-grown graphene formed on the growth surface of the substrate by CVD. Forming may be considered synonymous with synthesising, manufacturing, producing, depositing and growing. Graphene is a very well-known two-dimensional material referring to an allotrope of carbon comprising a single layer of carbon atoms in a hexagonal lattice. Graphene, as used herein, refers to a graphene layer structure, preferably having from 1 to 10 monolayers of graphene. Accordingly, the present invention relates to the formation of a monolayer of graphene as well as multilayer graphene (either of which may be termed a graphene layer structure). In many subsequent applications of a graphene laminate, in particular for electronic device fabrication, one monolayer of graphene is particularly preferred. Accordingly, the graphene layer structure is preferably a graphene monolayer. Nevertheless, multilayer graphene may be preferable for certain applications and 2 or 3 layers of graphene may be preferred. As described herein, the method of forming a graphene layer structure comprises forming graphene by CVD directly onto the growth surface of the substrate formed of scandium-aluminium oxide having a <111 >crystallographic orientation and an atomic ratio of scandium to aluminium of from 2:7 to 2:9. CVD refers generally to a range of chemical vapour deposition techniques, each of which involve deposition to produce thin film materials such as two-dimensional crystalline materials like graphene. Volatile precursors, those in the gas phase or suspended in a gas, are decomposed to liberate the necessary species to form the desired material, carbon in the case of graphene. CVD as described herein is intended to refer to thermal CVD such that the formation of graphene from the decomposition of a carbon-containing precursor is the result of the thermal decomposition of said carbon-containing precursor. Preferably, the method involves forming graphene by thermal CVD such that decomposition is a result of heating the carbon-containing precursor. Preferably, the temperature of the growth surface during CVD (i.e. wafer temperature) is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C. The temperature setting input to a CVD reactor (i.e. set temperature) will generally be greater than the actual wafer temperature. The set temperature may be 100°C (or more) greater than the wafer temperature, for example from 1,300°C to 1,400°C. The wafer temperature may be measured using conventional techniques, for example using an optical probe. The inventors have found that such temperatures are particularly effective for providing graphene growth directly on a non-metallic growth surface by CVD. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-walled reaction chamber wherein a heater coupled to the substrate is the only source of heat to the chamber. In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality, or an array, of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead may be known for use in MOCVD processes. Accordingly, the method may alternatively be said to be performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm, even more preferably less than 10 mm, between the surface of the substrate and the plurality of precursor entry points. As will be appreciated, by a constant separation it is meant that the minimum separation between the surface of the substrate and each precursor entry point is substantially the same. The minimum separation refers to the smallest separation between a precursor entry point and the substrate surface (i.e. the surface of the metal oxide layer). Accordingly, such an embodiment involves a “vertical” arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the substrate surface (i.e. the growth surface). The precursor entry points into the reaction chamber are preferably cooled. The inlets, or when used, the showerhead, are preferably actively cooled by an external coolant, for example water, so as to maintain a relatively cool temperature of the precursor entry points such that the temperature of the precursor as it passes through the plurality of precursor entry points and into the reaction chamber is less than 100°C, preferably less than 50°C. For the avoidance of doubt, the addition of precursor at a temperature above ambient does not constitute heating the chamber, since it would be a drain on the temperature in the chamber and is responsible in part for establishing a temperature gradient in the chamber. Preferably, a combination of a sufficiently small separation between the substrate surface and the plurality of precursor entry points and the cooling of the precursor entry points, coupled with the heating of the substrate to with a decomposition range of the precursor, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene formation on the substrate surface. As disclosed in WO 2017 / 029470, very steep thermal gradients may be used to facilitate the formation of high-quality and uniform graphene directly on non-metallic substrates, preferably across the entire surface of the substrate. The substrate may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include an Aixtron® Close-Coupled Showerhead® reactor and a Veeco® TurboDisk reactor. Consequently, in a particularly preferred embodiment wherein the method of the present invention involves using a method as disclosed in WO 2017 / 029470, forming the graphene layer structure on the growth surface by CVD comprises: providing the growth substrate on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; cooling the inlets to less than 100°C (i.e. so as to ensure that the precursor is cool as it enters the reaction chamber); introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the substrate surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm. In another particularly preferred embodiment wherein the method involves using a method as disclosed in WO 2019 / 138231, forming the graphene layer structure on the growth surface by CVD comprises: providing the growth substrate on a heated susceptor in a reaction chamber, the reaction chamber having a plurality of inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably up to 3000 rpm; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor; wherein the constant separation is at least 12 cm, preferably up to 20 cm. The most common carbon-containing precursor in the art for graphene growth is methane (CH4). The inventors have found that it is preferable that the carbon-containing precursor used to form graphene is an organic compound, that is, a chemical compound, or molecule, that contains a carbon-hydrogen covalent bond, which comprises two or more carbon atoms. Such precursors have a lower decomposition temperature than methane which advantageously allows the growth of graphene at lower temperatures when using the method described herein which is particularly advantageous for growth on such non-metallic surfaces. Preferably, the precursor is a liquid when measured at 20°C and 1 bar of pressure (i.e. under standard conditions according to IUPAC). Accordingly, the precursor has a melting point that is below 20°C, preferably below 10°C, and has a boiling point above 20°C, preferably above 30°C. Liquid precursors are simpler to store and handle when compared to gaseous precursors which typically require high pressure cylinders. Due to their relatively reduced volatility when compared to gaseous precursors, they present a lower safety risk during large scale manufacture. Increasing the molecular weight of the compounds beyond about Cw, particularly beyond about C12, typically reduces their volatility and suitability for CVD growth of graphene on non-metallic substrates (though graphene can be produced from solid organic compounds). Preferably, the organic compound consists of carbon and hydrogen and, optionally, oxygen, nitrogen, fluorine, chlorine and / or bromine. As discussed above, the method described herein preferably uses a carbon-containing precursor that is an organic compound comprising two of more carbon atoms, i.e. a C2+ organic compound. Preferably, the carbon-containing precursor is a C3-C12 organic compound consisting of carbon and hydrogen and, optionally, oxygen, nitrogen, fluorine, chlorine and / or bromine. As described herein, a Cn organic compound refers to one comprising “n” carbon atoms and optionally one or more further hetero atoms oxygen, nitrogen, fluorine, chlorine and / or bromine. Preferably, the organic compound comprises at most one heteroatom as such organic compounds are typically more readily available in high purity, for example ethers, amines, and haloalkanes. The carbon-containing precursor is preferably a C3-C10 organic compound consisting of carbon and hydrogen and, optionally, oxygen, nitrogen, fluorine, chlorine and / or bromine, even more preferably a C6-C9 organic compound. In a preferred embodiment, the precursor does not comprise a heteroatom, such that the precursor consists of carbon and hydrogen. In other words, preferably the carbon-containing precursor is a hydrocarbon, preferably an alkane. It is also preferable that the organic compound comprise at least two methyl groups (-CH3). Particularly preferred organic compounds for use as carbon-containing precursors, and methods of forming graphene therefrom by CVD, are described in GB 2604377. The inventors have found that when forming graphene directly on non-metallic substrates, precursors beyond the traditional hydrocarbons methane and acetylene allow for the formation of even higher quality graphene. Preferably, the precursor is a C4-C10 organic compound, more preferably the organic compound is branched such that the organic compound at least three methyl groups. Without wishing to be bound by theory, the inventors believe that heavier organic compounds (i.e. those greater than C12, or greater than C10, and / or those which are solid under standard conditions) provide a “less pure” source of CH3 radicals. With an increase in size and complexity of the organic compound there is an increase in the number of decomposition pathways and the possibility of a greater range of by-products which can lead to graphene defects. The organic compounds as described herein provide a balance of being large enough to deliver the required, and a desirably high fraction of, methyl groups under pyrolysis. The organic compounds are however small enough to be simple to purify, particularly where the precursor is liquid, and have a relatively simple pyrolysis chemistry with limited decomposition pathways. Furthermore, unlike heavier compounds, they do not so readily condense within the reactor plumbing which is a particular disadvantage for the industrial production of graphene due to the greater risk of reactor downtime. The graphene laminate comprises graphene which has been formed directly on scandium-aluminium oxide as disclosed herein by CVD which therefore avoids physical transfer processing. The physical transfer of graphene, usually from copper substrates, introduces numerous defects which negatively impacts the physical and electronic properties of graphene. As such, a person skilled in the art can readily ascertain whether a graphene layer structure, and by extension a graphene substrate as described herein, is one comprising a CVD-grown graphene layer structure that has been grown directly on the specific materials using conventional techniques in the art such as atomic force microscopy (AFM), energy dispersive X-ray (EDX) spectroscopy, X-ray photoelectron spectroscopy (XPS) and preferably time-of-flight secondary ion mass spectrometry (ToF-SIMS). The graphene layer structure is devoid of copper contamination and devoid of transfer polymer residues by virtue of the complete absence of these materials in the process of obtaining the graphene substrate. Furthermore, such processing is not suitable for large scale manufacture (such as on CMOS substrates in fabrication plants). Unintentional doping, particularly from the catalytic metal substrates together with the etching solutions, also results in the production of graphene which is not sufficiently consistent from sample to sample as is required for commercial production. In accordance with a further aspect of the present invention, there is provided an electronic device comprising the graphene laminate as described herein. As will be appreciated, the graphene layer structure of the graphene laminate may be patterned using known techniques and electrical contacts may be provided so as to enable the laminate to be incorporated into an electronic device. That is, an electronic device may be manufactured from a graphene laminate thereby incorporating a graphene layer structure directly on a <111> surface of a scandium-aluminium oxide layer, said scandiumaluminium oxide layer on a support layer as described herein. Further steps for forming electronic devices are known in the art and may include patterning, such as by photolithography, laser and / or plasma etching, and / or deposition of additional layers and materials such as dielectric layers and / or metal ohmic contacts. The electronic device may be diced from an array of devices formed simultaneously from a larger graphene substrate. An electronic device comprising such a graphene laminate (i.e. comprising graphene grown directly on a first layer) may be improved over prior art devices in view of the advantageous properties afforded by the graphene, in particular an improvement in carrier mobility. Photonic devices are preferable, for example, an electro-optic modulator is one preferred electronic device which may benefit from greater carrier mobility. In particular, an electro-optic modulator comprising the graphene substrate may operate with greater bandwidth. Other preferred electronic devices include transistors (i.e. graphene transistors) such as radio frequency graphene field effect transistors (RF GFETs) which rely on high carrier mobilities to switch “on” and “off” at such high frequencies. Biosensors are also preferred electronic devices which benefit from the higher mobility of graphene due to the associated reduction in sheet resistance which reduces the power required for operation. Another particularly preferred electronic device is a Hall effect sensor. The sensitivity of such devices may be improved with higher carrier mobilities. The present invention is particularly advantageous for photonic devices due to the need to integrate graphene on silicon wafers such that a photonic device could be manufactured using the resulting graphene substrate and processed using industry-standard silicon tools. Figures The present invention will now be described further with reference to the following non-limiting Figures, in which: Figure 1 illustrates a cross section of an exemplary embodiment of a substrate according to the present invention. Figure 2 illustrates a cross section of a further exemplary embodiment of a substrate according to the present invention. Figure 3 illustrates a cross section of a further exemplary embodiment of a substrate according to the present invention. Figure 4 illustrates a cross section of an exemplary embodiment of a graphene laminate according to the present invention. Figure 1 is a cross section of an exemplary embodiment of a substrate 100 according to the present invention. The substrate 100 comprises a support 105 and a first layer 110 which consists of scandium-aluminium oxide. The upper surface 110’ of the first layer 110 provides an exposed growth surface suitable for deposition of two-dimensional materials such as graphene, the upper surface 110’ having a <111 >crystallographic orientation. The atomic ratio of scandium to aluminium at the upper surface 110’ is preferably about 2:8. In some embodiments, the first layer 110 may have a uniform composition wherein the scandium to aluminium ratio is substantially constant across the thickness of the first layer 110 from the upper surface 110’ to the lower surface 110” which interfaces the upper surface of the support. In other embodiments, the scandium to aluminium ratio may be graded across the thickness of the first layer 110. Figure 2 is a cross section of a further exemplary embodiment of a substrate 200 according to the present invention. The substrate 200 comprises a support 205 and a first layer 210 which consists of a buffer layer 215 (i.e. a first sub-layer) and a second sub-layer 220 consisting of scandium-aluminium oxide having an atomic ratio of scandium to aluminium of from 2:7 to 2:9. The second sub-layer 220 provides the upper growth surface 220’ of the substrate 200, the second sub-layer 220 having a lower surface 220” which interfaces an upper surface 215’ of the buffer layer 215. The buffer layer 215 has a lower surface 215” which interfaces the support 205. The support 205 may preferably be a silicon wafer and the buffer layer 215 may be used to alleviate the lattice mismatch between the silicon of the support 205 and the scandium-aluminium oxide of the second sub-layer 220. Scandium oxide, yttrium oxide and erbium oxide are each particularly suitable for use in buffer layer 215. This can help to reduce stress and strain in the second sub-layer and therefore at the growth surface which in turn can lead to higher quality growth of graphene. Figure 3 is a cross section of a further exemplary embodiment of a substrate 300 according to the present invention. Like substrates 100 and 200 described above, substrate 300 comprises a support 305 and a first layer 310 provided thereon. The first layer comprises a second sub-layer 320 formed of scandium-aluminium oxide on a buffer layer, wherein in substrate 300, the buffer layer is formed of at least two buffer sub-layers 315a, 315b. For example, buffer sub-layer 315a may be formed of erbium oxide and provided directly on the support 305, which is particularly suitable for silicon supports since erbium oxide has good thermodynamic stability on silicon, and buffer sub-layer 315b may be formed of scandium oxide, for example, to further minimise lattice mismatch between the erbium oxide and the scandium-aluminium oxide. In further embodiments, a further buffer sub-layer comprising scandium-aluminium oxide having a different atomic ratio to the growth surface may be provided between the support and the growth surface, in particular as the uppermost buffer sub-layer. In other embodiments, the compositions of the buffer sub-layers may be continuously graded. Figure 4 illustrates a cross section of an exemplary embodiment of a graphene laminate 400 according to the present invention. The graphene laminate 400 comprises the substrate 200 as illustrated in Figure 2, and further comprises a CVD-grown graphene monolayer 405 on and across the growth surface 220’ of substrate 220. The graphene monolayer 405 is devoid of copper contamination and devoid of transfer polymer residues by virtue of having been formed by CVD. Examples Example 1: A first layer formed of scandium-aluminium oxide was deposited on and across a <111 >surface of a silicon wafer / support epitaxially by molecular beam epitaxy (MBE) to a thickness of about 40 nm. Graphene was grown on the surface of the first layer in an MOCVD reactor, in accordance with the method disclosed in WO 2017 / 029470, by first annealing the surface in a 60 slm flow of nitrogen at 400 mbar at a set temperature of 1,150°C for 600 s. The set temperature was then increased to 1,300°C and hydrocarbon was introduced to the chamber at a super-critical flow rate to form a graphene monolayer. The wafer was then cooled to room temperature under a flow of 60 slm nitrogen at 30 mbar. Example 2: A first sub-layer formed of erbium oxide was deposited on and across a <111 >surface of a silicon wafer / support epitaxially by MBE to a thickness of about 2 nm, thereby providing a buffer layer. A second sub-layer formed of scandium-aluminium oxide was deposited on and across the first sub-layer epitaxially by MBE to a thickness of about 10 nm. The first sub-layer and second sub-layer provide a first layer on the surface of a support and a growth surface formed of scandium-aluminium oxide. Graphene was grown on the surface of second sub-layer in an MOCVD reactor, in accordance with the method disclosed in WO 2017 / 029470, by first annealing the surface in a 60 slm flow of nitrogen at 400 mbar at a set temperature of 1,150°C for 600 s. The set temperature was then increased to 1,300°C and hydrocarbon was introduced to the chamber at a super-critical flow rate to form a graphene monolayer. The wafer was then cooled to room temperature under a flow of 60 slm nitrogen at 30 mbar. In an equivalent example, yttrium oxide may be deposited in place of erbium oxide. Example 3: A first buffer sub-layer formed of erbium oxide was deposited on and across a <111 >surface of a silicon wafer / support epitaxially by MBE to a thickness of about 2 nm. A second buffer sub-layer formed of scandium oxide was deposited on and across the first buffer sub-layer epitaxially by MBE to a thickness of about 10 nm. The first buffer sub-layer and the second buffer sub-layer together provide a buffer layer (i.e. a first sub-layer). A second sub-layer of scandium-aluminium oxide was deposited on and across the second buffer sub-layer epitaxially by MBE to a thickness of about 10 nm. Graphene was grown on the surface of the second sub-layer in an MOCVD reactor, in accordance with the method disclosed in WO 2017 / 029470, by first annealing the surface in a 60 slm flow of nitrogen at 400 mbar at a set temperature of 1,150°C for 600 s. The set temperature was then increased to 1,300°C and hydrocarbon was introduced to the chamber at a super-critical flow rate to form a graphene monolayer. The wafer was then cooled to room temperature under a flow of 60 slm nitrogen at 30 mbar. As used herein, the singular form of “a”, “an” and “the” include plural references unless the context clearly dictates otherwise. The use of the term “comprising” is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to those described. In other words, the term also includes the limitations of “consisting essentially of” (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and “consisting of” (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise. It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, layers and / or portions, the elements, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, layer or portion from another, or a further, element, layer or portion. It will be understood that the term “on” is intended to mean “directly on” such that there are no intervening layers between one material being said to be “on” another material. Spatially relative terms, such as “under”, "below", "beneath", "lower", “over”, "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device as described herein is turned over, elements described as "under” or “below" other elements or features would then be oriented “over” or "above" the other elements or features. Thus, the example term "under" can encompass both an orientation of over and under. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly. The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents. For the avoidance of doubt, the entire contents of all documents acknowledged herein are incorporated herein by reference.

Claims

1. A substrate for the CVD growth of graphene, the substrate comprising a support and a first layer provided thereon, the first layer having a growth surface distal from the support, the growth surface being formed of scandium-aluminium oxide having a <111> crystallographic orientation, wherein an atomic ratio of scandium to aluminium is from 1:24 to 1:4.

2. The substrate according to claim 1, wherein the atomic ratio of scandium to aluminium is from 1:16 to 1:5.

3. The substrate according to claim 2, wherein the atomic ratio of scandium to aluminium is from 1:12 to 1:

74. The substrate according to any preceding claim, wherein the first layer has a thickness of from 5 nm to 10 pm.

5. The substrate according to any preceding claim, wherein the support is a silicon wafer.

6. The substrate according to any preceding claim, wherein the first layer comprises a first sublayer as a buffer layer between the support and the growth surface.

7. The substrate according to claim 6, wherein the first layer consists of the first sub-layer and a second sub-layer consisting of the scandium-aluminium oxide.

8. The substrate according to claim 6 or claim 7, wherein the buffer layer comprises scandium-aluminium oxide having a different atomic ratio from the growth surface.

9. The substrate according to claim 8, wherein the buffer layer comprises scandium-aluminium oxide having a greater atomic ratio of scandium to aluminium than the growth surface.

10. The substrate according to any of claims 6 to 9, wherein the buffer layer has a thickness of from 1 nm to 100 nm.

11. The substrate according to any preceding claim, wherein the first layer consists of scandium-aluminium oxide.

12. The substrate according to any of claims 6 to 10, wherein the buffer layer comprises scandium oxide, yttrium oxide and / or erbium oxide.

13. The substrate according to any of claims 1 to 5, wherein the first layer consists of the scandium-aluminium oxide having the atomic ratio.

14. A graphene laminate comprising the substrate of any of claims 1 to 13 and further comprising 5 a CVD-grown graphene layer structure grown directly on the growth surface of the substrate.

15. A graphene laminate according to claim 14, wherein the graphene layer structure is a graphene monolayer.10 16. A method for the manufacture of a graphene laminate, the method comprising:(i) providing the substrate according to any of claims 1 to 13; and(ii) forming a graphene layer structure on the growth surface of the substrate by CVD.

17. The method according to claim 16, wherein the CVD is performed at a wafer temperature of15 from 700°C to 1350°C.

18. An electronic device comprising the graphene laminate according to claim 14 or claim 15, or the graphene laminate obtained by the method according to claim 16 or claim 17.

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