Layered structure

Abstract

Layered structure comprises polycyclic aromatic hydrocarbon layer on a silicon dioxide substrate and a graphene layer on the polycyclic aromatic hydrocarbon layer. The layered structure is formed at a

Description

The invention relates to a layered structure, an electronic device and a method of fabricating a layered structure. It is known to use an intermediate adhesion layer to promote adhesion between a substrate and another layer. According to a first aspect of the invention, there is provided a layered structure comprising: a silicon dioxide substrate; a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate; and a graphene-based layer on the polycyclic aromatic hydrocarbon-based layer, wherein the layered structure is formed at an edge of the silicon dioxide substrate. It will be appreciated that the layered structure is not necessarily limited to the edge of the silicon dioxide substrate but may be formed up to and at the edge of the silicon dioxide substrate. The silicon dioxide substrate itself may be provided on another substrate or layer, such as a silicon wafer. Graphene is a two-dimensional material of sp2-bonded carbon atoms arranged in a hexagonal lattice. In the invention, any type of graphene-based material, or a combination of different types of graphene-based materials, may be used to fabricate the graphene-based layer. The graphene in the graphene-based layer may include monolayer graphene, bilayer graphene, trilayer graphene and / or few-layer graphene (<10 layers of graphene). The graphene-based layer may include pristine graphene, chemically functionalised graphene and / or a graphene derivative. The graphene-based layer may be obtained via chemical vapour deposition (CVD) or by transferring graphene from a different substrate onto the polycyclic aromatic hydrocarbon-based layer. The polycyclic aromatic hydrocarbon-based layer may be, but is not limited to, a pyrene-based layer. The graphene-based layer may stay laminated to the silicon dioxide substrate when the layered structure is subjected to mechanical breakage, a chemical solution or electrochemical conditions. The graphene-based layer may stay laminated to the silicon dioxide substrate at an edge of the silicon dioxide substrate when the layered structure is subjected to mechanical breakage, a chemical solution or electrochemical conditions. The chemical solution may be a chemical etchant. The chemical solution may be a cleaning agent. According to a second aspect of the invention, there is provided an electronic device comprising the layered structure according to any one of the first aspect of the invention and its embodiments. The electronic device may be a tunnelling device. The graphene-based layer may include or may form part of a tunnelling electrode or junction of the tunnelling device. The graphene-based layer may include or may form part of a molecular break junction of the tunnelling device. The electronic device may be an electrochemical device. The electronic device may be operable in aqueous conditions with the graphene-based layer staying laminated to the silicon dioxide substrate at an edge of the silicon dioxide substrate. According to a third aspect of the invention, there is provided a method of fabricating a layered structure, the method comprising the steps of: exposing the silicon dioxide substrate to an amino-based solution to functionalise a surface of the silicon dioxide substrate with amines; reacting the amines with a polycyclic aromatic hydrocarbon-based compound so as to form a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate; providing a graphene-based layer on the polycyclic aromatic hydrocarbon-based layer. The amino-based solution may be, but is not limited to, aminosilane. The step of exposing a silicon dioxide substrate to an amino-based solution to functionalise a surface of the silicon dioxide substrate with amines may include the step of exposing the silicon dioxide substrate to a solution of aminopropyltriethoxysilane or aminopropyl-trimethoxysilane. The step of exposing a silicon dioxide substrate to an amino-based solution to functionalise a surface of the silicon dioxide substrate with amines may include the step of immersing the silicon dioxide substrate in the amino-based solution. The polycyclic aromatic hydrocarbon-based compound may be, but is not limited to, a polycyclic aromatic hydrocarbon-based acid. The step of reacting the amines with a polycyclic aromatic hydrocarbon-based acid so as to form a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate may include reacting the amines with a pyrene-based moiety so as to form a pyrene-based layer on the silicon dioxide substrate. The polycyclic aromatic hydrocarbon-based acid may be, but is not limited to, 1-pyrenebutyric acid. The step of reacting the amines with a polycyclic aromatic hydrocarbon-based acid so as to form a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate may include reacting the amines with the polycyclic aromatic hydrocarbonbased acid using a peptide coupling reaction. The step of reacting the amines with a polycyclic aromatic hydrocarbon-based acid so as to form a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate may include reacting the amines with the polycyclic aromatic hydrocarbonbased acid using a hexafluorophosphate azabenzotriazole tetramethyl uronium-catalysed peptide coupling reaction or a l-ethyl-3-(3-dimethylaminopropyl) carbodiimide (EDC) peptide coupling reaction. The amines may be reacted with the polycyclic aromatic hydrocarbon-based acid using the hexafluorophosphate azabenzotriazole tetramethyl uronium-catalysed peptide coupling reaction in a triethylamine-basified or a 4-dimethylaminopyridine solution, preferably a triethylamine-basified dimethylformamide solution. According to a third aspect of the invention, there is provided a layered structure comprising: a silicon dioxide substrate; a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate; and a graphene-based layer on the polycyclic aromatic hydrocarbon-based layer, wherein the graphene-based layer stays laminated to the silicon dioxide substrate when the layered structure is subjected to mechanical breakage, a chemical solution or electrochemical conditions. The graphene-based layer may stay laminated to the silicon dioxide substrate at an edge of the silicon dioxide substrate when the layered structure is subjected to mechanical breakage, a chemical solution or electrochemical conditions. The chemical solution may be a chemical etchant. The chemical solution may be a cleaning agent. Within the scope of this patent application it is expressly intended that the various aspects, embodiments, examples and alternatives set out in the preceding paragraphs, and the claims and / or the following description and drawings, and in particular the individual features thereof, may be taken independently or in any combination. That is, all embodiments and all features of any embodiment can be combined in any way and / or combination, unless such features are incompatible. The applicant reserves the right to change any originally filed claim or file any new claim accordingly, including the right to amend any originally filed claim to depend from and / or incorporate any feature of any other claim although not originally claimed in that manner. Preferred embodiments of the invention will now be described, by way of non-limiting examples, with reference to the accompanying drawings in which: Figure 1A illustrates modified surfaces of a Si / SiO2 wafer; Figures IB to IF illustrate the characterisation of non-modified and modified surfaces of a Si / SiO? wafer; Figure 2A is a schematic representation of a fabrication process of GFETs and graphene-edge devices; Figure 2B is a schematic representation of a liquid-gated GFET; Figures 2D to 2F illustrate the characterisation of liquid-gated GFETs; Figure 3A is a schematic representation of a liquid-gated GFET that is subjected to sonication; Figures 3B to 3F illustrate the characterisation of liquid-gated GFETs that are subjected to sonication; Figure 4A illustrates the fabrication of graphene-edge electrodes from GFETs; Figures 4B to 4E illustrate the characterisation of the graphene-edge electrodes; Figures 5A to 5C show optical images of wafers that underwent industrial processing; Figures 5D to 5F show Raman analysis of graphene on wafers that underwent industrial processing; Figures 6 to 8 illustrate delamination levels of graphene on different wafers when immersed in chemical solutions; Figure 9 shows optical images of graphene on wafers; and Figure 10 shows current-voltage measurements of graphene on wafers. The figures are not necessarily to scale, and certain features and certain views of the figures may be shown exaggerated in scale or in schematic form in the interests of clarity and conciseness. Graphene is a material with high potential for the semiconductor industry due to high sensitivity to its environment. In particular, its 2-dimensional nature enables the production of electronic tunnelling devices by creating a single-atom contact point which increases tunnelling measurement resolution. It is envisaged that electron tunnelling could become part of a solid-state DNA sequencing device, with which individual nucleobases are identified via tunnelling current fingerprints. For an optimal nucleobase resolution, the tunnelling contacts should be atomically sharp, which can be achieved with graphene-based electrodes. However, such devices conventionally face a low success rate of electron tunnelling due to poor adhesion of the graphene layer to a silicon wafer, thereby resulting in delamination of the graphene layer at the edge of the wafer. Crucially the graphene layer should stay laminated to the wafer at the edge of the wafer to allow tunnelling current in these devices. Furthermore, the graphene layer needs to stay laminated to the wafer under harsh industrial conditions, e.g. chemical cleaning or etching of the underlying substrate. Graphene, as an aromatic carbon-based material, does not have a high intrinsic affinity for the silicon dioxide (SiOz) layer of a silicon (Si) wafer. To overcome this limitation, the inventors have created a hybrid graphene-pyrene-SiOz structure that increases the stability and integrity of the graphene layer through the increased adhesion provided by the intermediate pyrene layer. In particular, this invention enables the fabrication of stable electronic devices that prevent delamination of graphene from the edge of the electronic device and promoting graphene adhesion up to and at the edge of the electronic device. Applications of the hybrid graphene-pyrene-SiOz structures include, but are not limited to, electronic devices, tunnelling electrodes, tunnelling junctions, molecular break junctions and electrochemical devices. In other embodiments, it is envisaged that the graphene layer may be replaced by another graphene-based layer and / or that the pyrene layer may be replaced by another pyrene-based layer or another polycyclic aromatic hydrocarbon-based layer. The incorporation of the pyrene layer between the graphene layer and the SiOz substrate preserves the robustness and integrity of graphene on the SiOz substrate under harsh conditions, such as industrial processing, cleaning and surface regeneration conditions, which are required for the fabrication of reliable electronic devices. For example, it was discovered that the hybrid graphene-pyrene-SiOz structure prevents graphene delamination under conditions in which the SiOz substrate underneath the graphene would normally be expected to be etched, e.g. by immersing the structure in a highly concentrated potassium hydroxide (KOH) etching solution. Yet, the inventors found that the surface chemistry in the hybrid graphene-pyrene-SiOz structure prevents the etching solution from interacting with the silicon wafer surface, hence protecting not only the graphene layer delaminating from the SiOz surface by intercalation of the etching solution between these two layers but also the etching of the SiOz layer underneath the graphene layer which would have led to the loss of the integrity of the graphene layer. A Si wafer with a SiOz coating (Si / SiOz wafer, 285 nm thermal oxide, prime grade) was covalently functionalised with a pyrene moiety using a two-step process via silane and peptide chemistry. The pyrene moiety was attached via a flexible linker to allow it to find the optimal configuration for binding the graphene layer. This creates a strong pi-pi interaction between the Si / SiOz wafer and the graphene layer. Figure 1A illustrates the two-step process. A clean, oxygen-plasma treated Si / SiOz wafer was first chemically modified with a 5v% solution of aminopropyl-triethoxysilane (APTES) in ethanol / water (96:4) to introduce amines (NHz) at the SiOz surface. The NHz were then reacted with 1-pyrenebutyric acid using a hexafluorophosphate azabenzotriazole tetramethyl uronium (HATU)-catalysed peptide coupling reaction in a triethylamine-basified dimethylformamide (DMF) solution. Both reactions are performed at room temperature. After 3 days, the wafers were retrieved from the triethylamine-basified DMF solution. They were then cleaned by sonication in acetone, followed by a sequential solvent rinse of acetone, water and isopropanol (IPA) before being dried with pressurized nitrogen (Nz). Non-functionalised Si / SiOz wafers (referred to as BARE), as well as wafers that were functionalised with octadecyltrimethoxysilane (OTMS), hexamethyldisilazane (HMDS), APTES and phenyltriethoxysilane (PHEN), were prepared as reference wafers for comparison purposes. Figure 1A illustrates the surface modifications for the OTMS, HMDS and PHEN wafers. Furthermore, the functionalised wafers were analysed with atomic force microscopy (AFM) to obtain the roughness of the modified surfaces. Figure IB shows optical images of contact angle measurements of the pyrene-functionalised wafer (PYRENE) and the BARE, OTMS, HMDS and PHEN reference wafers, while Figure IC shows the contact angle measurements for the PYRENE, BARE, OTMS, HMDS and PHEN wafers based on a sample size of four independently modified wafers for each wafer type. Figure ID shows the baseline-subtracted X-ray photoelectron spectroscopy (XPS) spectrum for the PYRENE wafer (deconvolution of the Cis peak; CPS = counts per second), Figure IE shows the Nls peaks for the BARE, APTES and PYRENE wafers (bottom graph line = BARE, middle graph line = APTES, top graph line = PYRENE), while Figure IF shows the Cis peaks for the BARE, APTES and PYRENE wafers (bottom graph line = BARE, middle graph line = APTES, top graph line = PYRENE). Contact angle (CA) measurements revealed that the hydrophobicity of the Si wafer changed as a result of its surface chemical modification (Table 1). Following the fabrication route, starting from a hydrophilic BARE wafer, the sequential APTES- and PYRENE-functionalisation increased the contact angle after both steps to 69°. The PYRENE wafers were in the end more hydrophobic than the HMDS wafers but were less hydrophobic than the OTMS wafers. The PHEN wafers were relatively hydrophilic, possibly due to a low coverage of the wafer with the phenyl moieties or high water permeability of the upstanding phenyl layer. Atomic force microscopy (AFM) showed that the surface chemical modification altered the surface roughness of the wafers. Table 1 shows the contact angle measurement of the different wafers and Raman analysis of graphene on such wafers. Standard deviations are in brackets. Table 1 Surface CA 6c (°) Raman - peak position G (cm1) 2D (cm'1) ISO VS. Vgate Hysteresis Vdirac (mV) (mV) Bare 35 (7) 1587.8 (2.6) 2679.3 (3.4) 379(86) 14 (44) OTMS 92 (5) 1585.0 (0.3) 2678.7 (0.7) 282 (30) 12(15) APTES 49 (7) 1592.1 (2.0) 2681.1 (3.1) 303 (55) 7(12) HMDS 61 (7) 1584.4 (1.0) 2679.1 (1.0) 377 (36) 10 (12) PHEN 42 (2) 1589.1 (1.0) 2680.6 (2.4) 353 (63) 2 (9) PYRENE 69 (5) 1592.3 (0.5) 2684.5 (1.9) 379 (50) -8 (7) The XPS analysis confirmed the presence of nitrogen after the APTES reaction, and the presence of sp2 carbon atoms for the PYRENE wafers. For the PYRENE wafers, the XPS peaks of all the carbon-based bonds were identified, especially the C=C peak at 285.2 eV (which was not found in the BARE and APTES wafers) which demonstrated the presence of the pyrene moieties at the wafer surface. Notably, the peaks were upshifted as compared to reported values due to charging effects. The Nls peak appeared after the APTES functionalisation, and at the same time the Cis peak increased after the APTES functionalisation step (due to the addition of the propanol linker), while it shifted to lower values after the pyrene coupling step, indicating that sp2 carbon atoms were introduced at the SiCh surface (before the graphene layer is added). These results confirmed that the pyrene functionalisation of the Si / SiO2 wafers was successful. To study how the different surfaces modified the physical properties of the graphene layer, both Raman and (top)-gating experiments were conducted. Figure 2A is a schematic representation of the fabrication process of graphene field effect transistors (GFETs) and graphene-edge devices. Figure 2B is a schematic representation of a liquid-gated GFET. Figure 2C shows the Raman spectra zoomed in at a 2D peak area of the graphene layer. Figure 2D is a statistical analysis of the 2D peak position for the graphene layer (4 unique samples per data point). Figure 2E shows the source-drain current Isd plotted against the gate voltage Vgate for the liquidgated GFETs (0.1M LiCI04). Vgate was swept 10 times between OV and 0.6V at a rate of O.OIVs \ with the 10th cycle displayed in the plot of Figure 2E. Figure 2F shows a statistical analysis of the Dirac point of the GFETs (at the 10th gating cycle), both during a forward sweep (left column) and a backward sweep (right column). Graphene (grown on a Cu film by chemical vapor deposition) was transferred to the modified wafers using PMMA-assisted transfer. For the gating experiments, graphene field-effect transistors (GFETs) were fabricated on the modified wafers (Figure 2A). Through protection of the gold (Au) electrodes, these GFETs were made suitable for liquid gating (Figure 2B). Notably, the GFETs could later be used to create grapheneedge devices by simply breaking the wafer between the source and drain electrodes. Raman analysis of the graphene layers (Aex = 532 nm, 2.30 mW) was performed after the PMMA was removed from the graphene layer by immersing the samples in acetone followed by a solvent rinse (acetone-water-IPA) and drying with pressurized N2. On all graphene samples, the common peaks indicative of the presence of graphene (i.e. the 2D, G, and occasionally the damage-indicating D peak) were present. Focussing on the 2D peak indicative of graphene, a red-shift of the peak is obvious for graphene on the PYRENE wafer (Figure 2C), from 2679 cm 1 to 2681 cm4 to 2685 cm4, progressing along the fabrication route from BARE to APTES to PYRENE. No such shift is observed for graphene on the BARE, OTMS or HMDS wafers. The effect of the different surface modifications on the electronic properties from a study with liquid-gated GFETs was less obvious. In such gating experiments, the presence of (surface) charges near the graphene are reflected by a positive Dirac point (Vdirac), indicating that the graphene layer is doped by these charges. Molecular layers can shield these charges, shifting the Dirac point towards neutrality. The inventors hypothesised that the presence of the pyrene layer between the SiO? surface and the graphene layer would shield the graphene layer, as is the case for example for OTMS-modified surfaces. While the shielding effect of OTMS was indeed confirmed (Vdirac = 0.28 V), a similar effect was not observed for the PYRENE wafers (Figures 2E and F), as the Dirac point was the same as for the unmodified surfaces (Vdirac = 0.38 V for both PYRENE and BARE). Possibly, the pyrene moieties were lying flat between the SiO? and graphene layers, thus limiting the distance between the two layers and hence the shielding effect. The weak shielding by the small molecules HMDS and PHEN (Vdirac = 0.38 V and 0.35 V respectively) seems to be in agreement with this distance theory. However the relatively strong shielding effect from the APTES wafer (Vdirac = 0.30 V) contradicts this distance theory. Figure 3A is a schematic representation of a liquid-gated GFET that is subjected to sonication. The liquid gating was performed during intervals between consecutive sonications. Figure 3B illustrates the number of devices that survive the sonication step. A survived device is one that still has a measurable conduction. Figure 3C illustrates a relative change of resistance at the Dirac point with respective to sonication time. The relative resistance at the Dirac point before sonication is set to 1. Figure 3D illustrates the change in Dirac point (Vdirac,forward) with respect to sonication time. Figure 3E illustrates the change in device hysteresis (Vdirac,forward-Vdirac,backward) with respect to sonication time. Figure 3F illustrates the change in the maximum of dlso / dVgate (relative to dlso / dVgate att = 0 min) during sonication. This value represents the electron mobility. Liquid gating was performed using 0.1M LiCI04, Vgate was swept 10 times between 0 and 0.6V at O.OIVs-1, and the data of the 10th cycle was used to construct the plots. When the devices were sonicated to study the durability of graphene via liquid gating of GFETs (Figure 3A), the effect of the pyrene layer in the PYRENE wafer was more obvious. Here, sonication was done stepwise to follow the electronic properties of the devices as the sonication time increased. The GFETs of the PYRENE wafer showed the highest stability under sonication. The GFETs of the PYRENE wafer remained intact, while in the other modified wafers at least one out of four GFETs lost electrical contact between the Au electrodes (Figure 3B). For all devices, the Dirac point increased in the first few minutes of sonication. For the GFETs of the APTES and PYRENE wafers the resistance at the Dirac point (Rmax) did not increase significantly, while for all of the other wafer types the value of Rmax increased significantly in a relatively short sonication period (<5 min, Figure 3C). After this initial increase, the behaviour starts to vary between the different wafer types. While Voirac dropped after increased sonication for the OTMS wafer (as well as for the BARE wafer due to only one device surviving), Voirac stabilised for the other wafer types after 10 minutes to values that are typically higher than the initial Dirac points (Figure 3D). The inventors also analysed the Dirac point hysteresis (Vdirac, forward - Vdirac,backward) of the GFETs. Hysteretic behaviour occurs due to charge transfer or trapping (e.g. at the graphene / oxide interface or at defect sites / dangling bonds in graphene), or due to the slow rearrangement of polar species near graphene, which can be impurities. Ideally, a GFET does not show hysteresis, i.e. the device is not hindered by the trapping or dipole rearrangements events and the electronic readout is not influenced by these processes. The devices on the BARE, OTMS, APTES and HMDS wafers showed Dirac point hysteresis right after fabrication, and this increased rapidly as they were sonicated (Figure 3E). This increase could be due to the formation of damages in graphene that can act as charge trapping sites, for example dangling bonds, or the capture of charged species underneath the graphene. For the APTES and OTMS wafers, the initially increased hysteretic behaviour decreases slowly as sonication progresses, which may indicate that polar species (e.g. impurities) are being removed from the graphene surface during sonication. Interestingly, the PHEN and PYRENE wafers' devices were practically hysteresis-free from the start, and remained hysteresis-free during the full sonication trajectory. This indicates that, for these devices, the graphene was shielded from charge trapping to the bulk oxide due to the organic layer, and no charge trapping sites were produced or polar species captured during sonication due to the surface-induced stability of the graphene layer. The inventors analysed the change of maximum of the slope (dl / dV) from the liquid gating curves, which is directly related to the electron mobility in graphene (Figure 3F). In most cases, the slope decreased quickly as sonication was applied. Yet for the APTES wafer, the slope did not decrease at all, and for the PYRENE wafer the slope increased. Sonication thus has a strong but surface dependent effect on the carrier mobility of graphene, and surface modifications are capable of preserving this mobility. Table 2 shows liquid gating results for GFETs constructed on the different wafers, and for GFETs after sonication (t=20 min). Standard deviations are in brackets. dI / dVt=2o values are reported relative to AdI / dVt=o. Different sets of GFETs were used for the graphene characterization and sonication experiments. Table 2 Surface Isd vs. Vgate- sonication Survival Vdirac, (mV) Hystersis (mV) ARmax AdI / dVt=2o, rel. Dt=O nt=2o 0 min 20 min 0 min 20 min Rt=20 / Rt=o min max Bare 4 1 336 (54) 309 (-) 8 (8) 37 (-) 2.38 (-) 0.33 (-) 0.36 (-) OTS 4 3 286 (53) 241 (84) 12 (3) 22 (15) 3.80 (2.6) 0.39 (0.44) 0.32 (0.45) APTES 4 3 272 (73) 312 (53) 11 (11) 7 (7) 1.19 (0.4) 1.02 (0.68) 1.01 (0.55) HMDS 4 3 333(24) 342 (17) 19 (7) 35 (11) 2.66 (1.2) 0.41 (0.17) 0.38 (0.17) PHEN 4 3 319 (96) 283 (21) 0 (7) 2 (1) 3.03 (3.8) 0.75 (0.69) 0.61 (0.47) PYRENE 4 4 279 (38) 330 (20) 0(2) 2 (16) 1.01 (0.2) 1.36 (0.57) 1.18 (0.23 The adhesion effect of the pyrene layer helped to maintain GFET performance in terms of preserving graphene quality and charge dissipation speed. This is seen in the device survival, unchanged sheet resistance, Dirac point stabilization, hysteresis-free behaviour and increasing carrier mobility of the GFETs on the PYRENE wafers. Figure 4A illustrates the fabrication of graphene-edge electrodes from GFETs by breaking the wafer. Figure 4B shows SEM images of the graphene edges after PMMA removal (scale bar = 4 pm). The graphene layer shows up as grey, the SiCh layer shows up as light grey, and the Si layer shows up as black. Due to limited visibility the delamination on the PYRENE sample is indicated with an arrow. Figure 4C is a schematic representation of an electrochemical edge current measurement using a graphene edge as the source electrode and using an Ag / AgCI electrode as the drain electrode. Figure 4D shows the graphene edge amperometry in current per mm on different wafers in 0.1M LiCI04. The graphene edge voltage Vedge is varied between 0.2 and -0.2V with 0.01V steps, over 10 cycles, and the average value is displayed in the plot. Figure 4E shows a slope of linear fit on I / V cycles vs. contact angle. Graphene delamination at the edge of a wafer was studied because it is critical for tunnelling current devices that the graphene layer does not delaminate from the edge of the wafer. Edge samples were created by breaking the GFETs in-between the Au electrodes (Figure 4A). As the silicon wafer is single-crystalline in nature, the breaks created in the wafer are typically atomically sharp. This is ideal for an electron tunnelling application because the breaks in the wafer are also expected to create atomically sharp edges in the graphene layer assuming no edge delamination. The adhesion of graphene at the wafer edge in respect of the different modified surfaces was evaluated with scanning electron microscopy (SEM) and amperometry. First, SEM was used to inspect the graphene layer at the edge of the wafer in detail (the PMMA layer was removed prior to SEM analysis). The graphene layer clearly delaminated at the edge (shown as light-grey areas) for all wafer types except for the PYRENE wafer (Figure 4B). The graphene delamination is quantified based on the images by dividing the area of delaminated graphene by the total image area. The graphene delamination was then expressed as a percentage of the total image area. The quantification results show that virtually no delamination occurred for graphene on the PYRENE wafers (1%), while for the other wafers delamination of graphene was always present. Notably, graphene on the BARE wafer delaminated the most (35%), especially from the wafer edge as shown in Figure 4B. It is therefore apparent that delamination is a probable cause for the tunnelling reproducibility issues. Second, amperometry was used to examine graphene delamination in aqueous conditions (Figure 4C). The graphene layer in this case was still covered with PMMA, which means that the basal plane of the graphene layer does not contact the electrolyte solution (0.1M Na2SO4). It is only the edge of the graphene layer that contacts the electrolyte solution. It was originally hypothesised that, if no delamination occurs, a very small current (pA range, between -0.2V and 0.2V) is expected due to the 1-dimensional nature of the graphene edge which acts as a current-carrying electrode, while for delaminated graphene the current is expected to be higher due to the now exposed basal plane. For all wafer types, the measured current stayed in the pA range. Yet, interestingly, the measurements showed relatively large capacitive current cycles for the hydrophilic surfaces, i.e. BARE, APTES and PHEN, as compared to the hydrophobic surfaces HMDS, OTMS and PYRENE (Figure 4D). A linear fitting was done on these cycles, of which the slope is an indicator of the edge I / V characteristics. These values, plotted against contact angle, demonstrated a clear relation between edge current and hydrophobicity of the wafer surface (Figure 4E). The PYRENE wafer has the lowest value of all, which can be explained by the improved adhesion: based on the contact angle the current should be higher than OTMS, yet water intercalation is prevented as the graphene layer is strongly attached to the Si / SiO2 wafer. These results suggest that water intercalation between the Si / SiO2 wafer and the graphene layer plays an important role in delamination of graphene in aqueous conditions. Overall, the pyrene layer prevents delamination of the graphene layer both in air and in aqueous conditions. It was also examined whether the wafer functionalisation would perform similarly at larger (industrial) scales. Figures 5A to 5C show optical images of BARE, OTMS and PYRENE wafers. Figures 5D to 5F show Raman analysis of graphene on BARE, OTMS and PYRENE wafers. The plots show 2D vs. G peak position of graphene on the wafers, while the vectors under the plots show the deconvolution of an average point into the strain (red) and doping (blue) components of the vector. 4" full Si / SiOz wafers were chemically modified with the pyrene layer and then coated with graphene via dry transfer, using an industry-integrated process. For comparison, graphene was transferred on BARE and OTMS-modified wafers as well. Contact angle measurements and AFM inspection of the wafers prior to dry transfer of the graphene showed that the modifications were successfully applied. After the dry transfer of the graphene, the graphene layers were inspected with optical microscopy and Raman spectroscopy mapping (Figures 5A and 5D = BARE wafer, Figures 5B and 5E = OTMS wafer, Figures 5C and 5F = PYRENE wafer). Remarkably, the effect of the surface modification was directly visible. For the BARE wafer (Figure 5A) and the PYRENE wafer (Figure 5C), the graphene was intact at the surface (99% coverage for both), but for the OTMS-modified wafer (Figure 5B) the graphene was badly damaged, i.e. ripped and in parts not transferred at all, during transfer (94% coverage). Plotting the 2D peak against the G peak position from a wafer-scale Raman analysis gives information about the strain and doping of the graphene. While graphene on the BARE wafer on average is clearly tensile-strained and doped (Figure 5D), the strain was reduced to near-zero and the doping was reduced for the OTMS wafer (Figure 5E), and even more so for the PYRENE wafer (Figure 5F). The standard deviation in the strain direction, i.e. the spread of the points in the direction of the doping vector component, was small for graphene on the PYRENE wafers as compared to the BARE wafers. Although the OTMS wafers seem to have a low base spread as well, many of the points have scattered away from the base cloud, likely as a result of a non-homogeneous graphene layer that has, e.g., folds and ripples. The PYRENE wafer was thus the only one among the BARE, OTMS and PYRENE wafers that enables strain free (on average) and charge-shielded graphene with high coverage and quality on the wafer scale. The inventors also evaluated whether the graphene, produced in an industrial way, could survive in chemical solutions that are commonly used in industrial chip processing. After dicing the wafers into 1 cm by 1 cm chips, these chips were immersed in 0.5M KOH, glacial acetic acid and N-methyl pyrrolidine, solvents that are commonly used for silicon etching and cleaning. It was evident that the surface modifications helped to preserve the graphene quality, as the graphene delaminated much slower for the OTMS wafers or hardly at all for the PYRENE wafers as compared to the BARE wafers. For example, while the graphene on the BARE wafers is completely removed after 30 minutes in KOH, the graphene on the PYRENE wafers was only slightly damaged after being immersed for 12 hours (Figure 6). Similarly for acetic acid, the graphene on the BARE wafers was removed relatively quickly in acetic acid, albeit slower than for KOH, while the graphene on the OTMS and PYRENE wafers remained fully intact (Figure 7). When immersed overnight in NMP, the graphene was only found to be stable on the PYRENE wafers; the graphene was completely removed from the BARE wafers, while the graphene on the OTMS wafers had mostly rolled up on itself, forming scrolls (Figure 8). Overall, the surface modifications help to preserve the graphene quality, with the highest quality observed for the PYRENE wafers (also taking into account that the graphene on the OTMS wafers was already heavily damaged after transfer). Table 3 shows the characterisation of full wafer-scale graphene on the BARE, OTMS and PYRENE wafers. Standard deviations are in brackets. Delamination values tabulated for 12 hours in 0.5M KOH, 12 hours in glacial acetic acid (AA), and 18 hours in pure NMP. Table 3 Surface Raman - peak position IsD VS. Vgate Delamination - area exposed G (cm4) 2D (cm4) Vdirac (mV) Hysteresis (mV) KOH (%) AA (%) NMP (%) Bare 1587.7 (1.8) 2672.2 (3.3) 100 (0) 70 (41) 97 (3) OTS 1590.0 (1.9) 2683.2 (3.8) n.a. n.a. 35 (19) 18 (16) 78 (18) PYRENE 1588.1 (1.7) 2681.7 (3.3) 2 (2) 1 (0) 1 (1) Figure 6 shows visually enhanced optical images of graphene on BARE, OTMS and PYRENE wafers before and after immersion in 0.5M KOH at room temperature. Figure 6A shows the BARE wafer before immersion, while Figure 6B shows the BARE wafer after a 12 hour immersion. Figure 6C shows the OTMS wafer before immersion, while Figure 6D shows the OTMS wafer after a 12 hour immersion. Figure 6E shows the PYRENE wafer before immersion, while Figure 6F shows the PYRENE wafer after a 12 hour immersion. Figure 6G shows the delamination over time for the samples (top graph line = BARE, middle graph line = OTMS, bottom graph line = PYRENE). Samples were optically inspected (three samples for each wafer type, four photos per sample). Delamination was determined as the percentage of area exposed in the center of the image (a circle with 0 = 150 pm). Figure 7 shows visually enhanced optical images of graphene on BARE, OTMS and PYRENE wafers before and after immersion in glacial acetic acid at room temperature. Figure 7A shows the BARE wafer before immersion, while Figure 7B shows the BARE wafer after a 12 hour immersion. Figure 7C shows the OTMS wafer before immersion, while Figure 7D shows the OTMS wafer after a 12 hour immersion. Figure 7E shows the PYRENE wafer before immersion, while Figure 7F shows the PYRENE wafer after a 12 hour immersion. Figure 7G shows the delamination over time for the samples (top graph line = BARE, middle graph line = OTMS, bottom graph line = PYRENE). Samples were optically inspected (three samples for each wafer type, four photos per sample). Delamination was determined as the percentage of area exposed in the center of the image (a circle with 0 = 150 pm). Figure 8 shows visually enhanced optical images of graphene on BARE, OTMS and PYRENE wafers before and after immersion in NMP at room temperature. Figure 8A shows the BARE wafer before immersion, while Figure 8B shows the BARE wafer after a 12 hour immersion. Figure 8C shows the OTMS wafer before immersion, while Figure 8D shows the OTMS wafer after a 12 hour immersion. Figure 8E shows the PYRENE wafer before immersion, while Figure 8F shows the PYRENE wafer after a 12 hour immersion. Figure 8G shows the delamination over time for the samples (top graph line = BARE, middle graph line = OTMS, bottom graph line = PYRENE). Samples were optically inspected (three samples for each wafer type, four photos per sample). Delamination was determined as the percentage of area exposed in the center of the image (a circle with 0 = 150 pm). The inventors also evaluated the stability of graphene on modified surfaces vs. bare surfaces under electrochemical conditions (Figures 9 and 10). Performing 100+ cycles was clearly damaging the graphene when it is on the BARE wafer. On the other hand, on PYRENE wafers, no damage was observed to the graphene layer after 150 cycles. The pyrene layer thus enables the use of graphene in the hybrid graphene-pyrene-SiOz in electrochemical conditions. Figures 9A to 9C show optical images of graphene on BARE wafers. Figure 9A shows the graphene before electrochemical measurement, Figure 9B shows the graphene after 100 cycles, and Figure 9C shows the graphene after 150 cycles where major delamination of the graphene was observed. Figures 9D to 9F show optical images of graphene on PYRENE wafers. Figure 9D shows the graphene before electrochemical measurement, Figure 9E shows the graphene after 100 cycles, and Figure 9F shows the graphene after 150 cycles where no change in the state of the graphene was observed. The scale bar is 250 pm. Figure 10A shows a current-voltage measurement of the graphene on the BARE wafer, while Figure 10B shows a current-voltage measurement of the graphene on the PYRENE wafer. For each current-voltage measurement, 150 scans were measured. The electrode size was 3.0 mm x 3.5 mm. Measurements were performed in Milli-Q (0.10 5 M Na2SO4). The listing or discussion of an apparently prior-published document or apparently prior-published information in this specification should not necessarily be taken as an acknowledgement that the document or information is part of the state of the art or is 10 common general knowledge. Preferences and options for a given aspect, feature or parameter of the invention should, unless the context indicates otherwise, be regarded as having been disclosed in combination with any and all preferences and options for all other aspects, features 15 and parameters of the invention.

Claims

1. A layered structure comprising: a silicon dioxide substrate; a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate; and a graphene-based layer on the polycyclic aromatic hydrocarbon-based layer, wherein the layered structure is formed at an edge of the silicon dioxide substrate.

2. A layered structure according to Claim 1 wherein the polycyclic aromatic hydrocarbon-based layer is a pyrene-based layer.

3. A layered structure according to any one of the preceding claims wherein the graphene-based layer stays laminated to the silicon dioxide substrate when the layered structure is subjected to mechanical breakage, a chemical solution or electrochemical conditions.

4. A layered structure according to Claim 3 wherein the graphene-based layer stays laminated to the silicon dioxide substrate at an edge of the silicon dioxide substrate when the layered structure is subjected to mechanical breakage, a chemical solution or electrochemical conditions.

5. A layered structure according to Claim 3 or Claim 4 wherein the chemical solution is a chemical etchant.

6. A layered structure according to any one of Claims 3 to 5 wherein the chemical solution is a cleaning agent.

7. An electronic device comprising the layered structure according to any one of the preceding claims.

8. An electronic device according to Claim 7 wherein the electronic device is a tunnelling device, and wherein the graphene-based layer includes or forms part of a tunnelling electrode or junction of the tunnelling device.

9. An electronic device according to Claim 8 wherein the graphene-based layer includes or forms part of a molecular break junction of the tunnelling device.

10. An electronic device according to any one of Claims 7 to 9 wherein the electronic device is an electrochemical device.

11. An electronic device according to any one of Claims 7 to 10 wherein the electronic device is operable in aqueous conditions with the graphene-based layer staying laminated to the silicon dioxide substrate at an edge of the silicon dioxide substrate.

12. A method of fabricating a layered structure, the method comprising the steps of:exposing a silicon dioxide substrate to an amino-based solution to functionalise a surface of the silicon dioxide substrate with amines;reacting the amines with a polycyclic aromatic hydrocarbon-based compound so as to form a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate;providing a graphene-based layer on the polycyclic aromatic hydrocarbon-based layer.

13. A method according to Claim 12 wherein the amino-based solution is aminosilane.

14. A method according to Claim 12 or Claim 13 wherein the step of exposing a silicon dioxide substrate to an amino-based solution to functionalise a surface of the silicon dioxide substrate with amines includes the step of exposing the silicon dioxide substrate to a solution of aminopropyl-triethoxysilane or aminopropyltrimethoxysilane.

15. A method according to any one of Claims 12 to 14 wherein the step of exposing a silicon dioxide substrate to an amino-based solution to functionalise a surface of the silicon dioxide substrate with amines includes the step of immersing the silicon dioxide substrate in the amino-based solution.

16. A method according to any one of Claims 12 to 15 wherein the polycyclic aromatic hydrocarbon-based compound is a polycyclic aromatic hydrocarbon-based acid.

17. A method according to any one of Claims 12 to 16 wherein the step of reacting the amines with a polycyclic aromatic hydrocarbon-based compound so as to form a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate includesreacting the amines with a pyrene-based moiety so as to form a pyrene-based layer on the silicon dioxide substrate.

18. A method according to Claim 17 wherein the polycyclic aromatic hydrocarbonbased compound is 1-pyrenebutyric acid.

19. A method according to any one of Claims 12 to 18 wherein the step of reacting the amines with a polycyclic aromatic hydrocarbon-based compound so as to form a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate includes reacting the amines with the polycyclic aromatic hydrocarbon-based compound using a peptide coupling reaction.

20. A method according to any one of Claims 12 to 19 wherein the step of reacting the amines with a polycyclic aromatic hydrocarbon-based compound so as to form a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate includes reacting the amines with the polycyclic aromatic hydrocarbon-based compound using a hexafluorophosphate azabenzotriazole tetramethyl uronium-catalysed peptide coupling reaction or a l-ethyl-3-(3-dimethylaminopropyl)carbodiimide peptide coupling reaction.

21. A method according to Clam 20 wherein the amines are reacted with the polycyclic aromatic hydrocarbon-based compound using the hexafluorophosphate azabenzotriazole tetramethyl uronium-catalysed peptide coupling reaction in a triethylamine-basified or a 4-dimethylaminopyridine solution.

22. A layered structure comprising: a silicon dioxide substrate; a polycyclic aromatic hydrocarbon-based layer on the silicon dioxide substrate; and a graphene-based layer on the polycyclic aromatic hydrocarbon-based layer, wherein the graphene-based layer stays laminated to the silicon dioxide substrate when the layered structure is subjected to mechanical breakage, a chemical solution or electrochemical conditions.

23. A layered structure according to Claim 22 wherein the graphene-based layer stays laminated to the silicon dioxide substrate at an edge of the silicon dioxide substrate when the layered structure is subjected to mechanical breakage, a chemical solution or electrochemical conditions.

24. A layered structure according to Claim 22 or Claim 23 wherein the chemical solution is a chemical etchant.

25. A layered structure according to any one of Claims 22 to 24 wherein the chemical solution is a cleaning agent.

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