Display substrate and display apparatus

Abstract

Provided are a display substrate and a display apparatus. The display substrate comprises a substrate (10), and a plurality of sub-pixels (20) and a plurality of power source signal lines (30), which are located on the substrate (10). The plurality of sub-pixels (20) are arranged in a plurality of rows and columns, the size of each sub-pixel (20) in a row direction is a first size (d1), the size of each sub-pixel (20) in a column direction is a second size (d2), and the first size (d1) is greater than the second size (d2); and each sub-pixel (20) comprises a first electrode (21) and a second electrode (22), which are arranged opposite each other, and liquid crystal molecules, which are located between the first electrode (21) and the second electrode (22). The plurality of power source signal lines (30) extend in the column direction (Y); and two adjacent first electrodes (21) in the row direction (X) are connected by means of a power source signal line (30), and two adjacent first electrodes (21) in the column direction (Y) are connected by means of a power source signal line (30). The display apparatus comprises a display substrate.

Description

[0001] The present disclosure relates to the field of display technologies, and in particular, relates to a display substrate and a display device. BACKGROUND

[0002] With the continuous development of display technology, display devices such as mobile phones, laptops, televisions, and the like have become necessities in people's work and daily life. Liquid crystal display (LCD) devices have become the mainstream display devices due to their advantages such as high brightness, vivid colors, and large viewing angles. Currently, LCD devices have the problem of low pixel aperture ratio. SUMMARY

[0003] The present disclosure provides a display substrate and a display device.

[0004] In a first aspect of embodiments of the present disclosure, a display substrate is provided. The display substrate includes: a substrate; a plurality of sub-pixels arranged in a plurality of rows and columns on the substrate, wherein for each of the plurality of sub-pixels, the sub-pixel has a first size in a row direction and a second size in a column direction, the first size being greater than the second size; and the sub-pixel includes a first electrode and a second electrode disposed opposite to each other, and liquid crystal molecules disposed between the first electrode and the second electrode; and a plurality of power signal lines extending along the column direction, wherein two first electrodes adjacent in the row direction are connected through one of the power signal lines, and two first electrodes adjacent in the column direction are connected through one of the power signal lines.

[0005] In one embodiment, for two second electrodes connected to a same power signal line and adjacent in the row direction, in the row direction, a distance from one of the two second electrodes to a portion of the power signal line extending along the column direction is a first distance, and a distance from another of the two second electrodes to the portion of the power signal line extending along the column direction is a second distance, the first distance being different from the second distance.

[0006] In one embodiment, each of the power signal lines includes a first sub-signal line and a second sub-signal line arranged alternately, wherein a size of the first sub-signal line in the column direction is larger than a size of the second sub-signal line in the column direction.

[0007] In one embodiment, the second sub-signal line extends along the column direction; and for two second electrodes adjacent in the column direction and disposed on both sides of a center of the second sub-signal line, a distance from one of the two second electrodes to the center of the second sub-signal line is equal to a distance from another of the two second electrodes to the center of the second sub-signal line.

[0008] In one embodiment, the display substrate further includes a first signal line extending along the row direction, wherein the second sub-signal line extends along the column direction, an orthographic projection of the second sub-signal line on the substrate overlaps with an orthographic projection of one first signal line on the substrate; and opposite ends of the second sub-signal line are connected to the first sub-signal line, and orthographic projections of the opposite ends of the second sub-signal line on the substrate are located on opposite sides of the orthographic projection of the first signal line on the substrate.

[0009] In one embodiment, the first sub-signal line includes a first segment, a second segment, and a third segment connected in sequence, wherein the first segment extends along the row direction, the second segment extends along the column direction, and the third segment and the first segment are disposed on opposite sides of the second segment; and an end portion of the first segment distal from the second segment and an end portion of the third segment distal from the second segment are connected to the second sub-signal line.

[0010] In one embodiment, for two second electrodes connected to a same power signal line and adjacent in the row direction, a distance from one of the two second electrodes to the second segment is different from a distance from another of the two second electrodes to the second segment in the row direction.

[0011] In one embodiment, for two second electrodes connected to a same power signal line and adjacent in the column direction, a distance from one of the two second electrodes to the second segment is different from a distance from another of the two second electrodes to the second segment in the row direction.

[0012] In one embodiment, the first sub-signal line includes a fourth segment and a fifth segment that are connected, wherein the fourth segment extends along the row direction, the fifth segment extends along the column direction, and an end portion of the fourth segment distal from the fifth segment and an end portion of the fifth segment distal from the fourth segment are connected to the second sub-signal line.

[0013] In one embodiment, for two second electrodes connected to a same power signal line and adjacent in the row direction, a distance from one of the two second electrodes to the fifth segment is different from a distance from another of the two second electrodes to the fifth segment in the row direction.

[0014] In one embodiment, for two sub-pixels connected to a same power signal line and adjacent in the column direction, a distance from one of the two second electrodes to the fifth segment is different from a distance from another of the two second electrodes to the fifth segment in the row direction.

[0015] In one embodiment, the first sub-signal line includes a sixth segment and a seventh segment that are connected, wherein the sixth segment extends along the row direction and is disposed on a side of the seventh segment, and the seventh segment extends along the column direction; and opposite ends of the seventh segment are connected to the second sub-signal line.

[0016] In one embodiment, for two second electrodes connected to a same power signal line and adjacent in the row direction, a distance from one of the two second electrodes to the seventh segment is different from a distance from another of the two second electrodes to the seventh segment in the row direction.

[0017] In one embodiment, the display substrate includes a first metal conductive layer and a second metal conductive layer disposed on a side of the first metal conductive layer distal from the substrate, wherein the first sub-signal line is disposed in the first metal conductive layer, and the second sub-signal line is disposed in the second metal conductive layer.

[0018] In one embodiment, the display substrate further includes an insulating layer disposed between the first metal conductive layer and the second metal conductive layer, wherein the insulating layer is provided with a via hole, and the first sub-signal line and the second subsignal line are connected through the via hole; and the display substrate further includes a light shading layer disposed on a side of the sub-pixels distal from the substrate, wherein the lightshading layer is provided with a plurality of openings, an orthographic projection of one of openings on the substrate falls within an orthographic projection of one of the second electrodes on the substrate, an orthographic projection of the via hole on the substrate falls in an edge region of the orthographic projection of the second electrode on the substrate and falls within an orthographic projection of the light-shading layer on the substrate.

[0019] In one embodiment, the first electrode overlaps with the first sub-signal line, or, the first electrode overlaps with the second sub-signal line.

[0020] In one embodiment, the display substrate includes a first metal conductive layer and a second metal conductive layer disposed on a side of the first metal conductive layer distal from the substrate, and each of the power signal lines includes a first portion extending along the column direction and a second portion extending along the row direction, wherein the first portion is disposed in the second metal conductive layer, the second portion is disposed in the first metal conductive layer or in a same layer with the first electrode, two adjacent first electrodes disposed in a same row are connected through the second portion, and the second portion is disposed between the second metal conductive layer and the substrate; and the display substrate further includes an insulating layer disposed between the second portion and the second metal conductive layer, wherein the insulating layer is provided with a via hole, and the first portion is connected to the second portion through the via hole.

[0021] In one embodiment, the display substrate further includes a plurality of first signal lines extending along the row direction and a plurality of second signal lines extending along the column direction, wherein an orthographic projection of each of the second signal lines on the substrate is located between orthographic projections of two adjacent columns of the subpixels on the substrate.

[0022] In one embodiment, the display substrate further includes a plurality of spacers; wherein at least two sides of an orthographic projection of each of the spacers on the substrate are surrounded by an orthographic projection of one of the power signal lines on the substrate, and a plurality of spacers disposed between two adjacent columns of sub-pixels are distributed on both side of the power signal line; or, each of the power signal lines includes a portion extending along the column direction, wherein orthographic projections of a plurality of spacers located between two adjacent columns of sub-pixels on the substrate is located on a same side as an orthographic projection of an adjacent portion extending along the column direction; or, the spacers are disposed on a side of the power signal lines distal from the substrate, and orthographic projection of each of the spacers overlaps with an orthographic projection of one of the power signal lines on the substrate.

[0023] In one embodiment, the display substrate further includes a pixel driving circuit including a driver transistor; wherein orthographic projections of two driver transistors adjacent in the column direction on the substrate are located on opposite sides of an orthographic projection of one of the power signal lines on the substrate, or, orthographic projections of two driver transistors adjacent in the column direction on the substrate are located on a same side of an orthographic projection of one of the power signal lines on the substrate.

[0024] In one embodiment, the display substrate includes a display region and a bezel region, wherein the sub-pixels are disposed in the display region; the display substrate further includes a wire disposed in the bezel region, wherein the wire is electrically connected to the power signal lines and a driver chip; and the display substrate further includes a metal conductive layer, wherein the wire is disposed in the metal conductive layer.

[0025] In one embodiment, the display substrate further includes a light-shading layer disposed on a side of the sub-pixels distal from the substrate, wherein the light-shading layer is provided with a plurality of openings, an orthographic projection of one of openings on the substrate falls within an orthographic projection of one of the second electrodes on the substrate; and the display substrate further includes a plurality of first signal lines extending along the row direction; each of the power signal lines includes a segment disposed between two openings adjacent in the row direction and extending along the column direction, wherein a minimum distance between an edge of an orthographic projection of the segment extending along the column direction on the substrate and an edge of an orthographic projection of an adjacent opening on the substrate ranges from 4 pm ~ 8 pm; and / or the first electrode is disposed on a side of the first signal lines distal from the substrate, and the display substrate further includes an insulating layer disposed between the first signal line and the first electrode; and in the columnar direction, a distance between an edge of an orthographic projection of each of the first signal lines on the substrate and an edge of an orthographic projection of the second electrode on the substrate ranges from 3 jam- 5 gm; and / or, an orthographic projection of each of the first signal lines on the substrate falls within an orthographic projection of the lightshading layer on the substrate, wherein a distance, extending along the row direction, between an orthographic projection of the first signal line on the substrate and an edge of an orthographic projection of an adjacent opening on the substrate ranges from 6 pm ~ 11 pm.

[0026] In a second aspect of embodiments of the present disclosure, a display device is provided. The display device includes the display substrate as described above.

[0027] In the display substrate and the display device provided in the embodiments of the present disclosure, the power signal lines extend in the column direction, which can avoid the problem of segment differences existing in different regions of the power signal line when the power signal line extends along the row direction and a portion of the power signal line overlaps with the first electrode in the stacking direction of the film layer, and in turn leads to poor anchoring of liquid crystal molecules in the region where there are segment differences in the power signal line and causes light leakage. That is, extending the power signal line in the column direction can solve this problem. Therefore, the opening for defining the light-emitting region of the sub-pixel opened in the light-shielding layer on the side of the sub-pixel away from the substrate can be arranged larger to improve the pixel aperture ratio of the display substrate, and thus improve the light efficiency of the display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. lisa partial schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0029] FIG. 2 is a partial schematic diagram of a plurality of film layers of a display substrate according to an exemplary embodiment of the present disclosure;

[0030] FIG. 3 is a partial schematic diagram of a plurality of film layers of a display substrate according to another exemplary embodiment of the present disclosure;

[0031] FIG. 4 is a partial schematic diagram of a plurality of film layers of a display substrate according to still another exemplary embodiment of the present disclosure;

[0032] FIG. 5 is a partial schematic diagram of a first metal conductive layer of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] FIG. 6 is a partial schematic diagram of a first metal conductive layer of a display substrate superimposed with a first electrode according to an exemplary embodiment of the present disclosure;

[0034] FIG. 7 is a partial schematic diagram of the superimposition of a first metal conductive layer, a first electrode, and a second metal conductive layer of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG. 8 is a cross-sectional view of the display substrate shown in FIG. 2 along AA;

[0036] FIG. 9 is a cross-sectional view of the display substrate shown in FIG. 2 along BB;

[0037] FIG. 10 is another cross-sectional view of the display substrate shown in FIG. 2 along BB;

[0038] FIG. 11 is a partial schematic diagram of a first electrode of a display substrate according to an exemplary embodiment of the present disclosure;

[0039] FIG. 12 is a partial schematic diagram of a first metal conductive layer of a display substrate superimposed with a first electrode according to an exemplary embodiment of the present disclosure;

[0040] FIG. 13 is a partial schematic diagram of the superimposition of a first metal conductive layer, a first electrode, and a second metal conductive layer of a display substrate according to an exemplary embodiment of the present disclosure;

[0041] FIG. 14 is a cross-sectional view of the display substrate shown in FIG. 3 along CC;

[0042] FIG. 15 is a partial schematic diagram of a plurality of film layers of a display substrate according to yet another exemplary embodiment of the present disclosure;

[0043] FIG. 16 is a partial schematic diagram of a plurality of film layers of a display substrate according to yet another exemplary embodiment of the present disclosure; and

[0044] FIG. 17 is a partial schematic diagram of a plurality of film layers of a display substrate according to yet another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described herein in detail, examples of which are represented in the accompanying drawings. When the following description relates to the accompanying drawings, the same numerals in different accompanying drawings indicate the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are only examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0046] The terms used in the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The singular forms "a," "the," and "said" used in the present disclosure and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0047] It should be understood that although terms such as first, second, third, etc. may be used in the present disclosure to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each another. For example, without departing from the scope of the present disclosure, first information may also be referred to as second information, and similarly, second information may be referred to as first information. Depending on the context, as used herein, the word "if as used herein can be interpreted as "when...", "while...", or "in response to determining".

[0048] Embodiments of the present disclosure provide a display substrate and a display device. Combined with the accompanying drawings, the display substrate and the display device in the embodiments of the present disclosure are described in detail below. Without conflict, the features in the embodiments described at below may complement or combine with each other.

[0049] The embodiments of the present disclosure provide a display substrate. As shown in FIG. 1, the display substrate includes a substrate 10 and a plurality of sub-pixels 20 disposed on the substrate 10. The plurality of sub-pixels 20 are arranged in a plurality of rows and columns, each of the sub-pixels 20 has a first size dl in a row direction X and a second size d2 in a column direction Y, the first size dl being greater than the second size d2.

[0050] As shown in FIGS. 2 to 4, the the sub-pixel includes a first electrode 21 and a second electrode 22 disposed opposite to each other. Each of the sub-pixels 20 also includes liquid crystal molecules disposed between the first electrode 21 and the second electrode 22. The display substrate also includes a plurality of power signal lines 30, the power signal lines 30 extending along the column direction Y. Two first electrodes 21 adjacent in the row direction X are connected through the power signal line 30, and two first electrodes 21 adjacent in the column direction Y are connected through the power signal line 30. The extension of the power signal line 30 along the column direction Y means that the power signal line 30 as a whole extends along the column direction Y, and the power signal line 30 may include a portion extending along the row direction X.

[0051] In the display substrate provided in the embodiments of the present disclosure, the power signal lines extend in the column direction, which can avoid the problem of segment differences existing in different regions of the power signal line when the power signal line extends along the row direction and a portion of the power signal line overlaps with the first electrode in the stacking direction of the film layer, and in turn leads to poor anchoring of liquid crystal molecules in the region where there are segment differences in the power signal line and causes light leakage. That is, extending the power signal line in the column direction can solve this problem. Therefore, the opening for defining the light-emitting region of the sub-pixel opened in the light-shielding layer on the side of the sub-pixel away from the substrate can be arranged larger to improve the pixel aperture ratio of the display substrate, and thus improve the light efficiency of the display substrate.

[0052] In one embodiment, the display substrate also includes a plurality of pixel driving circuits. The pixel driving circuits of the display substrate may be in one-to-one correspondence with the sub-pixels, and each of the pixel driving circuits is used to drive the corresponding sub-pixel.

[0053] In one embodiment, as shown in FIG. 1, the display substrate also includes a plurality of scanning signal lines Gate extending along the row direction X and a plurality of data signal lines Data extending along the column direction. The sub-pixels in the same row are connected to the same scanning signal line Gate, and the scanning signal line Gate may be disposed between two adjacent rows of sub-pixels. The number of data signal lines Data may be the same as the number of rows of sub-pixels, and the data signal lines Data may be disposed between two adjacent columns of sub-pixels. As the size of the sub-pixel 20 in the row direction X is larger than the size of the sub-pixel 20 in the column direction Y, the display substrate may reduce the number of columns of sub-pixels in the display substrate when the size of the subpixel 20 in the row direction X is certain, which may reduce the number of the data signal lines Data, which may reduce the number of the driver chips used to provide signals to the data signal lines Data, and reduce the cost of the display substrate.

[0054] In one embodiment, as shown in FIGS. 1 to 3, the data signal lines Data are provided on opposite sides of the same column of sub-pixels. Pixel driving circuits corresponding to two sub-pixels 20 adjacent in the column direction Y are provided, with one of the pixel driving circuits being connected to one of the data signal lines Data adjacent thereto, and the other of the pixel driving circuits being connected to another of the data signal lines Data adjacent thereto. That is, the pixel driving circuits corresponding to the two sub-pixels 20 adjacent in the column direction Y are connected to different data signal lines Data. In order to avoid polarization of the liquid crystal molecules, when the display substrate displays, a signal of one of the two adjacent data signal lines Data is larger than a signal of the power supply signal line 30, and a signal of the other data signal line Data is smaller than the signal of the power supply signal 30. The above setting may cause one of the two pixel driving circuits adjacent in the column direction to receive a data signal that is larger than the signal of the power supply signal line 30, and the other pixel driving circuit to receive a data signal that is smaller than the signal of the power supply signal line 30, and may cause one of the two pixel driving circuits adjacent in the row direction to receive a data signal that is larger than the signal of the power supply signal line 30, and the other pixel driving circuit to receive a signal that is smaller than the signal of the power supply signal line 30, which helps to improve the display uniformity of the display substrate and improve the display effect of the display substrate.

[0055] In one embodiment, the plurality of sub-pixels in the display substrate are divided into a plurality of pixel units, and each pixel unit may include a plurality of sub-pixels with different light-emitting colors. The plurality of sub-pixels in the same pixel unit may be arranged along the column direction Y. Each sub-pixel of the same pixel unit is connected to a different scanning signal line Gate. The light-emitting color of a plurality of sub-pixels disposed in the same row may be the same.

[0056] In one embodiment, the display substrate may include three sub-pixels with different light-emitting colors, for example, the display substrate may include a sub-pixel with a red light-emitting color, a sub-pixel with a green light-emitting color, and a sub-pixel with a blue light-emitting color. One pixel unit may include three sub-pixels with different light-emitting colors.

[0057] In one embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The material of the flexible substrate may include one or more of a polyimide, a polyethylene terephthalate, a polycarbonate, an organic resin material, and the organic resin material may include an epoxy resin, a triazine, a silicone resin, or a polyimide, and the like. The rigid substrate includes any one of, for example, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, and the like; or a semiconductor substrate such as a single-crystal semiconductor substrate or a polycrystal semiconductor substrate made of silicon or silicon carbide and the like, a compound semiconductor substrate such as silicon germanium and the like, and a silicon on insulator (SOI) substrate.

[0058] In one embodiment, the first electrode 21 is a cathode, the second electrode 22 is an anode, and the power signal line is a low level power signal line. In some embodiments, the second electrode 22 may be provided with a plurality of strip slits.

[0059] In one embodiment, the material of the first electrode 21 and the material of the second electrode 22 may both be transparent conductive materials. The transparent conductive material is, for example, indium zinc oxide, indium tin oxide, and the like.

[0060] In one embodiment, as shown in FIGS. 2 to 4, the pixel driving circuit includes a driver transistor 70. The driver transistor 70 includes a gate electrode 71, a first electrode 72, and a second electrode 73. The first electrode 72 and the second electrode 73 may be located on a side of the gate electrode 71 distal from the substrate. One of the first electrode 72 and the second electrode 73 may be a source electrode and the other may be a drain electrode, such as the first electrode 72 being a source electrode and the second electrode 73 being a drain electrode. The pixel driving circuit may also include an active layer. The active layer may be disposed between the gate electrode 71 and the substrate. The second electrode 22 of the subpixel is connected to the first electrode 72 of the corresponding driver transistor 70.

[0061] In one embodiment, as shown in FIGS. 5 to 7, the display substrate includes a first metal conductive layer 91 disposed on the substrate and a second metal conductive layer 92 disposed on a side of the first metal conductive layer 91 distal from the substrate.The display substrate also includes an insulating layer disposed between the first metal conductive layer 91 and the second metal conductive layer 92.

[0062] In one embodiment, the second electrode 22 is disposed on a side of the second metal conductive layer 92 distal from the substrate, and the display substrate also includes a insulating material layer disposed between the second metal conductive layer 92 and the second electrode 22.

[0063] In one embodiment, as shown in FIG. 5, the gate electrode 71 and the scanning signal line Gate are located in the first metal conductive layer 91, and the gate electrode 71 is connected to the scanning signal line Gate.

[0064] In one embodiment, as shown in FIG. 6, the first electrode 72, the second electrode 73, and the data signal line Data are disposed in the second metal conductive layer 92.

[0065] In one embodiment, as shown in FIG. 7, the insulating material layer is provided with a plurality of via holes 82, the second electrode 22 may be electrically connected to the first electrode 72 by the via hole 82.

[0066] In one embodiment, the display substrate also includes a light-shielding layer and a color filter layer disposed on a side of the sub-pixels distal from the substrate. The lightshielding layer is provided with a plurality of openings. As shown in FIGS. 2 to 4, an orthographic projection of one of the openings 50 on the substrate falls within an orthographic projection of one of the second electrodes 22 on the substrate. The openings may be in one-to-one correspondence with the first electrodes, with the orthographic projection of each opening on the substrate falling within the orthographic projection of the corresponding the second electrode on the substrate. The color filter layer includes a plurality of color filter portions, and at least a portion of one color filter portion is located in one opening.

[0067] In one embodiment, the display substrate may be obtained from an array substrate and a color filter substrate that are cell bonded. The array substrate includes a substrate, a first metal conductive layer, a second metal conductive layer, and a first electrode. The color filter substrate may include a second electrode, a light-shielding layer, and a color filter layer. In the process of cell bonding, one of the color filter substrate and the array substrate is coated with a frame sealing adhesive, and a liquid crystal material is added to the other of the color filter substrate and the array substrate; subsequently, the color filter substrate and the array substrate are cell bonded, then a display substrate is obtained.

[0068] In one embodiment, as shown in FIGS. 2 to 4, for two second electrodes 22 connected to the same the power signal line 30 and adjacent in the row direction, in the row direction X, a distance from one of the second electrodes 22 to a portion of the power signal line 30 extending along the column direction Y is a first distance, and a distance from the other of the two second electrodes 22 to the portion of the power signal line extending along the column direction Y is a second distance, the first distance being different from the second distance. In this way, at least a portion of the data signal line Data between two columns of sub-pixels can be arranged between the power signal line 30 and a column of sub-pixels further away from the power signal line 30.

[0069] In one embodiment, as shown in FIGS. 2 to 4, the power signal line 30 includes a first sub-signal line 31 and a second sub-signal line 32 arranged alternately. The size of the first subsignal line 31 in the column direction Y is d3, and the size of the second sub-signal line 32 in the column direction Y is d4, with d3 being greater than d4. In the same power signal line 30, opposite ends of the first sub-signal line 31 are connected to the adjacent second sub-signal lines 32, and opposite ends of the second sub-signal line 32 are connected to the adjacent first sub-signal lines 31.

[0070] In one embodiment, as shown in FIGS. 2 to 4, the second sub-signal line 32 extends along the column direction Y and for two second electrodes 22 adjacent in the column direction Y and disposed on both sides of a center of the second sub-signal line 32, a distance between one of the two second electrodes 22 to the center of the second sub-signal line 32 is equal to a distance between another of the two second electrodes 22 to the center of the second sub-signal line 32. For example, in the example shown in FIG. 2, for the two second electrodes 22 disposed on both side of the center of the second sub-signal line 32, a distance from one of the two second electrodes 22 to the center of the second sub-signal line 32 is d5, and a distance form the other second electrode 22 to the center of the second sub-signal line 32 is d6, with d5 and d6 being equal.

[0071] In one embodiment, as shown in FIGS. 2 to 4, the display substrate also includes a first signal line 41 extending along the row direction X. The second sub-signal line 32 extends along the column direction Y. An orthographic projection of the second sub-signal line 32 on the substrate overlaps with an orthographic projection of one first signal line 41 on the substrate, and opposite ends of the second sub-signal line 32 are connected to the first sub-signal line 31, and orthographic projections of the opposite ends of the second sub-signal line 32 on the substrate are located on opposite sides of the orthographic projection of the first signal line 41 on the substrate. An orthographic projection of the first sub-signal line 31 on the substrate is located between orthographic projections of two adjacent first signal lines 41 on the substrate. In some embodiments, the first signal line 41 is the scanning signal line Gate.

[0072] In one embodiment, as shown in FIGS. 2 to 4, the display substrate also includes a plurality of second signal lines 42 extending along the column direction. An orthographic projection of the second signal lines 42 on the substrate and an orthographic projection of the power signal line 30 on the substrate are both located between orthographic projections of two adjacent columns of sub-pixels on the substrate. In some embodiments, the second signal line 42 is the data signal line Data.

[0073] In one embodiment, as shown in FIG. 2, the first sub-signal line 31 includes a first segment 311, a second segment 312, and a third segment 313 connected in sequence. The first segment 311 extends along the row direction X, the second segment 312 extends along the column direction Y, and the third segment 313 and the first segment 311 are disposed on opposite sides of the second segment 312. An end portion of the first segment 311 distal from the second segment 312 and an end portion of the third segment 313 distal from the second segment 312 are connected to the second sub-signal line 32. In this way, it is convenient for the first sub-signal line 31 to be connected to the second sub-signal line 32 and for the first subsignal line 31 to be connected to two first electrodes 21 adjacent in the row direction X. In the embodiment shown in FIG. 2, an angle between the extension direction of the third segment 313 and the extension direction of the second segment 312 is an acute angle.

[0074] In one embodiment, as shown in FIG. 2, for two second electrodes 22 connected to the same the power signal line 30 and adjacent in the row direction X, a distance from one of the two second electrodes 22 to the second segment 312 is different from a distance from the other of the two second electrodes 22 to the second segment 312 in the row direction X.

[0075] In one embodiment, as shown in FIG. 2, for two second electrodes connected to the same the power signal line 30 and adjacent in the column direction Y, a distance from one of the two second electrodes 22 to the second segment 312 is different from a distance from the other of the two second electrodes 22 to the second segment 312 in the row direction X. In this way, the power signal line 30 is in a zigzag shape, and two driver transistors 70 adjacent in the column direction can be arranged on opposite sides of the power signal line 30, such that two adjacent driver transistors 70 are arranged on opposite sides of the data signal line Data, and thus the display uniformity of the display substrate is improved.

[0076] In one embodiment, as shown in FIG. 3, the first sub-signal line 31 includes a fourth segment 314 and a fifth segment 315 that are connected. The fourth segment 314 extends along the row direction X, the fifth segment 315 extends along the column direction Y, and an end portion of the fourth segment 314 distal from the fifth segment 315 and an end portion of the fifth segment 315 distal from the fourth segment 314 are connected to the second sub-signal line 32. In this way, it is convenient for the first sub-signal line 31 to be connected to the second sub-signal line 32, and it is convenient for the first sub-signal line 31 to be connected to the two first electrodes 21 adjacent in the row direction X. At the same time, it is possible to make the power signal line 30 in a zigzag shape, and it is convenient for the two driver transistors 70 adjacent in the column direction to be arranged on opposite sides of the power signal line 30, and it is possible to make the two adjacent driver transistors 70 to be arranged on the opposite sides of the data signal line Data, such that the display uniformity of the display substrate is improved.

[0077] In one embodiment, as shown in FIG. 3, for two second electrodes 22 connected to the same the power signal line 30 and adjacent in the row direction X, a distance from one of the two second electrodes 22 to the fifth segment 315 is different from a distance from the other of the two second electrodes 22 to the fifth segment 315 in the row direction X.

[0078] In one embodiment, as shown in FIG. 3, for two sub-pixels connected to the same the power signal line 30 and adjacent in the column direction Y, a distance from one of the two second electrodes 22 to the fifth segment 315 is different from a distance from the other of the two second electrodes 22 to the fifth segment 315 in the row direction X. In this way, it is more conducive to the power signal line 30 being in a zigzag shape.

[0079] In one embodiment, as shown in FIG. 4, the first sub-signal line 31 includes a sixth segment 316 and a seventh segment 317 that are connected. The sixth segment 316 extends along the row direction X and is disposed on a side of the seventh segment 317, and the seventh segment 317 extends along the column direction Y; and opposite ends of the seventh segment 317 are connected to the second sub-signal line 32 respectively. In this way, the sixth segment 316 and the seventh segment 317 are connected to two adjacent first electrodes 21 that are different in the row direction, which is convenient for the first sub-signal line 31 to be connected to the two first electrodes 21 adjacent in the row direction X, and for the first sub-signal line 31 to be connected to the second sub-signal line 32.

[0080] In one embodiment, as shown in FIG. 4, for two second electrodes 22 connected to the same the power signal line 30 and adjacent in the row direction X, a distance from one of the two second electrodes 22 to the seventh segment 317 is different from a distance from another of the two second electrodes 22 to the seventh segment 317 in the row direction X.

[0081] In one embodiment, as shown in FIGS. 5 to 7, the first sub-signal line 31 is disposed in the first metal conductive layer 91, and the second sub-signal line 32 is disposed in the second metal conductive layer 92. That is, the first sub-signal line 31 is disposed in the same layer as the gate electrode 71, and the second sub-signal line 32 is disposed in the same layer as the first electrode 72 and the second electrode 73. In this way, in the same power supply signal line 30, the second sub-signal line 32 can connect two adjacent first sub-signal lines 31 together while avoiding a short circuit between the second sub-signal line 32 and the scanning signal line Gate. In addition, the material of the first sub-signal line 31 and the material of the second sub-signal line 32 are both metal, which can make the resistance of the power supply signal line 30 smaller, which is conducive to improving the consistency of the level magnitude of each first electrode 21.

[0082] In one embodiment, as shown in FIG. 6 and FIG. 7, the insulating layer disposed between the first metal conductive layer 91 and the second metal conductive layer 92 is provided with a plurality of via holes 81, and the first sub-signal line 31 is connected to the second sub-signal line 32 through the via holes 81. Specifically, one end of the second subsignal line 32 is connected to the first sub-signal line 31 through one via hole 81 and the other end of the second sub-signal line 32 is connected to the first sub-signal line 31 through one via hole 81.

[0083] In one embodiment, as shown in FIG. 7, an orthographic projection of the via hole 81 on the substrate falls in an edge region of the orthographic projection of the second electrode 22 on the substrate and fals within an orthographic projection of the light-shading layer on the substrate. The via hole 81 is provided in the edge region of the second electrode 22 and covered by the light-shading layer, which can reduce the influence on the aperture ratio of the sub-pixels.

[0084] In one embodiment, as shown in FIG. 7, an orthographic projection of the via hole 82 in the insulating material layer on the substrate falls in the edge region of the orthographic projection of the second electrode 22 on the substrate and is located within the orthographic projection of the light-shielding layer on the substrate. The via hole 82 is provided in the edge region of the second electrode 22 and covered by the light-shielding layer, which can avoid the via hole 82 from affecting the display effect of the display substrate.

[0085] In one embodiment, as shown in FIGS. 5 to 7, when forming the array substrate of the display substrate, the first metal conductive layer 91 is first formed; an insulating layer disposed on a side of the first metal conductive layer 91 distal from the substrate is subsequently formed; the second metal conductive layer 92 is subsequently formed on the insulating layer, and the second sub-signal line 32 disposed in the second metal conductive layer 92 is connected to the first sub-signal line 31 disposed in the first metal conductive layer 91 through the via hole 81 provided in the insulating layer; and the first electrode 21 is subsequently formed, and the first electrode 21 overlaps with the second sub-signal line 32. The array substrate and the color filter substrate are cell bonded, as as to obtain the display substrate shown in FIG. 2.

[0086] If the first electrode is formed before the first metal conductive layer is formed when the display substrate is formed, in order to avoid short circuit between the first electrode and the scanning signal line Gate in the first metal conductive layer, it is necessary to set the distance between the first electrode and the scanning signal line Gate in the column direction to be greater than or equal to 7 pm. In this embodiment, as an insulating layer is provided between the first electrode 21 and the scanning signal line Gate located in the first metal conductive layer 91, there is no risk of short circuit between the first electrode 21 and the scanning signal line Gate. The distance between the first electrode 21 and the scanning signal line Gate in the column direction can be set to be relatively small, thereby increasing the area of the opening of the light-shielding layer and effectively improving the aperture ratio of the sub-pixels.

[0087] In one embodiment, the power signal line includes a segment (also known as a second segment 312) disposed between two openings 50 adjacent in the row direction X and extending along the column direction Y. As shown in FIG. 8, the minimum distance between an edge of an orthographic projection of the second segment 312 on the substrate 10 and an edge of an orthographic projection of an adjacent opening 50 on the substrate 10 is xl , with xl ranging from 4 pm~ 8 um. In this way, the problem of reflection caused by the exposure of the second segment 312 due to alignment deviation when the array substrate and the color filter substrate are cell bonded can be avoided when xl is too small. Also, the problem of affecting the aperture ratio of the sub-pixels when xl is too large can be avoided. In some embodiments, xl may be 4 pm, 4.5 um, 5 pm, 5.5 um, 6 um, 6.5 pm, 7 pm, 7.5 pm, 8 pm, and the like.

[0088] In one embodiment, as shown in FIG. 8, an orthographic projection of one first electrode 21 on the substrate 10 overlaps with the orthographic projection of the second segment 312 on the substrate 10, and an edge of the orthographic projection of the second segment on the substrate 10 is located inside an edge of the orthographic projection of the first electrode 21 on the substrate 10, and the minimum distance between the edge of the orthographic projection of the first electrode 21 on the substrate 10 and the edge of the orthographic projection of the second segment 312 on the substrate 10 is x2, with x2 ranging from 1.5 pm~ 3 pm. In this way, even if there is an alignment deviation between the first electrode 21 and the first sub-signal line 31, it can be ensured that there is an overlapping region between the first electrode and the second segment in the stacking direction of the film layer, so as to facilitate the first electrode being connected to the first sub-signal line. In some embodiments, x2 may be 1.5 pm, 2.0 pm, 2.5 pm, 3.0 pm, and the like.

[0089] In one embodiment, as shown in FIG. 9, in the column direction, a distance between an edge of an orthographic projection of the first signal line 41 on the substrate 10 and an edge of an orthographic projection of an adjacent opening 50 on the substrate 10 is x3, with x3 ranging from 6 pm~ 11 pm. In this way, it can avoid the problem of side view light leakage on the display substrate caused by too small the range of x3, and also avoid affecting the aperture ratio of the sub-pixels due to too large the range of x3. In some embodiments, x3 may be 6 pm, 7 pm, 8 pm, 9 pm, 10 pm, 11 pm, and the like.

[0090] In one embodiment, as shown in FIG. 9, in the column direction, a distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the first electrode 21 on the substrate 10 is x4, with x4 ranging from 3 pm~ 5 pm. In this way, it is possible to ensure that the signal of the first signal line 41 does not interfere with the signal of the first electrode 21 while reduce the effect on the aperture ratio of the sub-pixels. In some embodiments, x4 may be 3 pm, 3.5 pm, 4 pm, 4.5 pm, 5 pm, and the like.

[0091] It should be noted that the above range of values is determined when the liquid crystal molecules in the display substrate are positive liquid crystal molecules.

[0092] In another embodiment, when the liquid crystal molecules are negative liquid crystal molecules, as shown in FIG. 10, in the column direction, a distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the adjacent opening 50 on the substrate 10 is x5, with x5 ranging from 3 pm~ 5 pm. When the liquid crystal molecules are negative liquid crystal molecules, there is no problem of light leakage in the row direction of the liquid crystal molecules. Therefore, x5 can be set to a smaller value..

[0093] Further, as shown in FIG. 10, the edge of the orthographic projection of the opening 50 of the light-shading layer 51 on the substrate 10 extending along the column direction Y is located outside an orthographic projection of the corresponding first electrode 21 on the substrate 10. That is, when the liquid crystal molecules are negative liquid crystal molecules, most of the region where the opening 50 increases is a non-light-emitting region, but due to the alignment deviation when the color filter substrate and the array substrate are cell bonded, it can be avoided that the light-shading layer 51 covers the effective light-emitting region of the sub-pixel after being cell bonded, which helps to improve the aperture ratio of the sub-pixels.

[0094] In one embodiment, as shown in FIGS. 11 to 13, when forming the array substrate of the display substrate, the first electrode 21 is first formed; the first metal conductive layer 91 is subsequently formed, and the first sub-signal line 31 disposed in the first metal conductive layer overlaps with the first electrode 21; an insulating layer disposed on a side of the first metal conductive layer 91 distal from the substrate is subsequently formed; the second metal conductive layer 92 is subsequently formed on the insulating layer, and the second sub-signal line 32 disposed in the second metal conductive layer 92 is connected to the first sub-signal line 31 disposed in the first metal conductive layer 91 through the via hole 81 provided in the insulating layer. The array substrate and the color filter substrate are cell bonded to form the display substrate shown in FIG. 3.

[0095] Further, as shown in FIG. 14, in the column direction, a distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the first electrode 21 on the substrate 10 is x6, with x6 ranging from 5 pm~ 7 pm. In this way, it can be avoided that the conductive material falls into the gap between the first signal line 41 and the first electrode 21 during the formation of the first signal line 41 and the first electrode 21, resulting in short circuit between the first signal line 41 and the first electrode 21. In some embodiments, x6 may be 5 pm, 5.5 pm, 6 pm, 6.5 pm, 7 pm, and the like.

[0096] In another embodiment, as shown in FIG. 15 and FIG. 16, the power signal line 30 includes a first portion 33 extending along the column direction Y and a second portion 34 extending along the row direction X. The first portion 33 is disposed in the second metal conductive layer 92, the second portion 34 is disposed in the first metal conductive layer 91 or in the same layer as the first electrodes 21, and two adjacent first electrodes 21 disposed in a same row are connected through the second portion 34. The second portion 34 is disposed between the second metal conductive layer 92 and the substrate. The display substrate also includes an insulating layer disposed between the second portion 34 and the second metal conductive layer 92. The insulating layer is provided with a via hole 83, and the first portion 33 is connected to the second portion 34 through the via hole 83. In the embodiment shown in FIG. 15, the second portion 34 is disposed in the first metal conductive layer 91, and the first electrode 21 may overlap with the second portion 34. In the embodiment shown in FIG. 16, the second portion 34 is provided in the same layer as the first electrode 21 and is formed simultaneously in the same process. In this way, the portion of the power signal line 30 extending along the column direction Y is integrally formed in the same layer, compared with the embodiment in which different regions of the portion of the power signal line extending along the column direction Y are located in different layers and are connected through via holes, it helps to reduce the resistance of the power signal line 30 and improve the consistency of the level signal of the first electrode 21.

[0097] In one embodiment, as shown in FIGS. 2 to 4, FIG. 15 and FIG. 16, the display substrate also includes a plurality of spacers 62. The spacers 62 can keep a fixed distance between the color film substrate and the array substrate.

[0098] In one embodiment, as shown in FIG. 2, FIG. 4, FIG. 15, and FIG. 16, the display substrate also includes a plurality of supporting portions 61, with an orthographic projection of one spacer 62 on the substrate falling within an orthographic projection of one supporting portion 61 on the substrate. The supporting portions 61 may be in one-to-one correspondence with the spacers 62. The supporting portion 61 may be disposed in the second metal conductive layer 92, and the supporting portion 61 may be disposed in the second metal conductive layer and connected to the data signal line Data.

[0099] In one embodiment, as shown in FIG. 2, at least two sides of an orthographic projection of the spacer 62 on the substrate are surrounded by an orthographic projection of the power signal line 30 on the substrate, and a plurality of spacers 62 disposed between two adjacent columns of sub-pixels are distributed on both sides of the power signal line 30. In the embodiment shown in FIG. 2, both sides of the spacers 62 are surrounded by the second subsignal line 32 and the first segment 311.

[0100] In another embodiment, as shown in FIG. 3, the spacer 62 is disposed on a side of the power signal line 30 distal from the substrate, and an orthographic projection of the spacer 62 on the substrate overlaps with an orthographic projection of the power signal line 30 on the substrate. In the embodiment shown in FIG. 3, a portion of the orthographic projection of the spacer 62 on the substrate 10 overlaps with the orthographic projection of the power signal line 30 on the substrate, and a portion of the orthographic projection of the spacer 62 on the substrate 10 overlaps with the orthographic projection of the data signal line Data on the substrate. In this way, the supporting portion for supporting the spacer 62 may may not be provided, which helps to reduce the distance between two adjacent columns of sub-pixels.

[0101] In a further embodiment, as shown in FIG. 4, FIG. 15 and FIG. 16, the power signal line 30 includes a portion extending along the column direction, orthographic projections of a plurality of the spacers 62 disposed between two adj acent columns of sub-pixels on the substrate located on the same side as an of an adjacent portion extending along the column direction. The power signal line adjacent to the spacer refers to a power signal line with the smallest distance from the spacer. Both the power signal line and the spacer are located between the adjacent two columns of sub-pixels as mentioned above.

[0102] In one embodiment, as shown in FIG. 2 and FIG. 3, orthographic projections of two driver transistors 70 adjacent in the column direction Y on the substrate are located on opposite sides of an orthographic projection of an adjacent power signal lines 30 on the substrate. In another embodiment, as shown in FIG. 4, FIG. 14, and FIG. 15, the orthographic projections of two drive transistors 70 adjacent in the column direction Y on the substrate are located on the same side as the orthographic projection of the adjacent power signal lines 30 on the substrate. The power supply signal line 30 adjacent to the drive transistor 70 refers to the power supply signal line 30 with the smallest distance from the drive transistor 70 in the row direction X.

[0103] In one embodiment, as shown in FIG. 2, FIG. 3, and FIG. 16, the orthographic projections of two driver transistors 70 adjacent in the column direction Y on the substrate are located on opposite sides of the orthographic projection of an adjacent data signal line Data on the substrate. In another embodiment, as shown in FIG. 4 and FIG. 14, the orthographic projections of two drive transistors 70 adjacent in the column direction Y on the substrate are located on the same side as the orthographic projection of the adjacent data signal line Data on the substrate. The data signal line Data adjacent to the drive transistor 70 refers to the data signal line Data with the smallest distance from the drive transistor 70 in the row direction X.

[0104] In one embodiment, as shown in FIG. 17, the display substrate includes a display region 101 and a bezel region 102. The sub-pixels are disposed in the display region 101. The display substrate also includes a wire 63 disposed in the bezel region 102. The wire 63 is electrically connected to the power supply signal line 30 and a driver chip, respectively. The display substrate also includes a metal conductive layer. The wire 63 is disposed in the metal conductive layer. The wire 63 may transmit a power signal provided by the driver chip to the power signal line 30.

[0105] Further, the wire 63 is disposed in the first metal conductive layer 91, the first subsignal line 31 of the power signal line 30 is disposed in the first metal conductive layer 91, and the wire 63 is connected to the first sub-signal line 31. In this way, the power signal line 30 does not need to be connected to the wire 63 through the via hole in the insulating layer, which helps to improve the signal uniformity of the first electrode. Moreover, the wire 63 and the data signal line Data are located in different metal layers, and the portion of the data signal line Data that extends to the bezel region 102 does not intersect with the wire 63, and the wire 63 is arranged more flexibly.

[0106] The embodiments of the present disclosure also provide a display device. The display device includes the display substrate as described in any of the above embodiments.

[0107] In some embodiments, the display device also includes a housing. The display substrate is embedded within the housing.

[0108] The display device provided by the embodiments of the present disclosure may be any suitable display device, including but not limited to a cell phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, an e-book, and any other product or component having a display function.

[0109] It should be noted that in the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Moreover, it is to be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intervening layers. Additionally, it is to be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intervening layer or element. Furthermore, it is to be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or elements, or there may be more than one intervening layer or element. Like reference numerals refer to like elements throughout.

[0110] After considering the specification and practicing the content disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure. These variations, uses, or adaptations follow the general principles of the present disclosure and include common knowledge or commonly used technical means in the technical field that are not disclosed in the present disclosure. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0111] It should be understood that the present disclosure is not limited to the precise structure which has been described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display substrate, comprising:a substrate;a plurality of sub-pixels arranged in a plurality of rows and columns on the substrate, wherein for each of the plurality of sub-pixels, the sub-pixel has a first size in a row direction and a second size in a column direction, the first size being greater than the second size; and the sub-pixel comprises a first electrode and a second electrode disposed opposite to each other, and liquid crystal molecules disposed between the first electrode and the second electrode; anda plurality of power signal lines extending along the column direction, wherein two first electrodes adjacent in the row direction are connected through one of the power signal lines, and two first electrodes adjacent in the column direction are connected through one of the power signal lines.

2. The display substrate according to claim 1, wherein for two second electrodes connected to a same power signal line and adjacent in the row direction, in the row direction, a distance from one of the two second electrodes to a portion of the power signal line extending along the column direction is a first distance, and a distance from another of the two second electrodes to the portion of the power signal line extending along the column direction is a second distance, the first distance being different from the second distance.

3. The display substrate according to claim 1, wherein each of the power signal lines comprises a first sub-signal line and a second sub-signal line arranged alternately, wherein a size of the first sub-signal line in the column direction is larger than a size of the second subsignal line in the column direction.

4. The display substrate according to claim 3, wherein the second sub-signal line extends along the column direction; and for two second electrodes adjacent in the column direction and disposed on both sides of a center of the second sub-signal line, a distance from one of the two second electrodes to the center of the second sub-signal line is equal to a distance from another of the two second electrodes to the center of the second sub-signal line.

5. The display substrate according to claim 3, further comprising a first signal line extending along the row direction, wherein the second sub-signal line extends along the column direction, an orthographic projection of the second sub-signal line on the substrate overlaps with an orthographic projection of one first signal line on the substrate; and opposite ends of the second sub-signal line are connected to the first sub-signal line, and orthographic projections of the opposite ends of the second sub-signal line on the substrate are located on opposite sides of the orthographic projection of the first signal line on the substrate.

6. The display substrate according to any one of claims 3 to 5, wherein the first sub-signal line comprises a first segment, a second segment, and a third segment connected in sequence, wherein the first segment extends along the row direction, the second segment extends along the column direction, and the third segment and the first segment are disposed on opposite sides of the second segment; and an end portion of the first segment distal from the second segment and an end portion of the third segment distal from the second segment are connected to the second sub-signal line.

7. The display substrate according to claim 6, wherein for two second electrodes connected to a same power signal line and adjacent in the row direction, a distance from one of the two second electrodes to the second segment is different from a distance from another of the two second electrodes to the second segment in the row direction.

8. The display substrate according to claim 6, wherein for two second electrodes connected to a same power signal line and adjacent in the column direction, a distance from one of the two second electrodes to the second segment is different from a distance from another of the two second electrodes to the second segment in the row direction.

9. The display substrate according to any one of claims 3 to 5, wherein the first sub-signal line comprises a fourth segment and a fifth segment that are connected, wherein the fourth segment extends along the row direction, the fifth segment extends along the column direction,and an end portion of the fourth segment distal from the fifth segment and an end portion of the fifth segment distal from the fourth segment are connected to the second sub-signal line.

10. The display substrate according to claim 9, wherein for two second electrodes connected to a same power signal line and adjacent in the row direction, a distance from one of the two second electrodes to the fifth segment is different from a distance from another of the two second electrodes to the fifth segment in the row direction.

11. The display substrate according to claim 9, wherein for two sub-pixels connected to a same power signal line and adjacent in the column direction, a distance from one of the two second electrodes to the fifth segment is different from a distance from another of the two second electrodes to the fifth segment in the row direction.

12. The display substrate according to any one of claims 3 to 5, wherein the first sub-signal line comprises a sixth segment and a seventh segment that are connected, wherein the sixth segment extends along the row direction and is disposed on a side of the seventh segment, and the seventh segment extends along the column direction; and opposite ends of the seventh segment are connected to the second sub-signal line.

13. The display substrate according to claim 12, wherein for two second electrodes connected to a same power signal line and adjacent in the row direction, a distance from one of the two second electrodes to the seventh segment is different from a distance from another of the two second electrodes to the seventh segment in the row direction.

14. The display substrate according to claim 3, further comprising a first metal conductive layer and a second metal conductive layer disposed on a side of the first metal conductive layer distal from the substrate, wherein the first sub-signal line is disposed in the first metal conductive layer, and the second sub-signal line is disposed in the second metal conductive layer.

15. The display substrate according to claim 14, further comprising an insulating layer disposed between the first metal conductive layer and the second metal conductive layer, wherein the insulating layer is provided with a via hole, and the first sub-signal line and the second sub-signal line are connected through the via hole; andthe display substrate further comprises a light-shading layer disposed on a side of the subpixels distal from the substrate, wherein the light-shading layer is provided with a plurality of openings, an orthographic projection of one of openings on the substrate falls within an orthographic projection of one of the second electrodes on the substrate, an orthographic projection of the via hole on the substrate falls in an edge region of the orthographic projection of the second electrode on the substrate and falls within an orthographic projection of the lightshading layer on the substrate.

16. The display substrate according to claim 15, wherein the first electrode overlaps with the first sub-signal line, or, the first electrode overlaps with the second sub-signal line.

17. The display substrate according to claim 1, further comprising a first metal conductive layer and a second metal conductive layer disposed on a side of the first metal conductive layer distal from the substrate, and each of the power signal lines comprises a first portion extending along the column direction and a second portion extending along the row direction, wherein the first portion is disposed in the second metal conductive layer, the second portion is disposed in the first metal conductive layer or in a same layer with the first electrode, two adjacent first electrodes disposed in a same row are connected through the second portion, and the second portion is disposed between the second metal conductive layer and the substrate; and the display substrate further comprises an insulating layer disposed between the second portion and the second metal conductive layer, wherein the insulating layer is provided with a via hole, and the first portion is connected to the second portion through the via hole.

18. The display substrate according to claim 1, further comprising a plurality of first signal lines extending along the row direction and a plurality of second signal lines extending along the column direction, wherein an orthographic projection of each of the second signal lines onthe substrate is located between orthographic projections of two adjacent columns of the subpixels on the substrate.

19. The display substrate according to claim 1, further comprising a plurality of spacers;wherein at least two sides of an orthographic projection of each of the spacers on the substrate are surrounded by an orthographic projection of one of the power signal lines on the substrate, and a plurality of spacers disposed between two adjacent columns of sub-pixels are distributed on both side of the power signal line; or,each of the power signal lines comprises a portion extending along the column direction, wherein orthographic projections of a plurality of spacers located between two adjacent columns of sub-pixels on the substrate is located on a same side as an orthographic projection of an adjacent portion extending along the column direction; or,the spacers are disposed on a side of the power signal lines distal from the substrate, and orthographic projection of each of the spacers overlaps with an orthographic projection of one of the power signal lines on the substrate.

20. The display substrate according to claim 1, further comprising a pixel driving circuit comprising a driver transistor;wherein orthographic projections of two driver transistors adjacent in the column direction on the substrate are located on opposite sides of an orthographic projection of one of the power signal lines on the substrate, or, orthographic projections of two driver transistors adjacent in the column direction on the substrate are located on a same side of an orthographic projection of one of the power signal lines on the substrate.

21. The display substrate according to claim 1, wherein the display substrate comprises a display region and a bezel region, wherein the sub-pixels are disposed in the display region; the display substrate further comprises a wire disposed in the bezel region, wherein the wire is electrically connected to the power signal lines and a driver chip; and the display substrate further comprises a metal conductive layer, wherein the wire is disposed in the metal conductive layer.

22. The display substrate according to claim 1, the display substrate further comprises a light-shading layer disposed on a side of the sub-pixels distal from the substrate, wherein the light-shading layer is provided with a plurality of openings, an orthographic projection of one of openings on the substrate falls within an orthographic projection of one of the second electrodes on the substrate; and the display substrate further comprises a plurality of first signal lines extending along the row direction;each of the power signal lines comprises a segment disposed between two openings adjacent in the row direction and extending along the column direction, wherein a minimum distance between an edge of an orthographic projection of the segment extending along the column direction on the substrate and an edge of an orthographic projection of an adjacent opening on the substrate ranges from 4 pm ~ 8 pm; and / or,the first electrode is disposed on a side of the first signal lines distal from the substrate, and the display substrate further comprises an insulating layer disposed between the first signal line and the first electrode; and in the columnar direction, a distance between an edge of an orthographic projection of each of the first signal lines on the substrate and an edge of an orthographic projection of the second electrode on the substrate ranges from 3 pm~ 5 pm; and / or, an orthographic projection of each of the first signal lines on the substrate falls within an orthographic projection of the light-shading layer on the substrate, wherein a distance, extending along the row direction, between an orthographic projection of the first signal line on the substrate and an edge of an orthographic projection of an adjacent opening on the substrate ranges from 6 pm ~ 11 pm.

23. A display device, comprising the display substrate as defined in any one of claims 1 to 22.PCT / CN2024 / 093114A. CLASSIFICATION OF SUBJECT MATTER G02Fl / 1343(2006.01)i; G02Fl / 1362(2006.01)i According to International Patent Classification (IPC) or to both national classification and IPC B. FIELDS SEARCHED Minimum documentation searched (classification system followed by classification symbols) IPC: G02F Documentation searched other than minimum documentation to the extent that such documents are included in the fields searched Electronic data base consulted during the international search (name of data base and, where practicable, search terms used) CNTXT, ENTXTC, VEN: ¢8¾ ¢,8(38¾ ¢8(¾ ¢8(83¾ 33<8, 38^8¾ 38, Mffl, SgH, 3 8, 38¾ <ffirt, *8®, fi / K (O, 8, Mw, 8(8¾ FFS, ips, IPS, PVDD, fringe field, electrode line, power connection line, power line, power signal line, common, electrode, , distance, connection, line, column, adjacent, in-plane, scan line, data line, horizontal field, display, pixel, row, extension, liquid crystal, source line C. DOCUMENTS CONSIDERED TO BE RELEVANT Category* Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. X US 2023154935 Al (BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. et al.) 18 May 2023 (2023-05-18) description, paragraphs 45-83, and figures 3-1 1,21,23 A A CN 104317089 A (HEFEI XINSHENG OPTOELECTRONIC TECHNOLOGY CO., LTD. et al.) 28 January 2015 (2015-01-28) entire document CN 102468308 A (BOE TECHNOLOGY GROUP CO., LTD.) 23 May 2012 (2012-05-23) entire document 1-23 1-23 A CN 104216183 A (HEFEI XINSHENG OPTOELECTRONIC TECHNOLOGY CO., LTD. et al.) 17 December 2014 (2014-12-17) entire document 1-23 A CN 112068377 A (CHENGDU CEC PANDA DISPLAY TECHNOLOGY CO., LTD.) 11 December 2020 (2020-12-11) entire document 1-23 | | Further documents are listed in the continuation of Box C. | J | See patent family annex. * Special categories of cited documents: “T” later document published after the international filing date or priority “A” document defining the general state of the art which is not considered date and not in conflict with the application but cited to understand the to be of particular relevance principle or theory underlying the invention “D” document cited by the applicant in die international application “X” document of particular relevance; the claimed invention cannot be “E" earlier application orpatent but published on or after the international considered novel or cannot be considered to involve an inventive step filing date when the document is taken alone •SL” document which may throw doubts on priority claim(s) or which is “Y” document of particular relevance; the claimed invention cannot be cited to establish the publication date of another citation or other considered to involve an inventive step when the document is special reason (as specified) combined with one or more other such documents, such combination “O” document referring to an oral disclosure, use, exhibition or other being obvious to a person skilled in the art means document member of the same patent family “P” document published prior to the international filing date but later than the priority date claimed Date of the actual completion of the international search 30 August 2024 Date of mailing of the international search report 02 September 2024 Name and mailing address of the ISA / CN China National Intellectual Property Administration (ISA / CN) China No. 6, Xitucheng Road, Jimenqiao, Haidian District, Beijing 100088 Authorized officer Telephone No.PCT / CN2024 / 093114C. DOCUMENTS CONSIDERED TO BE RELEVANTCategory* Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. A US 2016254275 Al (BOE TECHNOLOGY GROUP CO., LTD. et al.) 01 September 2016 (2016-09-01) entire document 1-23PCT / CN2024 / 093114Patent document cited in search report Publication date (day / month / year) Patent family member)s) Publication date (day / month / year) US 2023154935 Al 18 May 2023 US 11876102 B2 16 January 2024 CN 104317089 A 28 January 2015 EP 3214485 Al 06 September 2017 EP 3214485 A4 09 May 2018 WO 2016065805 Al 06 May 2016 US 2016349580 Al 01 December 2016 US 9766520 B2 19 September 2017 CN 102468308 A 23 May 2012 None CN 104216183 A 17 December 2014 US 2016254275 Al 01 September 2016 US 9865623 B2 09 January 2018 WO 2016029601 Al 03 March 2016 EP 3187929 Al 05 July 2017 EP 3187929 A4 25 April 2018 EP 3187929 Bl 30 June 2021 CN 112068377 A 11 December 2020 None US 2016254275 Al 01 September 2016 None

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