Wiring board and manufacturing method of the same

Abstract

To improve the HAST resistance of a wiring board.SOLUTION: The wiring board has: an insulating layer; a first pad and a second pad for external connection that are provided on the insulating layer and each include a first surface in contact with the insulating layer, a second surface on the opposite side of the first surface, and a side surface connecting the first surface and the second surface; and a protective insulating layer provided on the insulating layer. Each of the first pad and the second pad has a part exposed in an opening of the protective insulating layer. The first pad has a part facing the second pad without having the protective insulating layer therebetween. A region exposed from the protective insulating layer of the second surface of each of the first pad and the second pad is covered with a plating layer. A region exposed from the protective insulating layer of the side surface of each of the first pad and the second pad is exposed from the plating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board and a manufacturing method thereof. [Background technology]

[0002] A wiring board is known that has a structure in which a protective insulating layer with openings is formed on an insulating layer, and a plurality of pads for external connection are exposed from the openings of the protective insulating layer. The pads for external connection include SMD pads and NSMD pads, and may be a mixture of both. In such a wiring board, for example, a plating layer is formed to cover the top and side surfaces of the NSMD pads (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-192205 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the distance between adjacent pads becomes narrow, it may not be possible to place a protective insulating layer between the adjacent pads. In such a case, the plating layer formed on the side of the adjacent pads extends onto the upper surface of the insulating layer, which effectively narrows the distance between the adjacent pads and may result in a decrease in HAST resistance.

[0005] The present invention has been made in view of the above-mentioned points, and has an object to improve the HAST resistance of a wiring board. [Means for solving the problem]

[0006] This wiring board has an insulating layer, first and second pads for external connection provided on the insulating layer, each having a first surface in contact with the insulating layer, a second surface opposite the first surface, and a side surface connecting the first surface and the second surface, and a protective insulating layer provided on the insulating layer, wherein each of the first pad and the second pad has a portion exposed within an opening in the protective insulating layer, and the first pad has a portion facing the second pad without the protective insulating layer in between, and the areas of the second surfaces of each of the first pad and the second pad that are exposed from the protective insulating layer are covered with a plating layer, and the areas of the side surfaces of each of the first pad and the second pad that are exposed from the protective insulating layer are exposed from the plating layer. Effect of the Invention

[0007] According to the disclosed technique, the HAST resistance of a wiring board can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating a wiring board according to a first embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of the wiring board according to the first embodiment; [Diagram 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4] 5A to 5C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; [Diagram 5] 4A to 4D are views illustrating the manufacturing process of the wiring board according to the first embodiment; [Figure 6] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment; [Figure 7] 6 is a diagram illustrating a manufacturing process of the wiring board according to the first embodiment; FIG. [Figure 8] 1A to 1C are diagrams illustrating a part of a manufacturing process for a wiring board according to a comparative example. [Figure 9] 1A to 1C are diagrams illustrating a wiring board according to a first modified example of the first embodiment. [Figure 10] 11A and 11B are diagrams illustrating a wiring board according to a second modified example of the first embodiment. [Figure 11] 13A and 13B are diagrams illustrating a wiring board according to a third modified example of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted.

[0010] First Embodiment [Wiring board structure] 1A and 1B are diagrams illustrating a wiring board according to a first embodiment, in which FIG. 1A is a cross-sectional view showing the entire wiring board, and FIG. 1B is a partial bottom view of part P in FIG. 1A and its vicinity.

[0011] Referring to FIG. 1, wiring board 1 is a wiring board in which wiring layers and insulating layers are laminated on both sides of core layer 10.

[0012] Specifically, in the wiring board 1, a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, and a solder resist layer 17 are laminated in this order on one surface 10a of the core layer 10. Also, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, a solder resist layer 27, and a plating layer 28 are laminated in this order on the other surface 10b of the core layer 10.

[0013] In the first embodiment, for convenience, the solder resist layer 17 side of the wiring board 1 is referred to as the upper side or one side, and the solder resist layer 27 side is referred to as the lower side or the other side. Also, the surface of each part on the solder resist layer 17 side is referred to as one side or upper side, and the surface on the solder resist layer 27 side is referred to as the other side or lower side. However, the wiring board 1 can be used upside down or placed at any angle. Also, the planar view refers to viewing the object from the normal direction of one surface 10a of the core layer 10, and the planar shape refers to the shape of the object viewed from the normal direction of one surface 10a of the core layer 10.

[0014] The core layer 10 may be, for example, a so-called glass epoxy substrate in which a glass cloth is impregnated with an insulating resin such as an epoxy resin. The core layer 10 may be a substrate in which a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber is impregnated with an epoxy resin. The thickness of the core layer 10 is, for example, about 60 to 1000 μm. The core layer 10 is provided with a through hole 10x that penetrates the core layer 10 in the thickness direction. The planar shape of the through hole 10x is, for example, a circle.

[0015] The wiring layer 12 is formed on one surface 10a of the core layer 10. The wiring layer 22 is formed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by the through wiring 11 formed in the through hole 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. The wiring layers 12 and 22 and the through wiring 11 may be made of, for example, copper (Cu). The thickness of the wiring layers 12 and 22 is, for example, about 10 to 40 μm. The wiring layer 12, the wiring layer 22, and the through wiring 11 may be formed integrally.

[0016] The insulating layer 13 is an interlayer insulating layer formed on one surface 10a of the core layer 10 so as to cover the wiring layer 12. The material of the insulating layer 13 may be, for example, a non-photosensitive thermosetting resin mainly composed of an epoxy resin or the like. The thickness of the insulating layer 13 is, for example, about 25 to 40 μm. The insulating layer 13 may contain a filler such as silica (SiO2). The insulating layer 13 has a via hole 13x which is an opening. The via hole 13x penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12. The via hole 13x is, for example, an inverted truncated cone-shaped recess in which the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 12.

[0017] The wiring layer 14 fills the via holes 13x to be electrically connected to the wiring layer 12, and extends from the via holes 13x to the upper surface of the insulating layer 13. In detail, the wiring layer 14 includes via wiring filled in the via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 through the via wiring. The material of the wiring layer 14 and the thickness of the wiring pattern are, for example, similar to those of the wiring layer 12.

[0018] The insulating layer 15 is an interlayer insulating layer formed on the upper surface of the insulating layer 13 so as to cover the wiring layer 14. The material and thickness of the insulating layer 15 are, for example, the same as those of the insulating layer 13. The insulating layer 15 may contain a filler such as silica (SiO2). The insulating layer 15 has a via hole 15x which is an opening. The via hole 15x penetrates the insulating layer 15 and exposes the upper surface of the wiring layer 14. The via hole 15x is, for example, an inverted truncated cone-shaped recess in which the diameter of the opening on the solder resist layer 17 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 14.

[0019] The wiring layer 16 fills the via holes 15x to be electrically connected to the wiring layer 14, and extends from the via holes 15x to the upper surface of the insulating layer 15. In detail, the wiring layer 16 includes via wirings filled in the via holes 15x and a wiring pattern formed on the upper surface of the insulating layer 15. The wiring pattern of the wiring layer 16 is electrically connected to the wiring layer 14 through the via wirings. The material of the wiring layer 16 and the thickness of the wiring pattern are similar to those of the wiring layer 12, for example.

[0020] The solder resist layer 17 is a protective insulating layer located at the outermost position on one side of the wiring board 1, and is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The solder resist layer 17 has an opening 17x, and a part of the upper surface of the wiring layer 16 is exposed in the opening 17x. The planar shape of the opening 17x is, for example, circular. The wiring layer 16 exposed in the opening 17x can be used as a pad for electrically connecting to a semiconductor chip or the like. The material of the solder resist layer 17 can be, for example, a photosensitive insulating resin mainly composed of a phenolic resin, a polyimide resin, or the like. The solder resist layer 17 may contain a filler such as silica (SiO2). The thickness of the solder resist layer 17 is, for example, about 25 to 40 μm.

[0021] A surface treatment layer (not shown) may be formed on the upper surface of the wiring layer 16 exposed in the opening 17x. Examples of the surface treatment layer include an Au layer, a Ni / Au layer (a metal layer in which a Ni layer and a Au layer are laminated in this order), and a Ni / Pd / Au layer (a metal layer in which a Ni layer, a Pd layer, and a Au layer are laminated in this order). The surface treatment layer may be formed by performing an oxidation prevention treatment such as an OSP (Organic Solderability Preservative) treatment on the upper surface of the wiring layer 16 exposed in the opening 17x. The OSP treatment can form an organic coating made of an azole compound, an imidazole compound, or the like as the surface treatment layer. A protruding electrode (not shown) such as a metal post may be formed on the upper surface of the wiring layer 16 exposed in the opening 17x.

[0022] The insulating layer 23 is an interlayer insulating layer formed on the other surface 10b of the core layer 10 so as to cover the wiring layer 22. The material and thickness of the insulating layer 23 are, for example, the same as those of the insulating layer 13. The insulating layer 23 may contain a filler such as silica (SiO2). The insulating layer 23 has a via hole 23x which is an opening. The via hole 23x penetrates the insulating layer 23 and exposes the lower surface of the wiring layer 22. The via hole 23x is, for example, a truncated cone-shaped recess in which the diameter of the opening on the insulating layer 25 side is larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 22.

[0023] The wiring layer 24 fills the via holes 23x to be electrically connected to the wiring layer 22, and extends from the via holes 23x to the lower surface of the insulating layer 23. In detail, the wiring layer 24 includes via wirings filled in the via holes 23x, and a wiring pattern formed on the lower surface of the insulating layer 23. The wiring pattern of the wiring layer 24 is electrically connected to the wiring layer 22 through the via wirings. The material of the wiring layer 24 and the thickness of the wiring pattern are similar to those of the wiring layer 12, for example.

[0024] The insulating layer 25 is an interlayer insulating layer formed on the lower surface of the insulating layer 23 so as to cover the wiring layer 24. The material and thickness of the insulating layer 25 are, for example, the same as those of the insulating layer 13. The insulating layer 25 may contain a filler such as silica (SiO2). The insulating layer 25 has a via hole 25x which is an opening. The via hole 25x penetrates the insulating layer 25 and exposes the lower surface of the wiring layer 24. The via hole 25x is, for example, a truncated cone-shaped recess in which the diameter of the opening on the solder resist layer 27 side is larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 24.

[0025] The wiring layer 26 fills the via holes 25x to be electrically connected to the wiring layer 24, and extends from within the via holes 25x to the lower surface of the insulating layer 25. In detail, the wiring layer 26 includes via wiring filled in the via holes 25x, and pads and wiring formed on the lower surface of the insulating layer 25. The pads and wiring of the wiring layer 26 are electrically connected to the wiring layer 24 through the via wiring. The material of the wiring layer 26 and the thickness of the pads and wiring are similar to those of the wiring layer 12, for example.

[0026] The solder resist layer 27 is a protective insulating layer located at the outermost position on the other side of the wiring board 1, and is formed on the lower surface of the insulating layer 25. The solder resist layer 27 has openings 27x, and a part of the lower surface of the wiring layer 26 is exposed in the openings 27x. The material of the solder resist layer 27 may be, for example, a photosensitive insulating resin mainly composed of a phenolic resin or a polyimide resin. The solder resist layer 27 may contain a filler such as silica (SiO2). The thickness of the solder resist layer 27 based on the lower surface of the insulating layer 25 is, for example, about 30 to 45 μm. The thickness of the solder resist layer 27 based on the lower surface of the wiring layer 26 is, for example, about 15 to 30 μm.

[0027] A plating layer 28 is formed on the lower surface of the wiring layer 26 exposed in the openings 27x of the solder resist layer 27. The plating layer 28 may be a single-layer or multi-layer metal layer exemplified as the surface treatment layer. The thickness of the plating layer 28 may be, for example, about 5 μm to 10 μm.

[0028] Here, the wiring layer 26, the solder resist layer 27, and the plating layer 28 will be described in more detail. The wiring layer 26 includes a first pad 26a having a non-solder mask defined (NSMD) structure and a second pad 26b having a solder mask defined (SMD) structure. The entire lower surface and side surfaces of the first pad 26a are exposed from the solder resist layer 27. In addition, a part of the lower surface and side surfaces of the second pad 26b are covered with the solder resist layer 27.

[0029] The wiring layer 26 may have wiring 26c formed on the same surface as the first pad 26a and the second pad 26b of the insulating layer 25 and having a portion exposed from the inner wall surface of the opening 27x of the solder resist layer 27. The wiring layer 26 may also have wiring (not shown) electrically connected to the first pad 26a and / or the second pad 26b. This wiring may be entirely covered with the solder resist layer 27.

[0030] For example, the first pad 26a is a pad for signals, and the second pad 26b is a pad for power supply or ground. In this case, the wiring connected to the second pad 26b can be made thicker than the wiring connected to the first pad 26a. The wiring connected to the second pad 26b may be a wiring that is close to a solid color.

[0031] The first pad 26a and the second pad 26b are provided on the insulating layer 25, and each has a first surface in contact with the insulating layer 25, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface. In the example of Fig. 1, the upper surfaces of the first pad 26a and the second pad 26b are the first surfaces, and the lower surfaces are the second surfaces. Each of the first pad 26a and the second pad 26b has a portion exposed in the opening 27x of the solder resist layer 27.

[0032] The first pad 26a and the second pad 26b exposed in the opening 27x are, for example, circular in plan view. In this case, the diameter of the first pad 26a and the second pad 26b exposed in the opening 27x can be, for example, about 300 μm to 1000 μm. The diameter of the first pad 26a and the diameter of the second pad 26b may be the same or different. The distance between the first pad 26a and the second pad 26b can be, for example, about 50 μm to 150 μm. However, the first pad 26a and the second pad 26b exposed in the opening 27x may be in a shape other than a circle, for example, a polygon such as a rectangle, an ellipse, etc., in plan view. The first pad 26a and the second pad 26b exposed in the opening 27x can be used as an external connection pad for electrically connecting to a mounting board such as a motherboard.

[0033] The first pad 26a has a portion facing the second pad 26b without sandwiching the solder resist layer 27. For example, the solder resist layer 27 is not disposed between the portions where the first pad 26a and the second pad 26b are closest to each other in a plan view. The regions of the second surfaces (lower surfaces) of the first pad 26a and the second pad 26b that are exposed from the solder resist layer 27 are covered with the plating layer 28. The regions of the side surfaces of the first pad 26a and the second pad 26b that are exposed from the solder resist layer 27 are not covered with the plating layer 28 and are exposed from the plating layer 28.

[0034] The inner wall surface of the opening 27x of the solder resist layer 27 is separated from the insulating layer 25. That is, the inner wall surface of the opening 27x of the solder resist layer 27 is not in contact with the upper surface of the insulating layer 25. The inner wall surface of the opening 27x of the solder resist layer 27 is in contact with the second surface (lower surface) of the first pad 26a, the second pad 26b, or the wiring 26c. The inner wall surface of the opening 27x of the solder resist layer 27 may have a portion in contact with a side surface of the plating layer 28. The inner wall surface of the opening 27x of the solder resist layer 27 may have a portion that is flush with the side surface of the wiring 26c.

[0035] As described below, since the first pad 26a and the second pad 26b are formed by etching, the side surfaces may not be perpendicular to the lower surface of the insulating layer 25 but may be inclined. For example, the first pad 26a may be a trapezoid in which the length of the second surface (lower surface) is shorter than the length of the first surface (upper surface) in the cross-sectional view shown in Fig. 1. The difference between the length of the second surface (lower surface) and the length of the first surface (upper surface) may be, for example, about several µm.

[0036] [Method of manufacturing wiring board] 2 to 7 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment. In Fig. 2 to Fig. 7, the wiring board is shown upside down compared to Fig. 1. In each diagram, (a) is a plan view corresponding to region P in Fig. 1, and (b) is a cross-sectional view taken along line AA in (a). Although (a) is a plan view, hatching corresponding to the cross-sectional view in (b) is shown for the sake of convenience in order to facilitate understanding.

[0037] 1 can be manufactured by sequentially laminating wiring layers and insulating layers, for example, by a well-known build-up method, on one surface 10a and the other surface 10b of a core layer 10. Here, while illustrating region P, a process of forming a wiring layer 26, a solder resist layer 27, and a plating layer 28 on the wiring board after lamination of an insulating layer 25 has been completed will be described.

[0038] First, in the process shown in FIG. 2, after forming a via hole 25x in the insulating layer 25, the wiring layer 26 is formed on the insulating layer 25. The via hole 25x can be formed by, for example, a laser processing method using a CO2 laser or the like. After forming the via hole 25x, a resist layer 300 having an opening 300x exposing an area where the wiring layer 26 is to be formed is formed on the upper surface of the insulating layer 25. The resist layer 300 can be formed, for example, by attaching a photosensitive dry film resist onto the insulating layer 25. The opening 300x can be formed, for example, by exposing and developing the photosensitive dry film resist. The wiring layer 26 can be formed in the via hole 25x exposed in the opening 300x and on the upper surface of the insulating layer 25 by, for example, a well-known semi-additive method. The wiring layer 26 has a first surface in contact with the insulating layer 25 and a second surface that is the opposite surface of the first surface. Here, in the wiring layer 26, the first surface is the lower surface and the second surface is the upper surface.

[0039] 3, after removing the resist layer 300, a solder resist layer 27 having openings 27x that selectively expose the second surface (upper surface) of the wiring layer 26 is formed on the insulating layer 25. The solder resist layer 27 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin to the upper surface of the insulating layer 25 so as to cover the wiring layer 26 by a screen printing method, a roll coating method, a spin coating method, or the like. Alternatively, for example, the solder resist layer 27 may be formed by laminating a film-like photosensitive epoxy insulating resin on the upper surface of the insulating layer 25 so as to cover the wiring layer 26. The openings 27x can be formed, for example, by exposing and developing the solder resist layer 27.

[0040] 4 to 6, plating layer 28 is formed in a first region and a second region that are independent of each other on the second surface (upper surface) of wiring layer 26 exposed from openings 27x of solder resist layer 27. Note that, although an example in which plating layer 28 is formed in the first region and the second region will be described here, plating layer 28 may be formed in three or more regions that are independent of each other.

[0041] 4, a resist layer 310 having openings 310x exposing the first and second regions where the plating layer 28 is to be formed is formed on the second surface (upper surface) of the wiring layer 26 exposed from the openings 27x of the solder resist layer 27. The method for forming the resist layer 310 and the openings 310x is the same as the method for forming the resist layer 300 and the openings 300x, for example.

[0042] 5, a plating layer 28 is formed in the first and second regions exposed from the openings 310x of the resist layer 310. The plating layer 28 can be formed on the second surface (upper surface) of the wiring layer 26 exposed from the openings 310x of the resist layer 310, for example, by electrolytic plating in which power is supplied from the wiring layer 26. The plating layer 28 may be formed by electroless plating. Note that the plating layer 28 may be a single layer or multiple layers, as described above.

[0043] 6, the resist layer 310 is removed. The resist layer 310 can be removed using, for example, a stripping solution. As a result, the plating layer 28 is formed in the first region and the second region, which are independent of each other, on the second surface (upper surface) of the wiring layer 26 exposed from the openings 27x of the solder resist layer 27.

[0044] Next, in the process shown in FIG. 7, the wiring layer 26 exposed from the plating layer 28 is removed by etching using the plating layer 28 as a mask. This separates the first region from the second region, and forms a first pad 26a for external connection including the first region, a second pad 26b for external connection including the second region, and wiring 26c. The first pad 26a is formed to have a portion facing the second pad 26b without sandwiching the solder resist layer 27. When the wiring layer 26 is a copper layer, for example, an aqueous solution of sulfuric acid and hydrogen peroxide, an aqueous solution of sodium persulfate, an aqueous solution of ammonium persulfate, or the like can be used as the etching solution. At this time, the plating layer 28 formed of a Ni layer, a Pd layer, an Au layer, or the like is not removed by the etching solution for the copper layer.

[0045] Here, the technical significance of wiring board 1 will be described with reference to a comparative example.

[0046] 8 is a diagram illustrating a part of a manufacturing process of a wiring board according to a comparative example. Here, a process of forming first pads 26x, second pads 26y, a solder resist layer 27, and a plating layer 28A on a wiring board on which lamination of insulating layer 25 has been completed is described.

[0047] First, in the process shown in FIG. 8(a), after forming the via hole 25x in the insulating layer 25, the first pad 26x and the second pad 26y are formed on the insulating layer 25. Specifically, after forming the via hole 25x by a laser processing method, a resist layer 320 having an opening 320x exposing the region where the first pad 26x and the second pad 26y are to be formed is formed on the upper surface of the insulating layer 25. The method of forming the resist layer 320 and the opening 320x is, for example, the same as the method of forming the resist layer 300 and the opening 300x. The first pad 26x and the second pad 26y can be formed in the via hole 25x exposed in the opening 320x and on the upper surface of the insulating layer 25 by, for example, a well-known semi-additive method. Next, in the process shown in FIG. 8(b), the resist layer 320 is peeled off.

[0048] Next, in the step shown in FIG. 8(c), a solder resist layer 27 having openings 27x that selectively expose the upper surfaces of the first pads 26x and the second pads 26y is formed on the insulating layer 25 in the same manner as in the step shown in FIG. 3. The first pads 26x have an NSMD structure, and the second pads 26y have an SMD structure. In this step, a part of the inner wall surface of the openings 27x of the solder resist layer 27 contacts the insulating layer 25. In order to form the openings 27x so that the inner wall surface of the openings 27x contacts the insulating layer 25, it is necessary to expose the solder resist layer 27 to light up to a deep portion. However, the deep portion of the solder resist layer 27 is easily scraped off during development because light does not easily reach the deep portion during exposure and the deep portion is weakly solidified. Therefore, as shown in FIG. 8(c), an undercut 27z may be formed in the portion of the inner wall surface of the openings 27x that contacts the insulating layer 25. When the undercut 27z is formed, there is a risk that the solder resist layer 27 will peel off starting from the undercut 27z. The deep portion of the solder resist layer 27 refers to a portion that is lower than the height of the upper surfaces of the first pads 26x and the second pads 26y with the upper surface of the insulating layer 25 as the reference point.

[0049] Next, in the step shown in FIG. 8(d), a plating layer 28A is formed on the first pad 26x and the second pad 26y exposed from the opening 27x of the solder resist layer 27. The plating layer 28A can be formed by electroless plating using the same material as the plating layer 28, for example. In FIG. 8(c) before the plating layer 28A is formed, the upper surface and part of the side surface of the first pad 26x and the second pad 26y are exposed from the opening 27x of the solder resist layer 27. Therefore, the plating layer 28A is formed not only on the upper surface of the first pad 26x and the second pad 26y exposed from the opening 27x of the solder resist layer 27, but also on the side surface of the first pad 26x and the second pad 26y exposed from the opening 27x of the solder resist layer 27. Furthermore, the plating layer 28A extends from the side surface of the first pad 26x and the second pad 26y to the upper surface of the insulating layer 25 to form an extension portion 28z. The length of the extension portion 28z is, for example, about 10 μm. As a result, the distance between the adjacent first pad 26x and second pad 26y is effectively narrowed, which reduces HAST resistance and raises concerns about insulation failure. Here, HAST resistance refers to resistance to a HAST (Highly Accelerated temperature and humidity Stress Test). The HAST test is one of the environmental tests standardized by IEC68-2-66.

[0050] In contrast, in the wiring board 1, the plating layer 28 is formed on the wiring layer 26, and then the wiring layer 26 is etched to form the first pad 26a and the second pad 26b, so that the plating layer 28 is not formed on the side surfaces of the first pad 26a and the second pad 26b. Therefore, in the wiring board 1, the extension portion 28z as shown in FIG. 8(d) is not formed, so that the distance between the adjacent first pad 26a and the second pad 26b is not substantially narrowed by the extension portion 28z. As a result, the wiring board 1 has improved HAST resistance and can maintain good insulation properties compared to the wiring board according to the comparative example. This is particularly effective when the distance between the first pad 26a and the second pad 26b is narrow.

[0051] In addition, in the wiring board 1, the first pad 26a and the second pad 26b are formed by etching the wiring layer 26 after forming the solder resist layer 27, so that the inner wall surface of the opening 27x of the solder resist layer 27 is separated from the insulating layer 25 and does not contact the upper surface of the insulating layer 25. That is, when forming the opening 27x, it is not necessary to expose a deep portion of the solder resist layer 27 to light. Therefore, the undercut 27z as shown in FIG. 8(c) is unlikely to be formed, and the risk of peeling of the solder resist layer 27 can be reduced.

[0052] Modification of the First Embodiment In the modified example of the first embodiment, an example of a wiring board having a pad structure different from that of the first embodiment is shown. Note that in the modified example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0053] Fig. 9 is a diagram illustrating a wiring board according to Modification 1 of the first embodiment. Fig. 10 is a diagram illustrating a wiring board according to Modification 2 of the first embodiment. Fig. 11 is a diagram illustrating a wiring board according to Modification 3 of the first embodiment. In Figs. 9 to 11, (a) is a plan view corresponding to region P in Fig. 1, and (b) is a cross-sectional view taken along line AA in (a). Although (a) is a plan view, hatching corresponding to the cross-sectional view in (b) is shown for the sake of ease of understanding.

[0054] As shown in FIG. 9, the wiring board 1A is different from the wiring board 1 in that the second pad 26b is replaced with the second pad 26d. The first pad 26a and the second pad 26d both have an NSMD structure. That is, the second surface (upper surface) and the side surface of the first pad 26a and the second pad 26d are entirely exposed from the solder resist layer 27. The regions of the second surface (upper surface) of each of the first pad 26a and the second pad 26d exposed from the solder resist layer 27 are covered with the plating layer 28. The regions of the side surfaces of each of the first pad 26a and the second pad 26d exposed from the solder resist layer 27 are exposed from the plating layer 28. In the case of such a structure, the same effect as that of the wiring board 1 is also achieved.

[0055] As shown in FIG. 10, the wiring board 1B is different from the wiring board 1 in that the first pad 26a is replaced with the first pad 26e. The first pad 26e and the second pad 26b both have an SMD structure. That is, the second surface (upper surface) and part of the side surface of the first pad 26e and the second pad 26b are covered with a solder resist layer 27. The areas of the second surface (upper surface) of each of the first pad 26e and the second pad 26b that are exposed from the solder resist layer 27 are covered with a plating layer 28. The areas of the side surfaces of each of the first pad 26e and the second pad 26b that are exposed from the solder resist layer 27 are exposed from the plating layer 28. In the case of such a structure, the same effects as those of the wiring board 1 are also achieved.

[0056] 11, wiring board 1C differs from wiring board 1 in that it further includes surface treatment layer 29. Surface treatment layer 29 covers the surface (upper surface and side surface) of plating layer 28 exposed from solder resist layer 27, and also covers the side surfaces of first pad 26a and second pad 26b and the area of ​​the side surface of wiring 26c exposed from solder resist layer 27.

[0057] The surface treatment layer 29 may be a single-layer or multi-layer metal layer exemplified as the surface treatment layer in the first embodiment. Alternatively, an organic coating formed by OSP treatment may be used as the surface treatment layer 29. The surface treatment layer 29 may have the same configuration as the plating layer 28. For example, when the plating layer 28 is a Ni / Pd / Au layer, the surface treatment layer 29 may be a Ni / Pd / Au layer. The surface treatment layer 29 is thinner than the plating layer 28. The thickness of the surface treatment layer 29 is preferably about 1 / 10 to 1 / 5 of the thickness of the plating layer 28.

[0058] 7, a step of forming surface treatment layer 29 thinner than plating layer 28 may be further performed. In this step, surface treatment layer 29 may be formed by electroless plating or the like so as to cover the surface of plating layer 28 exposed from solder resist layer 27 and to cover the side surfaces of first pad 26a and second pad 26b and the region of side surface of wiring 26c exposed from solder resist layer 27.

[0059] In this way, by covering the side surfaces of the first pads 26a and the second pads 26b and the side surfaces of the wiring 26c in the areas exposed from the solder resist layer 27 with the surface treatment layer 29, it is possible to prevent corrosion (oxidation, etc.) of the side surfaces of the first pads 26a and the second pads 26b and the side surfaces of the wiring 26c. Note that since the surface treatment layer 29 is significantly thinner than the plating layer 28, no extensions such as the extensions 28z shown in FIG. 8(d) are formed in the wiring board 1C. Therefore, the presence of the surface treatment layer 29 does not reduce the HAST resistance.

[0060] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0061] For example, in the above embodiment and modified example, an example was shown in which the present invention is applied to the pads on the side of the wiring board that connects to a motherboard or the like. However, the present invention may also be applied to the pads on the side of the wiring board that connects to a semiconductor chip or the like. Alternatively, the present invention may be applied to both the pads on the side of the wiring board that connects to a motherboard or the like and the pads on the side of the wiring board that connects to a semiconductor chip or the like. [Explanation of symbols]

[0062] 1,1A,1B,1C Wiring board 10 Core Layer 10a One side 10b The other side 10x through holes 11 Through Wiring 12, 14, 16, 22, 24, 26 wiring layer 13, 15, 23, 25 Insulating layer 13x, 15x, 23x, 25x via holes 17, 27 Solder resist layer 17x, 27x opening 26a, 26e 1st pad 26b, 26d 2nd pad 26c Wiring 28 Plating layer 29 Surface treatment layer

Claims

1. An insulating layer; a first pad and a second pad for external connection provided on the insulating layer, each of which has a first surface in contact with the insulating layer, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface; a protective insulating layer provided on the insulating layer, each of the first pad and the second pad has a portion exposed within an opening in the protective insulating layer; the first pad has a portion facing the second pad without the protective insulating layer therebetween; a region of each of the first pad and the second pad that is exposed from the protective insulating layer on the second surface is covered with a plating layer; A wiring board, wherein an area of ​​the side surface of each of the first pad and the second pad that is exposed from the protective insulating layer is exposed from the plating layer.

2. The wiring board according to claim 1 , wherein an inner wall surface of the opening of the protective insulating layer is separated from the insulating layer.

3. 2 . The wiring board according to claim 1 , further comprising: a wiring formed on the same surface of the insulating layer as the first pad and the second pad, the wiring having a portion exposed from an inner wall surface of the opening in the protective insulating layer.

4. Further, the plated layer has a surface treatment layer which is thinner than the plated layer. The wiring board according to claim 1 , wherein the surface treatment layer covers a surface of the plating layer exposed from the protective insulating layer and covers an area of ​​the side surface of each of the first pad and the second pad exposed from the protective insulating layer.

5. the second surface and the side surface of the first pad are entirely exposed from the protective insulating layer; The wiring board according to claim 1 , wherein the second surface and a part of the side surface of the second pad are covered with the protective insulating layer.

6. The wiring board according to claim 1 , wherein the second surface and the side surface of the first pad and the second pad are entirely exposed from the protective insulating layer.

7. The wiring board according to claim 1 , wherein the second surface and the side surface of the first pad and the second pad are partially covered with the protective insulating layer.

8. forming a wiring layer on an insulating layer, the wiring layer having a first surface in contact with the insulating layer and a second surface opposite to the first surface; forming a protective insulating layer on the insulating layer to selectively expose the second surface of the wiring layer; forming a plating layer on a first region and a second region independent of each other on the second surface exposed from the protective insulating layer; and removing the wiring layer exposed from the plating layer by etching to separate the first region and the second region, and forming a first pad for external connection including the first region and a second pad for external connection including the second region, The first pad has a portion facing the second pad without the protective insulating layer therebetween.

9. The method further includes, before the step of forming the plating layer, a step of forming a resist layer on the second surface exposed from the protective insulating layer, the resist layer exposing the first region and the second region; In the step of forming the plating layer, the plating layer is formed in the first region and the second region exposed from the resist layer, The method for manufacturing a wiring board according to claim 8 , further comprising removing the resist layer after forming the plating layer.

10. The method further includes a step of forming a surface treatment layer thinner than the plating layer after the step of forming the first pad and the second pad, 10. The method for manufacturing a wiring board according to claim 8 or 9, wherein the surface treatment layer is formed so as to cover a surface of the plating layer exposed from the protective insulating layer and to cover an area of ​​each side of the first pad and the second pad exposed from the protective insulating layer.

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