Semiconductor element and manufacturing method thereof

Abstract

To provide a semiconductor element and a manufacturing method for improving switching characteristics.SOLUTION: A semiconductor element includes a first conductivity type semiconductor substrate 100, a first conductivity type epitaxial layer 110 disposed on the semiconductor substrate, a plurality of trenches 120 formed in an epitaxial layer, a shield insulating film 130 formed inside the plurality of trenches, a shield electrode 140 formed in the lower part of the plurality of trenches and surrounded by the shield insulating film, an inter-electrode insulating film layer 150 formed on the shield insulating film and the shield electrode, a gate insulating film 160 disposed on the inter-electrode insulating film layer, a gate electrode 170 disposed on the gate insulating film, a second conductivity type body region 210 formed on the upper part of the epitaxial layer between the plurality of trenches, a source region 220 formed on the body region, and an interlayer insulating film 230 formed on an upper surface of the gate electrode and an upper surface of the source region, and the position and thickness of the gate electrode are determined by the position and thickness of the inter-electrode insulating film layer.SELECTED DRAWING: Figure 1a

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a trench MOSFET structure in which a split gate trench structure is applied, a shield electrode or a source electrode is formed in a lower part of the trench, and a gate electrode is formed in an upper part of the trench, and a manufacturing method thereof. [Background technology]

[0002] Electrical and electronic products require increasingly complex circuits and high performance technology. In order to reduce the power consumption of such products and maximize efficiency, high performance power semiconductor elements are required, and in particular, the demand for power discrete trench MOSFET elements is increasing.

[0003] In a semiconductor device having a power trench MOSFET structure, the breakdown voltage and switching characteristics are important factors for measuring the performance of the MOSFET device. Furthermore, it is also necessary to reduce the high breakdown voltage and ON-resistance in order to improve the characteristics of the semiconductor device.

[0004] As an example of the conventional technology, a power MOSFET having a triple poly structure has a structure in which a shield poly electrode is formed in a trench, and a gate poly electrode is formed on both sides of the upper part of the shield poly electrode. In this conventional technology, it is not easy to simultaneously secure a stable breakdown voltage and ON-OFF switching. In a power MOSFET having a triple poly structure, a gate poly electrode must be formed on both sides of the upper part of the shield poly electrode, so that a parasitic capacitance occurs between the shield poly electrode and the gate poly electrode, and thus the parasitic capacitance between the shield poly electrode and the gate poly electrode is high. In order to reduce the parasitic capacitance, the area of ​​the gate poly electrode must be reduced or the thickness of the oxide, which is an insulating film formed between the shield poly electrode and the gate poly electrode, must be secured. However, if the area of ​​the gate poly electrode is reduced, it becomes difficult to secure a certain level of breakdown voltage. In addition, in order to improve the parasitic capacitance, the thickness of the oxide disposed between the gate poly electrode and the shield poly electrode must be increased, but in this case, the width of the trench increases by increasing the thickness of the oxide, making it difficult to secure a small cell pitch, i.e., it is difficult to secure many cells in a power trench MOSFET device, making it difficult to increase the integration density of cells in a MOSFET device.

[0005] In addition, the triple poly structure of the prior art has gate poly electrodes formed on both sides of the top of the shield poly electrode, which reduces the input capacitance (C iss ) value also increases. Here, the input capacitance means the capacitance that is charged when the element is turned on. The smaller this value is, the faster the input switching speed when turned on is. The input capacitance value is C iss =C gs +C gdHowever, since there are two gate poly electrodes, C gs This increases the input capacitance (C iss ) value. g ) value becomes large, and switching loss occurs. If the gate charge value is large, it takes time to charge up to the capacity required to turn the power mosfet on, and switching loss becomes large. Therefore, it is necessary to improve the switching characteristics. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2010-56552 A Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made in consideration of the above-mentioned problems in the conventional art, and an object of the present invention is to provide a semiconductor device having improved switching characteristics and a method for manufacturing the same. [Means for solving the problem]

[0008] Therefore, in order to solve the above problems, in various embodiments of the present invention, a split gate trench structure is applied to a power trench mosfet device, and a shield electrode is formed in the lower part of the trench and a gate electrode is formed in the upper part of the trench, thereby realizing a small cell pitch.

[0009] Also, by optimizing the thickness of the gate electrode, the input capacitance and parasitic capacitance are reduced while maintaining the breakdown voltage, thereby realizing fast switching characteristics.

[0010] In addition, by optimizing the etching process of the shield electrode and the thickness of the insulating layer of the inter-electrode formed between the shield electrode and the gate electrode, a low input capacitance (C iss ) value.

[0011] In addition, a split gate trench structure is applied to reduce the cell pitch compared to conventional technologies, thereby improving the integration of cells within a MOSFET device.

[0012] In addition, the device manufacturing process, which involves multiple ion implantation processes for the body region, a gate poly recess process, and a multi-epi structure, allows the device to maintain the desired breakdown voltage while reducing the on-resistance (R on ) and capacitance characteristics.

[0013] In order to achieve the above-mentioned object, a semiconductor element according to one aspect of the present invention comprises a first conductivity type semiconductor substrate, a first conductivity type epitaxial layer arranged on the semiconductor substrate, a plurality of trenches formed in the epitaxial layer, a shield insulating film formed inside the plurality of trenches, a shield electrode formed in a lower portion of the plurality of trenches and surrounded by the shield insulating film, an insulating film layer of an inter-electrode formed on the shield insulating film and the shield electrode, a gate insulating film arranged on the insulating film layer of the inter-electrode, a gate electrode arranged on the gate insulating film, a body region of a second conductivity type formed on an upper surface of the epitaxial layer between the plurality of trenches, a source region formed on the body region, an interlayer insulating film formed on an upper surface of the gate electrode and an upper surface of the source region, and a body contact region in contact with the source region and the body region, and the position and thickness of the gate electrode are determined by the position and thickness of the insulating film layer of the inter-electrode.

[0014] According to an embodiment, the position and thickness of the insulating layer of the inter-electrode are determined by the depth to which the shield electrode is etched. According to one embodiment, a thickness ratio of the insulating film of the inter-electrode to the gate electrode is 1:1 to 1:10. According to one embodiment, a thickness ratio of the insulating film of the inter-electrode to the shield electrode is 1:3 to 1:15. In one embodiment, an upper surface of the body region is disposed below an upper surface of the gate electrode. According to one embodiment, a thickness ratio of the shield electrode to the gate electrode is 1:1 to 15:1. According to one embodiment, the trenches are formed such that the side surfaces of the trenches are inclined at an angle of 85° to 90° with respect to the entrances of the trenches. According to an embodiment, the shield insulating layer is deposited by a first thermal oxidation process, or by performing a second chemical vapor deposition (CVD) process after the first thermal oxidation process. In one embodiment, the semiconductor device further includes a metal layer formed on the body region, the source region, and the interlayer insulating film.

[0015] In order to achieve the above object, a method for manufacturing a semiconductor device according to one aspect of the present invention includes the steps of forming an epitaxial layer of a first conductivity type on a semiconductor substrate of a first conductivity type, forming a plurality of trenches in the epitaxial layer, forming a shield insulating film inside the plurality of trenches, forming a shield electrode surrounded by the shield insulating film at a lower part of the plurality of trenches, forming an insulating film layer of an inter-electrode on the shield insulating film and the shield electrode inside the plurality of trenches, forming a gate insulating film disposed on the insulating film layer of the inter-electrode, forming a gate electrode disposed on the gate insulating film, forming a body region of a second conductivity type on an upper part of the epitaxial layer between the plurality of trenches, forming a source region on the body region, forming an interlayer insulating film on an upper surface of the gate electrode and an upper surface of the source region, and forming a body contact region in contact with the source region and the body region, and the position and thickness of the gate electrode are determined by the position and thickness of the insulating film layer of the inter-electrode.

[0016] According to one embodiment, the step of forming an inter-electrode insulating layer on the shield insulating film and the shield electrode inside the plurality of trenches includes determining a position and a thickness of the inter-electrode insulating layer depending on the depth to which the shield electrode is etched. In one embodiment, forming the epilayer comprises forming at least two or more epilayers. In one embodiment, forming the epilayer includes forming the epilayer to a thickness that is within three times the depth of the trench. According to an embodiment, forming the trench includes forming the epitaxial layer, depositing a mask, and then performing an etching process to form the trench, and forming a side of the trench at an angle of 85° to 90° based on an entrance of the trench. According to one embodiment, forming the trench includes forming a sacrificial oxide layer to repair damage or uneven areas on an inner wall of the epitaxial layer during an etching process to form the trench. According to one embodiment, the step of forming the shield insulating layer includes forming the shield insulating layer by a first thermal oxidation process, or by performing a first thermal oxidation process followed by a second chemical vapor deposition (CVD) process. According to one embodiment, the step of forming the shield electrode includes the steps of depositing a shield poly from inside the shield insulating film to above its upper surface, etching the shield poly to the upper surface of the trench by performing a CMP process or etching the shield poly to the height of the upper surface of the epilayer by performing a blanket etching process, and further etching the shield poly etched to the height of the upper surface of the trench or the upper surface of the epilayer within the trench to a position where the insulating film of the inter-electrode will be formed, thereby forming the shield electrode. In one embodiment, forming the shield electrode includes etching a portion of a side of the shield insulating film to increase a width of an opening of the shield insulating film disposed over the shield electrode. According to one embodiment, the step of forming the insulating layer of the interelectrode includes depositing polyoxide on the upper surface of the shield electrode and the surface of the shield insulating layer through a CVD process, then performing a CMP process, a blanket etching process, or a combination of the CMP process and the blanket etching process to etch the polyoxide down to the upper surface of the epilayer, and dry etching, wet etching, or a combination of dry and wet etching of the insulating layer of the interelectrode so that an insulating layer of the interelectrode etched down to the upper surface of the epilayer is formed in the trench. According to an embodiment, a thickness ratio of the insulating film of the inter-electrode formed in the trench to the gate electrode is 1:1.2 to 1:3. According to one embodiment, the step of forming the gate electrode includes the steps of depositing a gate poly on the shield insulating film and the gate insulating film, performing a CMP process on the gate poly to an upper surface of the epitaxial layer, and performing a recess etching process on the gate poly after the CMP process so that the gate poly is lower than the upper surface of the epitaxial layer. In one embodiment, the recess etch process includes etching the gate poly to a thickness of 500 Å to 5000 Å. In one embodiment, forming the body region includes forming the body region with a maximum thickness from a top of the epitaxial layer to a depth of the gate electrode formed on an upper surface of the insulating layer of the inter-electrode. In one embodiment, the method further includes forming a metal layer over the body region, the source region, and the interlayer dielectric. Effect of the Invention

[0017] According to the present invention, a power trench MOSFET device employs a split poly trench structure to form a shield electrode inside the trench and a gate electrode on the shield electrode, thereby realizing a small cell pitch and thereby improving the integration density of the MOSFET device.

[0018] In addition, by optimizing the thickness of the gate electrode, the capacitance characteristics and the total charge of the gate (Q g ) value can be reduced to implement fast switching characteristics.

[0019] In addition, by providing an inter-electrode insulating film (IPO: Inter Poly Oxide) layer of an appropriate thickness between the shield electrode and the gate electrode, the switching characteristics of the device, including the input capacitance and parasitic capacitance, can be improved without reducing the breakdown voltage.

[0020] In addition, the desired input capacitance (C iss ) value, feedback capacitance (C rss ) value and breakdown voltage value can be ensured.

[0021] In addition, the thickness ratio of the shield electrode, gate electrode, and insulating film of the inter-electrode is optimized to obtain the desired input capacitance (C iss ) value, feedback capacitance (C rss ) value and breakdown voltage value can be ensured.

[0022] The effects obtained by the present invention are not limited to those mentioned above. Other effects not mentioned will be clearly understood by those having ordinary skill in the art to which the present invention pertains from the following description. [Brief description of the drawings]

[0023] [Figure 1a] 1 is a diagram showing a structure of a semiconductor device according to an embodiment of the present invention; [Figure 1b] 2 is a diagram illustrating thicknesses of components of a semiconductor device according to one embodiment of the present invention. [Diagram 2] 2A and 2B are diagrams illustrating the structure of a trench formed in an epi layer according to one embodiment of the present invention. [Diagram 3] 1 is a diagram showing a structure of a shield insulating film according to an embodiment of the present invention; [Figure 4a] 5A to 5C are diagrams illustrating a process of forming a shield electrode according to an embodiment of the present invention. [Figure 4b] 5A to 5C are diagrams illustrating a process of forming a shield electrode according to an embodiment of the present invention. [Figure 4c] 5A to 5C are diagrams illustrating a process of forming a shield electrode according to an embodiment of the present invention. [Figure 4d] 5A to 5C are diagrams illustrating a process of forming a shield electrode according to an embodiment of the present invention. [Figure 4e] 5A to 5C are diagrams illustrating a process of forming a shield electrode according to an embodiment of the present invention. [Figure 5a] 4A to 4C are diagrams illustrating a process of forming an insulating film layer of an inter-electrode according to an embodiment of the present invention. [Figure 5b] 4A to 4C are diagrams illustrating a process of forming an insulating film layer of an inter-electrode according to an embodiment of the present invention. [Figure 5c] 4A to 4C are diagrams illustrating a process of forming an insulating film layer of an inter-electrode according to an embodiment of the present invention. [Figure 6] 1 is a diagram showing a structure of a gate insulating film according to an embodiment of the present invention; [Figure 7a] 1A to 1C are diagrams illustrating a process of forming a gate electrode according to an embodiment of the present invention. [Figure 7b] 1A to 1C are diagrams illustrating a process of forming a gate electrode according to an embodiment of the present invention. [Figure 7c] 1A to 1C are diagrams illustrating a process of forming a gate electrode according to an embodiment of the present invention. [Figure 8] 2A to 2C are diagrams illustrating a process of forming a body region, a source region, and an interlayer insulating film according to an embodiment of the present invention. [Figure 9] 2 is a diagram showing a structure of a metal layer according to one embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The advantages and features of the present invention, as well as the methods for achieving them, will be clearly understood by referring to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. Therefore, it should be understood that the embodiments disclosed below are provided merely to make the disclosure of the present invention complete and to fully inform those skilled in the art to which the present invention pertains. That is, the present invention is defined only by the claims. And, the same reference numerals refer to the same elements throughout this specification.

[0025] In the description of the embodiments of the present invention, when one component is described as being "connected to" or "coupled to" another component, it includes not only the case where the component is directly connected or coupled to the other component, but also the case where there is another component in between. In contrast, when one component is described as being "directly connected to" or "directly coupled to" another component, it means that there is no other component in between. And "and / or" includes each and every combination of one or more of the mentioned items.

[0026] The terms used in the description of the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention. In the description of the embodiments, the singular form includes the plural form unless otherwise specified in the text. And, the words "comprises" and / or "comprsing" used in the description of the embodiments do not exclude that the components, steps, operations, and / or elements referred to have one or more different components, steps, operations, and / or elements.

[0027] In addition, although terms such as "first" and "second" are used to describe various components, the components are not limited by these terms, and these terms are used merely to distinguish one component from another component.

[0028] Therefore, the first component referred to below may be the second component within the scope of the technical idea of ​​the present invention. Unless otherwise defined, all terms (including technical and scientific terms) used in this specification are used in the sense commonly understood by those having ordinary knowledge in the technical field to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless otherwise defined.

[0029] The term "unit" or "module" used in the embodiments of the present invention means a software component or a hardware component such as an FPGA or an ASIC, and the "unit" or "module" performs a certain function. However, the meaning of "unit" or "module" is not limited to software or hardware. The "unit" or "module" may be configured to reside on an addressable recording medium or to execute one or more processors. Thus, as an example, the "unit" or "module" includes components such as software components, object-oriented software components, class components, task components, etc., as well as processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided in these components and "units" or "modules" may be combined into a "unit" or "module" with fewer components, or may be further separated into a "unit" or "module" from additional components.

[0030] Each step of the method or algorithm described in relation to some embodiments of the present invention may be embodied by hardware, software modules, or a combination thereof, executed by a processor. The software modules may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. Illustratively, the storage medium is coupled to the processor, and the processor reads information from the storage medium and records the information on the storage medium. Alternatively, the storage medium is integral to the processor. The processor and the storage medium may reside in an application-on-demand integrated circuit (ASIC). The ASIC may also reside in a user terminal.

[0031] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings, in which: FIG.

[0032] A structure of a semiconductor device according to an embodiment of the present invention will now be described.

[0033] FIG. 1a is a diagram showing a structure of a semiconductor device according to one embodiment of the present invention.

[0034] 1a, a semiconductor device according to an embodiment of the present invention includes a semiconductor substrate 100 having a first conductivity type.

[0035] The semiconductor substrate 100 has a first conductivity type that has a higher concentration of dopants of the first conductivity type than the epi layer 110 .

[0036] The epitaxial layer 110 has the same first conductivity type as the semiconductor substrate 100 having the first conductivity type. The epitaxial layer 110 is formed in at least two layers by performing a multi-epi formation process, where a lower epitaxial layer (not shown) is formed on the semiconductor substrate 100, and an upper epitaxial layer (not shown) is formed on the lower epitaxial layer. The lower epitaxial layer has a reduced resistivity due to an increase in the concentration of the lower epitaxial layer as a result of the diffusion of the first conductivity type dopant in the semiconductor substrate 100 into the lower epitaxial layer by a thermal process performed as a post-process. The upper epitaxial layer has a relatively low diffusion of the first conductivity type dopant and a lower concentration of the first conductivity type dopant than the lower epitaxial layer, so that the resistivity of the epitaxial layer is relatively high. As a result, the resistivity of the epitaxial layer of the drift layer is reduced overall, resulting in a low on-resistance (R dson The epitaxial layer 110 is formed to a thickness of 2 μm to 15 μm, which is within three times the depth of the trench 120.

[0037] The shield insulating layer 130 is formed inside the plurality of trenches 120. The shield insulating layer 130 is formed through a first thermal oxidation process and a second deposition process.

[0038] The shield electrode 140 is formed within the plurality of trenches 120 and surrounded by the shield insulating film 130. The shield electrode 140 is formed within the shield insulating film 130 by performing a deposition process of a shield poly.

[0039] The inter-electrode insulating layer 150 is formed on the shield insulating layer 130 and the shield electrode 140 inside the multiple trenches 120. By adjusting the area of ​​the inter-electrode insulating layer 150, a desired input capacitance value and a total charge amount (Q q The inter-electrode insulating layer 150 is also called an inter-electrode insulating film made of oxide, an inter-electrode oxide layer (Inter Poly Oxide Layer), or an inter-electrode dielectric layer (Inter Poly Dielectric).

[0040] The gate insulating film 160 is formed to be disposed on the inter-electrode insulating film layer 150 inside the plurality of trenches 120. The gate insulating film 160 is formed on the upper surface of the inter-electrode insulating film layer 150, the sidewalls of the trenches 120, and a portion of the upper surface of the epitaxial layer 110 through a deposition process.

[0041] The gate electrode 170 is formed to be disposed on the gate insulating film 160. The gate electrode 170 is formed by recess etching the gate poly from the upper surface of the epitaxial layer 110 to the inside of the trench 120. The thickness A of the gate electrode 170 is adjusted through the recess etching process to adjust the input capacitance (C iss ) value, and the total charge (Q q ) value can be adjusted.

[0042] The gate electrode 170 disposed within the trench 120 is referred to as the upper electrode, and the shield electrode 140 is referred to as the lower electrode.

[0043] Body regions 210 are formed in the upper surface of epilayer 110 on either side of the plurality of trenches 120 .

[0044] The on-resistance (R on ) and capacitance value can be adjusted by forming the body region 210 to different depths depending on the intended device application.

[0045] The source region 220 is formed on the body region 210 .

[0046] The interlayer insulating film 230 is formed on the upper surface of the gate electrode 170 and part of the upper surface of the source region 220 .

[0047] The body contact region 215 contacts the source region 220 and the body region 210. The body contact region 215 is formed in the body region 210 that is formed between the plurality of trenches 120.

[0048] A metal layer 240 is formed on the body region 210, the source region 220, and the interlayer insulating film 230. The metal layer 240 is also called a source electrode that is electrically connected to the source region 220.

[0049] FIG. 1b is a diagram illustrating thicknesses of components of a semiconductor device according to one embodiment of the present invention.

[0050] Referring to FIG. 1b, "A" in the drawing indicates the thickness of the gate electrode 170, "B" indicates the thickness of the shield electrode 140, and "C" indicates the thickness of the insulating film layer 150 of the inter-electrode.

[0051] Moreover, the ratio of the thickness B of the shield electrode 140 to the thickness A of the gate electrode 170 is 1:1 to 15:1.

[0052] By adjusting the thickness A of the gate electrode 170, the area of ​​the interlayer insulating film 230 formed on the gate electrode 170 can be adjusted. In addition, by adjusting the thickness A of the gate electrode 170, the area of ​​the gate electrode 170 can be reduced, thereby changing the capacitance value. In addition, by adjusting the thickness B of the gate electrode 170 and the shield electrode 140, the MOSFET voltage (guaranteed breakdown voltage) can be adjusted. As the thickness B of the shield electrode 140 increases compared to the thickness A of the gate electrode 170, a power MOSFET device with a higher guaranteed breakdown voltage can be implemented.

[0053] The ratio of the thickness C of the insulating film layer 150 of the inter-electrode to the thickness A of the gate electrode 170 is 1:1 to 1:10.

[0054] Moreover, the ratio of the thickness C of the insulating film layer 150 of the inter-electrode to the thickness B of the shield electrode 140 is 1:3 to 1:15.

[0055] By adjusting the thickness, the capacitance value can be adjusted according to the characteristics of the device.

[0056] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.

[0057] FIG. 2 is a diagram showing a structure of a trench formed inside an epitaxial layer according to an embodiment of the present invention. FIG. 3 is a diagram showing a structure of a shield insulating film according to an embodiment of the present invention. FIGS. 4a to 4e are diagrams showing a process of forming a shield electrode according to an embodiment of the present invention. FIGS. 5a to 5c are diagrams showing a process of forming an insulating film layer of an inter-electrode according to an embodiment of the present invention. FIG. 6 is a diagram showing a structure of a gate insulating film according to an embodiment of the present invention. FIGS. 7a to 7c are diagrams showing a process of forming a gate electrode according to an embodiment of the present invention. FIG. 8 is a diagram showing a process of forming a body region, a source region, and an interlayer insulating film according to an embodiment of the present invention, and FIG. 9 is a diagram showing a structure of a metal layer according to an embodiment of the present invention.

[0058] Referring to FIG. 2, an epitaxial layer 110 is formed on a semiconductor substrate 100. The semiconductor substrate 100 is formed to have a first conductivity type. The epitaxial layer 110 is formed to have a first conductivity type similar to the semiconductor substrate 100. The epitaxial layer 110 is formed to have at least two layers, i.e., a multi-epitaxial layer. A lower epitaxial layer (not shown) is formed on the semiconductor substrate 100, and an upper epitaxial layer (not shown) is formed on the lower epitaxial layer. The lower epitaxial layer is diffused with the first conductivity type dopant of the semiconductor substrate 100 into the lower epitaxial layer by a thermal process performed as a post-process, and the resistivity of the lower epitaxial layer is reduced due to the increase in the concentration of the lower epitaxial layer. The upper epitaxial layer is relatively less diffused with the first conductivity type dopant, and the concentration of the first conductivity type dopant is lower than that of the lower epitaxial layer, so that the resistivity of the epitaxial layer is relatively high. This reduces the resistance of the epitaxial layer 110 of the drift layer, resulting in a low on-resistance (R dson The epitaxial layer 110 is formed to a thickness of 2 μm to 15 μm, and is formed to a thickness within three times the depth of a trench 120, which will be described later.

[0059] 2, the plurality of trenches 120 are formed in the epitaxial layer 110. The plurality of trenches 120 are formed by performing a mask process and an etching process after forming the epitaxial layer 110. The plurality of trenches 120 are formed by performing trench etching from the upper surface of the epitaxial layer 110 downward, and the inclination of the side of the trench 120 is at an angle of 85° to 90° based on the entrance of the trench 120. In addition, the plurality of trenches 120 are formed by forming the side of the trench 120 at an angle of 90° to 95° based on the entrance. That is, the width of the lower part of the trench 120 is narrower than or equal to the width of the upper part.

[0060] This is to optimize characteristics such as step coverage, cell pitch, and breakdown voltage of the poly shield formed inside the trench 120 and the gate electrode 170.

[0061] When the trench 120 is etched, it is formed into a U-shape or a V-shape depending on the etching angle.

[0062] The semiconductor substrate 100 and the epitaxial layer 110 are made of silicon or silicon carbide.

[0063] The method further includes forming a sacrificial oxide film (not shown) on the side of the trench 120 after etching the trench 120. The sacrificial oxide film is formed on the side of the trench 120 etched in the epitaxial layer 110. The sacrificial oxide film is used to recover damage or unevenness formed on the inner wall of the epitaxial layer 110 when etching the trench 120. The sacrificial oxide film is formed thinly to a thickness of 100 Å to 1500 Å by performing a thermal process at about 900° C. to 1200° C. The sacrificial oxide film is removed after recovering damage or unevenness formed on the inner wall of the epitaxial layer 110.

[0064] Referring to FIG. 3, the shield insulating film 130 is formed inside the plurality of trenches 120. The shield insulating film 130 is formed by deposition using a first thermal oxidation process. In the first thermal oxidation process, the shield insulating film 130 is deposited to a thickness of 1000 Å to 7000 Å. In another embodiment, the shield insulating film 130 is formed by additionally performing a second chemical vapor deposition (CVD) process after the first thermal oxidation process. In the second chemical vapor deposition (CVD) process, the shield insulating film is deposited to a thickness of 500 Å to 5000 Å. At this time, the first thermal oxide film serves as a buffer layer. The shield insulating film 130 is formed only using a first thermal oxidation process, or is formed using a first thermal oxidation process and a second CVD process.

[0065] The secondary CVD process includes processes such as SACVD (Sub-atmospheric Pressure CVD), PECVD (Plasma-Enhanced CVD), and HDPCVD (High Density Plasma CVD).

[0066] The shield insulating film 130 is formed of a silicon oxide film through a first thermal oxidation process, and is formed of an oxide layer or a nitride layer during a second CVD process, or is formed of a stacked structure of an oxide layer and a nitride layer in another embodiment.

[0067] Referring to FIGS. 4a to 4d, a shield electrode 140 is formed through deposition and etching of shield polys (140a to 140d).

[0068] 4a, after forming the shield insulating film 130, a deposition process of the shield polysilicon 140a is performed on the shield insulating film 130. The thickness of the shield polysilicon 140a deposited on the shield insulating film 130 is 0.3 μm to 8 μm.

[0069] 4b, a portion of the shield poly 140a deposited on the shield insulating film 130 is etched and removed. A CMP process is performed to remove the portion of the shield poly 140a to the height of the entrance of the trench 120, and then a blanket etching process is performed to remove the shield poly 140a to the height of the upper surface of the epitaxial layer 110.

[0070] 4c, the shield poly 140b, which has been etched to the height of the upper surface of the epitaxial layer 110, is further etched to form a shield poly 140c whose upper surface is located inside the trench. The thickness of the inter-electrode insulating film layer 150 is determined by the depth to which the shield poly 140c is etched inside the trench 120. The shield poly 140c serves as a shield electrode 140.

[0071] 4d, a portion of the shield insulating film 130 formed on the side of the trench on the upper side of the shield poly 140d is etched. The width of the opening 131 of the shield insulating film 130 is increased by etching a portion of the shield insulating film 130. This allows the insulating film layer 150 of the inter-electrode to be easily deposited inside the shield insulating film 130 and the trench 120. The etching process is called a partial etching process.

[0072] Referring to Fig. 4e, as an embodiment different from the process described in Fig. 4d, an upper portion of the shield insulating film 130 formed on the side of the trench on the upper side of the shield poly 140d is etched. The upper portion of the shield insulating film 130 is etched to widen the width of the opening 132 of the shield insulating film 130 to be wider than the width of the opening 131 shown in Fig. 4d. The shield insulating film 130 is etched deeper than the upper surface of the shield poly 140d. This allows the insulating film layer 150 of the inter-electrode to be more easily deposited inside the shield insulating film 130 and the trench 120.

[0073] The etching process may be a dry etching process, a wet etching process, or a mixture of these.

[0074] 5a to 5c, inside the plurality of trenches 120, an inter-electrode insulating film layer (150a to 150c) is deposited on the shield insulating film 130 and the shield electrode 140, and then etched to form the inter-electrode insulating film layer 150.

[0075] First, referring to Fig. 5a, after performing the partial etching process shown in Fig. 4d, an inter-electrode insulating film layer 150a is deposited on the shield insulating film 130 and the shield electrode 140. The inter-electrode insulating film layer 150a is deposited by a CVD process. Alternatively, the inter-electrode insulating film layer 150a is deposited by a SACVD (Sub-atmospheric Pressure CVD) process among CVD processes. The inter-electrode insulating film layer 150a is deposited to a thickness of 1000 Å to 15000 Å from the surface of the shield insulating film 130.

[0076] Furthermore, the CVD process includes processes such as PECVD (Plasma-Enhanced CVD) and HDPCVD (High Density Plasma CVD).

[0077] The shield insulating film 130 and the insulating film layer 150a of the inter-electrode may be made of the same material or different materials.

[0078] 5b, a CMP process and a blanket etching process are performed on a portion of the shield insulating film 130 deposited on the upper surface of the epitaxial layer 110 and a portion of the inter-electrode insulating film layer 150a, so that a portion of the shield insulating film 130 is present on the upper surface of the epitaxial layer 110. At this time, the surface of the shield insulating film 130 present on the upper surface of the epitaxial layer 110 and the surface of the inter-electrode insulating film are flush with each other, and the inter-electrode insulating film layer is referred to as "150b."

[0079] Referring to FIG. 5c, the thickness C of the inter-electrode insulating layer 150 in the trench is adjusted by additionally etching the shield insulating layer 130 and the inter-electrode insulating layer 150b. Through the additional etching process, a part of the shield insulating layer 130 formed inside the trench 120 and a part of the upper part of the inter-electrode insulating layer 150b are removed through a dry etching process, a wet etching process, or a combination of these etching processes. The shield insulating layer 130 and a part of the upper part of the inter-electrode insulating layer 150b are removed to form the inter-electrode insulating layer 150c inside the trench 120. The thickness C of the inter-electrode insulating layer 150c formed on the shield electrode 140 in the trench 120 is 1000 Å to 8000 Å. By adjusting the thickness C of the inter-electrode insulating layer 150c through the etching process, the area of ​​the inter-electrode insulating layer 150c can be adjusted. In addition, by adjusting the area of ​​the inter-electrode insulating layer 150c, the input capacitance (C iss ) value, and input capacitance (C iss ) value to drive the total gate charge (Q q ) value can be adjusted.

[0080] FIG. 6 is a diagram showing a structure of a gate insulating film 160 according to an embodiment of the present invention.

[0081] The gate insulating film 160 is formed by a deposition process on the upper surface of the insulating film layer 150 of the inter-electrode formed inside the trench 120, the side surface of the trench 120, and the upper surface of the epitaxial layer 110. The gate insulating film 160 is formed to a thickness of about 100 Å to 1000 Å.

[0082] 7a to 7c, gate polysilicon layers (170a to 170c) are deposited on the gate insulating film 160 and then etched.

[0083] 7a, a gate poly 170a is deposited on the surface of the gate insulating film 160. Thus, the gate poly 170a is deposited from inside the trench 120 to above the upper surface of the epi layer 110.

[0084] 7b, the gate polysilicon 170a deposited on the epitaxial layer 110 is removed by a CMP process to the height of the surface of the gate insulating film 160. Here, the gate polysilicon remaining inside the trench 120 with the gate insulating film 160 sandwiched therebetween is referred to as "170b."

[0085] Referring to FIG. 7c, the gate poly 170b is recess-etched toward the inside of the trench. The gate poly 170c formed by the recess etching is the gate electrode 170, and the thickness A of the gate electrode 170 is adjusted accordingly. The thickness of the gate poly 170c recess-etched from the height of the upper surface of the epitaxial layer 110 is 500 Å to 5000 Å. The thickness A of the gate electrode 170 after the recess etching is 0.3 μm to 1 μm. By adjusting the thickness A of the gate electrode 170 through the recess etching process, the input capacitance value and the total gate charge (Q q ) value can be adjusted.

[0086] 8, a body region 210 is formed on an upper surface of an epitaxial layer 110 between a plurality of trenches 120. Here, the semiconductor substrate 100 and the epitaxial layer 110 have a first conductivity type, and the body region 210 has a second conductivity type. The body region 210 is formed by a single implant process or multiple implant processes. In the multiple implant processes, a first body region forming process and a second body region forming process are separately performed, and the concentrations of the first body region and the second body region are adjusted to be different from each other.

[0087] Furthermore, the top surface of body region 210 is disposed below the top surface of gate electrode 170 .

[0088] When ions are implanted into the body region 210, impurities such as boron, boron fluoride (BF2) or the like are implanted.

[0089] The on-resistance (R on ) value, input capacitance (C iss ) value, and feedback capacitance (C rss ) value is adjusted, the depth of the body region 210 is formed differently depending on the application of the power semiconductor device.

[0090] After forming the body region 210, the source region 220 is formed by a source pattern process. A source photo pattern process is performed to prevent the source region 220 from being formed in a termination region, etc., on the body region 210, except for an active region where the source region 220 is to be formed. After the source photo pattern process is performed, the source region 220 is formed. The source region 220 is formed on the body region 210. The source region 220 has a first conductivity type opposite to the body region 210. After forming the source region 220, the source pattern mask used in the source photo pattern process is removed.

[0091] The impurities used in forming the source region 220 include arsenic and phosphorus. After the source region 220 is formed, the interlayer insulating film 230 is formed. The interlayer insulating film 230 is an ILD (Inter Layer Dielectric). The interlayer insulating film 230 is formed on the upper surface of the gate electrode 170 and the upper surface of the source region 220. The interlayer insulating film 230 is formed by a TEOS (Tetra-Ethyl-Ortho-Silicate) process, a BPSG (Boro Phosphorus Silicate Glass) process, or the like. When the interlayer insulating film 230 is formed by a TEOS process, it is formed to a thickness of about 1000 Å to 5000 Å. When the interlayer insulating film 230 is formed by a BPSG process, it is formed to a thickness of about 1000 Å to 5000 Å.

[0092] A body contact region 215 is formed. The body contact region 215 is formed in the body region 210 formed between the plurality of trenches 120. The body contact region 215 is formed by etching the interlayer insulating film 230. The body contact region 215 is also formed by a contact recess etching process. A metal layer 240 is deposited on the body contact region 215 formed between the interlayer insulating films 230.

[0093] The body contact region 215 is heavily implanted with the second conductivity type, which is a higher concentration than the body region 210 .

[0094] 9, a metal layer 240 is formed. The metal layer 240 is formed to cover the body region 210, the body contact region 215, the source region 220, and the interlayer insulating film 230. The metal layer 240 is formed by performing a deposition process to a certain thickness and then a CMP process.

[0095] The metal layer 240 is formed of a metal material such as aluminum (Al), tungsten (W), or copper (Cu).

[0096] A passivation film (not shown) is formed on the metal layer 240 to protect the elements.

[0097] Metal layer 240 is referred to as the source electrode.

[0098] As described above, the method for manufacturing a semiconductor device according to the embodiment of the present invention can realize a small cell pitch by forming the shield electrode 140 inside the trench 120 and forming the gate electrode 170 on the shield electrode 140 by applying a split gate trench structure. In addition, by minimizing the thickness A of the gate electrode 170, the input capacitance value and the total charge amount (Q q) value, thereby realizing fast switching characteristics.

[0099] In addition, a shield poly recess process and an oxide forming process are used to form an inter-electrode insulating layer 150 having a thickness suitable for device characteristics between the shield electrode 140 and the gate electrode 170, thereby achieving low input capacitance (C iss ) value can be secured.

[0100] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0101] 100 Semiconductor substrate 110 Epilayer 120 Trench 130 Shield insulating film 131, 132 Opening 140 Shield electrode 140a~140d Shielded Poly 150, 150a~150c Insulating film layer 160 Gate insulating film 170 Gate electrode 170a~170c Gate Poly 210 Body Region 215 Body Contact Area 220 Source Region 230 Interlayer insulating film 240 Metal Layer

Claims

1. a semiconductor substrate of a first conductivity type; an epitaxial layer of a first conductivity type disposed on the semiconductor substrate; a plurality of trenches formed in the epitaxial layer; a shield insulating film formed inside the plurality of trenches; a shield electrode formed in a lower portion of the plurality of trenches and surrounded by the shield insulating film; an inter-electrode insulating film layer formed on the shield insulating film and the shield electrode; a gate insulating film disposed on the insulating film layer of the inter-electrode; a gate electrode disposed on the gate insulating film; a body region of a second conductivity type formed on the epilayer between the plurality of trenches; a source region formed on the body region; an interlayer insulating film formed on an upper surface of the gate electrode and an upper surface of the source region; a body contact region in contact with the source region and the body region; A semiconductor device, comprising: a gate electrode; a first insulating layer formed on the first insulating layer and a second insulating layer formed on the second insulating layer;

2. The semiconductor device of claim 1 , wherein the position and thickness of the insulating film layer of the inter-electrode are determined according to the depth to which the shield electrode is etched.

3. 2. The semiconductor device according to claim 1, wherein a ratio of a thickness of the insulating film of the inter-electrode to that of the gate electrode is 1:1 to 1:

10.

4. 2. The semiconductor device according to claim 1, wherein a ratio of a thickness of the insulating film of the inter-electrode to that of the shield electrode is 1:3 to 1:

15.

5. 2. The semiconductor device of claim 1, wherein an upper surface of the body region is disposed below an upper surface of the gate electrode.

6. 2. The semiconductor device of claim 1, wherein a ratio of thicknesses of the shield electrode and the gate electrode is 1:1 to 15:

1.

7. 2. The semiconductor device of claim 1, wherein the trenches are formed such that the sidewalls of the trenches are inclined at an angle of 85° to 90° with respect to the entrance of the trench.

8. 2. The semiconductor device of claim 1, wherein the shield insulating film is deposited by a first thermal oxidation process, or by performing a second chemical vapor deposition (CVD) process after the first thermal oxidation process.

9. 2. The semiconductor device of claim 1, further comprising a metal layer formed on the body region, the source region, and the interlayer insulating film.

10. forming an epitaxial layer of a first conductivity type on a semiconductor substrate of a first conductivity type; forming a plurality of trenches in the epilayer; forming a shield insulating film within the plurality of trenches; forming a shield electrode surrounded by the shield insulating film at a lower portion of the plurality of trenches; forming an inter-electrode insulating layer on the shield insulating layer and the shield electrode within the plurality of trenches; forming a gate insulating film disposed on the insulating film layer of the inter-electrode; forming a gate electrode disposed on the gate insulating film; forming a body region of a second conductivity type on the epilayer between the plurality of trenches; forming a source region above the body region; forming an interlayer insulating film on an upper surface of the gate electrode and an upper surface of the source region; forming a body contact region in contact with the source region and the body region; A method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a first insulating film formed on the first electrode;

11. 11. The method of claim 10, wherein forming an inter-electrode insulating layer on the shield insulating film and the shield electrode inside the plurality of trenches includes determining a position and a thickness of the inter-electrode insulating layer depending on a depth to which the shield electrode is etched.

12. The method of claim 10, wherein the forming of the epitaxial layer comprises forming at least two epitaxial layers.

13. 11. The method of claim 10, wherein forming the epitaxial layer comprises forming the epitaxial layer to a thickness within three times the depth of the trench.

14. 11. The method of claim 10, wherein forming the trench comprises forming the epitaxial layer, depositing a mask, and performing a trench etching process to form the trench, and forming a side of the trench at an angle of 85° to 90° based on an entrance of the trench.

15. 11. The method of claim 10, wherein forming the trench includes forming a sacrificial oxide film to repair damage or uneven areas occurring on an inner wall of the epitaxial layer during an etching process to form the trench.

16. 11. The method of claim 10, wherein forming the shield insulating layer comprises forming the shield insulating layer through a first thermal oxidation process, or through a second chemical vapor deposition (CVD) process after the first thermal oxidation process.

17. 11. The method of claim 10, wherein forming the shield electrode includes depositing a shield poly from inside the shield insulating film to above its upper surface, etching the shield poly to the upper surface of the trench by a CMP process or etching the shield poly to the height of the upper surface of the epilayer by a blanket etching process, and etching the shield poly etched to the height of the upper surface of the trench or the upper surface of the epilayer within the trench to a position where the insulating film of the inter-electrode is to be formed, thereby forming the shield electrode.

18. 11. The method of claim 10, wherein forming the shield electrode includes etching a portion of a side surface of the shield insulating film to widen a width of an opening of the shield insulating film disposed on the shield electrode.

19. 11. The method of claim 10, wherein forming the inter-electrode insulating layer includes depositing polyoxide on the upper surface of the shield electrode and the surface of the shield insulating layer through a CVD process, and then performing a CMP process, a blanket etching process, or a combination of the CMP process and the blanket etching process to etch the polyoxide down to the upper surface of the epitaxial layer, and dry-etching, wet-etching, or a combination of dry and wet-etching the inter-electrode insulating layer so that an inter-electrode insulating layer etched down to the upper surface of the epitaxial layer is formed in the trench.

20. 20. The method of claim 19, wherein a ratio of a thickness of the insulating film of the inter-electrode formed inside the trench to a thickness of the gate electrode is 1:1.2 to 1:

3.

21. 11. The method of claim 10, wherein forming the gate electrode comprises depositing a gate poly on the shield insulating film and the gate insulating film, performing a CMP process on the gate poly to an upper surface of the epitaxial layer, and performing a recess etching process on the gate poly after the CMP process so that the gate poly is lower than an upper surface of the epitaxial layer.

22. 22. The method of claim 21, wherein the recess etching process includes etching the gate poly to a thickness of 500 Å to 5000 Å.

23. 11. The method of claim 10, wherein forming the body region includes forming the body region with a maximum thickness from an upper portion of the epitaxial layer to a depth of the gate electrode formed on an upper surface of the insulating film layer of the inter-electrode.

24. 11. The method of claim 10, further comprising forming a metal layer on the body region, the source region, and the interlayer insulating film.

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