Vehicle control apparatus

Abstract

To solve a problem that in a micro computer for executing a plurality of tasks having execution timings different from one another and priority orders, there is no method of measuring load given to a CPU by respective tasks, which makes it unclear which task increases the load when the CPU load is increased and which makes it difficult to modify a program effectively.SOLUTION: Use of a microcomputer equipped with a CPU having a plurality of cores allows calculation of processing load and processing time of a task whose execution time is to be calculated by reference to the total execution time of the tasks with higher priority when a task with higher priority interrupts during execution of a task whose execution time is to be calculated, with an arrangement that when one core executes a plurality of tasks in a preemptive fashion, the other core records start time and end time of all of the tasks.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a vehicle control device, and more particularly to an on-board control device capable of measuring the processing time of a task to be executed. [Background technology]

[0002] In programs for embedded control, it is common to determine the execution timing of the program according to each function. The execution timing is roughly divided into periodic processing, which executes the program at regular intervals, and interrupt processing, which executes due to external inputs. A group of processes divided according to these execution timings is called a task, and the execution priority is preset and managed by the operating system (OS). Tasks are executed based on this priority, but as the amount of processing increases, the computer (hereinafter referred to as the CPU) cannot keep up with the processing, and a situation may arise in which a task with a higher priority than the task being executed at that time must be processed. In such a case, the engine control unit (hereinafter referred to as the ECU) of the vehicle generally adopts a method called preemptive, which interrupts the processing of a low-priority task currently being executed and executes the processing of a high-priority task first. However, if the amount of processing increases further, the CPU's calculations will not be able to keep up, and there is a possibility that an unacceptable delay will occur in the low-priority task, resulting in a situation in which the low-priority task will not be executed. To prevent this problem, the CPU load rate is defined in advance, and design considerations are made to keep this below a certain value.

[0003] An example of a method for measuring the load factor is the following method described in Japanese Patent Laid-Open No. 11-232148 (Patent Document 1): Note that the idle time is the processing time of the task with the lowest priority. Load factor = (measurement time - idle time) / measurement time [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 11-232148 Summary of the Invention [Problem to be solved by the invention]

[0005] Although the method of Patent Document 1 makes it possible to measure the overall CPU load, it is not possible to measure the load rate for each task. Therefore, when the overall CPU load increases, it becomes unclear which task is increasing the load, making it extremely difficult to make effective program modifications.

[0006] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a processing method that uses a multi-core CPU and implements a task processing time measurement process in one of the cores, thereby recording the load rate for each task in an embedded control program being executed in another core. [Means for solving the problem]

[0007] In order to solve the above problems and achieve the objective, the vehicle control device disclosed herein is a vehicle control device capable of measuring the processing time of a task when multiple tasks including a first task and a second task are executed in series by a microprocessor, and when the processing of the second task interrupts during the execution of the first task, the processing time of the first task is measured based on the execution time of the second task.

[0008] For example, in the vehicle control device of the present disclosure, when a microprocessor executes multiple tasks in series, the start and end times of all tasks are recorded, and when a second task with a higher priority interrupts during the execution of a first task whose execution time it is desired to calculate, the processing load and processing time of the first task whose execution time it is desired to calculate are measured based on the total execution time of the second task with the higher priority. Effect of the Invention

[0009] According to the vehicle control device of the present disclosure, it is possible to calculate the processing time of a task for which the execution time is to be calculated. Therefore, in addition to measuring the load of the CPU core, it is possible to calculate the load ratio for each task, and it is possible to devise a measure to reduce the load more efficiently. [Brief description of the drawings]

[0010] [Figure 1] 1 is a system configuration diagram of a vehicle control device according to an embodiment. [Diagram 2] FIG. 2 is a sequence diagram for explaining the execution status of tasks in the core A in FIG. [Diagram 3] 3 is a diagram for explaining the configuration of data acquired by core B in FIG. 2; [Figure 4] FIG. 2 is a sequence diagram illustrating the processing of core A and core B in FIG. [Diagram 5] 2 is a flowchart illustrating a processing time calculation process of the core B in FIG. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the drawings. EXAMPLES

[0012] 1 is a system configuration diagram of a vehicle control device according to an embodiment, and is a block diagram showing the system configuration of an engine control device (ECU) 1 as a vehicle control device. A central processing unit (CPU) 2 has a core A3 and a core B4 each having a calculation function, and each can execute a program independently. In other words, the CPU 2 can be considered as a one-chip microprocessor formed on a single silicon semiconductor substrate, the core A3 as the first core, and the core B4 as the second core.

[0013] In addition, the memory area of ​​the volatile memory (RAM: Random Access Memory) 5, which can be accessed by both core A3 and core B4, stores variables used in calculations by both cores (core A3, core B4), and includes a storage area 6 and a calculation area 7 required for calculations, which will be described later. The calculation results are also stored in this memory area of ​​the RAM 5.

[0014] Fig. 2 is a sequence diagram for explaining the execution status of a task in the core A in Fig. 1. Fig. 2 is a schematic diagram of an example of the execution status of a task in the core A3 in Fig. 1.

[0015] Task 1 and task 2 are tasks for realizing the original function of ECU 1. A background task (hereinafter, BG task) is a periodic task provided for load measurement of ECU 1, and does not affect the original function of ECU. CPU 2 is configured to execute a plurality of tasks including task 1, task 2, and BG task in series (preemptively). As shown in FIG. 2, the processing priority of the tasks is higher in the order of task 1, task 2, and BG task (processing priority: task 1>task 2>BG task). In this embodiment, as an example, the BG task is executed from t0 [ms], and then task 2 is executed from t1 [ms], and task 1 is executed from t2 [ms]. The BG task executed at t0 [ms] is interrupted by the start of execution of task 2, which has a higher priority than the BG task, at t1 [ms]. Then, the processing of task 2 is interrupted by the start of execution of task 1, which has a higher priority than task 2, at t2 [ms]. At the time t3 [ms], the processing of task 1 is completed, and the processing of task 2, which has the highest priority among the suspended tasks (BG task and task 2), is resumed. After that, at t5 [ms], the processing of task 2 is completed, and the suspended BG task, which has the lowest processing priority, is resumed. During the above processing, core B4 obtains data x (x = 1 to 4) at the start and end of processing of tasks other than the BG task, and stores it in the storage area 6 of RAM 5. Data x (x = 1 to 4) is data summarizing the execution status of tasks in core A3, and is used to calculate the processing time of the tasks. Details are shown in Figure 3.

[0016] That is, ECU1 uses a processing method in which a process for measuring the task processing time (task processing time measurement task) is implemented in core B4 to record the load factor (here, processing time) for each task in the embedded control program being executed on core A3. In this example, when the processing of task 1 interrupts during the execution of task 2, the processing time of task 2 is measured based on the execution time of task 1. By having core B4 measure the processing load of the tasks being executed on core A3, it is possible to calculate the processing load of only the original functions of core A3 without adding the calculation load of the load measurement to core A3, and to suppress an increase in the processing load of core A3.

[0017] In addition, in the case of task 1, task 2, and the BG task, if the BG task is considered to be the first task, then task 2 can be considered to be the second task. Also, if task 2 is considered to be the first task, then task 1 can be considered to be the second task.

[0018] FIG. 3 is a diagram explaining the configuration of data acquired by core B in FIG. 2. FIG. 3 shows the data configuration of data 1 to 4 in FIG. 2. Each of data 1 to 4 is composed of a time, a task status (the status of the start or end of a task), and the number of interrupted tasks, and is memorized or stored in storage area 6. The time is a timestamp of the timing at which the corresponding data was acquired. The status of the start or end of a task is data indicating which task processing has started or ended. The number of interrupted tasks is data indicating how many tasks, including BG tasks, are in an interrupted state, and when a task with a high processing priority interrupts and the processing being performed at that time is interrupted, the number of interrupted tasks in the previous data +1 is stored.

[0019] FIG. 4 is a sequence diagram for explaining the processing of core A3 and core B4 in FIG. 1. Core B4 monitors the task processing in core A3 shown in FIG. 2, and acquires data 1 to 4 between t1 and t5 [ms]. After that, the BG task resumes at t5 [ms], and the BG task notifies core B4 of processing time calculation permission. This triggers core B4 to move data 1 to 4 from storage area 6 in FIG. 1 to calculation use area 7, clear storage area 6, and calculate the processing time of each task executed by core A3 using data 1 to 4 moved to calculation use area 7. The notification of the BG task in core B4 can be performed by defining a processing time calculation permission flag in the memory area of ​​RAM5, and by manipulating the processing time calculation permission flag (for example, changing the flag from 0 (zero) to 1), without the need for direct communication between cores A3 and B4.

[0020] In other words, in a situation where there is no processing task (i.e., the BG task is resumed), core A3 (first core) marks (here, notifies processing time calculation permission or operates the processing time calculation permission flag) to ensure that one set for calculating the processing time of each task is completed. Core B4 (second core) uses the mark as a trigger to read information using data 1 to 4 transferred to calculation use area 7 of RAM 5, and calculates the processing time of each task executed by core A3.

[0021] FIG. 5 is a flowchart for explaining the processing time calculation process of the core B in FIG. 1, and is a flowchart for the calculation process of the processing time in the core B4 after the notification of the BG task processing time calculation permission. In step 501, a loop is set to check all acquired data (from data 1 to task N) individually. In step 502, it is determined whether the task status data of a certain data n is data acquired at the start of the task. If the data being checked in step 502 is data acquired at the start of the task (YES), in step 503, data acquired at the end of the task (hereinafter referred to as task k) is searched from data n+1 onwards (hereinafter referred to as data n'). After that, in step 504, the data of the number of interrupted tasks in the data between data n and data n' is referenced, and if a number larger than the number of interrupted tasks in data n is confirmed (YES), the process proceeds to step 505. In step 505, the interruption time Tk' of task k is calculated. Then, in step 506, the processing time Tk of task k is calculated from the time data tn of data n, the time data tn' of data n', and the interruption time Tk' of task k (processing time Tk = tn'-tn-Tk'). If in step 504 there is no number greater than the number of interrupted tasks in data n (NO), it is determined that task k was not interrupted, and in step 507 the processing time Tk of task k is calculated from tn and tn' (processing time Tk = tn'-tn).

[0022] If the data being checked in step 502 is not the data acquired at the start of the task (NO), the process proceeds to step 501. When all acquired data has been checked in step 501 (NO), the process of calculating the processing time ends (END).

[0023] In the processing time measurement method of the embodiment, the time required to process task 1 is taken into account in the processing time for task 2, so that the processing time for task 2 can be accurately measured. Even if the processing of other tasks besides task 1 is included, the processing times for those tasks can be further taken into account, thereby having the effect of not compromising the accuracy of the measurement of the processing time for task 2.

[0024] According to the embodiment, by using an ECU1 equipped with a CPU having multiple cores (core A3, core B4), when one core (core A3) preemptively executes multiple tasks, another core (core B4) records the start and end times of all tasks. As a result, when a task with a higher priority (task 1) interrupts during the execution of a task (task 1, task 2) whose execution time is to be calculated, the processing load and processing time of the task (task 1, task 2) whose execution time is to be calculated can be calculated by referring to the total execution time of the task with the higher priority (task 1).

[0025] Therefore, according to the embodiment, when the load on the entire CPU 2 increases, it becomes clear which task is increasing the load, which has the effect of making it very easy to make effective program modifications.

[0026] In the above embodiment, the execution status of the tasks in the core A3 shown in FIG. 2 is an example of a total of three tasks, namely, task 1, task 2, and BG task, but the above embodiment can be applied to a program with three or more tasks set as long as the tasks can be interrupted. In this case, the calculation of the interruption time during the processing time calculation process may become complicated, but since this is the processing of the core B4, it does not affect the core A3, which is the target of the load measurement. In addition, regarding the usage method and the number of storable data of the storage area 6 shown in FIG. 1, it is preferable to set the specification method to a ring buffer and the number of storable data to the number of acquired data expected when the core load is 100%. In other words, the storage area 6, which is the storage area of ​​the RAM 5, is configured by a ring buffer.

[0027] This makes it easy to determine whether a load of more than 100% is applied to the core A3 from the order of the time data in the acquired data (it is easy to determine that the processing of the core A3 has failed). When the processing of the core A3 is performed properly, the oldest data is at the top of the storage area 6, that is, the time data increases in order from the top of the storage area 6. However, when a load of more than 100% is applied, when the data is stored to the end by the ring buffer function, the next data is overwritten at the top of the storage area 6, that is, the oldest data, so that the oldest data is no longer the top data. In other words, when the information read by the core B4 from the calculation use area 7 does not match the data order expected in advance and the information is not appropriate, it is erased by the processing of the ring buffer before the core B4 reads the information of the storage area 6, and it is determined that the processing of the core A3 has failed. By configuring the storage area 6 of the RAM 5 as a ring buffer, it is possible to suppress an increase in the processing load of the core A3. [Explanation of symbols]

[0028] 1: ECU, 2: CPU, 3: Core A, 4: Core B, 5: RAM, 6: Storage area, 7: Calculated utilization area.

Claims

1. A vehicle control device capable of measuring task processing times when a plurality of tasks including a first task and a second task are executed in series by a microprocessor, the vehicle control device comprising: When the processing of the second task interrupts the execution of the first task, a processing time of the first task is measured based on an execution time of the second task.

2. The vehicle control device according to claim 1, the microprocessor includes a first core and a second core; the first core executes the plurality of tasks; The second core measures a processing time of the first task.

3. The vehicle control device according to claim 2, The execution time of the second task is calculated based on a start time and an end time of processing of the second task.

4. The vehicle control device according to claim 3, storing information about the second task and the start time and end time of the second task in a volatile memory; The second core obtains information from the volatile memory.

5. The vehicle control device according to claim 4, A vehicle control device, wherein the storage area of ​​the volatile memory is configured by a ring buffer.

6. The vehicle control device according to claim 5, The first core marks a set to ensure that it is completed in the absence of processing tasks; The second core reads information from the volatile memory using the mark as a trigger; A vehicle control device, wherein if the read information does not match a data order expected in advance and the information is inappropriate, it can be determined that the information was erased by processing of the ring buffer before the second core read the information from the volatile memory, and that the processing of the first core has failed.

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