Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a method for manufacturing the same.SOLUTION: A semiconductor device includes a capacitor, the capacitor including a first electrode; a second electrode; and a dielectric layer arranged between the first and second electrodes, at least one of the first and second electrodes includes a nanolaminate electrode, a nanolaminate electrode includes a plurality of alternating first material layers and a plurality of second material layers, the plurality of first material layers include indium oxide (In2O3), the plurality of second material layers include molybdenum oxide (MoOx), and each of the plurality of first material layers has a thickness of 2 to 6 Å, and each of the plurality of second material layers contains a monolayer of molybdenum oxide.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a capacitor and a manufacturing method thereof. [Background technology]

[0002] Due to the downscaling of semiconductor devices, the size of capacitors used in DRAM devices and the like is also being reduced. As the size of the capacitor is reduced, there is a problem of increased leakage current, and research has been proposed to use dielectric materials with high dielectric constants as the dielectric layer. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide a semiconductor device including a capacitor that employs a novel electrode material having a high work function, has reduced leakage current, and exhibits relatively high capacitance even in a high frequency region. [Means for solving the problem]

[0004] A semiconductor device according to an exemplary embodiment for achieving the above technical problem includes a capacitor, the capacitor including a first electrode; a second electrode; and a dielectric layer disposed between the first electrode and the second electrode; at least one of the first electrode and the second electrode includes a nanolaminate electrode, the nanolaminate electrode including a plurality of first material layers and a plurality of second material layers alternately disposed, the plurality of first material layers being made of indium oxide (In 2 O 3 ), and the plurality of second material layers include molybdenum oxide (MoO x Each of the plurality of first material layers has a thickness of 2 to 6 Å, and each of the plurality of second material layers includes a monolayer of molybdenum oxide.

[0005] A semiconductor device according to an exemplary embodiment for achieving the above technical problem includes a capacitor, the capacitor including a first electrode; a second electrode; and a dielectric layer disposed between the first electrode and the second electrode, at least one of the first electrode and the second electrode including a nanolaminate electrode; and the nanolaminate electrode is made of indium oxide (In 2 O 3 A plurality of first material layers each including a molybdenum oxide (MoO x ) monolayers of a second material layer, and the nanolaminate electrode has a work function of 4.95 to 5.05 eV.

[0006] A semiconductor device according to an exemplary embodiment for achieving the above technical problem includes a substrate; a contact structure disposed on the substrate; a lower electrode disposed on the contact structure, the lower electrode having a cylindrical shape and including a first nanolaminate electrode; a dielectric layer disposed on the lower electrode; and an upper electrode disposed on the dielectric layer; the first nanolaminate electrode is made of indium oxide (In 2 O 3 A plurality of first material layers each including a molybdenum oxide (MoO x ) monolayers of a second material layer, and the nanolaminate electrode has a work function of 4.95 to 5.05 eV.

[0007] According to an exemplary embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a nanolaminate electrode on a substrate by an atomic layer deposition process; the forming of the nanolaminate electrode comprises repeating a deposition cycle of a material layer pair k times; the deposition cycle of the material layer pair comprises repeating a first material layer deposition cycle m times on the substrate; and repeating a second material layer deposition cycle n times on the substrate; the first material layer deposition cycle is a deposition cycle of indium oxide (In 2 O 3), m is in the range of 10 to 30, and the second material layer deposition cycle is a process for depositing a molybdenum oxide (MoO x ), wherein n is 1. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Diagram 2] FIG. 2 is a cross-sectional view of the first electrode of FIG. [Diagram 3] FIG. 2 is a cross-sectional view of the second electrode of FIG. [Figure 4] FIG. 1 is a timing diagram illustrating a method for fabricating a nanolaminate electrode according to an example embodiment. [Diagram 5] 1 is a flow chart that generally illustrates a first material layer deposition cycle. [Figure 6] 4 is a flow chart that generally illustrates a second material layer deposition cycle. [Figure 7] 1 is an X-ray diffraction analysis graph of a nanolaminate electrode according to an example embodiment. [Figure 8] 1 is a graph showing binding energies of nanolaminate electrodes according to example embodiments measured by Ultraviolet Photoelectron Spectroscopy (UPS). [Figure 9] 1 is a graph showing resistivity, carrier concentration, and mobility of a nanolaminate electrode according to an example embodiment. [Figure 10] 1 is an image showing the surface morphology of a nanolaminate electrode according to an example embodiment measured using Atomic Force Microscopy (AFM). [Figure 11] 1 is a scanning electron microscopy image of a capacitor according to a comparative example. [Figure 12] 1 is a scanning electron microscope image of a capacitor according to an embodiment. [Figure 13]FIG. 13 is a schematic diagram of an energy band diagram of a capacitor according to a comparative example. [Figure 14] FIG. 2 is a schematic diagram of an energy band diagram of a capacitor according to an embodiment. [Figure 15] 4 is a graph illustrating capacitance over frequency for a capacitor in accordance with an example embodiment. [Figure 16] 10 is a graph showing capacitance in a high frequency range of a capacitor according to an exemplary embodiment. [Figure 17] 1 is a graph illustrating current density versus voltage characteristics of a capacitor in accordance with an example embodiment. [Figure 18] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 19] FIG. 19 is an enlarged view of part A in FIG. [Figure 20] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 21] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 22] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0010] Fig. 1 is a cross-sectional view of a semiconductor device 1 according to an exemplary embodiment. Fig. 2 is a cross-sectional view of a first electrode 20 of Fig. 1. Fig. 3 is a cross-sectional view of a second electrode 40 of Fig. 1.

[0011] 1, a semiconductor device 1 may include a substrate 10, a first electrode 20, a dielectric layer 30, and a second electrode 40. For example, the first electrode 20, the dielectric layer 30, and the second electrode 40 may form a capacitor, for example, a capacitor having a metal-insulator-metal (MIM) structure.

[0012] The first electrode 20 may include a nanolaminate electrode NE as described with reference to Figure 2. The nanolaminate electrode NE may include a plurality of first material layers 22 and a plurality of second material layers 24 arranged in alternating fashion.

[0013] In an exemplary embodiment, the first material layers 22 are made of indium oxide (In 2 O 3 For example, the first material layers 22 may be formed by an atomic layer deposition ALD process, and each of the first material layers 22 may have a first thickness t11 of about 2 to 6 Å.

[0014] In an exemplary embodiment, the layers of second material 24 are made of molybdenum oxide (MoO x For example, the plurality of second material layers 24 may be formed by an atomic layer deposition ALD process and may have a second thickness t12 of about 1 Å or less.

[0015] For example, each of the plurality of second material layers 24 may include a monolayer of molybdenum oxide. In an exemplary embodiment, each of the plurality of second material layers 24 may form a continuous connected monolayer as shown in FIG. 2. In another embodiment, each of the plurality of second material layers 24 may be formed as island-shaped particles or agglomerates disposed on the top surface of the first material layer 22.

[0016] For example, in the present specification, a monolayer of molybdenum oxide may refer to a continuously connected monolayer or an island-shaped particle or aggregate layer of molybdenum oxide. For example, a monolayer of molybdenum oxide may be formed by repeating a second material layer deposition cycle of an atomic layer deposition process n times, where n can be 1. However, in other embodiments, a monolayer of molybdenum oxide may be formed by repeating a second material layer deposition cycle of an atomic layer deposition process n times, where n can be any number from 1 to 5.

[0017] The first electrode 20 may be formed by repeating a first material layer deposition cycle for forming each of the first material layers 22 and a second material layer deposition cycle for forming each of the second material layers 24 at a predetermined ratio. For example, the first material layer deposition cycle may be performed until the first material layer 22 is formed to have a first thickness t11 of about 2 to 6 Å, the second material layer deposition cycle may be formed to form a monolayer of molybdenum oxide, the first material layer deposition cycle may be performed until the first material layer 22 is formed to have a first thickness t11 of about 2 to 6 Å, and then the second material layer deposition cycle may be formed to form a monolayer of molybdenum oxide, and the first material layer deposition cycle and the second material layer deposition cycle may be repeatedly performed. The first electrode 20 may have a thickness t10 of, for example, 10 to 50 nm.

[0018] In some embodiments, the dielectric layer 30 may include a metal oxide that is a high dielectric constant material. In some embodiments, the dielectric layer 30 may include titanium oxide. In other embodiments, the dielectric layer 30 may include at least one of zirconium oxide, hafnium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanum oxides.

[0019] The second electrode 40 may include a nanolaminate electrode NE as described with reference to Figure 3. The nanolaminate electrode NE may include a plurality of first material layers 42 and a plurality of second material layers 44 arranged in alternating fashion.

[0020] In an exemplary embodiment, the first material layers 42 are made of indium oxide (In 2 O 3 For example, the first material layers 42 may be formed by an atomic layer deposition (ALD) process, and each of the first material layers 42 may have a first thickness t21 of about 2 to 6 Å.

[0021] In an exemplary embodiment, the layers of second material 44 are made of molybdenum oxide (MoO xFor example, the plurality of second material layers 44 may be formed by an atomic layer deposition (ALD) process and may have a second thickness t22 of about 1 Å or less. The second electrode 40 may have a thickness t20 of, for example, 10 to 50 nm.

[0022] For example, each of the plurality of layers of second material 44 may include a monolayer of molybdenum oxide. In an exemplary embodiment, each of the plurality of layers of second material 44 may form a continuous connected monolayer as shown in FIG. 3. In another embodiment, each of the plurality of layers of second material 44 may be formed as island-shaped particles or agglomerates disposed on the top surface of the first layer of material 42.

[0023] 2 and 3 has a work function of about 4.95 eV to 5.05 eV. Since the nanolaminate electrode NE is made of a laminated structure of indium oxide and molybdenum oxide, which have a relatively high work function, the nanolaminate electrode NE has a work function higher than the work function (e.g., 4.5 eV) of an electrode according to a comparative example, such as titanium nitride (TiN).

[0024] In an exemplary embodiment, the nanolaminate electrode NE illustrated in Figures 2 and 3 may show a first peak at 30.48±0.02° derived from the (222) plane of indium oxide having a cubic structure and a second peak at 35.43±0.02° derived from the (400) plane of indium oxide in an X-ray diffraction analysis. In an exemplary embodiment, the nanolaminate electrode NE illustrated in Figures 2 and 3 has a surface roughness of 1 nm or less, for example, a surface roughness in the range of 0.6 nm to 1.0 nm.

[0025] In an exemplary embodiment, the nanolaminate electrode NE illustrated in Figures 2 and 3 has a carrier concentration higher than or equal to the carrier concentration of indium oxide. Also, the nanolaminate electrode NE illustrated in Figures 2 and 3 has a resistivity lower than or equal to the resistivity of indium oxide. For example, when the first material layer 22 of the nanolaminate electrode NE is formed to a thickness t11 of 2 to 6 Å, the resistivity of the nanolaminate electrode NE is in the range of 0.1 to 1 times the resistivity of indium oxide.

[0026] In an exemplary embodiment, the first electrode 20, the dielectric layer 30, and the second electrode 40 constitute a MIM type capacitor, which has a relatively high capacitance value over the entire frequency range from low to high frequencies. For example, the capacitor has a first capacitance at 1 kHz and a second capacitance at 1 MHz, the second capacitance being greater than 50% of the first capacitance, e.g., greater than 80% of the first capacitance. The capacitor also has a significantly lower leakage current than a comparative capacitor (e.g., compared to a capacitor including titanium nitride as an electrode).

[0027] In an exemplary embodiment, when the first material layer 22 of the nanolaminate electrode NE is formed to a thickness t11 of 2 to 6 Å and a second material layer 24 consisting of a single layer of molybdenum oxide is formed between each of the multiple first material layers 22, the nanolaminate electrode NE exhibits a high work function, high carrier mobility, low resistivity, and low surface roughness, and a capacitor including the same not only has a relatively high capacitance value from the low frequency region to the high frequency region, but also has a significantly low leakage current.

[0028] Figure 4 is a timing diagram illustrating a method DP for manufacturing a nanolaminate electrode according to an exemplary embodiment, Figure 5 is a schematic flow chart of a first material layer deposition cycle DPA, and Figure 6 is a schematic flow chart of a second material layer deposition cycle DPB.

[0029] 4 to 6, the manufacturing method DP of the nanolaminate electrode is also a method based on the atomic layer deposition process, and for example, a nanolaminate electrode can be formed by sequentially and repeatedly performing a first material layer deposition cycle DPA and a second material layer deposition cycle DPB on a substrate in a reaction chamber. The first material layer deposition cycle DPA and the second material layer deposition cycle DPB are collectively referred to as a deposition cycle of a material layer pair. For example, as shown in Fig. 4, a nanolaminate electrode may be formed by first performing a first cycle DP_A1 of a first material layer, then performing a first cycle DP_B1 of a second material layer, and then performing a second cycle DP_A2 of the first material layer and a second cycle DP_B2 of the second material layer in sequence, and performing a k-th cycle DP_Ak of ​​the first material layer and a k-th cycle DP_Bk of the second material layer. That is, the deposition cycle of the material layer pair may be repeatedly performed k times. Here, the range of k may be determined in consideration of the total thickness of the nanolaminate electrode, the growth rate of the material layer in each cycle, etc.

[0030] 5, the first material layer deposition cycle DPA may include a unit cycle including, in sequence, a first metal source supply step (S12) including indium, a purging step (S14), a first oxygen source supply step (S16), and a purging step (S18). The first material layer deposition cycle DPA may include a step of repeating the unit cycle including, in sequence, a first metal source supply step (S12), a purging step (S14), a first oxygen source supply step (S16), and a purging step (S18) m times (S20), where m is in the range of 10 to 30.

[0031] In an exemplary embodiment, a first metal source is supplied into the reaction chamber in the first metal source supply step (step S12), and the first metal source is also an organometallic precursor containing indium. The first metal source is TMIn (trimethyl indium, In(CH 3 ) 3 ), InCA-1 ([1,1,1-trimethyl-N-(trimethylsilyl)silanaminato]indium), DADI The first metal source may include at least one of dimethyl indium ([3-(dimethylamino)propyl]dimethyl indium), and InCp (cyclopentadienyl indium). In some embodiments, the first metal source may be DADI, but is not limited thereto. For example, the first metal source supplying step (step S12) may be performed for about 0.5 to 3 seconds.

[0032] Thereafter, in a purging step (step S14), excess first metal source that is not adsorbed on the substrate may be purged and / or removed.

[0033] In the first oxygen source supplying step (S16), a first oxygen source is supplied into the reaction chamber, and the first oxygen source may include at least one of hydrogen peroxide, oxygen, ozone, and oxygen plasma. The first oxygen source may also be referred to as a reactant. In the first oxygen source supplying step (S16), a reaction occurs between the first metal source adsorbed on the substrate and the first oxygen source, and a first material layer including indium oxide may be formed. For example, the first oxygen source supplying step (S16) may be performed for about 1 to about 20 seconds.

[0034] Thereafter, in a purging step (step S18), excess first oxygen source that is not adsorbed on the substrate may be purged and / or removed.

[0035] For example, during a unit cycle including a first metal source supply step (step S12), a purging step (step S14), a first oxygen source supply step (step S16), and a purging step (step S18) in sequence, an indium oxide layer having a thickness of about 0.15 to 0.20 Å may be formed. When m, which is the number of repetitions of the unit cycle in the first material layer deposition cycle DPA, is less than 10, the first material layer (indium oxide) is difficult to form to a sufficient thickness to crystallize, and when m is greater than 30 in the amorphous first material layer, the first material layer (indium oxide) is formed to an excessively large thickness, and the nanolaminate electrode has a relatively high resistivity or a relatively low work function.

[0036] 6, the second material layer deposition cycle DPB may include a unit cycle including, in sequence, a step of supplying a second metal source including molybdenum (step S32), a purge step (step S34), a step of supplying a second oxygen source (step S36), and a purge step (step S38). The second material layer deposition cycle DPB may include a step of repeating a unit cycle including, in sequence, a step of supplying a second metal source (step S32), a purge step (step S34), a step of supplying a second oxygen source (step S36), and a purge step (step S38) n times (step S40), where n may be 1.

[0037] In an exemplary embodiment, in the second metal source supply step (step S32), a second metal source is supplied into the reaction chamber, and the second metal source is also an organometallic precursor containing molybdenum. The first metal source is Bis(tert-butylimido)bis(dimethylamido)molybdenum (TBDMMo), bis(ethylbenzene)molybdenum, MoF 6 , MoCl 6 and Mo(CO) 6 In some embodiments, the second metal source may be, but is not limited to, TBDMMo. For example, the second metal source supplying step (S32) may be performed for about 0.5 to 5 seconds.

[0038] Then, in a purging step (step S34), excess second metal source that is not adsorbed on the substrate may be purged and / or removed.

[0039] In the second oxygen source supplying step (S36), a second oxygen source is supplied into the reaction chamber, and the second oxygen source may include at least one of hydrogen peroxide, oxygen, ozone, and oxygen plasma. The second oxygen source is also referred to as a reactant. In the second oxygen source supplying step (S36), a reaction occurs between the second metal source adsorbed on the first material layer and the second oxygen source, and a second material layer including molybdenum oxide may be formed. For example, a monolayer of molybdenum oxide may be formed on the first material layer. For example, the second oxygen source supplying step (S36) may be performed for about 1 to 20 seconds.

[0040] Thereafter, in a purge step (step S38), excess second oxygen source that is not adsorbed on the substrate may be purged and / or removed.

[0041] For example, during a unit cycle including a second metal source supply step (step S32), a purge step (step S34), a second oxygen source supply step (step S36), and a purge step (step S38) in sequence, a molybdenum oxide layer having a thickness of about 1 Å or less, or 0.15 to 0.20 Å, may be formed. In the second material layer deposition cycle DPB, the number of repetitions of the unit cycle, n, may be 1.

[0042] In some embodiments, the second material layer, which may be a monolayer of molybdenum oxide, is disposed on the first material layer and may be formed as island-shaped particles or aggregates disposed on an upper surface of the first material layer, including a monolayer that is continuously connected to one another. In some embodiments, the relatively small ionic radius of molybdenum atoms allows the molybdenum atoms to be positioned within the first material layer to occupy interstitial sites that are not occupied by indium atoms.

[0043] The ratio of m, which is the number of repetitions of a unit cycle in the first material layer deposition cycle DPA, to n, which is the number of repetitions of a unit cycle in the second material layer deposition cycle DPB, may be determined to be 10: 1 to 30: 1. For example, when the first material layer deposition cycle DPA and the second material layer deposition cycle DPB are performed in the range of 10: 1 to 30: 1, a nanolaminate electrode may be formed having a high work function, high carrier mobility, low resistivity, and low surface roughness.

[0044] Hereinafter, the physical and electrical properties of the nanolaminate electrode according to the ratio of the number of first material layer deposition cycles DPA to the number of second material layer deposition cycles DPB will be described with reference to FIGS. Experimental Example 1 In the atomic layer deposition apparatus, a first material layer deposition cycle DPA and a second material layer deposition cycle DPB were performed on the substrate at a ratio of 30:1, 20:1, 10:1, and 5:1 to form a nanolaminate electrode having a total thickness of 20 nm. As a comparative example, only the first material layer deposition cycle DPA was performed to form an indium oxide (In 2 O 3 ) was formed as a single membrane electrode.

[0045] [Table 1] FIG. 7 is an X-ray diffraction analysis graph of a nanolaminate electrode according to an example embodiment.

[0046] Referring to FIG. 7, the X-ray diffraction analysis graphs of Examples 1 to 4 are shown together with the X-ray diffraction analysis graph of the Comparative Example. Examples 1 to 3 showed a first peak derived from the (222) plane of indium oxide having a cubic crystal structure and a second peak derived from the (400) plane. The first peak was shown at 30.48±0.02°, and the second peak was shown at 35.43±0.02°. Meanwhile, it can be seen that Comparative Example and Example 4 do not have a second peak derived from the (400) plane. This is presumably because, in the case of Examples 1 to 3 in which a single layer of molybdenum oxide is formed at a ratio of 30:1, 20:1, and 10:1, the single layer of molybdenum oxide or molybdenum atoms act as an intermediate layer (insertion layer) or an additive element that improves the crystallinity of indium oxide.

[0047] Figure 8 shows the results of ultraviolet photoelectron spectroscopy. 1 is a graph showing binding energies of nanolaminate electrodes according to example embodiments measured by Photoelectron Spectroscopy (UPS).

[0048] 8, the binding energies of Examples 1 to 4 are shown together with those of Comparative Example 1 (indium oxide) and Comparative Example 2 (titanium nitride). The work functions of Examples 1 to 4, Comparative Example 1, and Comparative Example 2 calculated from the binding energies measured by ultraviolet photoelectron spectroscopy (UPS) are shown in Table 2.

[0049] [Table 2] As shown in Table 2, the work function increases as the molybdenum content increases, for example, in the case of Examples 1 to 3 in which a single layer of molybdenum oxide is formed at a molybdenum content ratio of 30:1, 20:1, and 10:1, it can be seen that they have relatively high work functions of 4.95, 5.03, and 5.05 eV, which are higher than the work functions of Comparative Example 1 (indium oxide) and Comparative Example 2 (titanium nitride).

[0050] FIG. 9 is a graph showing resistivity, carrier concentration, and mobility of a nanolaminate electrode according to an example embodiment.

[0051] 9, it was confirmed that the resistivity, carrier concentration, and mobility of Examples 1 to 3 were superior to or comparable to those of the comparative example. In particular, Example 2, in which a single layer of molybdenum oxide was formed at a ratio of 20:1, exhibited the highest carrier concentration and the highest charge mobility (e.g., 92.6 cm 2 / V·s) and the lowest resistivity (e.g., 240 μΩ·cm), showing the best electrical properties. That is, it can be seen that the nanolaminate electrode in which a 2-6 Å thick indium oxide layer and a molybdenum oxide monolayer are repeatedly formed as in Examples 1 to 3 has the best carrier concentration and the lowest resistivity.

[0052] On the other hand, Example 4 in which a single layer of molybdenum oxide was formed at a ratio of 5:1 exhibited a lower carrier concentration, mobility and the highest resistivity than the Comparative Example. This may be due to the increase in molybdenum content inducing amorphization of indium oxide or the reduction in free carrier mobility due to the scattering effect of molybdenum.

[0053] Figure 10 shows the atomic force microscope (AFM). 1 is an image showing the surface morphology of a nanolaminate electrode according to an example embodiment measured using AFM (Atomic Force Microscopy).

[0054] 10, Examples 1 and 2 have larger surface roughness values ​​than the Comparative Example. That is, in Examples 1 and 2, as the molybdenum content increases, the crystallinity of the indium oxide layer is improved and the surface roughness value increases, whereas Example 4 has the smallest surface roughness value. This may be because in Example 4, in which a single layer of molybdenum oxide is formed at a ratio of 5:1 with a relatively high molybdenum content, amorphization is induced, resulting in the smallest surface roughness.

[0055] On the other hand, all of Examples 1 to 4 have a surface roughness of 1 nm or less, which is also low enough to reduce trap sites at the interface between the dielectric layer and the nanolaminate electrode and reduce leakage current. Experimental Example 2 Capacitors according to the example and the comparative example were formed on a substrate in an atomic layer deposition apparatus.

[0056] [Table 3] FIG. 11 is a scanning electron microscopy image of a capacitor according to a comparative example, and FIG. 12 is a scanning electron microscopy image of a capacitor according to an embodiment.

[0057] 11 and 12, it can be seen that the lower electrodes of the comparative example and the embodiment are both continuous material layers that cover the entire substrate and are formed to a uniform thickness. In addition, it can be seen that the interface between the lower electrode and the dielectric layer has excellent interface characteristics without interface defects such as voids or seams.

[0058] FIG. 13 is a schematic diagram of an energy band diagram EB_CO of the capacitor according to the comparative example, and FIG. 14 is a schematic diagram of an energy band diagram EB_EX of the capacitor according to the example.

[0059] Referring to FIG. 13, the capacitor according to the comparative example has a work function WF1 of the lower electrode (TiN) of 4.5 eV. 2 ) is 4.2 eV, which is a relatively small difference. Therefore, the band offset BO_1 at the interface between the lower electrode and the dielectric layer is relatively small. If the band offset at the interface between the lower electrode and the dielectric layer is small, leakage current due to thermionic emission may occur.

[0060] Referring to FIG. 14, the capacitor according to the embodiment has a lower electrode (In 2 O 3 The work function WF2 of the MoOx layer is 4.95 to 5.05 eV, and the dielectric layer (TiO 2 ) is 4.2 eV, which is a relatively large difference. As a result, the band offset BO_2 at the interface between the lower electrode and the dielectric layer is relatively large. When the band offset at the interface between the lower electrode and the dielectric layer is large, the generation of leakage current due to thermionic emission can be significantly reduced or prevented.

[0061] FIG. 15 is a graph showing the capacitance of a capacitor according to an exemplary embodiment relative to frequency, and FIG. 16 is a graph showing the capacitance of a capacitor according to an exemplary embodiment in the high frequency range.

[0062] 15 and 16, the capacitor according to the comparative example has a large capacitance value of 800pF or more in the low frequency region, but as the frequency increases, the capacitance value gradually decreases and has a capacitance value of 240pF or less in the high frequency region of 1MHz. On the other hand, the capacitor according to the embodiment has a large capacitance value of 950pF or more in the low frequency region, and even as the frequency increases, the capacitance value remains almost constant and has a capacitance value of about 800pF or less in the high frequency region of 1MHz.

[0063] That is, in the low frequency region, the capacitance value of the embodiment is larger than that of the comparative example, but the difference is not significant. However, in the high frequency region, the capacitance value of the embodiment is significantly larger, equivalent to three times that of the comparative example.

[0064] Generally, in the low frequency range, the equivalent series resistance (ESR) It is known that the equivalent series resistance (ESR) component shows a value corresponding to the dielectric loss due to dielectric relaxation, and as the frequency increases, the effects of series resistance and inductance become dominant, the capacitance decreases, and the equivalent series resistance is affected by the loss due to the electrodes. The lower electrode according to the embodiment has a dielectric loss factor of 0.243 at 1 MHz, while the lower electrode according to the comparative example has a dielectric loss factor of 1.31. Therefore, since the lower electrode according to the embodiment has a significantly lower dielectric loss factor than the lower electrode according to the comparative example in the high frequency range (i.e., because the lower electrode according to the embodiment has high carrier mobility and low resistivity), it can be inferred that the lower electrode according to the embodiment has a high capacitance value.

[0065] FIG. 17 is a graph illustrating current density versus voltage characteristics of a capacitor in accordance with an example embodiment.

[0066] Referring to FIG. 17, the capacitor according to the comparative example has a capacitance of 1.75×10 -5 while the capacitor according to the embodiment exhibits a leakage current density of 6.03×10 at 1000 mV. -9 This was about 3000 times lower than that of the comparative example.

[0067] The narrow band gap of titanium oxide used as the dielectric layer may cause a large leakage current due to Schottky emission from the interface between the dielectric layer and the bottom electrode. 2 O 3 :MoO xIt can be speculated that since ZnO has a high work function, it increases the potential barrier between the bottom electrode and the dielectric layer, effectively blocking the leakage path, thereby reducing the leakage current of the capacitor.

[0068] 18 is a cross-sectional view showing a semiconductor device 100 according to an exemplary embodiment. FIG. 19 is an enlarged view of part A in FIG.

[0069] 18 and 19, a semiconductor device 100 includes a DRAM device, and may include a cell transistor (not shown) formed on a substrate 110 and a capacitor CAP electrically connected to the cell transistor.

[0070] A lower insulating layer 112 may be disposed on the substrate 110, and a contact structure 114 may be disposed on the substrate 110 through the lower insulating layer 112. The contact structure 114 may include a conductive material. An etch stop layer 116 having an opening exposing an upper surface of the contact structure 114 may be disposed on the lower insulating layer 112.

[0071] A capacitor CAP may be disposed on the etch stop layer 116. The capacitor CAP may include a lower electrode 120, a dielectric layer 130, and an upper electrode 140. The lower electrode 120 may have a cylindrical shape, the sidewall of the bottom of the lower electrode 120 may be surrounded by the etch stop layer 116, and the bottom of the lower electrode 120 may be disposed on the upper surface of the contact structure 114. The lower electrode 120 may be formed to a relatively high height in the vertical direction or may have a large aspect ratio, and a support member 118 may be disposed on the sidewall of the lower electrode 120. The dielectric layer 130 may be conformally disposed on the inner and outer walls of the lower electrode 120. The upper electrode 140 may be disposed on the dielectric layer 130 to cover the lower electrode 120.

[0072] In an exemplary embodiment, the bottom electrode 120 may include a plurality of first material layers 122 and a plurality of second material layers 124 that are alternately arranged. The bottom electrode 120 has a structure similar to the nanolaminate electrode NE described with reference to Fig. 2. For example, the plurality of first material layers 122 may include indium oxide having a thickness of 2 to 6 Å, and the plurality of second material layers 124 may include a single layer made of molybdenum oxide.

[0073] In an exemplary embodiment, the dielectric layer 130 may include a metal oxide that is a high dielectric constant material. In some embodiments, the dielectric layer 130 may include titanium oxide. In other embodiments, the dielectric layer 130 may include at least one of zirconium oxide, hafnium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanum oxides.

[0074] In an exemplary embodiment, the upper electrode 140 may include a plurality of alternating first material layers 142 and a plurality of second material layers 144. The upper electrode 140 has a structure similar to the nanolaminate electrode NE described with reference to Fig. 3. For example, the plurality of first material layers 142 may include indium oxide having a thickness of 2-6 Å, and the plurality of second material layers 144 may include a single layer composed of molybdenum oxide.

[0075] FIG. 20 is a cross-sectional view showing a semiconductor device 100A according to an exemplary embodiment.

[0076] 20, the lower electrode 120 is also a nanolaminate electrode including a plurality of first material layers 122 and a plurality of second material layers 124 that are alternately arranged, and the upper electrode 140A is made of a material selected from the group consisting of metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and tungsten (W), conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN), and iridium oxide (IrO 2), ruthenium oxide (RuO 2 ), strontium ruthenium oxide (SrRuO 3 ) may be included.

[0077] FIG. 21 is a cross-sectional view showing a semiconductor device 100B according to an exemplary embodiment.

[0078] 21, the bottom electrode 120A may be disposed on the top surface of the contact structure 114 and may have a pillar shape extending in the vertical direction. A dielectric layer 130 may be conformally disposed on the top surface and sidewalls of the bottom electrode 120A.

[0079] In an exemplary embodiment, the bottom electrode 120A includes a vertically extending monolithic material layer, and the bottom electrode 120A may include the nanolaminate electrode NE described with reference to Figures 1 to 3. According to a manufacturing method according to an exemplary embodiment, the bottom electrode 120A may be formed by forming a mold insulating layer having pillar-shaped openings on a substrate, and forming the nanolaminate electrode NE in the openings using the manufacturing method described with reference to Figures 4 to 6, as described with reference to Figures 1 to 3.

[0080] In another exemplary embodiment, the bottom electrode 120A may include a vertically extending base pillar and an electrode layer conformally disposed on the sidewalls and top surface of the base pillar, the base pillar being made of metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), tungsten nitride (WN), and iridium oxide (IrO). 2 ), ruthenium oxide (RuO 2 ), strontium ruthenium oxide (SrRuO 3), and the electrode layer may include the nanolaminate electrode NE described with reference to FIGS. 1 to 3.

[0081] FIG. 22 is a cross-sectional view of a semiconductor device 200 according to an example embodiment.

[0082] 22, the semiconductor device 200 is also a global shutter type image sensor including a plurality of photoelectric conversion regions PD formed in a semiconductor substrate 210 and a capacitor CAP disposed on a front face of the semiconductor substrate 210. A transmission gate TG may be disposed to extend into the semiconductor substrate 210 and configured to control photoelectrons stored in the photoelectric conversion region PD. A pixel transistor may be further formed on the front face of the semiconductor substrate 210, and the pixel transistor may be electrically connected to the capacitor CAP so that charges transferred from the photoelectric conversion region PD of each pixel may be stored in the capacitor CAP. The capacitor CAP may include a lower electrode 220, a dielectric layer 230, and an upper electrode 240, and at least one of the lower electrode 220 and the upper electrode 240 may include the nanolaminate electrode NE described with reference to FIGS. 1 to 3. A front wiring layer FL may be disposed on the front face of the semiconductor substrate 210, and a front insulating layer FI may be disposed to cover the front wiring layer FL and the capacitor CAP. A color filter CF and a microlens ML may be disposed on the rear face of the semiconductor substrate 210.

[0083] As above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in the present specification to describe the embodiments, these terms are merely used to describe the technical ideas of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present disclosure must be determined by the technical ideas of the claims. [Explanation of symbols]

[0084] 10 Substrate 20 1st electrode 22 First material layer 24 Second material layer 30 Dielectric layer 40 2nd electrode t10, t20 Thickness: 10-50 nm

Claims

1. a capacitor, the capacitor comprising: A first electrode; A second electrode; a dielectric layer disposed between the first electrode and the second electrode; At least one of the first electrode and the second electrode includes a nanolaminate electrode; The nanolaminate electrode includes a plurality of alternating layers of a first material and a plurality of layers of a second material, The first material layers are made of indium oxide (In ２ O ３ ), The second material layers are made of molybdenum oxide (MoO ｘ ), each of the plurality of first material layers having a thickness of 2-6 Å; Each of the plurality of second material layers comprises a monolayer of molybdenum oxide.

2. 2. The semiconductor device according to claim 1, wherein the nanolaminate electrode has a thickness of 10 to 50 nm.

3. 2. The semiconductor device according to claim 1, wherein the nanolaminate electrode has a work function of 4.95 to 5.05 eV.

4. 2. The semiconductor device according to claim 1, wherein the nanolaminate electrode exhibits a first peak at 30.48±0.02° originating from a (222) plane of indium oxide having a cubic structure and a second peak at 35.43±0.02° originating from a (400) plane of indium oxide in an X-ray diffraction analysis.

5. 2. The semiconductor device of claim 1, wherein the dielectric layer comprises a high dielectric constant metal oxide.

6. The dielectric layer is made of titanium oxide (TiO ２ 2. The semiconductor device according to claim 1, further comprising:

7. The semiconductor device of claim 1 , wherein the nanolaminate electrode has a surface roughness of 1 nm or less.

8. the capacitor has a first capacitance at 1 kHz; the capacitor has a second capacitance at 1 MHz; 2. The semiconductor device according to claim 1, wherein the second capacitance is greater than 50% of the first capacitance.

9. 9. The semiconductor device according to claim 8, wherein the second capacitance is greater than 80% of the first capacitance.

10. a capacitor, the capacitor comprising: A first electrode; A second electrode; a dielectric layer disposed between the first electrode and the second electrode; At least one of the first electrode and the second electrode includes a nanolaminate electrode; The nanolaminate electrode comprises: Indium oxide (In ２ O ３ a plurality of layers of a first material comprising: The first material layers are disposed between two adjacent first material layers, and each of the first material layers is made of molybdenum oxide (MoO ｘ and a plurality of layers of a second material consisting of monolayers of The semiconductor device is characterized in that the nanolaminate electrode has a work function of 4.95 to 5.05 eV.

11. each of the plurality of first material layers having a thickness of 2-6 Å; 11. The semiconductor device according to claim 10, wherein the nanolaminate electrode has a thickness of 10 to 50 nm.

12. 11. The semiconductor device according to claim 10, characterized in that the nanolaminate electrode exhibits a first peak at 30.48±0.02° originating from a (222) plane of indium oxide having a cubic structure and a second peak at 35.43±0.02° originating from a (400) plane of indium oxide in an X-ray diffraction analysis.

13. The semiconductor device of claim 10 , wherein the dielectric layer comprises a high dielectric constant metal oxide.

14. The dielectric layer is made of titanium oxide (TiO ２ 11. The semiconductor device according to claim 10, further comprising:

15. The semiconductor device of claim 10 , wherein the nanolaminate electrode includes a surface roughness of 1 nm or less.

16. the capacitor has a first capacitance at 1 kHz; the capacitor has a second capacitance at 1 MHz; 11. The semiconductor device according to claim 10, wherein the second capacitance is greater than 50% of the first capacitance.

17. A substrate; a contact structure disposed on the substrate; a lower electrode disposed on the contact structure, the lower electrode having a cylindrical shape and including a first nanolaminate electrode; a dielectric layer disposed on the bottom electrode; a top electrode disposed on the dielectric layer; The first nanolaminate electrode comprises: Indium oxide (In ２ O ３ a plurality of first material layers including The first material layers are disposed between two adjacent first material layers, and each of the first material layers is made of molybdenum oxide (MoO ｘ and a plurality of layers of a second material consisting of monolayers of The semiconductor device is characterized in that the first nanolaminate electrode has a work function of 4.95 to 5.05 eV.

18. The dielectric layer is made of titanium oxide (TiO ２ 20. The semiconductor device according to claim 17, further comprising:

19. each of the plurality of first material layers having a thickness of 2-6 Å; The semiconductor device according to claim 17, wherein the first nanolaminate electrode has a thickness of 10 to 50 nm.

20. the top electrode includes a second nanolaminate electrode; The second nanolaminate electrode comprises: Indium oxide (In ２ O ３ a plurality of layers of a third material including The third material layers are disposed between two adjacent third material layers of the plurality of third material layers, and each of the third material layers is made of molybdenum oxide (MoO ｘ and a plurality of layers of a fourth material consisting of monolayers of 18. The semiconductor device of claim 17, wherein the second nanolaminate electrode has a work function of 4.95 to 5.05 eV.

Images