Semiconductor package and manufacturing method of the same

Abstract

To provide a semiconductor package of which an integration degree is improved, and provide a manufacturing method of the same.SOLUTION: A semiconductor package comprises: a package substrate; a lower semiconductor chip mounted onto the package substrate; an upper semiconductor chip that is arranged onto the lower semiconductor chip so as to be shifted horizontally to the lower semiconductor chip; and a wiring layer that is in contact with an upper surface of the lower semiconductor chip and a lower surface of the upper semiconductor chip. The wiring layer covers the lower surface of the upper semiconductor chip on one side of the lower semiconductor chip, and is extended between the lower semiconductor chip and the upper semiconductor chip. The upper semiconductor chip contains a first circuit layer provided on the lower surface of the upper semiconductor chip. A thickness of a wiring pattern of the first circuit layer is smaller than that of the wiring pattern of the wiring layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same. [Background technology]

[0002] Recently, the electronic product market has seen a rapid increase in the demand for portable devices, which has led to a continuous demand for electronic components mounted in these products to be more compact, lightweight, and more powerful. In particular, the demand for high-performance memory semiconductors has been increasing, and there has been a demand for high bandwidth or high processing capacity.

[0003] To achieve the miniaturization and weight reduction of such electronic components, not only is there a need for technology to reduce the size of each mounted component, but also for semiconductor packaging technology that can integrate many individual elements into one package.In particular, semiconductor packages that handle high-frequency signals are required to not only be miniaturized, but also to have mounting with excellent electrical characteristics.

[0004] Generally, a TSV process, a flip chip process, a wire bonding process, etc. are used to stack multiple memory chips on a package substrate. However, the TSV process has problems such as a complicated process and excessive cost, and therefore a need for a process that solves these problems may arise. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent No. 11,201,135 B2 Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a semiconductor package having an improved integration density and a method for manufacturing the same.

[0007] Another object of the present invention is to provide a semiconductor package having improved electrical characteristics and a method for manufacturing the same.

[0008] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] A semiconductor package according to an embodiment of the present invention for solving the above-mentioned technical problems may include a package substrate, a lower semiconductor chip mounted on the package substrate, an upper semiconductor chip disposed on the lower semiconductor chip so as to be horizontally shifted from the lower semiconductor chip, and a wiring layer contacting an upper surface of the lower semiconductor chip and a lower surface of the upper semiconductor chip. The wiring layer may cover the lower surface of the upper semiconductor chip on one side of the lower semiconductor chip and extend between the lower semiconductor chip and the upper semiconductor chip. The upper semiconductor chip may include a first circuit layer provided on the lower surface of the upper semiconductor chip. A thickness of a wiring pattern of the first circuit layer may be thinner than a thickness of a wiring pattern of the wiring layer.

[0010] A semiconductor package according to an embodiment of the present invention for solving the above technical problems may include a package substrate, a first semiconductor chip flip-chip mounted on the package substrate, a first molding film surrounding the first semiconductor chip on the package substrate, a first wiring layer covering an upper surface of the first semiconductor chip and an upper surface of the first molding film, a second semiconductor chip on the first wiring layer, a second molding film surrounding the second semiconductor chip on the first wiring layer, and an external terminal provided on a lower surface of the package substrate. The second semiconductor chip may be shifted from the first semiconductor chip so as to overlap one side of the first semiconductor chip in a vertical direction. The first semiconductor chip and the first molding film may be separated from the second semiconductor chip and the second molding film by the first wiring layer.

[0011] A semiconductor package according to an embodiment of the present invention for solving the above technical problems may include a package substrate, a first semiconductor chip on the package substrate, the first semiconductor chip including a first circuit layer provided on one side of the first semiconductor chip and a first via vertically penetrating the first semiconductor chip and connected to the first circuit layer, a first molding film surrounding the first semiconductor chip on the package substrate, a second semiconductor chip horizontally shifted from the first semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit layer provided on a lower side of the second semiconductor chip and a second via vertically penetrating the second semiconductor chip and connected to the second circuit layer, a first wiring layer interposed between the second circuit layer and the first semiconductor chip and between the second circuit layer and the first molding film, and a second molding film surrounding the first wiring layer and the second semiconductor chip on the first molding film. The first wiring layer may expose an upper surface of the first semiconductor chip at one side of the second semiconductor chip. The second semiconductor chip is connected to the first wiring layer through a chip pad of the second circuit layer, at least a portion of the chip pad is located on one side of the first semiconductor chip in a planar view, and the wiring pattern of the first wiring layer can electrically connect the portion of the chip pad to the first via.

[0012] In order to solve the above-mentioned technical problems, a manufacturing method for a semiconductor package according to an embodiment of the present invention may include providing a package substrate, mounting a first semiconductor chip on the package substrate, forming a first molding film surrounding the first semiconductor chip on the package substrate, providing a second semiconductor chip, forming a wiring layer on at least one of an upper surface of the first semiconductor chip and a lower surface of the second semiconductor chip, mounting the second semiconductor chip on the first semiconductor chip, the second semiconductor chip being electrically connected to the first semiconductor chip through the wiring layer, and forming a second molding film surrounding the second semiconductor chip on the first molding film. Effect of the Invention

[0013] The semiconductor package according to the embodiment of the present invention can provide a redistribution layer between stacked semiconductor chips to electrically connect through vias or chip pads that are not aligned with each other, thereby providing a semiconductor package with improved electrical characteristics by providing good electrical connection between the semiconductor chips.

[0014] Furthermore, even if the chip pads of the upper semiconductor chip are disposed on one side of the lower semiconductor chip, a vertical connection structure such as a conductive post or a bridge chip for connecting the upper chip pads to the package substrate may not be necessary. Therefore, restrictions on the thickness and width of the conductive post, which are required when forming the conductive post on the molding film in the semiconductor package manufacturing process, may be eliminated. Also, the integration degree of the wiring connecting the semiconductor chip and the package substrate may be increased. That is, a semiconductor package with improved integration degree may be provided. [Brief description of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Diagram 2] 1 is a plan view illustrating a semiconductor package according to an embodiment of the present invention; [Diagram 3] 2 is an enlarged view of region A in FIG. 1. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Diagram 5] 1 is a plan view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 6] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 7] 7 is an enlarged view of region B in FIG. 6. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 9] 1 is a plan view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 10] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 11] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 12] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 14] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 15] 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 16] 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 17] 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 18] 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 19] 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 20] 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 21] 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 22] 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] A semiconductor package according to the concept of the present invention will now be described with reference to the drawings.

[0017] Fig. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention, Fig. 2 is a plan view illustrating a semiconductor package according to an embodiment of the present invention, and Fig. 3 is an enlarged view of region A in Fig. 1.

[0018] 1 to 3, a package substrate 100 may be provided. The package substrate 100 may be a redistribution substrate. For example, the package substrate 100 may include at least one substrate wiring layer stacked on top of one another. Each of the substrate wiring layers may include a substrate insulating layer 110 and a substrate wiring pattern 120 in the substrate insulating layer 110. The substrate wiring pattern 120 of any one substrate wiring layer may be electrically connected to the substrate wiring pattern 120 of another adjacent substrate wiring layer.

[0019] The substrate insulating layer 110 may include an insulating polymer or a photoimageable dielectric (PID), for example, the substrate insulating layer 110 may include at least one of a photosensitive polyimide, a polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer.

[0020] The substrate wiring pattern 120 may be provided in the substrate insulating layer 110. The substrate wiring pattern 120 may extend horizontally in the substrate insulating layer 110. For example, the substrate wiring pattern 120 may be a pad portion or a wiring portion of the substrate wiring layer. That is, the substrate wiring pattern 120 may be a component for horizontal redistribution in the package substrate 100. The substrate wiring pattern 120 may be provided on the substrate insulating layer 110. An upper surface of the substrate wiring pattern 120 may be exposed on an upper surface of the substrate insulating layer 110. The substrate wiring pattern 120 provided on the uppermost substrate wiring layer may serve as a substrate pad to which the first semiconductor chip 200 described below is connected. The substrate wiring pattern 120 may include a conductive material. For example, the substrate wiring pattern 120 may include a metal such as copper (Cu).

[0021] The substrate wiring pattern 120 may have a via protruding from a lower surface of the substrate wiring pattern 120. The via may be configured to vertically connect the substrate wiring patterns 120 of adjacent substrate wiring layers. Alternatively, the via may be configured to connect the substrate wiring pattern 120 of the lowermost substrate wiring layer to the external pad 130. For example, the via may extend from the lower surface of the substrate wiring pattern 120, penetrate the substrate insulating layer 110, and then be connected to an upper surface of the substrate wiring pattern 120 of another substrate wiring layer located therebelow. Alternatively, the via may extend from the lower surface of the substrate wiring pattern 120, penetrate the substrate insulating layer 110 of the lowermost substrate wiring layer, and then be connected to an upper surface of the external pad 130.

[0022] Contrary to what is shown in the figure, within one of the substrate wiring layers, the substrate wiring pattern 120 may be located on the upper surface of the substrate insulating layer 110, and the vias of the substrate wiring pattern 120 may penetrate the substrate insulating layer 110 and be connected to the substrate wiring pattern 120 of another substrate wiring layer located below it.

[0023] An external pad 130 may be provided on a lower surface of the lowermost substrate wiring layer. The external pad 130 may be electrically connected to the substrate wiring pattern 120. The external pad 130 may serve as a pad to which an external terminal 150 is connected.

[0024] A substrate protection layer 140 may be provided. The substrate protection layer 140 may cover the lower surface of the lowermost substrate wiring layer and expose the external pad 130. An external terminal 150 may be provided on the exposed lower surface of the external pad 130. The external terminal 150 may include a solder ball or a solder bump.

[0025] As described above, the package substrate 100 may be provided. However, the present invention is not limited thereto. The package substrate 100 may be a printed circuit board (PCB). For example, the package substrate 100 may have a core layer and a peripheral portion for connecting wiring between the upper and lower portions of the core layer.

[0026] A first semiconductor chip 200 may be disposed on the package substrate 100. The first semiconductor chip 200 may be a logic chip. Alternatively, the first semiconductor chip 200 may be a memory chip such as a DRAM, an SRAM, an MRAM, or a flash memory. The first semiconductor chip 200 may have a front surface 200a and a rear surface 200b. Hereinafter, the front surface may be defined as a surface on an active surface side of an integrated device in a semiconductor chip, on which pads of the semiconductor chip are formed, and the rear surface may be defined as an opposite surface facing the front surface. The lower surface of the first semiconductor chip 200 may be the front surface 200a. That is, the first semiconductor chip 200 may be disposed face down on the package substrate 100. The first semiconductor chip 200 may include a first base layer 210, a first circuit layer 220, and at least one first through via 230.

[0027] The first base layer 210 may include a semiconductor material. For example, the first base layer 210 may be a silicon (Si) single crystal substrate. A semiconductor element may be provided on the first base layer 210. In particular, an integrated element or an integrated circuit may be formed under the first base layer 210. For example, an integrated element such as a transistor may be formed on a lower surface of the first base layer 210, or a passive element such as a resistor, a capacitor, or an inductor, or a wiring pattern, etc. may be formed on the lower surface of the first base layer 210. That is, the lower surface of the first base layer 210 may be a front surface, and the upper surface of the first base layer 210 may be a back surface.

[0028] A first circuit layer 220 may be provided on the lower surface of the first base layer 210. The first circuit layer 220 may be electrically connected to the integrated device or the integrated circuit formed in the first base layer 210. For example, the first circuit layer 220 may have a first insulating pattern 222 and a first wiring pattern 224 provided in the first insulating pattern 222, and the first wiring pattern 224 may be connected to the integrated device or the integrated circuit formed in the first base layer 210.

[0029] The first insulating pattern 222 may cover the integrated device or the integrated circuit on the lower surface of the first base layer 210. Although the first insulating pattern 222 is illustrated as being one layer in FIG. 1, the present invention is not limited thereto. According to another embodiment, a plurality of first insulating patterns 222 may be provided, and the plurality of first insulating patterns 222 may be stacked on one another. In this case, the first insulating patterns 222 may be wiring layers connected vertically to each other. The first insulating patterns 222 may include silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).

[0030] The first wiring pattern 224 may be provided in the first insulating pattern 222. When the first insulating pattern 222 is provided in a plurality of layers, the first wiring pattern 224 may also be provided in a plurality of layers, and one first insulating pattern 222 and one first wiring pattern 224 provided in the one first insulating pattern 222 may constitute one wiring layer. The first wiring pattern 224 may be connected to the integrated device or the integrated circuit formed in the first base layer 210. That is, the first circuit layer 220 may be electrically connected to the integrated device or the integrated circuit formed in the first base layer 210. A portion of the first wiring pattern 224 may be exposed on the lower surface of the first circuit layer 220. The exposed portion 225 of the first wiring pattern 224 may correspond to a first chip pad 225 of the first semiconductor chip 200. A plurality of first chip pads 225 may be provided. The first wiring pattern 224 may include a wiring portion extending horizontally for horizontal wiring and a via portion vertically connected for vertical wiring. The first wiring pattern 224 may include a metal material such as copper (Cu) or aluminum (Al). The lower surface of the first semiconductor chip 200 on which the first wiring pattern 224 is provided may be an active surface of the first semiconductor chip 200.

[0031] The first through via 230 may vertically penetrate the first base layer 210. For example, the first through via 230 may have a columnar shape vertically penetrating the first base layer 210. One end of the first through via 230 may extend toward the front surface 200a of the first semiconductor chip 200 and be connected to the first circuit layer 220. The first through via 230 may be connected to the first wiring pattern 224 of the first circuit layer 220. The other end of the first through via 230 may be exposed on the top surface of the first base layer 210. For example, the other end of the first through via 230 may be located at the same level as the top surface of the first base layer 210, i.e., the back surface 200b of the first semiconductor chip 200. The top surface of the first through via 230 may be substantially flat and coplanar with the top surface of the first base layer 210. Alternatively, the first through via 230 may protrude above the top surface of the first base layer 210. For example, the other end of the first through via 230 may be located at a higher level than the top surface of the first base layer 210. In this case, a protective layer may be provided on the top surface of the first base layer 210, and the protective layer may cover the top surface of the first base layer 210 and surround the first through via 230. The top surface of the first through via 230 may be exposed on the top surface of the protective layer. A plurality of first through vias 230 may be provided. The first through via 230 may include a metal material, for example, copper (Cu) or tungsten (W), etc.

[0032] Although not shown, the first through via 230 may further include a via barrier film surrounding the outer surface of the first through via 230. In this case, the via barrier film may not cover the upper surface of the first through via 230. That is, the upper surface of the first through via 230 may be exposed without being covered by the via barrier film. The via barrier film may be provided to insulate the first through via 230 from the first base layer 210 or to prevent the material of the first through via 230 from diffusing into the first base layer 210. The via barrier film may include a conductive metal nitride, for example, titanium nitride (TiN) or tantalum nitride (TaN). Alternatively, the via barrier film may include an insulating film. The via barrier film may not be provided as necessary.

[0033] The first semiconductor chip 200 may be mounted on the package substrate 100 by a flip chip method. For example, the first semiconductor chip 200 may be disposed such that a first chip pad 225 faces the package substrate 100. That is, the first semiconductor chip 200 may be disposed such that a front surface 200a of the first semiconductor chip 200 faces the package substrate 100. A first chip terminal 240 may be provided between the first chip pad 225 and the package substrate 100. The first chip terminal 240 may be connected to the first chip pad 225. The first semiconductor chip 200 may be connected to the package substrate 100 through the first chip pad 225, the first chip terminal 240, and the substrate wiring pattern 120. The first chip terminal 240 may include a solder ball or a solder bump.

[0034] A first molding film 410 may be provided on the package substrate 100. The first molding film 410 may cover an upper surface of the package substrate 100. The first molding film 410 may surround the first semiconductor chip 200. The first molding film 410 may protect the first semiconductor chip 200. For example, the first molding film 410 may cover a side surface of the first semiconductor chip 200. The first molding film 410 may fill a space between the package substrate 100 and the first semiconductor chip 200. The first molding film 410 may surround a first chip terminal 240 between the package substrate 100 and the first semiconductor chip 200. The first molding film 410 may expose an upper surface 200b of the first semiconductor chip 200. An upper surface of the first molding film 410 may be coplanar with an upper surface 200b of the first semiconductor chip 200, and the upper surface of the first molding film 410 and the upper surface 200b of the first semiconductor chip 200 may be substantially flat. The first molding film 410 may include an insulating material. For example, the first molding film 410 may include an epoxy molding compound (EMC).

[0035] According to another embodiment, an underfill portion may be provided between the first semiconductor chip 200 and the package substrate 100. The underfill portion may include a non-conductive film (NCF). For example, the underfill portion may be a polymer tape including an insulating material. Alternatively, the underfill portion may include a fluid-type adhesive material. The underfill portion may fill a space between the first semiconductor chip 200 and the package substrate 100 and surround the first chip terminals 240. The underfill portion may be interposed between the first chip terminals 240 to prevent an electrical short between the first chip terminals 240. The underfill portion may protrude from a side surface of the first semiconductor chip 200. In this case, the first molding film 410 may surround both the underfill portion and the first semiconductor chip 200 on the package substrate 100.

[0036] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200. The second semiconductor chip 300 may be located on the back surface 200b of the first semiconductor chip 200. The second semiconductor chip 300 and the first semiconductor chip 200 may be disposed in an offset stack structure. For example, the first semiconductor chip 200 and the second semiconductor chip 300 may be stacked inclined in the first direction D1, which may be a step shape diagonally upward. In particular, in a plan view, a portion of the second semiconductor chip 300 may overlap the first semiconductor chip 200, and another portion of the second semiconductor chip 300 may protrude on a side surface of the first semiconductor chip 200 in the first direction D1. That is, the second semiconductor chip 300 may be stacked on the first semiconductor chip 200 so as to be shifted from the first semiconductor chip 200 in the first direction D1. In other words, the second semiconductor chip 300 may overlap a side surface of the first semiconductor chip 200 in the first direction D1 in a vertical direction. For example, when viewed from below the semiconductor package, a portion of the bottom surface of the second semiconductor chip 300 may be exposed and not covered by the first semiconductor chip 200 .

[0037] The configuration of the second semiconductor chip 300 may be substantially the same as or similar to the configuration of the first semiconductor chip 200 described above. That is, the second semiconductor chip 300 and the first semiconductor chip 200 may include the same semiconductor chip. For example, the width of the second semiconductor chip 300 may be the same as the width of the first semiconductor chip 200. Or, the second semiconductor chip 300 may be another semiconductor chip different from the first semiconductor chip 200. The second semiconductor chip 300 may be a logic chip. Alternatively, the second semiconductor chip 300 may be a memory chip such as a DRAM, an SRAM, an MRAM, or a flash memory. The second semiconductor chip 300 may have a front surface 300a and a back surface. The lower surface of the second semiconductor chip 300 may be the front surface 300a. That is, the second semiconductor chip 300 may be disposed face down on the first semiconductor chip 200. The second semiconductor chip 300 may include a second base layer 310 , a second circuit layer 320 , and at least one second through via 330 .

[0038] The second base layer 310 may include a semiconductor material. For example, the second base layer 310 may be a silicon (Si) single crystal substrate. A semiconductor element may be provided on the second base layer 310. In particular, an integrated element or an integrated circuit may be formed under the second base layer 310. For example, an integrated element such as a transistor may be formed on a lower surface of the second base layer 310, or a passive element such as a resistor, a capacitor, or an inductor, or a wiring pattern, etc. may be formed on the lower surface of the second base layer 310. That is, the lower surface of the second base layer 310 may be a front surface, and the upper surface of the second base layer 310 may be a back surface.

[0039] A second circuit layer 320 may be provided on the lower surface of the second base layer 310. The second circuit layer 320 may be electrically connected to the integrated device or the integrated circuit formed in the second base layer 310. For example, the second circuit layer 320 may have a second insulating pattern 322 and a second wiring pattern 324 provided in the second insulating pattern 322, and the second wiring pattern 324 may be connected to the integrated device or the integrated circuit formed in the second base layer 310.

[0040] The second insulating pattern 322 may cover the integrated device or the integrated circuit on the lower surface of the second base layer 310. Although the second insulating pattern 322 is illustrated as being one layer in FIGS. 1 and 3, the present invention is not limited thereto. According to another embodiment, a plurality of the second insulating patterns 322 may be provided, and the plurality of the second insulating patterns 322 may be stacked on one another. In this case, the second insulating patterns 322 may be wiring layers connected vertically to each other. The second insulating patterns 322 may include silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).

[0041] The second wiring pattern 324 may be provided in the second insulating pattern 322. When the second insulating pattern 322 is provided in a plurality of layers, the second wiring pattern 324 may also be provided in a plurality of layers, and one second insulating pattern 322 and one second wiring pattern 324 provided in the one second insulating pattern 322 may constitute one wiring layer. The second wiring pattern 324 may be connected to the integrated device or the integrated circuit formed in the second base layer 310. That is, the second circuit layer 320 may be electrically connected to the integrated device or the integrated circuit formed in the second base layer 310. A portion of the second wiring pattern 324 may be exposed on the lower surface of the second circuit layer 320. The exposed portion 325 of the second wiring pattern 324 may correspond to the second chip pad 325 of the second semiconductor chip 300. A plurality of second chip pads 325 may be provided. The second wiring pattern 324 may include a wiring portion extending horizontally for horizontal wiring and a via portion vertically connected for vertical wiring. The second wiring pattern 324 may include a metal material such as copper (Cu) or aluminum (Al). The lower surface of the second semiconductor chip 300 on which the second wiring pattern 324 is provided may be an active surface of the second semiconductor chip 300.

[0042] Since the second semiconductor chip 300 and the first semiconductor chip 200 are stacked in an offset stacking structure, the arrangement of the second chip pad 325 may not correspond to the arrangement of the first through via 230. More specifically, the second chip pad 325 may not be aligned vertically with the first through via 230. For example, at least a portion 230s of the first through via 230 may be spaced apart from the second semiconductor chip 300 in the opposite direction to the first direction D1. A portion 325s of the second chip pad 325 may be spaced apart from the first semiconductor chip 200 in the first direction D1. The second chip pad 325 may be aligned with the first through via 230 in a region where the first semiconductor chip 200 and the second semiconductor chip 300 overlap vertically. In contrast, the second chip pad 325 may not be aligned vertically with the first through via 230 in a region where the first semiconductor chip 200 and the second semiconductor chip 300 overlap vertically.

[0043] The second through via 330 may vertically penetrate the second base layer 310. For example, the second through via 330 may have a columnar shape vertically penetrating the second base layer 310. One end of the second through via 330 may extend toward the front surface 300a of the second semiconductor chip 300 and be connected to the second circuit layer 320. The second through via 330 may be connected to the second wiring pattern 324 of the second circuit layer 320. The other end of the second through via 330 may be exposed on the top surface of the second base layer 310. For example, the other end of the second through via 330 may be located at the same level as the top surface of the second base layer 310, i.e., the back surface of the second semiconductor chip 300. The top surface of the second through via 330 may be substantially flat and coplanar with the top surface of the second base layer 310. Alternatively, the second through via 330 may be protruded above the upper surface of the second base layer 310, and a protective film may be provided on the upper surface of the second base layer 310, and the protective film may cover the upper surface of the second base layer 310 and surround the second through via 330. A plurality of second through vias 330 may be provided. The second through via 330 may include a metal material, for example, copper (Cu) or tungsten (W), etc. If necessary, the second through via 330 may further include a via barrier film surrounding an outer surface of the second through via 330.

[0044] A redistribution layer 420 may be provided between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact an upper surface 200b of the first semiconductor chip 200 and a lower surface 300a of the second semiconductor chip 300. The redistribution layer 420 may extend from the first semiconductor chip 200 onto the first molding film 410. That is, the redistribution layer 420 may cover the upper surface 200b of the first semiconductor chip 200 and the upper surface of the first molding film 410. The redistribution layer 420 may be provided for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may include one wiring layer. The wiring layer may include one redistribution insulating pattern 422 and a redistribution pattern 424 in the redistribution insulating pattern 422.

[0045] The redistribution insulating pattern 422 may include an insulating polymer or a photoimageable dielectric (PID). For example, the redistribution insulating pattern 422 may include at least one of a photosensitive polyimide, a polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer. Alternatively, the redistribution insulating pattern 422 may include an insulating material such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc.

[0046] A redistribution pattern 424 may be provided in the redistribution insulating pattern 422. The redistribution pattern 424 may extend horizontally in the redistribution insulating pattern 422. For example, as shown in FIG. 2, the redistribution pattern 424 may include a pad portion 424p and a wiring portion 424w. That is, the redistribution pattern 424 may be configured for horizontal redistribution in the redistribution layer 420. The pad portions 424p of the redistribution pattern 424 may be exposed on the upper or lower surface of the redistribution insulating pattern 422, and the wiring portion 424w may connect the pad portions 424p. The redistribution pattern 424 may include a conductive material. For example, the redistribution pattern 424 may include a metal such as copper (Cu).

[0047] The pad portion 424p of the rewiring pattern 424 may be arranged to correspond to the positions of the first through vias 230 and the second chip pads 325. As an example, the pad portion 424p may be arranged along a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be parallel to the top surface of the package substrate 100 and may cross each other. As an example, the pad portion 424p may be arranged in a grid shape. Unlike what is illustrated, the pad portion 424p may be arranged in a honeycomb shape or in various other shapes. The pad portion 424p may serve as a substrate pad to which the first semiconductor chip 200 or the second semiconductor chip 300 is connected. For example, at least a portion of the pad portion 424p may be disposed on the first semiconductor chip 200. More specifically, the portion of the pad portion 424p may be disposed on one of the first through vias 230. On the interface between the redistribution layer 420 and the first semiconductor chip 200, the first through via 230 may be connected to the pad portion 424p. A portion of the pad portion 424p may be disposed under the second semiconductor chip 300. More specifically, the portion of the pad portion 424p may be disposed under one of the second chip pads 325. On the interface between the redistribution layer 420 and the second semiconductor chip 300, the second chip pad 325 may be connected to the pad portion 424p.

[0048] Since the second semiconductor chip 300 and the first semiconductor chip 200 are stacked in an offset stacking structure, the pad portion 424p located on one side of the first semiconductor chip 200 may be connected only to the second chip pad 325s of the second semiconductor chip 300, and the pad portion 424p located on one side of the second semiconductor chip 300 may be connected only to the first through via 230s of the first semiconductor chip 200. In an area where the first semiconductor chip 200 and the second semiconductor chip 300 overlap in the vertical direction, the pad portion 424p may be aligned with the first through via 230 and the second chip pad 325 as shown in FIG. 2. In this case, one of the pad portions 424p may be connected to both one of the first through vias 230 and one of the second chip pads 325. Unlike the illustrated example, in a region where the first semiconductor chip 200 and the second semiconductor chip 300 overlap in the vertical direction, the pad portion 424p may be aligned with only one of the first through vias 230 and the second chip pads 325. In this case, one of the pad portions 424p may be connected to one of the first through vias 230 or one of the second chip pads 325. The first through vias 230 and the second chip pads 325 may be connected by the pad portion 424p of the redistribution layer 420, or may be connected through the pad portion 424p and the wiring portion 424w. As an example, each of the wiring portions 424w may connect the pad portion 424p to which the first through vias 230 are connected and the pad portion 424p to which the second chip pads 325 are connected.

[0049] The thickness of the redistribution layer 420 may be greater than the thickness of one wiring layer in the second circuit layer 320. More specifically, a first thickness TH1 of the redistribution pattern 424 of the redistribution layer 420 may be greater than a second thickness TH2 of the second wiring pattern 324. Here, the thickness of the wiring pattern refers to the thickness of one wiring portion extending horizontally of the wiring pattern.

[0050] According to an embodiment of the present invention, since the second semiconductor chip 300 and the first semiconductor chip 200 are stacked in an offset stacking structure, at least a portion of the second chip pads 325 of the second semiconductor chip 300 may not be aligned with the first through vias 230 of the first semiconductor chip 200. In particular, a portion of the second chip pads 325 may be located on one side of the first semiconductor chip 200 in a plan view depending on the position of the second semiconductor chip 300. However, by providing a redistribution layer 420 between the first semiconductor chip 200 and the second semiconductor chip 300, the first through vias and the second chip pads 325 that are not aligned with each other may be electrically connected. That is, the electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300 may be good, and a semiconductor package with improved electrical characteristics may be provided.

[0051] Furthermore, the second semiconductor chip 300 may be electrically connected to the package substrate 100 through the redistribution layer 420 and the first through via 230 of the first semiconductor chip 200. That is, even if some 325s of the second chip pads 325 of the second semiconductor chip 300 are disposed on one side of the first semiconductor chip 200, a vertical connection structure such as a conductive post or a bridge chip for connecting some of the second chip pads 325s to the package substrate 100 may not be necessary. Therefore, restrictions on the thickness and width of the conductive post required when forming the conductive post on the first molding film 410 in the manufacturing process of the semiconductor package may be eliminated. Also, since the second semiconductor chip 300 is connected to the package substrate 100 through the first through via 230 formed in the first base layer 210 of the first semiconductor chip 200, the integration degree of the wiring connecting the second semiconductor chip 300 and the package substrate 100 may be increased. That is, a semiconductor package with improved integration degree may be provided. For example, the pitch PI between the first through vias 230 and the pitch between the second through vias 330 may be 4 μm to 30 μm. The third thickness TH3 of the first semiconductor chip 200 and the thickness of the second semiconductor chip 300 may be 100 μm to 1000 μm.

[0052] A second molding film 430 may be provided on the redistribution layer 420. The second molding film 430 may cover the redistribution layer 420. The first molding film 410 and the second molding film 430 may be spaced apart from each other by the redistribution layer 420. The second molding film 430 may embed the second semiconductor chip 300 on the redistribution layer 420. For example, the second molding film 430 may cover the side and top surface of the second semiconductor chip 300. Unlike what is illustrated, the second molding film 430 may expose the top surface of the second semiconductor chip 300. The bottom surface of the second molding film 430 may be coplanar with the bottom surface 300a of the second semiconductor chip 300. In other words, the redistribution layer 420 may cover the bottom surface of the second molding film 430 and the bottom surface 300a of the second semiconductor chip 300.

[0053] In the following embodiments, the same reference numerals are used for the components described in the embodiment of Figures 1 to 3, and for convenience of description, the description thereof will be omitted or will be briefly described, that is, the description will be focused on the differences between the embodiment of Figures 1 to 3 and the following embodiments.

[0054] Fig. 4 is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention, and Fig. 5 is a plan view for explaining a semiconductor package according to an embodiment of the present invention.

[0055] 4 and 5, a redistribution layer 420 may be provided between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the upper surface 200b of the first semiconductor chip 200 and the lower surface 300a of the second semiconductor chip 300. The redistribution layer 420 may include a plurality of wiring layers stacked on top of each other. Each of the wiring layers may include a redistribution insulating pattern 422 and a redistribution pattern 424 in the redistribution insulating pattern 422. The redistribution pattern 424 of any one wiring layer may be electrically connected to the redistribution pattern 424 of another adjacent wiring layer.

[0056] 4, the redistribution insulating pattern 422 is illustrated as being one layer, but the redistribution layer 420 may have a plurality of redistribution insulating patterns 422 stacked vertically. Within each redistribution insulating pattern 422, a redistribution pattern 424 may be provided.

[0057] The redistribution pattern 424 may include a first pad portion 424p1 exposed on a lower surface of the redistribution layer 420, a second pad portion 424p2 exposed on an upper surface of the redistribution layer 420, and a wiring portion 424w connecting the first pad portion 424p1 and the second pad portion 424p2 within the redistribution layer 420. For convenience of explanation, the wiring portion 424w is shown by an arbitrary dotted line in Figures 4 and 5, but this is merely to show an electrical connection of the wiring portion 424w and is not intended to limit the shape and position of the wiring portion 424w.

[0058] The first pad portion 424p1 may be located above the first semiconductor chip 200. The first pad portion 424p1 may be connected to the first through via 230 on the interface between the redistribution layer 420 and the first semiconductor chip 200.

[0059] The second pad portion 424p2 may be located under the second semiconductor chip 300. The second pad portion 424p2 may be connected to a second chip pad 325 on the interface between the redistribution layer 420 and the second semiconductor chip 300.

[0060] As in the embodiments of Figures 4 and 5, when the redistribution layer 420 has multiple wiring layers, i.e., when the redistribution layer 420 has an internal wiring portion 424w, the degree of wiring freedom for connecting the first semiconductor chip 200 and the second semiconductor chip 300 can be high.

[0061] 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention, and FIG 7 is an enlarged view of region B of FIG 6.

[0062] 6 and 7, a first semiconductor chip 200 may be disposed on a package substrate 100. A lower surface of the first semiconductor chip 200 may be a back surface 200b. That is, the first semiconductor chip 200 may be disposed face up on the package substrate 100. The first semiconductor chip 200 may include a first base layer 210, a first circuit layer 220, and at least one first through via 230.

[0063] The first circuit layer 220 may be provided on the upper surface of the first base layer 210. The first circuit layer 220 may be electrically connected to the integrated device or the integrated circuit formed in the first base layer 210. For example, the first circuit layer 220 may have a first insulating pattern 222 and a first wiring pattern 224 provided in the first insulating pattern 222. A portion of the first wiring pattern 224 may be exposed on the upper surface of the first circuit layer 220. The exposed portion 225 of the first wiring pattern 224 may correspond to a first chip pad 225 of the first semiconductor chip 200. A plurality of first chip pads 225 may be provided.

[0064] The first through via 230 may vertically penetrate the first base layer 210. One end of the first through via 230 may extend toward the front surface 200a of the first semiconductor chip 200 and be connected to the first circuit layer 220. The other end of the first through via 230 may be exposed on the bottom surface of the first base layer 210.

[0065] The first semiconductor chip 200 may further include a rear pad 252 and a rear protective film 254 .

[0066] Rear pads 252 may be disposed on the lower surface 200b of the first semiconductor chip 200. Each of the rear pads 252 may be connected to one of the first through vias 230 on the lower surface of the first base layer 210. The rear pads 252 may include a conductive material. For example, the rear pads 252 may include a metal material such as copper (Cu) or tungsten (W).

[0067] A rear protective film 254 may be disposed on the lower surface of the first base layer 210. The rear protective film 254 may cover the lower surface of the first base layer 210. The rear protective film 254 may surround the rear pad 252. In this case, the lower surface of the rear protective film 254 and the lower surface of the rear pad 252 may be substantially flat and coplanar. The rear protective film 254 may include an insulating material. For example, the rear protective film 254 may include silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). Alternatively, the rear protective film 254 may include an adhesive material.

[0068] The first semiconductor chip 200 may be mounted on the package substrate 100 by a flip chip method. For example, the first semiconductor chip 200 may be arranged such that a rear pad 252 faces the package substrate 100. That is, the first semiconductor chip 200 may be arranged such that a rear surface 200b of the first semiconductor chip 200 faces the package substrate 100. A first chip terminal 240 may be provided between the rear pad 252 and the package substrate 100. The first chip terminal 240 may be connected to the rear pad 252. The first semiconductor chip 200 may be connected to the package substrate 100 through the rear pad 252, the first chip terminal 240, and the substrate wiring pattern 120.

[0069] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200. Since the second semiconductor chip 300 and the first semiconductor chip 200 are stacked in an offset stacking structure, the arrangement of the second chip pads 325 may not correspond to the arrangement of the first chip pads 225. More specifically, the second chip pads 325 may not be aligned vertically with the first chip pads 225. For example, at least a portion 225s of the first chip pads 225 may be spaced apart from the second semiconductor chip 300 in the opposite direction to the first direction D1. A portion 325s of the second chip pads 325 may be spaced apart from the first semiconductor chip 200 in the first direction D1. The second chip pads 325 may be aligned with the first chip pads 225 in an area where the first semiconductor chip 200 and the second semiconductor chip 300 overlap vertically. Alternatively, in an area where the first semiconductor chip 200 and the second semiconductor chip 300 overlap vertically, the second chip pads 325 may not be vertically aligned with the first chip pads 225 .

[0070] A redistribution layer 420 may be provided between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may be in contact with the upper surface 200a of the first semiconductor chip 200 and the lower surface 300a of the second semiconductor chip 300.

[0071] A redistribution pattern 424 may be provided in the redistribution insulation pattern 422. The redistribution pattern 424 may extend horizontally in the redistribution insulation pattern 422. Pad portions of the redistribution pattern 424 may be arranged to correspond to the positions of the first chip pad 225 and the second chip pad 325. Thus, the redistribution layer 420 may electrically connect the first chip pad 225 and the second chip pad 325.

[0072] The thickness of the redistribution layer 420 may be greater than the thickness of one wiring layer in the first circuit layer 220 and the thickness of one wiring layer in the second circuit layer 320. More specifically, the first thickness TH1 of the redistribution pattern 424 of the redistribution layer 420 may be greater than the fourth thickness TH4 of the first wiring pattern 224 and the second thickness TH2 of the second wiring pattern 324.

[0073] According to an embodiment of the present invention, the front surface 200a of the first semiconductor chip 200 and the front surface 300a of the second semiconductor chip 300 may be directly connected to each other through the redistribution layer 420. Therefore, the length of the electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300 may be short, and a semiconductor package with improved electrical characteristics may be provided.

[0074] Fig. 8 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention, Fig. 9 is a plan view illustrating a semiconductor package according to an embodiment of the present invention, and Fig. 10 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0075] 8 and 9, a redistribution layer 420 may be provided between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the upper surface 200b of the first semiconductor chip 200 and the lower surface 300a of the second semiconductor chip 300. In this case, the redistribution layer 420 may cover the entire lower surface 300a of the second semiconductor chip 300, or may cover only a portion of the upper surface 200b of the first semiconductor chip 200. More specifically, the redistribution layer 420 may not cover the upper surface 200b of the first semiconductor chip 200 at one side of the second semiconductor chip 300, but may be exposed. The second molding film 430 may surround the second semiconductor chip 300 and the redistribution layer 420. At the one side of the second semiconductor chip 300, the second molding film 430 may contact the exposed upper surface 200b of the first semiconductor chip 200. At one side of the first semiconductor chip 200, the first semiconductor chip 200 may expose a lower surface of the redistribution layer 420. At the one side of the first semiconductor chip 200, the first molding film 410 may be in contact with the exposed lower surface of the redistribution layer 420. At one side of the first and second semiconductor chips 200 and 300, the second molding film 430 may be in contact with the first molding film 410. The redistribution layer 420 may be provided for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may include one wiring layer. The wiring layer may include one redistribution insulation pattern 422 and a redistribution pattern 424 in the redistribution insulation pattern 422.

[0076] Since the second semiconductor chip 300 and the first semiconductor chip 200 are stacked in an offset stacking structure, the pad portion 424p located on one side of the first semiconductor chip 200 may be connected only to the second chip pad 325s of the second semiconductor chip 300. The first through via 230s of the first semiconductor chip 200 located on one side of the second semiconductor chip 300 may not contact the redistribution layer 420. In the region where the first semiconductor chip 200 and the second semiconductor chip 300 overlap in the vertical direction, as shown in FIG. 9, one of the pad portions 424p may be connected to one of the first through vias 230 and one of the second chip pads 325. Unlike the illustrated example, one of the pad portions 424p may be connected to one of the first through vias 230 or one of the second chip pads 325. The first through via 230 and the second chip pad 325 may be connected by the pad portion 424p of the redistribution layer 420, or may be connected through the pad portion 424p and the wiring portion 424w.

[0077] Although the first semiconductor chip 200 is illustrated in a face-down configuration in FIGS. 8 and 9, the present invention is not limited thereto.

[0078] 10, a first semiconductor chip 200 may be disposed on a package substrate 100 in the same or similar manner as described with reference to FIG. 6. A lower surface of the first semiconductor chip 200 may be a rear surface 200b. That is, the first semiconductor chip 200 may be disposed face up on the package substrate 100. The first semiconductor chip 200 may include a first base layer 210, a first circuit layer 220, and at least one first through via 230. The first semiconductor chip 200 may further include a rear pad 252 and a rear protective film 254.

[0079] Since the second semiconductor chip 300 and the first semiconductor chip 200 are stacked in an offset stacking structure, the pad portion of the rewiring pattern 424 located on one side of the first semiconductor chip 200 may be connected only to the second chip pad 325s of the second semiconductor chip 300. The first chip pad 225s of the first semiconductor chip 200 located on one side of the second semiconductor chip 300 may not contact the rewiring layer 420. In an area where the first semiconductor chip 200 and the second semiconductor chip 300 are vertically overlapped, one of the pad portions of the rewiring pattern 424 may be connected to both one of the first chip pads 225 and one of the second chip pads 325. Unlike as illustrated, one of the pad portions of the rewiring pattern 424 may be connected to one of the first chip pads 225 or one of the second chip pads 325.

[0080] FIG. 11 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0081] 11, redistribution layers 420-1 and 420-2 may be provided between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layers 420-1 and 420-2 may include a first redistribution layer 420-1 provided on the upper surface 200b of the first semiconductor chip 200 and a second redistribution layer 420-2 provided on the lower surface 300a of the second semiconductor chip 300.

[0082] The configuration of the first redistribution layer 420-1 may be substantially the same as or similar to the redistribution layer 420 described with reference to FIG. 1. For example, the first redistribution layer 420-1 may contact the upper surface 200b of the first semiconductor chip 200. The first redistribution layer 420-1 may extend from the upper surface 200b of the first semiconductor chip 200 onto the first molding film 410. That is, the first redistribution layer 420-1 may cover the upper surface 200b of the first semiconductor chip 200 and the upper surface of the first molding film 410. The first redistribution layer 420-1 may include one wiring layer. The wiring layer may include one first redistribution insulating pattern 422-1 and a first redistribution pattern 424-1 in the first redistribution insulating pattern 422-1. The first redistribution pattern 424-1 may be connected to the first through vias 230, 230s of the first semiconductor chip 200.

[0083] The configuration of the second redistribution layer 420-2 may be substantially the same as or similar to the redistribution layer 420 described with reference to FIG. 8. For example, the second redistribution layer 420-2 may contact the lower surface 300a of the second semiconductor chip 300. In this case, the second redistribution layer 420-2 may cover the entire lower surface 300a of the second semiconductor chip 300. The second molding film 430 may surround the second semiconductor chip 300 and the second redistribution layer 420-2. The second redistribution layer 420-2 may include one wiring layer. The wiring layer may include one second redistribution insulating pattern 422-2 and a second redistribution pattern 424-2 in the second redistribution insulating pattern 422-2. The second redistribution pattern 424-2 may be connected to a second chip pad 325 of the second semiconductor chip 300.

[0084] The second redistribution layer 420-2 may be disposed on the first redistribution layer 420-1. An upper surface of the first redistribution layer 420-1 and a lower surface of the second redistribution layer 420-2 may be in contact with each other. The second redistribution layer 420-2 may cover a portion of the upper surface of the first redistribution layer 420-1. More specifically, the second redistribution layer 420-2 may not cover the upper surface of the first redistribution layer 420-1 at one side of the second semiconductor chip 300, but may be exposed. At the one side of the second semiconductor chip 300, the second molding film 430 may be in contact with the exposed upper surface of the first redistribution layer 420-1. The first redistribution pattern 424-1 of the first redistribution layer 420-1 and the second redistribution pattern 424-2 of the second redistribution layer 420-2 may be connected to each other. The first and second semiconductor chips 200 and 300 may be electrically connected to each other through a first redistribution layer 420-1 and a second redistribution layer 420-2.

[0085] FIG. 12 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0086] 12, a plurality of first semiconductor chips 200 may be provided. The first semiconductor chips 200 may be arranged on the package substrate 100 and spaced apart from each other horizontally.

[0087] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200. The second semiconductor chip 300 may be located on an upper surface of the first semiconductor chip 200. The second semiconductor chip 300 may be disposed in an offset stack structure with one of the first semiconductor chips 200. For example, in a plan view, a portion of the second semiconductor chip 300 may overlap one of the first semiconductor chips 200, and another portion of the second semiconductor chip 300 may overlap another one of the first semiconductor chips 200.

[0088] A redistribution layer 420 may be provided between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the upper surface of the first semiconductor chip 200 and the lower surface of the second semiconductor chip 300. The redistribution layer 420 may cover the upper surface of the first semiconductor chip 200 and the upper surface of the first molding film 410. The redistribution layer 420 may be provided for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may include a redistribution insulating pattern 422 and a redistribution pattern 424 in the redistribution insulating pattern 422. The redistribution pattern 424 may electrically connect the second chip pad 325 of the second semiconductor chip 300 and the first through via 230 of the first semiconductor chip 200.

[0089] FIG. 13 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0090] 13, a plurality of second semiconductor chips 300 may be provided. The second semiconductor chips 300 may be disposed on the first semiconductor chip 200 and spaced apart horizontally from each other.

[0091] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200. The second semiconductor chip 300 may be located on an upper surface of the first semiconductor chip 200. Each of the second semiconductor chips 300 may be disposed in an offset stack structure with the first semiconductor chip 200. For example, in a plan view, each of the second semiconductor chips 300 may have a portion overlapping with the first semiconductor chip 200 and the other portion protruding from one side of the first semiconductor chip 200.

[0092] A redistribution layer 420 may be provided between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the upper surface of the first semiconductor chip 200 and the lower surface of the second semiconductor chip 300. The redistribution layer 420 may cover the upper surface of the first semiconductor chip 200 and the upper surface of the first molding film 410. The redistribution layer 420 may be provided for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may include a redistribution insulating pattern 422 and a redistribution pattern 424 in the redistribution insulating pattern 422. The redistribution pattern 424 may electrically connect the second chip pad 325 of the second semiconductor chip 300 and the first through via 230 of the first semiconductor chip 200.

[0093] FIG. 14 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0094] 1 to 13, the second semiconductor chip 300 may have a different configuration from the first semiconductor chip 200. For example, the width of the second semiconductor chip 300 may be greater than the width of the first semiconductor chip 200. Thus, a portion of the second semiconductor chip 300 may protrude from the first semiconductor chip 200 to one side in the first direction D1. For example, a portion 325s of the second chip pad 325 of the second semiconductor chip 300 may be located on one side of the first semiconductor chip 200 in a plan view.

[0095] A redistribution layer 420 may be provided between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the upper surface of the first semiconductor chip 200 and the lower surface of the second semiconductor chip 300. The redistribution layer 420 may cover the upper surface of the first semiconductor chip 200 and the upper surface of the first molding film 410. The redistribution layer 420 may be provided for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may include a redistribution insulating pattern 422 and a redistribution pattern 424 in the redistribution insulating pattern 422. The redistribution pattern 424 may electrically connect the second chip pad 325 of the second semiconductor chip 300 and the first through via 230 of the first semiconductor chip 200.

[0096] According to an embodiment of the present invention, by providing a redistribution layer 420 between the first semiconductor chip 200 and the second semiconductor chip 300, it is possible to more easily achieve electrical connection between the first and second semiconductor chips 200, 300, which are different in size from each other.

[0097] 15 to 18 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0098] 15, a carrier substrate 900 may be provided. The carrier substrate 900 may be an insulating substrate including glass or polymer, or a conductive substrate including metal. An adhesive member may be provided on an upper surface of the carrier substrate 900. As an example, the adhesive member may include an adhesive tape.

[0099] The package substrate 100 may be formed on the carrier substrate 900. A process for forming the substrate 100 will now be described in detail.

[0100] A lower insulating layer 910 may be provided on the carrier substrate 900. The lower insulating layer 910 may include an insulating polymer or a photosensitive polymer.

[0101] The external pad 130 may be formed inside the lower insulating layer 910. For example, the lower insulating layer 910 may be patterned to form an opening for the external pad 130 to be formed therein, a seed layer may be conformally formed in the opening, and a plating process may be performed using the seed layer as a seed to form the external pad 130 filling the opening.

[0102] A substrate insulating layer 110 may be formed on the lower insulating layer 910. The substrate insulating layer 110 may be formed by a coating process such as spin coating or slit coating.

[0103] A substrate wiring pattern 120 may be formed. For example, after patterning the substrate insulating layer 110 to form an opening exposing the external pad 130, a barrier film and a conductive layer may be formed on the substrate insulating layer 110 to fill the opening, and a planarization process may be performed on the barrier film and the conductive layer to form the substrate wiring pattern 120. As described above, a substrate wiring layer having the substrate insulating layer 110 and the substrate wiring pattern 120 may be formed. The process of forming the substrate wiring layer may be repeated to form a package substrate 100 in which the substrate wiring layers are stacked. The substrate wiring pattern 120 of the substrate wiring layer located at the top may correspond to a substrate pad of the package substrate 100.

[0104] A first semiconductor chip 200 may be provided. The first semiconductor chip 200 may be substantially the same as or similar to the first semiconductor chip 200 described with reference to FIG.

[0105] A first semiconductor chip 200 may be mounted on a package substrate 100. For example, solder balls may be provided on first chip pads 225 of the first semiconductor chip 200. The first semiconductor chip 200 may be positioned on the package substrate 100 such that the first chip pads 225 are aligned with the board wiring pattern 120 of the package substrate 100. Then, the first semiconductor chip 200 may be lowered such that the solder balls contact the board wiring pattern 120, and a reflow process may be performed on the solder balls to form first chip terminals 240 connecting the first semiconductor chip 200 and the package substrate 100.

[0106] 16, a first molding film 410 may be formed on a package substrate 100. For example, a first molding material may be applied to an upper surface of the package substrate 100 to embed the first semiconductor chip 200, and the first molding material may be hardened to form the first molding film 410. The first molding film 410 may cover an upper surface of the package substrate 100, a side surface of the first semiconductor chip 200, and a rear surface of the first semiconductor chip 200. That is, the first semiconductor chip 200 may not be exposed to the outside of the first molding film 410.

[0107] A portion of the first molding film 410 and a portion of the first semiconductor chip 200 may be removed. In particular, the first semiconductor chip 200 may be thinned. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on the upper surface of the first molding film 410. Thus, the back surface of the first semiconductor chip 200 and the upper surface of the first molding film 410 may be flat. An upper portion of the first molding film 410 may be removed by the thinning process. That is, the back surface of the first semiconductor chip 200 may be exposed by the thinning process. The back surface of the first semiconductor chip 200 and the upper surface of the first molding film 410 may be substantially flat and coplanar.

[0108] 17, a redistribution layer 420 may be formed on the first molding film 410 and the first semiconductor chip 200. For example, a redistribution insulating pattern 422 may be formed by applying or depositing an insulating material on the top surface of the first molding film 410 and the back surface of the first semiconductor chip 200. Then, the redistribution insulating pattern 422 may be patterned to form an opening, a seed film may be conformally formed in the opening, and a plating process may be performed using the seed film as a seed to form a redistribution pattern 424 filling the opening. A portion of the opening may expose the first through via 230 of the first semiconductor chip 200. The portion of the opening may define an area in which a pad portion of the redistribution pattern 424 connected to the first semiconductor chip 200 is to be formed. The other portion of the opening may be located on one side of the first semiconductor chip 200. The other portion of the opening may define an area in which a pad portion of the redistribution pattern 424 to which a second chip pad 325 of the second semiconductor chip 300 is to be connected is to be formed. During the process of forming the openings in the redistribution insulating pattern 422, trenches may be formed in the redistribution insulating pattern 422. The trenches may connect the openings. The trenches may define an area in which a wiring portion of the redistribution pattern 424 is to be formed.

[0109] 18, a second semiconductor chip 300 may be provided on a redistribution layer 420. For example, second chip pads 325 of the second semiconductor chip 300 may be aligned with redistribution patterns 424 of the redistribution layer 420. Then, the second semiconductor chip 300 may be lowered such that the second chip pads 325 come into contact with the redistribution patterns 424. The second chip pads 325 may be bonded to the redistribution patterns 424 on the interface between the second semiconductor chip 300 and the redistribution layer 420.

[0110] 1, a second molding film 430 may be formed on the redistribution layer 420. For example, a second molding material may be applied to an upper surface of the redistribution layer 420 to embed the second semiconductor chip 300, and the second molding material may be hardened to form the second molding film 430. The second molding film 430 may cover an upper surface of the redistribution layer 420, a side surface of the second semiconductor chip 300, and a rear surface of the second semiconductor chip 300.

[0111] The carrier substrate 900 may be removed, so that the bottom surface of the package substrate 100, for example the external pads 130 of the package substrate 100, may be exposed.

[0112] The lower insulating layer 910 may be removed, and a substrate protection layer 140 may be formed under the substrate 100. The substrate protection layer 140 may cover the substrate wiring pattern 120 and the external pads 130 under the substrate insulating layer 110. Alternatively, an insulating material layer may be additionally applied on the lower insulating layer 910. The lower insulating layer 910 may form the substrate protection layer 140 together with the insulating material layer.

[0113] 19 to 21 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0114] 19, a second semiconductor chip 300 may be provided. The second semiconductor chip 300 may be substantially the same as or similar to the second semiconductor chip 300 described with reference to FIG.

[0115] 20, a redistribution layer 420 may be formed on the second semiconductor chip 300. More specifically, for example, an insulating material may be applied or deposited on an upper surface of the second circuit layer 320 of the second semiconductor chip 300 to form a redistribution insulating pattern 422. Then, the redistribution insulating pattern 422 may be patterned to form an opening, a seed layer may be conformally formed in the opening, and a plating process may be performed using the seed layer as a seed to form a redistribution pattern 424 filling the opening. A portion of the opening may expose a second chip pad 325 of the second semiconductor chip 300. The portion of the opening may define an area in which a pad portion of the redistribution pattern 424 connected to the second semiconductor chip 300 is to be formed. Another portion of the opening may be located on one side of the second semiconductor chip 300. The other portion of the opening may define an area in which a pad portion of the redistribution pattern 424 to which the first chip pad 225 of the first semiconductor chip 200 is to be connected is to be formed. During the process of forming the openings in the redistribution insulating pattern 422, trenches may be formed in the redistribution insulating pattern 422. The trenches may connect the openings. The trenches may define an area in which a wiring portion of the redistribution pattern 424 is to be formed.

[0116] 21, on the resultant structure of FIG. 16, a first semiconductor chip 200 and a second semiconductor chip 300 may be provided on a first molding film 410. For example, a redistribution pattern 424 of a redistribution layer 420 may be aligned with a first through via 230 of the first semiconductor chip 200. Then, the second semiconductor chip 300 may be lowered so that the redistribution pattern 424 contacts the first through via 230. The redistribution pattern 424 and the first through via 230 may be bonded to an interface between the redistribution layer 420 and the first semiconductor chip 200.

[0117] 8, a second molding film 430 may be formed on the first molding film 410. For example, a second molding material may be applied on an upper surface of the first molding film 410 and the upper surface 200a of the first semiconductor chip 200 to embed the second semiconductor chip 300, and the second molding material may be hardened to form the second molding film 430. The second molding film 430 may cover a side surface of the redistribution layer 420, a side surface of the second semiconductor chip 300, and a back surface of the second semiconductor chip 300.

[0118] The carrier substrate 900 may be removed, so that the bottom surface of the package substrate 100, for example the external pads 130 of the package substrate 100, may be exposed.

[0119] The lower insulating layer 910 may be removed, and a substrate protection layer 140 may be formed under the package substrate 100 .

[0120] FIG. 22 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0121] 22, the resultant structure of FIG. 20 may be provided on the resultant structure of FIG. 17. Here, the redistribution layer 420 (see FIG. 17) manufactured with reference to FIG. 17 will be referred to as a first redistribution layer 420-1, and the redistribution layer 420 (see FIG. 20) manufactured with reference to FIG. 20 will be referred to as a second redistribution layer 420-2.

[0122] The second semiconductor chip 300 may be provided on the first redistribution layer 420-1. For example, the second redistribution pattern 424-2 of the second redistribution layer 420-2 may be aligned with the first redistribution pattern 424-1 of the first redistribution layer 420-1. Then, the second semiconductor chip 300 may be lowered so that the first and second redistribution patterns 424-1, 424-2 contact each other. The first and second redistribution patterns 424-1, 424-2 may be bonded to each other on the interface between the first redistribution layer 420-1 and the second redistribution layer 420-2. The first redistribution insulating pattern 422-1 and the second redistribution insulating pattern 422-2 may contact each other on the interface between the first redistribution layer 420-1 and the second redistribution layer 420-2.

[0123] 11 again, a second molding film 430 may be formed on the first redistribution layer 420-1. For example, a second molding material may be applied on an upper surface of the first redistribution layer 420-1 to embed the second semiconductor chip 300, and the second molding material may be hardened to form the second molding film 430. The second molding film 430 may cover a side surface of the second redistribution layer 420-2, a side surface of the second semiconductor chip 300, and a back surface of the second semiconductor chip 300.

[0124] The carrier substrate 900 may be removed, so that the bottom surface of the package substrate 100, for example the external pads 130 of the package substrate 100, may be exposed.

[0125] The lower insulating layer 910 may be removed, and a substrate protection layer 140 may be formed under the package substrate 100 .

[0126] Although the embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0127] 100 Package Substrate 200 First semiconductor chip 300 Second semiconductor chip 410 First molding film 420 Redistribution layer 430 Second molding film

Claims

1. A package substrate; a lower semiconductor chip mounted on the package substrate; an upper semiconductor chip disposed on the lower semiconductor chip so as to be shifted horizontally with respect to the lower semiconductor chip; a wiring layer in contact with an upper surface of the lower semiconductor chip and a lower surface of the upper semiconductor chip; the wiring layer covers the lower surface of the upper semiconductor chip on one side of the lower semiconductor chip and extends between the lower semiconductor chip and the upper semiconductor chip; the upper semiconductor chip includes a first circuit layer provided on the lower surface of the upper semiconductor chip; A semiconductor package in which the thickness of the wiring pattern of the first circuit layer is thinner than the thickness of the wiring pattern of the wiring layer.

2. a first molding layer surrounding the lower semiconductor chip on the package substrate; a second molding layer surrounding the upper semiconductor chip on the first molding layer, The semiconductor package of claim 1 , wherein the wiring layer is interposed between the first molding film and the lower surface of the upper semiconductor chip.

3. The semiconductor package of claim 2 , wherein the wiring layer extends between the first molding film and the second molding film.

4. 4. The semiconductor package of claim 3, wherein the lower semiconductor chip and the first molding film are separated from the upper semiconductor chip and the second molding film by the wiring layer.

5. The semiconductor package of claim 2 , wherein the first molding film and the second molding film contact each other on one side of the upper semiconductor chip.

6. the lower semiconductor chip includes a second circuit layer provided on the top surface of the lower semiconductor chip; the wiring layer is directly connected to the first circuit layer and the second circuit layer; 2. The semiconductor package according to claim 1, wherein the thickness of the wiring pattern of the second circuit layer is thinner than the thickness of the wiring pattern of the wiring layer.

7. The lower semiconductor chip includes: a second circuit layer provided on a lower surface of the lower semiconductor chip; a first via that is connected to the second circuit layer by vertically penetrating the lower semiconductor chip and is exposed on the top surface of the lower semiconductor chip; The semiconductor package of claim 1 , wherein the wiring layer is directly connected to the first circuit layer and the first via.

8. The wiring layer is a first sub-wiring layer in contact with the upper surface of the lower semiconductor chip; a second sub-wiring layer in contact with the lower surface of the upper semiconductor chip; the first sub-wiring layer overlaps the upper surface of the lower semiconductor chip and the lower surface of the upper semiconductor chip, The semiconductor package according to claim 1 , wherein the second sub-wiring layer overlaps the lower surface of the upper semiconductor chip and does not cover at least a portion of the upper surface of the lower semiconductor chip.

9. the lower semiconductor chip includes a first via vertically penetrating the lower semiconductor chip and connected to a second circuit layer of the lower semiconductor chip; the upper semiconductor chip includes a second via vertically penetrating the upper semiconductor chip and connected to the first circuit layer, and a chip pad of the first circuit layer; The semiconductor package of claim 1 , wherein at least a portion of the chip pad is located on one side of the lower semiconductor chip in a plan view.

10. The semiconductor package of claim 9 , wherein the wiring pattern of the wiring layer electrically connects the portion of the chip pad and the first via.

11. A package substrate; a first semiconductor chip mounted on the package substrate by flip chip mounting; a first molding layer surrounding the lower semiconductor chip on the package substrate; a first wiring layer covering an upper surface of the first semiconductor chip and an upper surface of the first molding film; a second semiconductor chip on the first wiring layer; a second molding film surrounding the second semiconductor chip on the first wiring layer; and an external terminal provided on a lower surface of the package substrate; the second semiconductor chip is shifted with respect to the first semiconductor chip so as to overlap one side of the first semiconductor chip in a vertical direction; The first semiconductor chip and the first molding film are separated from the second semiconductor chip and the second molding film by the first wiring layer.

12. The first semiconductor chip is a first circuit layer provided on one side of the first semiconductor chip; a first via that vertically penetrates the first semiconductor chip and is connected to the first circuit layer; The second semiconductor chip is a second circuit layer provided on one side of the second semiconductor chip; The semiconductor package of claim 11 , further comprising: a second via that vertically passes through the second semiconductor chip and is connected to the second circuit layer.

13. the first circuit layer is provided on the top surface of the first semiconductor chip facing the second semiconductor chip; the second circuit layer is provided on a bottom surface of the second semiconductor chip facing the first semiconductor chip; The semiconductor package according to claim 12 , wherein the first wiring layer is connected to the first circuit layer and the second circuit layer.

14. the first circuit layer is provided on a bottom surface of the first semiconductor chip facing the package substrate; the second circuit layer is provided on a bottom surface of the second semiconductor chip facing the first semiconductor chip; The semiconductor package according to claim 12 , wherein the first wiring layer is connected to the first via exposed on the top surface of the first semiconductor chip and the second circuit layer.

15. The semiconductor package according to claim 12 , wherein a thickness of the wiring pattern of the first circuit layer and a thickness of the wiring pattern of the second circuit layer are thinner than a thickness of the wiring pattern of the first wiring layer.

16. At least a portion of the chip pads of the second circuit layer is located on one side of the first semiconductor chip in a plan view, The semiconductor package of claim 12 , wherein the wiring pattern of the first wiring layer electrically connects the portion of the chip pad of the second via to the first via.

17. a second wiring layer provided on a lower surface of the second semiconductor chip; The semiconductor package of claim 11 , wherein the second molding film surrounds the second semiconductor chip and the second wiring layer on the first wiring layer.

18. 18. The semiconductor package of claim 17, wherein the second wiring layer is interposed between the first molding film and the second semiconductor chip and between the first semiconductor chip and the second semiconductor chip, and exposes an upper surface of the first wiring layer on one side of the second semiconductor chip.

19. A package substrate; a first semiconductor chip on the package substrate, the first semiconductor chip including a first circuit layer provided on one surface of the first semiconductor chip and a first via vertically penetrating the first semiconductor chip and connected to the first circuit layer; a first molding film surrounding the first semiconductor chip on the package substrate; a second semiconductor chip that is shifted horizontally with respect to the first semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit layer provided on a lower surface of the second semiconductor chip and a second via that vertically penetrates the second semiconductor chip and is connected to the second circuit layer; a first wiring layer interposed between the second circuit layer and the first semiconductor chip and between the second circuit layer and the first molding film; a second molding film surrounding the first wiring layer and the second semiconductor chip on the first molding film; the first wiring layer exposes a top surface of the first semiconductor chip at one side of the second semiconductor chip; a second semiconductor chip connected to the first wiring layer through a chip pad of the second circuit layer, at least a portion of the chip pad being located on one side of the first semiconductor chip in a planar view, and a wiring pattern of the first wiring layer electrically connecting the portion of the chip pad to the first via.

20. 20. The semiconductor package according to claim 19, wherein the thickness of the wiring pattern of the second circuit layer is thinner than the thickness of the wiring pattern of the first wiring layer.

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