integrator

Abstract

To miniaturize a circuit for reducing a noise of a same phase in a whole difference type integrator.SOLUTION: An integrator 100 comprises: a positive side circuit 110 to which a positive input signal AIN+ is input, and from which a positive output signal AOUT+ is output; and a negative side circuit 130 into which a negative input signal AIN- is input, and from which a negative output signal AOUT- is output. The positive side circuit includes: a positive side delay circuit 112 that outputs a positive output signal by delaying a signal generated in accordance with the positive input signal and a positive feedback signal FB+; and a positive feedback circuit 170 that amplifies a difference between the positive output signal and the negative output signal, and generates the positive feedback signal. The positive side feedback circuit includes: a first subtraction part 114 that outputs a difference between the positive output signal and the negative output signal; and a first amplification part 113 that amplifies the signal output by the first subtraction part, and generates the positive feedback signal on the basis of the signal output by the first amplification part.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an integrator. [Background technology]

[0002] Conventionally, a fully differential structure is known as a technique for reducing common-mode noise in an integrator (see, for example, FIG. 21 of Patent Document 1). In a fully differential integrator, if a common-mode feedback circuit for stabilizing the output common voltage is provided, the circuit size increases. [Prior art document] [Patent documents] Patent Document 1: JP 2019-118100 A Summary of the Invention

[0003] One aspect of the present invention provides an integrator. The integrator may include a positive-side circuit that receives a positive input signal and outputs a positive output signal. Any of the integrators may include a negative-side circuit that receives a negative input signal and outputs a negative output signal. In any of the integrators, the positive-side circuit may include a positive-side delay circuit that delays a signal generated in response to the positive input signal and a positive feedback signal and outputs the positive output signal. In any of the integrators, the positive-side circuit may include a positive-side feedback circuit that amplifies a difference between the positive output signal and the negative output signal to generate the positive feedback signal.

[0004] In any of the above integrators, the positive-side feedback circuit may have a first subtraction unit that outputs a difference between the positive output signal and the negative output signal. In any of the above integrators, the positive-side feedback circuit may have a first amplification unit that amplifies the signal output by the first subtraction unit. In any of the above integrators, the positive-side feedback circuit may generate the positive feedback signal based on the signal output by the first amplification unit.

[0005] In any of the above integrators, the positive-side feedback circuit may have two input terminals to which the positive output signal is respectively input, and may have a second subtraction unit that outputs a difference between the positive output signals input to the two input terminals. In any of the above integrators, the positive-side feedback circuit may have a second amplification unit that amplifies a signal output by the second subtraction unit. In any of the above integrators, the positive-side feedback circuit may have a first delay unit that delays one of the positive output signal and the negative output signal input to the first subtraction unit with respect to the other, and inputs the delayed signal to the first subtraction unit. In any of the above integrators, the positive-side feedback circuit may have a second delay unit that delays one of the positive output signals input to the two input terminals of the second subtraction unit with respect to the other, and inputs the delayed signal to the second subtraction unit. In any of the above integrators, the positive-side feedback circuit may generate the positive feedback signal based on a signal output by the first amplification unit and a signal output by the second amplification unit.

[0006] In any of the integrators described above, the first amplifying section and the second amplifying section may have the same gain.

[0007] In any of the integrators described above, the first amplifying section and the second amplifying section may each have a gain of 0.5.

[0008] In any of the above integrators, the negative circuit may include a negative delay circuit that delays a signal generated in response to the negative input signal and a negative feedback signal to output the negative output signal. In any of the above integrators, the negative circuit may include a negative feedback circuit that amplifies a difference between the negative output signal and the positive output signal to generate the negative feedback signal.

[0009] In any of the above integrators, the negative feedback circuit may have a third subtraction unit that outputs a difference between the negative output signal and the positive output signal. In any of the above integrators, the negative feedback circuit may have a third amplification unit that amplifies the signal output by the third subtraction unit. In any of the above integrators, the negative feedback circuit may generate the negative feedback signal based on the signal output by the third amplification unit.

[0010] In any of the above integrators, the negative feedback circuit may have two input terminals to which the negative output signal is respectively input, and may have a fourth subtraction unit that outputs a difference between the negative output signals input to the two input terminals. In any of the above integrators, the negative feedback circuit may have a fourth amplification unit that amplifies a signal output by the fourth subtraction unit. In any of the above integrators, the negative feedback circuit may have a third delay unit that delays one of the negative output signal and the positive output signal input to the third subtraction unit with respect to the other and inputs the delayed signal to the third subtraction unit. In any of the above integrators, the negative feedback circuit may have a fourth delay unit that delays one of the negative output signals input to the two input terminals of the fourth subtraction unit with respect to the other and inputs the delayed signal to the fourth subtraction unit. In any of the above integrators, the negative feedback circuit may generate the negative feedback signal based on a signal output by the third amplification unit and a signal output by the fourth amplification unit.

[0011] In any of the above integrators, the positive side feedback circuit may have a fifth subtraction unit that outputs a difference between the positive output signal and the negative output signal. In any of the above integrators, the positive side feedback circuit may have a fifth amplification unit that amplifies a signal output by the fifth subtraction unit. In any of the above integrators, the positive side feedback circuit may have a fifth delay unit that delays one of the positive output signal and the negative output signal input to the fifth subtraction unit with respect to the other and inputs it to the fifth subtraction unit. In any of the above integrators, the positive side feedback circuit may have two input terminals to each of which the positive output signal is input, and may have a sixth subtraction unit that outputs a difference between the positive output signals input to the two input terminals. In any of the above integrators, the positive side feedback circuit may have a sixth amplification unit that amplifies a signal output by the sixth subtraction unit. In any of the above integrators, the positive-side feedback circuit may have a sixth delay section that delays one of the positive output signals input to the two input terminals of the sixth subtraction section with respect to the other, and inputs the delayed signal to the sixth subtraction section. In any of the above integrators, the delay amounts of the fifth delay section and the sixth delay section may be greater than the delay amounts of the first delay section and the second delay section. In any of the above integrators, the positive-side feedback circuit may generate the positive feedback signal based on signals output by the first amplification section, the second amplification section, the fifth amplification section, and the sixth amplification section.

[0012] In any of the above integrators, the negative feedback circuit may have a seventh subtraction unit that outputs a difference between the negative output signal and the positive output signal. In any of the above integrators, the negative feedback circuit may have a seventh amplification unit that amplifies a signal output by the seventh subtraction unit. In any of the above integrators, the negative feedback circuit may have a seventh delay unit that delays one of the negative output signal and the positive output signal input to the seventh subtraction unit with respect to the other and inputs it to the seventh subtraction unit. In any of the above integrators, the negative feedback circuit may have two input terminals to each of which the negative output signal is input, and an eighth subtraction unit that outputs a difference between the negative output signals input to the two input terminals. In any of the above integrators, the negative feedback circuit may have an eighth amplification unit that amplifies a signal output by the eighth subtraction unit. In any of the above integrators, the negative feedback circuit may have an eighth delay section that delays one of the negative output signals input to the two input terminals of the eighth subtraction section with respect to the other and inputs the delayed signal to the eighth subtraction section. In any of the above integrators, the delay amounts of the seventh delay section and the eighth delay section may be greater than the delay amounts of the third delay section and the fourth delay section. In any of the above integrators, the negative feedback circuit may generate the negative feedback signal based on signals output by the third amplification section, the fourth amplification section, the seventh amplification section, and the eighth amplification section.

[0013] In any of the above integrators, the positive feedback circuit may have a plurality of subtraction units that output a difference between the positive output signal and the negative output signal. In any of the above integrators, the positive feedback circuit may have a delay unit that is provided corresponding to each of the plurality of subtraction units and delays one of the positive output signal and the negative output signal input to the corresponding subtraction unit with respect to the other and inputs it to the subtraction unit. In any of the above integrators, the positive feedback circuit may have an amplifier unit that is provided corresponding to each of the plurality of subtraction units and amplifies a signal output by the corresponding subtraction unit. In any of the above integrators, the delay time of at least one of the delay units may be different from the delay time of at least one other of the delay units. In any of the above integrators, the gain of at least one of the amplifier units may be different from the gain of at least one other of the amplifier units. In any of the above integrators, the positive feedback circuit may generate the positive feedback signal based on the signal output by each of the amplifier units.

[0014] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of an integrator 300 according to a reference example. [Diagram 2] 1 is a diagram illustrating an example of the configuration of an integrator 100 according to an embodiment of the present invention. [Diagram 3] FIG. 4 is a diagram illustrating another exemplary configuration of the integrator 100. [Figure 4] FIG. 4 is a diagram illustrating another exemplary configuration of the integrator 100. [Diagram 5] 5 is a diagram illustrating a specific example of the circuit configuration of the integrator 100 illustrated in FIG. 4. [Figure 6] FIG. 4 is a diagram illustrating another exemplary configuration of the integrator 100. [Figure 7] FIG. 4 is a diagram illustrating another exemplary configuration of the integrator 100. [Figure 8] FIG. 4 is a diagram illustrating another exemplary configuration of the integrator 100. [Figure 9] FIG. 4 is a diagram illustrating another exemplary configuration of the integrator 100. [Figure 10] 10 is a diagram illustrating an example of the configuration of a negative-side circuit 130 in the integrator 100 shown in FIG. [Figure 11] 1 shows an example of the configuration of a delta-sigma modulator 200 using an integrator 100. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0017] FIG. 1 is a diagram showing an example of the configuration of an integrator 300 according to a reference example. The integrator 300 of this example is a fully differential circuit in which both the input and the output are differential. The integrator 300 receives a positive input signal A IN+ Positive output signal A obtained by integrating OUT+ and the negative input signal A IN- Negative output signal A obtained by integrating OUT- Positive input signal A IN+ and the negative input signal A IN- are mutually inverted signals. Positive input signal A IN+ and the negative input signal A IN- Input signal A IN Positive output signal A OUT+ and negative output signal A OUT- Combine these to produce output signal A OUT The differential input signal is called A IN+ -A IN- The differential output signal is A OUT+ -A OUT- In this way, a differential output signal can be obtained by amplifying a differential input signal.

[0018] In a fully differential circuit, the input signal A IN+ and A IN-Even if common-mode noise is superimposed on both the output signal A and the differential input signal B, the common-mode noise component is removed from the differential input signal and the differential output signal. OUT+ and A OUT- Both of the output signals A and B may increase due to the influence of manufacturing errors, etc. In this case, the increased components are integrated according to the number of integrations in the integrator 300. However, the increased components are removed from the differential output signal. OUT+ and A OUT- Therefore, the output signal A OUT+ and A OUT- The output common voltage at the output signal A gradually increases or decreases. When the output common voltage reaches the vicinity of the upper or lower limit of the operating voltage of the integrator 300, the integrator cannot continue the integral operation. The output common voltage is the voltage at the output signal A OUT+ and A OUT- For example, the output signal A OUT+ and A OUT- The output common voltage is the average voltage of the output signal A OUT 1 shows the offset with respect to the reference potential.

[0019] In contrast, the output signal A of the integrator 300 OUT+ and A OUT- A common mode feedback signal corresponding to the magnitude of the output signal A is generated and fed back to the input of the integrator 300. OUT+ and A OUT- 1 includes a positive side circuit 310, a negative side circuit 330, and a common mode feedback section 320. Integrator 300 of FIG.

[0020] The positive side circuit 310 receives a positive input signal A IN+ is input, and the positive input signal A IN+ Positive output signal A obtained by integrating OUT+ The positive side circuit 310 of this example includes an adder-subtracter unit 311, a delay unit 312, and an amplifier unit 313. The adder-subtracter unit 311 receives a positive input signal A IN+ The output signal of the amplifier 313 is added to this and the common mode feedback signal is subtracted.

[0021] The delay unit 312 delays the signal output by the addition / subtraction unit 311. The delay unit 312 may generate a delay of one cycle of a clock signal that defines the operation cycle of the integrator 300. The delay unit 312 delays the positive output signal A OUT+ Output.

[0022] The amplifier 313 outputs a positive output signal A OUT+ is amplified by a factor of coefficient x and output. In this example, coefficient x is a positive value. Coefficient x may be 1 or a value other than 1. The signal output by the amplifier 313 is amplified by the adder / subtracter 311 as a positive input signal A IN+ This adds to the positive input signal A IN+ The positive output signal A is obtained by integrating according to a given coefficient x. OUT+ Generate.

[0023] The negative side circuit 330 receives a negative input signal A IN- is input, and the negative input signal A IN- Negative output signal A obtained by integrating OUT- The negative side circuit 330 of this example includes an adder-subtracter 331, a delay unit 332, and an amplifier unit 333. The adder-subtracter 331 receives a negative input signal A IN- The output signal of the amplifier 333 is added to this and the common mode feedback signal is subtracted.

[0024] The delay unit 332 delays the signal output by the adder / subtractor unit 331. The delay unit 332 may generate the same delay as the delay unit 312. The delay unit 332 generates a negative output signal A OUT- Output.

[0025] The amplifier 333 outputs a negative output signal A OUT- The amplification unit 313 amplifies the signal by a factor of coefficient x and outputs the amplified signal. The coefficient x in the amplification unit 313 and the amplification unit 333 may be the same value. The signal output by the amplification unit 333 is amplified by the addition / subtraction unit 331 as a negative input signal A IN- This results in a negative input signal A IN- The negative output signal A is obtained by integrating OUT- Generate.

[0026] The common mode feedback section 320 outputs the output signal A OUT+ and A OUT- The common mode feedback unit of this example includes an adder unit 322 and an amplifier unit 321.

[0027] The adder 322 outputs the output signal A OUT+ and output signal A OUT- Output signal A is added to the signal. OUT+ and output signal A OUT- By adding these, a signal with a voltage twice as high as the output common voltage can be obtained. The amplifier 321 outputs a common mode feedback signal obtained by amplifying the signal output by the adder 322 by a factor of coefficient y. The coefficient y is equal to or greater than 0.5 times the coefficient x. The common mode feedback signal is input to the adder / subtracter 311 and the adder / subtracter 331. With this configuration, the output signal A OUT+ and A OUT- In addition, the common mode feedback signal is fed back to the input stages of the positive side circuit 310 and the negative side circuit 330 and subtracted, thereby generating an output signal A OUT+ and A OUT- The output common voltage can be maintained almost constant.

[0028] 2 is a diagram showing an example of the configuration of an integrator 100 according to an embodiment of the present invention. Like the integrator 300, the integrator 100 is a fully differential circuit integrator. The integrator 100 includes a positive side circuit 110 and a negative side circuit 130. Like the positive side circuit 310, the positive side circuit 110 receives a positive input signal A IN+ is input, and the positive input signal A IN+ Positive output signal A obtained by integrating OUT+ The negative side circuit 130, like the negative side circuit 330, outputs a negative input signal A IN- is input, and the negative input signal A IN- Negative output signal A obtained by integrating OUT-In the integrator 100, the positive side circuit 110 and the negative side circuit 130 have a function similar to that of the common mode feedback section 320 in addition to the functions of the positive side circuit 310 and the negative side circuit 330. In the integrator 100 of this example, the positive side circuit 110 and the negative side circuit 130 output the output signal A OUT By subtracting the signal according to the magnitude of OUT This suppresses fluctuations in the output common voltage.

[0029] The positive side circuit 110 includes an adder 111, a positive side delay circuit 112, and a positive side feedback circuit 170. The adder 111 receives a positive input signal A IN+ and a positive feedback signal FB + Positive sum signal A obtained by adding PRE+ Output.

[0030] The positive delay circuit 112 receives the positive sum signal A PRE+ is delayed to produce the positive output signal A OUT+ The positive side delay circuit 112 may generate a delay of one period of a clock signal that defines the operation period of the integrator 100.

[0031] The positive feedback circuit 170 outputs a positive output signal A OUT+ and negative output signal A OUT- Difference from (A OUT+ -A OUT- ) to generate a positive feedback signal FB + The positive side feedback circuit 170 of the present example includes a first subtraction unit 114 and a first amplification unit 113.

[0032] The first subtraction unit 114 subtracts the positive output signal A OUT+ and negative output signal A OUT- Difference from (A OUT+ -A OUT- The first amplifier 113 outputs the signal (A OUT+ -A OUT- ) is amplified by a factor of a1, where a1 is a positive value greater than 0.

[0033] The positive feedback circuit 170 generates a positive feedback signal FB + In this example, the signal output from the first amplifier 113 is a positive feedback signal FB + However, in another example, a positive feedback signal FB + may be generated.

[0034] The negative side circuit 130 includes an adder 131, a negative side delay circuit 132, and a negative side feedback circuit 180. The adder 131 receives a negative input signal A IN- and the negative feedback signal FB - Negative sum signal A obtained by adding PRE- Output.

[0035] The negative delay circuit 132 outputs the negative sum signal A PRE- is delayed to produce the negative output signal A OUT- The delay amount of the negative side delay circuit 132 may be the same as the delay amount of the positive side delay circuit 112.

[0036] The negative feedback circuit 180 outputs a negative output signal A OUT- and positive output signal A OUT+ Difference from (A OUT- -A OUT+ ) to generate a negative feedback signal FB ― The negative feedback circuit 180 of the present example includes a third subtraction unit 134 and a third amplification unit 133.

[0037] The third subtraction unit 134 outputs a negative output signal A OUT- and positive output signal A OUT+ Difference from (A OUT- -A OUT+ The third amplifier 133 outputs the signal (A OUT- -A OUT+ ) is amplified by a factor of coefficient a2. Coefficient a2 is a positive value greater than 0. Coefficient a2 may be the same value as coefficient a1.

[0038] The negative feedback circuit 180 generates a negative feedback signal FB - In this example, the signal output from the third amplifier 133 is a negative feedback signal FB - However, in another example, a negative feedback signal FB - may be generated.

[0039] In the example shown in FIG. 1, if x=1 and y=0.5, the signal fed back to the adder / subtractor 311 is 0.5×A OUT+ -0.5×A OUT- Similarly, the signal fed back to the adder / subtractor 331 is 0.5×A OUT- -0.5×A OUT+ However, A OUT+ and A OUT- is delayed by one period of the clock signal. In the example of FIG. 2, the signal fed back to the adder 111 is a1×(A OUT+ -A OUT- ), and the signal fed back to the adder 131 is a2×(A OUT- -A OUT+ ) Therefore, by setting a1 = a2 = 0.5, a signal similar to the example shown in FIG. 1 can be fed back to the adder 111 and the adder 131. For this reason, the integrator 100 in FIG. 2 does not include a common mode feedback section and can feed back the input signal A IN While integrating, the fluctuation of the output common voltage can be suppressed.

[0040] The output signal A of the integrator 100 shown in FIG. OUT+ , A OUT- is shown in Equation 1.

number

number

[0041] Positive input signal A of integrator 100 IN+ Assume that the output common voltage is 0V and the output common voltage is 0.1V. The first positive output signal A OUT+ [1] is shown in number 3 based on number 1.

number

[0042] As explained in Equation 2, integrator 100 has a feedback coefficient of (a1+a2). Since the feedback coefficient of integrator 300 is x, a1+a2 corresponds to x. In integrator 300, two x-times amplifiers (amplifier 313 and amplifier 333) are provided. In integrator 100, a function equivalent to that of integrator 300 can be realized using small-scale amplifiers (first amplifier 113 and third amplifier 133) with relatively small gain.

[0043] In the integrator 100, a first subtraction unit 114 and a third subtraction unit 134 are provided. The amplification unit in the integrator 100 can be configured with a switched capacitor having a capacitor and a plurality of switches, as shown in FIG. 5 and the like. The switched capacitor can also function as a subtraction unit. Therefore, even if the functions of the first subtraction unit 114 and the third subtraction unit 134 are added to the integrator 100, the circuit area does not increase. According to the integrator 100, it is possible to suppress an increase in the output common voltage in the same way as the integrator 300 while realizing a feedback coefficient equivalent to that of the integrator 300 with a circuit area smaller than that of the integrator 300.

[0044] The coefficients a1 and a2 may both be 0.5. In this case, the integrator 100 can operate as a first-order or second-order integrator. The coefficients a1 and a2 may be greater than 0.5. The coefficients a1 and a2 may be 1 or 2.

[0045] 3 is a diagram showing another example of the configuration of the integrator 100. The positive side circuit 110 of this example has an adder 117, a second subtracter 116, and a second amplifier 115 in addition to the configuration of the positive side circuit 110 shown in FIG. 2. The negative side circuit 130 of this example has an adder 137, a fourth subtracter 136, and a fourth amplifier 135 in addition to the configuration of the negative side circuit 130 shown in FIG. 2. Also, the feedback coefficient of the first amplifier 113 is a2, and the feedback coefficient of the third amplifier 133 is a1. The other configurations are the same as those of the example of FIG. 2.

[0046] The second subtraction unit 116 respectively outputs a positive output signal A OUT+ The second subtraction unit 116 has two input terminals (+, -) to which the positive output signal A OUT+ The difference between (A OUT+ -A OUT+ ) to output.

[0047] The second amplifier 115 amplifies the signal output by the second subtractor 116. In this example, the feedback coefficient of the second amplifier 115 is a1. As described above, the coefficient a1 and the coefficient a2 may be the same value.

[0048] The adder 117 adds the output signal of the first amplifier 113 and the output signal of the second amplifier 115 to generate a positive feedback signal FB + Generates a positive feedback signal FB + is input to the adder 111.

[0049] The fourth subtraction unit 136 outputs a negative output signal A OUT- The fourth subtraction unit 136 has two input terminals (+, -) to which the negative output signal A OUT- The difference between (A OUT- -A OUT- ) to output.

[0050] The fourth amplifier 135 amplifies the signal output by the fourth subtractor 136. The feedback coefficient of the fourth amplifier 135 in this example is a2.

[0051] The adder 137 adds the output signal of the third amplifier 133 and the output signal of the fourth amplifier 135 to generate a negative feedback signal FB - Generates a negative feedback signal FB - is input to the adder 131.

[0052] The output signal A of the integrator 100 shown in FIG. OUT is shown in Equation 4.

number

number

[0053] Positive input signal A of integrator 100 IN+ Assume that the output common voltage is 0V and the output common voltage is 0.1V. The first positive output signal A OUT+ [1] is expressed by Equation 6 based on Equation 4. Negative output signal AOUT- The same applies to.

number

[0054] 4 is a diagram showing another example of the configuration of the integrator 100. In addition to the configuration of the integrator 100 shown in FIG. 3, the integrator 100 of this example has a first delay unit 118, a second delay unit 119, a third delay unit 138, and a fourth delay unit 139. Furthermore, each of the positive side delay circuit 112 and the negative side delay circuit 132 of this example generates a delay equivalent to a half cycle of the clock signal. Furthermore, the adder 111 adds a positive input signal A IN+ For positive feedback signal FB + and positive output signal A OUT+ The adder 131 adds the negative input signal A IN- For the negative feedback signal FB - and negative output signal A OUT- The other structures are the same as in the example of FIG.

[0055] The first delay unit 118 delays the positive output signal A OUT+ and negative output signal A OUT- One of the signals is delayed from the other and input to the first subtraction unit 114. The first delay unit 118 in this example delays the positive output signal OUT+ The delay amount of the first delay unit 118 may be the same as the delay amount of the positive side delay circuit 112.

[0056] The second delay unit 119 receives the positive output signal A OUT+ The second delay unit 119 of this example delays the positive output signal A OUT+The delay amount of the second delay unit 119 may be the same as the delay amount of the positive side delay circuit 112.

[0057] The third delay unit 138 delays the negative output signal A OUT- and positive output signal A OUT+ One of the signals is delayed from the other and input to the third subtraction unit 134. The third delay unit 138 in this example outputs a negative output signal OUT- The delay amount of the third delay unit 138 may be the same as the delay amount of the negative delay circuit 132.

[0058] The fourth delay unit 139 receives the negative output signal A OUT- The fourth delay unit 139 of this example delays the negative output signal A OUT- The delay amount of the fourth delay unit 139 may be the same as the delay amount of the negative side delay circuit 132.

[0059] The output signal A of the integrator 100 shown in FIG. OUT is shown in equation 7.

number

number

[0060] Positive input signal A of integrator 100 IN+ Assume that the output common voltage is 0V and the output common voltage is 0.1V. The first positive output signal A OUT+ [1] and the second positive output signal A OUT+ [2] is expressed by Equation 9 based on Equation 7. Negative output signal A OUT- The same applies to.

number

[0061] Fig. 5 is a diagram showing a specific example of the circuit configuration of the integrator 100 shown in Fig. 4. The integrator 100 of this example has a switched capacitor 70-1, a switched capacitor 70-2, a switched capacitor 10-1, a switched capacitor 10-2, a switched capacitor 10-3, a switched capacitor 10-4, a capacitor circuit 60-1, a capacitor circuit 60-2, and an amplifier circuit 62.

[0062] The switched capacitor 70-1, the capacitor circuit 60-1, and the amplifier circuit 62 function as the adder unit 111, the adder unit 117, and the positive side delay circuit 112 in Fig. 4. The switched capacitor 70-2, the capacitor circuit 60-2, and the amplifier circuit 62 function as the adder unit 131, the adder unit 137, and the negative side delay circuit 132 in Fig. 4. The amplifier circuit 62 is a fully differential amplifier in which both the input and the output are differential.

[0063] The switched capacitor 10-1 functions as a first amplification section 113, a first subtraction section 114, and a first delay section 118. The switched capacitor 10-2 functions as a second amplification section 115, a second subtraction section 116, and a second delay section 119. The switched capacitor 10-3 functions as a third amplification section 133, a third subtraction section 134, and a third delay section 138. The switched capacitor 10-4 functions as a fourth amplification section 135, a fourth subtraction section 136, and a fourth delay section 139.

[0064] The switched capacitor 70-1 has a capacitor 75, a switch 71, a switch 72, a switch 73, and a switch 74. The on and off states of each switch are controlled by a signal φk (k indicates 1 or 2). In the drawings attached to this specification, a plurality of switches having the same signal φk in parentheses following the reference numerals have the same on and off states. In this example, when the signal φk indicates an H level, the corresponding switch is in an on state, and when the signal φk indicates an L level, the corresponding switch is in an off state.

[0065] A switch 71 and a switch 72 are connected to one electrode of the capacitor 75. The switch 71 applies a positive input signal A IN+ The switch 72 switches whether or not the corresponding electrode of the capacitor 75 is connected to a reference potential. The other electrode of the capacitor 75 is connected to switches 73 and 74. The switch 73 switches whether or not the corresponding electrode of the capacitor 75 is connected to the capacitor circuit 60-1. The switch 74 switches whether or not the corresponding electrode of the capacitor 75 is connected to a reference potential. The reference potential is, for example, 0V.

[0066] The switches 71 and 74 are controlled by a signal φ1. The switches 72 and 73 are controlled by a signal φ2. When the signal φ1 indicates an on state and the signal φ2 indicates an off state, the capacitor 75 is connected to the input signal A. INWhen the signal φ1 indicates an off state and the signal φ2 indicates an on state, the voltage of the capacitor 75 is applied to the capacitor circuit 60-1. The signals φ1 and φ2 are signals out of phase with each other by a half period. For example, the signal φ1 is a clock signal, and the signal φ2 is an inverted clock signal.

[0067] The switched capacitor 70-2 has a similar configuration to the switched capacitor 70-1. However, the switch 71 of the switched capacitor 70-2 receives a negative input signal A IN- is applied and switch 73 is connected to capacitor circuit 60-2.

[0068] The capacitor circuit 60-1 has a feedback capacitor 64 and a switch 66. A capacitor 75 and a switch 74 are connected to the negative input terminal of the amplifier circuit 62 via a switch 73. In addition, a switched capacitor 10-1 and a switched capacitor 10-2 are each connected in parallel to the switch 73 to the negative input terminal of the amplifier circuit 62.

[0069] A feedback capacitor 64 and a switch 66 are connected in parallel between the positive output terminal and the negative input terminal of the amplifier circuit 62. The feedback capacitor 64 stores a signal input to the negative input terminal of the amplifier circuit 62. The feedback capacitor 64 is connected in parallel to the positive input signal A. IN+ and the positive feedback signal FB + The feedback capacitor 64 is connected to the positive input signal A IN+ A positive feedback signal FB + The signal sigma 114 functions as an adder 111 that adds the signal sigma 114.

[0070] The voltage of the feedback capacitor 64 of the capacitor circuit 60-1 is OUT+ The switch 66 switches between connecting and not connecting the two electrodes of the feedback capacitor 64. By connecting the two electrodes of the feedback capacitor 64, the charge stored in the feedback capacitor 64 is discharged, and a positive output signal A OUT+ The voltage is reset to a reference potential (e.g., 0V).

[0071] The capacitor circuit 60-2 has a similar structure to the capacitor circuit 60-1. However, the capacitor circuit 60-2 is connected to the positive input terminal and the negative output terminal of the amplifier circuit 62. The positive input terminal of the amplifier circuit 62 is connected to a switched capacitor 70-2, a switched capacitor 10-3, and a switched capacitor 10-4. The voltage of the feedback capacitor 64 of the capacitor circuit 60-2 is connected to the negative output signal A. OUT― The voltage is

[0072] The switched capacitor 10-1 includes a capacitor 15, a switch 11, a switch 12, a switch 13, and a switch 14. The capacitor 15 is connected to a positive output signal A OUT+ and negative output signal A OUT- The switches 11, 12, 13 and 14 store electric charges according to the output signal A OUT Depending on the input, the capacitor 15 is either charged or connected to the feedback capacitor 64.

[0073] A switch 11 and a switch 12 are connected to one electrode of the capacitor 15. The switch 11 switches whether or not the corresponding electrode of the capacitor 15 is connected to the feedback capacitor 64. The switch 12 switches whether or not the corresponding electrode of the capacitor 15 is connected to a reference potential. A switch 13 and a switch 14 are connected to the other electrode of the capacitor 15. The switch 13 supplies a positive output signal A OUT+ The switch 14 switches whether or not the negative output signal A is applied to the corresponding electrode of the capacitor 15. OUT- Switch whether or not to apply.

[0074] The switches 11 and 14 are controlled by a signal φ2. The switches 12 and 13 are controlled by a signal φ1. The switches 13 and 14 are alternately switched on and off to transmit a positive output signal A to the capacitor 15. OUT+ and negative output signal A OUT-A charge corresponding to the difference in voltage between the positive and negative terminals is accumulated.

[0075] The switched capacitor 10-2 has a structure similar to that of the switched capacitor 10-1. However, the switch 14 of the switched capacitor 10-2 is connected to a positive output signal A OUT+ The other structure is the same as that of the switched capacitor 10-1.

[0076] The switched capacitor 10-3 has a structure similar to that of the switched capacitor 10-1. However, the switch 13 of the switched capacitor 10-3 is connected to a negative output signal A OUT- is applied to the switch 14, and a positive output signal A OUT+ is applied to the switch 11. The switch 11 is also connected to a feedback capacitor 64 of the capacitor circuit 60-2. The other structures are similar to those of the switched capacitor 10-1.

[0077] The switched capacitor 10-4 has a structure similar to that of the switched capacitor 10-1. However, the switch 13 of the switched capacitor 10-4 is connected to a negative output signal A OUT- is applied to the switch 11. The switch 11 is also connected to a feedback capacitor 64 of the capacitor circuit 60-2. The other structures are similar to those of the switched capacitor 10-1.

[0078] The capacitance of the capacitor 15 of each switched capacitor 10 may be the same or different. In this example, the capacitance of each capacitor 15 can adjust the corresponding feedback coefficients a1 and a2.

[0079] 6 is a diagram showing another example of the configuration of the integrator 100. In the integrator 100 of this example, the potential applied to each switch 12 is different from the reference potential. The other structure is similar to the example of FIG.

[0080] In this example, the switch 12 of the switched capacitor 10-1 receives a negative output signal A OUT-A negative output signal A is applied to the switch 12 of the switched capacitor 10-2. OUT- A positive output signal A is applied to the switch 12 of the switched capacitor 10-3. OUT+ A positive output signal A is applied to the switch 12 of the switched capacitor 10-4. OUT+ is applied.

[0081] In this example, when the signal φ1 is turned on, each capacitor 15 is connected to a positive output signal A OUT+ and negative output signal A OUT- Therefore, the voltage applied to each capacitor 15 can be doubled compared to the example of Fig. 5. Compared to the example of Fig. 5, the capacitance of the capacitor 15 in this example can be halved.

[0082] FIG. 7 is a diagram showing another example of the configuration of the integrator 100. The integrator 100 may have an order of 2 or more. The integrator 100 in FIG. 7 is an integrator with an order of 2. The positive-side feedback circuit 170 of this example further includes a fifth subtraction unit 124, a fifth amplification unit 123, a fifth delay unit 128, a sixth subtraction unit 126, a sixth amplification unit 125, and a sixth delay unit 129 in addition to the configuration of the positive-side feedback circuit 170 shown in FIG. 5. The positive-side circuit 110 of this example further includes an adder unit 127 in addition to the configuration of the positive-side circuit 110 shown in FIG. 5.

[0083] 5, negative side feedback circuit 180 of the present example further includes a seventh subtraction unit 144, a seventh amplification unit 143, a seventh delay unit 148, an eighth subtraction unit 146, an eighth amplification unit 145, and an eighth delay unit 149. Moreover, negative side circuit 130 of the present example further includes an addition unit 147 in addition to the configuration of negative side circuit 130 shown in FIG.

[0084] The fifth subtraction unit 124 subtracts the positive output signal A OUT+ and negative output signal A OUT- The fifth delay unit 128 outputs the difference between the positive output signal A OUT+ and negative output signal A OUT-The fifth delay unit 128 of this example delays one of the positive output signals A with respect to the other and inputs it to the fifth subtraction unit 124. OUT+ The fifth delay unit 128 delays the signal output from the fifth subtraction unit 124. The delay amount of the fifth delay unit 128 may be larger than the delay amount of the first delay unit 118. The delay amount of the fifth delay unit 128 in this example is 1.5 cycles of the clock signal. The fifth amplification unit 123 amplifies the signal output from the fifth subtraction unit 124 by a factor of a4. The coefficient a4 is a value smaller than 0. The absolute value of the coefficient a4 may be the same as either the coefficient a1 or the coefficient a2, or may be different from either of them. The coefficients a1 and a2 in this example have opposite signs to the coefficients a3 and a4. For example, when the coefficients a1 and a2 are positive values, the coefficients a3 and a4 are negative values.

[0085] The sixth subtraction unit 126 respectively outputs the positive output signal A OUT+ The sixth subtraction unit 126 has two input terminals to which the positive output signal A OUT+ The sixth delay unit 129 outputs the difference between the positive output signal A OUT+ The sixth delay unit 129 of this example delays the positive output signal A OUT+ The delay amount of the sixth delay unit 129 is the same as the delay amount of the fifth delay unit 128. The sixth amplification unit 125 amplifies the signal output by the sixth subtraction unit 126 by a factor of coefficient a3. The coefficient a3 is a value smaller than 0. The coefficient a3 may be the same as the coefficient a4.

[0086] The adder 127 adds the output signal of the fifth amplifier 123 and the output signal of the sixth amplifier 125. The positive-side feedback circuit 170 outputs a positive feedback signal FB + In this example, the signal output by the adder 127 is a positive feedback signal FB + is input to the adder 111 as a part of

[0087] The seventh subtraction unit 144 outputs a negative output signal A OUT- and positive output signal A OUT+ The seventh delay unit 148 outputs the difference between the negative output signal A OUT- and positive output signal A OUT+ The seventh delay unit 148 of this example delays one of the negative output signals A OUT- The seventh delay unit 148 delays the signal output from the seventh subtraction unit 144. The delay amount of the seventh delay unit 148 may be larger than the delay amount of the third delay unit 138. In this example, the delay amount of the seventh delay unit 148 is 1.5 cycles of the clock signal. The seventh amplification unit 143 amplifies the signal output from the seventh subtraction unit 144 by a factor of coefficient a3. The coefficient a3 is a value smaller than 0. The absolute value of the coefficient a3 may be the same as either the coefficient a1 or the coefficient a2, or may be different from either of them.

[0088] The eighth subtraction unit 146 outputs a negative output signal A OUT- The eighth subtraction unit 146 has two input terminals to which the negative output signal A OUT- The eighth delay unit 149 outputs the difference between the negative output signal A OUT- The eighth delay unit 149 of this example delays the negative output signal A OUT- The delay amount of the eighth delay unit 149 is the same as the delay amount of the seventh delay unit 148. The eighth amplification unit 145 amplifies the signal output by the eighth subtraction unit 146 by a factor of a4. The coefficient a4 is a value smaller than 0.

[0089] The adder 147 adds the output signal of the seventh amplifier 143 and the output signal of the eighth amplifier 145. The negative feedback circuit 180 outputs a negative feedback signal FB - In this example, the adder 147 outputs a negative feedback signal FB - is input to the adder 131 as a part of

[0090] The output signal A of the integrator 100 shown in FIG. OUT is shown in number 10.

number

number

number

[0091] Positive input signal A of integrator 100 IN+ Assume that the output common voltage is 0V and the output common voltage is 0.1V. The first positive output signal A OUT+ [1] is shown in equation 13. Negative output signal A OUT- The same applies to.

number

[0092] Fig. 8 is a diagram showing another example of the configuration of the integrator 100. In the integrator 100 of this example, the signals input to the fifth subtraction unit 124, the sixth subtraction unit 126, the seventh subtraction unit 144, and the eighth subtraction unit 146 are different from those of the example of Fig. 7. In addition, the signs of the coefficients a1, a2, a3, and a4 are the same. In this example, the coefficients a3 and a4 are positive values ​​greater than 0. The other structures are the same as those of the example of Fig. 7.

[0093] In this example, the positive input terminal of the fifth subtraction unit 124 receives the negative output signal A via the fifth delay unit 128. OUT- The negative input terminal of the fifth subtraction unit 124 receives a negative output signal A OUT- is entered.

[0094] In this example, the positive input terminal of the sixth subtraction unit 126 receives the negative output signal A via the sixth delay unit 129. OUT- The sixth subtraction unit 126 receives a positive output signal A OUT+ is entered.

[0095] In this example, the seventh subtraction unit 144 has a positive input terminal to which a positive output signal A is input via a seventh delay unit 148. OUT+ The seventh subtraction unit 144 receives a positive output signal A OUT+ is entered.

[0096] The positive input terminal of the eighth subtraction unit 146 in this example receives the positive output signal A via the eighth delay unit 149. OUT+ The negative input terminal of the eighth subtraction unit 146 receives a negative output signal A OUT- is entered.

[0097] The output signal A of the integrator 100 shown in FIG. OUT is shown in Equation 14.

number

number

number

[0098] In the integrator 100 of this example, the coefficients a3 and a4 are positive values. IN+ Assume that the output common voltage is 0V and the output common voltage is 0.1V. The first positive output signal A OUT+ [1] is shown in equation 17. Negative output signal A OUT- The same applies to.

number

[0099] Fig. 9 is a diagram showing another example of the configuration of the integrator 100. Fig. 9 mainly shows the positive side circuit 110 of the integrator 100. The integrator 100 of this example is a high-order integrator of third order or higher. Although the integrator 100 of Fig. 9 is a third-order integrator, the integrator 100 may be a fourth-order or higher integrator.

[0100] 8, positive side feedback circuit 170 of this example further includes a ninth subtraction unit 154, a ninth delay unit 158, a ninth amplification unit 153, a tenth subtraction unit 156, a tenth delay unit 159, and a tenth amplification unit 155. Also, positive side circuit 110 further includes an adder unit 157 in addition to the configuration of positive side circuit 110 of FIG.

[0101] The ninth subtraction unit 154 subtracts the positive output signal A OUT+ and negative output signal A OUT- The ninth delay unit 158 ​​outputs the difference between the positive output signal A OUT+ and negative output signal A OUT- One of the positive output signal A is delayed from the other and input to the ninth subtraction unit 154. OUT+The delay amount of the ninth delay unit 158 ​​may be larger than the delay amount of the fifth delay unit 128. In this example, the delay amount of the ninth delay unit 158 ​​is 2.5 cycles of the clock signal. The ninth amplification unit 153 amplifies the signal output by the ninth subtraction unit 154 by a factor of coefficient a6. The coefficient a6 is a value greater than 0. The coefficient a6 may be the same as any of the coefficients a1 to a4, or may be different from any of them.

[0102] The tenth subtraction unit 156 respectively receives the positive output signal A OUT+ The tenth subtraction unit 156 has two input terminals to which the positive output signal A OUT+ The tenth delay unit 159 outputs the difference between the positive output signal A OUT+ The tenth delay unit 159 of this example delays the positive output signal A OUT+ The delay amount of the tenth delay unit 159 is the same as the delay amount of the ninth delay unit 158. The tenth amplification unit 155 amplifies the signal output by the tenth subtraction unit 156 by a factor of coefficient a5. Coefficient a5 is a value greater than 0. Coefficient a5 may be the same as coefficient a6.

[0103] The adder 157 adds the output signal of the ninth amplifier 153 and the output signal of the tenth amplifier 155. The positive-side feedback circuit 170 generates a positive feedback signal FB + In this example, the signal output by the adder 157 is a positive feedback signal FB + is input to the adder 111 as a part of

[0104] 9, the positive side circuit 110 in the third or higher order integrator 100 has a plurality of subtraction units, a plurality of delay units, and a plurality of amplification units. The positive side circuit 110 may have three or more subtraction units, or may have four or more subtraction units, excluding a subtraction unit (e.g., second subtraction unit 116) to which the same output signal is input. A delay unit and an amplification unit are provided for each subtraction unit.

[0105] Each subtraction unit (for example, the first subtraction unit 114, the sixth subtraction unit 126, and the ninth subtraction unit 154) outputs a positive output signal A OUT+ and negative output signal A OUT- A plurality of delay units (for example, the first delay unit 118, the sixth delay unit 129, and the ninth delay unit 158) are provided corresponding to the plurality of subtraction units. Each delay unit outputs a difference between the positive output signal A OUT+ and negative output signal A OUT- One of the signals is delayed with respect to the other and input to the subtraction unit. A plurality of amplification units (for example, a first amplification unit 113, a sixth amplification unit 125, and a ninth amplification unit 153) are provided corresponding to the plurality of subtraction units, respectively, and amplify the signal output by the corresponding subtraction unit by a magnification factor of a predetermined coefficient.

[0106] The delay time of at least one delay section is different from the delay time of at least one other delay section. In this example, the delay times of the first delay section 118, the sixth delay section 129, and the ninth delay section 158 are different from each other.

[0107] The gain (coefficient) of at least one amplifier unit is different from the gain of at least one other amplifier unit. In this example, the gain a2 of the first amplifier unit 113, the gain a4 of the fifth amplifier unit 123, and the gain a6 of the ninth amplifier unit 153 are different from each other. As an example, the gain a2 is 1, the gain a4 is 1.5, and the gain a6 is 0.5, but is not limited to this. When the integrator 100 is of the fourth order or higher, the positive side circuit 110 has more subtraction units, delay units, and amplification units.

[0108] Fig. 10 is a diagram showing a configuration example of the negative side circuit 130 in the integrator 100 shown in Fig. 9. The negative side feedback circuit 180 of this example further includes an eleventh subtraction unit 164, an eleventh delay unit 168, an eleventh amplification unit 163, a twelfth subtraction unit 166, a twelfth delay unit 169, and a twelfth amplification unit 165 in addition to the configuration of the negative side circuit 130 in Fig. 8. Moreover, the negative side circuit 130 further includes an adder unit 167 in addition to the configuration of the negative side circuit 130 in Fig. 8.

[0109] The eleventh subtraction unit 164 subtracts the positive output signal A OUT+ and negative output signal A OUT- The eleventh delay unit 168 outputs the difference between the positive output signal A OUT+ and negative output signal A OUT- One of the negative output signals A is delayed from the other and input to the eleventh subtraction unit 164. OUT- The delay amount of the eleventh delay unit 168 may be larger than the delay amount of the seventh delay unit 148. The delay amount of the eleventh delay unit 168 in this example is 2.5 cycles of the clock signal. The eleventh amplification unit 163 amplifies the signal output by the eleventh subtraction unit 164 by a factor of a5.

[0110] The twelfth subtraction unit 166 respectively outputs a negative output signal A OUT- The twelfth subtraction unit 166 has two input terminals to which the negative output signal A OUT- The twelfth delay unit 169 outputs the difference between the negative output signal A OUT- The twelfth delay unit 169 of this example delays the negative output signal A OUT- The amount of delay of the twelfth delay unit 169 is the same as the amount of delay of the eleventh delay unit 168. The twelfth amplifier unit 165 amplifies the signal output by the twelfth subtractor unit 166 by a factor of a6.

[0111] The adder 167 adds the output signal of the eleventh amplifier 163 and the output signal of the twelfth amplifier 165. The negative feedback circuit 180 generates a negative feedback signal FB - In this example, the adder 167 outputs a negative feedback signal FB - is input to the adder 131 as a part of

[0112] 10, the negative side circuit 130 in the third or higher order integrator 100 has a plurality of subtraction units, a plurality of delay units, and a plurality of amplification units. The negative side circuit 130 may have three or more subtraction units, or may have four or more subtraction units, except for a subtraction unit (e.g., the fourth subtraction unit 136) to which the same output signal is input. A delay unit and an amplification unit are provided for each subtraction unit.

[0113] Each subtraction unit (for example, the third subtraction unit 134, the eighth subtraction unit 146, and the eleventh subtraction unit 164) receives the positive output signal A OUT+ and negative output signal A OUT- A plurality of delay units (for example, the third delay unit 138, the eighth delay unit 149, and the eleventh delay unit 168) are provided corresponding to the plurality of subtraction units. Each delay unit outputs a difference between the positive output signal A OUT+ and negative output signal A OUT- One of the signals is delayed with respect to the other and input to the subtraction unit. A plurality of amplification units (e.g., the third amplification unit 133, the eighth amplification unit 145, and the eleventh amplification unit 163) are provided corresponding to the plurality of subtraction units, respectively, and amplify the signal output by the corresponding subtraction unit by a magnification factor of a predetermined coefficient.

[0114] The delay time of at least one delay section is different from the delay time of at least one other delay section. In this example, the delay times of the third delay section 138, the eighth delay section 149, and the eleventh delay section 168 are different from each other.

[0115] The gain (coefficient) of at least one amplifier unit is different from the gain of at least one other amplifier unit. In this example, the gain a1 of the third amplifier unit 133, the gain a4 of the eighth amplifier unit 145, and the gain a6 of the eleventh amplifier unit 163 are different from each other. As an example, the gain a1 is 1, the gain a4 is 1.5, and the gain a6 is 0.5, but is not limited to this. When the integrator 100 is fourth order or higher, the negative side circuit 130 has more subtraction units, delay units, and amplification units.

[0116] 11 shows an example of the configuration of a delta-sigma modulator 200 using the integrator 100. The delta-sigma modulator 200 is an example of a circuit using the integrator 100, and the circuit in which the integrator 100 is provided is not limited to the delta-sigma modulator 200.

[0117] The delta-sigma modulator 200 receives an analog signal A SIG to the digital signal D OUT As an example, the delta-sigma modulator 200 is an incremental AD converter that resets the integrated value of the integrator 100 to an initial value for each AD conversion cycle. The delta-sigma modulator 200 alternates between an AD conversion period and a reset period.

[0118] 1 includes a subtraction unit 210, an integrator 100, an analog-to-digital converter (referred to as an AD conversion unit 220), and a digital-to-analog converter (referred to as a DA conversion unit 230). The delta-sigma modulator 200 may further include a control unit 214 and a reset circuit 216. The subtraction unit 210 receives an analog signal A SIG From feedback signal A FB Input signal A is subtracted IN In this example, the feedback signal A FB and input signal A IN is an analog signal.

[0119] The integrator 100 receives an input signal A IN The output signal A is the integrated OUTThe integrator 100 is an integrator according to any one of the aspects described in FIG. 1 to FIG. 10. The control unit 214 controls the integrator 100. For example, the control unit 214 controls each switch described in each figure. The reset circuit 216 resets the output signal A output by the integrator 100 every time an AD conversion period ends. OUT The reset circuit 216 resets the value of the output signal A to its initial value by turning on the switch 66 described with reference to FIG. OUT You may reset the value of to its initial value.

[0120] The AD conversion unit 220 outputs the output signal A OUT to the digital signal D OUT The AD conversion unit 220 converts the output signal A OUT The AD conversion section 220 may quantize the binary digital signal D OUT For example, the AD conversion section 220 may output an output signal A OUT A 1-bit quantizer outputs one pulse when the value of analog signal A is equal to or greater than a preset value, and does not output a pulse when the value is less than the preset value. SIG The magnitude of the digital signal D is converted into the density of the pulses during the AD conversion. OUT may be output.

[0121] The DA conversion unit 230 converts the digital signal D output by the AD conversion unit 220 into OUT Feedback signal A according to FB Generates a feedback signal A FB For example, a digital signal D OUT When the AD conversion unit 220 is a 1-bit quantizer, the DA conversion unit 230 generates a feedback signal A of a preset magnitude every time the AD conversion unit 220 outputs a pulse. FB may be generated.

[0122] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0123] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0124] 10···switched capacitor, 11, 12, 13, 14···switch, 15···capacitor, 60···capacitor circuit, 62···amplifier circuit, 64···feedback capacitor, 66···switch, 70···switched capacitor, 71, 72, 73, 74···switch, 75···capacitor, 100···integrator, 110···positive side circuit, 111···adder section, 112···positive side delay circuit, 113···first amplifier section, 114···first subtracter section, 115···second amplifier section, 116···second subtracter section, 117···adder section , 118...first delay unit, 119...second delay unit, 123...fifth amplifier unit, 124...fifth subtraction unit, 125...sixth amplifier unit, 126...sixth subtraction unit, 127...adder unit, 128...fifth delay unit, 129...sixth delay unit, 130...negative side circuit, 131...adder unit, 132...negative side delay circuit, 133...third amplifier unit, 134...third subtraction unit, 135...fourth amplifier unit, 136...fourth subtraction unit, 137...adder unit, 138...third delay unit, 139...fourth delay unit, 143...seventh amplifier unit, 144... 7th subtraction unit, 145...8th amplifier unit, 146...8th subtraction unit, 147...addition unit, 148...7th delay unit, 149...8th delay unit, 153...9th amplifier unit, 154...9th subtraction unit, 155...10th amplifier unit, 156...10th subtraction unit, 157...addition unit, 158...9th delay unit, 159...10th delay unit, 163...11th amplifier unit, 164...11th subtraction unit, 165...12th amplifier unit, 166...12th subtraction unit, 167...addition unit, 168...11th delay unit, 169...12th delay unit, 17 0 positive feedback circuit, 180 negative feedback circuit, 200 delta sigma modulator, 210 subtractor, 214 control section, 216 reset circuit, 220 AD converter, 230 DA converter, 300 integrator, 310 positive circuit, 311 adder / subtractor, 312 delay section, 313 amplifier, 320 common mode feedback section, 321 amplifier, 322 adder, 330 negative circuit, 331 adder / subtractor, 332 delay section, 333 amplifier

Claims

1. a positive side circuit that receives a positive input signal and outputs a positive output signal; a negative side circuit that receives a negative input signal and outputs a negative output signal; Equipped with The positive side circuit is a positive side delay circuit that delays a signal generated in response to the positive input signal and a positive feedback signal to output the positive output signal; a positive-side feedback circuit that amplifies a difference between the positive output signal and the negative output signal to generate the positive feedback signal; An integrator having

2. The positive feedback circuit includes: a first subtraction unit that outputs a difference between the positive output signal and the negative output signal; a first amplifier that amplifies the signal output by the first subtractor; having The positive feedback signal is generated based on the signal output from the first amplifier.

2. The integrator of claim 1.

3. The positive feedback circuit includes: a second subtraction unit having two input terminals to which the positive output signals are respectively input, and outputting a difference between the positive output signals input to the two input terminals; a second amplifier that amplifies the signal output by the second subtractor; a first delay unit that delays one of the positive output signal and the negative output signal input to the first subtraction unit with respect to the other, and inputs the delayed signal to the first subtraction unit; a second delay unit that delays one of the positive output signals input to the two input terminals of the second subtraction unit with respect to the other, and inputs the delayed one to the second subtraction unit; having The positive feedback signal is generated based on the signal output from the first amplifier and the signal output from the second amplifier.

3. The integrator of claim 2.

4. The first amplifier and the second amplifier have equal gains.

4. The integrator of claim 3.

5. The gain of the first amplifier unit and the second amplifier unit is both 0.

5.

5. The integrator of claim 4.

6. The negative side circuit includes: a negative side delay circuit that delays a signal generated in response to the negative input signal and a negative feedback signal to output the negative output signal; a negative feedback circuit that amplifies a difference between the negative output signal and the positive output signal to generate the negative feedback signal; 6. An integrator according to claim 1, comprising:

7. The negative feedback circuit includes: a third subtraction unit that outputs a difference between the negative output signal and the positive output signal; a third amplifier that amplifies the signal output by the third subtractor; having The negative feedback signal is generated based on the signal output from the third amplifier.

7. The integrator of claim 6.

8. The negative feedback circuit includes: a fourth subtraction unit having two input terminals to which the negative output signals are respectively input, and outputting a difference between the negative output signals input to the two input terminals; a fourth amplifier that amplifies the signal output by the fourth subtractor; a third delay unit that delays one of the negative output signal and the positive output signal input to the third subtraction unit with respect to the other, and inputs the delayed signal to the third subtraction unit; a fourth delay unit that delays one of the negative output signals input to the two input terminals of the fourth subtraction unit with respect to the other, and inputs the delayed one to the fourth subtraction unit; having The negative feedback signal is generated based on the signal output from the third amplifier and the signal output from the fourth amplifier.

8. The integrator of claim 7.

9. The positive feedback circuit includes: a fifth subtraction unit that outputs a difference between the positive output signal and the negative output signal; a fifth amplifier that amplifies the signal output by the fifth subtractor; a fifth delay unit that delays one of the positive output signal and the negative output signal input to the fifth subtraction unit with respect to the other, and inputs the delayed signal to the fifth subtraction unit; a sixth subtraction unit having two input terminals to which the positive output signals are respectively input, and outputting a difference between the positive output signals input to the two input terminals; a sixth amplifier that amplifies the signal output by the sixth subtractor; a sixth delay unit that delays one of the positive output signals input to the two input terminals of the sixth subtraction unit with respect to the other, and inputs the delayed one to the sixth subtraction unit; having a delay amount of the fifth delay section and a delay amount of the sixth delay section are greater than a delay amount of the first delay section and a delay amount of the second delay section, The positive feedback signal is generated based on the signals output from the first amplifier, the second amplifier, the fifth amplifier, and the sixth amplifier.

5. The integrator of claim 4.

10. The negative feedback circuit includes: a seventh subtraction unit that outputs a difference between the negative output signal and the positive output signal; a seventh amplifier that amplifies the signal output by the seventh subtractor; a seventh delay unit that delays one of the negative output signal and the positive output signal input to the seventh subtraction unit with respect to the other, and inputs the delayed signal to the seventh subtraction unit; an eighth subtraction unit having two input terminals to which the negative output signals are respectively input, and outputting a difference between the negative output signals input to the two input terminals; an eighth amplifier that amplifies the signal output by the eighth subtractor; an eighth delay unit that delays one of the negative output signals input to the two input terminals of the eighth subtraction unit with respect to the other, and inputs the delayed one to the eighth subtraction unit; having a delay amount of the seventh delay section and the eighth delay section is greater than a delay amount of the third delay section and the fourth delay section; The negative feedback signal is generated based on the signals output from the third amplifier, the fourth amplifier, the seventh amplifier, and the eighth amplifier.

9. The integrator of claim 8.

11. The positive feedback circuit includes: a plurality of subtraction units that output a difference between the positive output signal and the negative output signal; a delay unit provided corresponding to each of the plurality of subtraction units, the delay unit delaying one of the positive output signal and the negative output signal input to the corresponding subtraction unit with respect to the other, and inputting the delayed one to the corresponding subtraction unit; an amplifier provided corresponding to each of the plurality of subtraction units, the amplifier amplifying a signal output from the corresponding subtraction unit; having a delay time of at least one of the delay units is different from a delay time of at least another of the delay units; a gain of at least one of the amplifier units is different from a gain of at least one other of the amplifier units; The positive feedback circuit generates the positive feedback signal based on the signal output from each of the amplifiers.

2. The integrator of claim 1.

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