Method for manufacturing photoelectric conversion panel, photoelectric conversion panel, and x-ray imaging panel

Abstract

To provide a method for manufacturing a photoelectric conversion panel that can reduce the number of parts and the number of manufacturing steps while preventing wirings from being exposed, a photoelectric conversion panel, and an x-ray imaging panel.SOLUTION: A method for manufacturing a photoelectric conversion panel includes forming a short ring, forming a plurality of data lines to be connected to TFT and the short ring, forming a first conductive portion of a bias line to be connected to a photodiode on a layer above the photodiode, and cutting the plurality of data lines 12 after forming the first conductive portion, thereby electrically isolating the short ring 53 and the TFT 15 from each other, and forming an inorganic insulating film 107b in an isolation portion 42 created by cutting the data lines 12.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a photoelectric conversion panel, a photoelectric conversion panel, and an X-ray imaging panel. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor light-emitting device. In this manufacturing method, a step of forming a plurality of electrodes on a substrate, and a step of forming short-circuit wiring connected to all of the plurality of electrodes on the substrate so as to straddle a dividing line before dividing the substrate are performed. Then, a step of dividing the substrate along the dividing line is performed.

[0003] Patent Document 2 discloses an active matrix substrate with a short ring. This active matrix substrate includes a display circuit section including a plurality of gate wirings, a plurality of source wirings, and a transistor, an electrostatic protection element, a short ring, a fuse, and a heater. The fuse is disposed between the short ring and the display circuit section. The short ring is connected to the display circuit section via the fuse and the electrostatic protection element, and shorts the display circuit section before the fuse is cut off. Then, after the fuse is heated by the heater, a current is passed through the fuse to cut off the fuse. This causes the display circuit section to be cut off from the short ring. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 7-99344

[0005] [Patent Document 2] JP 2011-164231 A Summary of the Invention [Problem to be solved by the invention]

[0006] According to the manufacturing method of the semiconductor light emitting device of the above-mentioned Patent Document 1, in the process prior to the dividing process, the short-circuiting wires can disperse static electricity. However, after the process of dividing the substrate along the dividing line, the short-circuiting wires are exposed on the outer end surface of the substrate. This causes a problem in that static electricity easily intrudes from the exposed short-circuiting wires.

[0007] In the method for manufacturing an active matrix substrate described in Patent Document 2, the fuse is heated by a heater, and then a current is passed through the fuse to cut it off, thereby isolating the short ring from the display circuit section. As a result, unlike Patent Document 1, in which the substrate is divided, the short ring is not exposed on the outer edge surface of the substrate.

[0008] However, in the active matrix substrate described in Patent Document 2, it is necessary to provide a fuse and a heater on the active matrix substrate in order to electrically isolate the short ring from the display circuit section (transistor). This increases the number of components in the active matrix substrate (panel). In addition, a manufacturing process is required to place the fuse and the heater on the active matrix substrate, and a manufacturing process is required to pass current through the fuse and the heater.

[0009] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a manufacturing method for a photoelectric conversion panel, a photoelectric conversion panel, and an X-ray imaging panel that can reduce the number of parts and the number of manufacturing steps while preventing exposure of wiring. [Means for solving the problem]

[0010] In order to solve the above problem, a manufacturing method for a photoelectric conversion panel according to a first aspect of the present disclosure includes forming a transistor in a pixel region on a substrate, forming a photodiode connected to the transistor in the pixel region, forming a short ring so as to surround the pixel region in a planar view, forming a plurality of wirings short-circuited by the short ring, the plurality of wirings being connected to the transistor or the photodiode and the short ring, forming a bias line connected to the photodiode above the photodiode, and after forming the bias line, cutting the plurality of wirings to electrically isolate the short ring from the transistor or the photodiode, and forming a first insulating film in a recess created by cutting the plurality of wirings.

[0011] A photoelectric conversion panel according to a second aspect includes a transistor formed in a pixel region on a substrate, a photodiode formed in the pixel region, the photodiode connected to the transistor, a ring-shaped wiring formed to surround the pixel region in a planar view, a wiring portion having a first conductive portion connected to the transistor or the photodiode, and a second conductive portion connected to the ring-shaped wiring, the first conductive portion and the second conductive portion being electrically isolated from each other, a bias line formed in a layer above the photodiode, the bias line connected to the photodiode, and a first insulating film formed in a layer above the bias line, the first insulating film being at least partially formed between the first conductive portion and the second conductive portion, thereby insulating the first conductive portion from the second conductive portion.

[0012] An X-ray imaging panel according to a third aspect includes a transistor formed in a pixel region on a substrate, a photodiode formed in the pixel region, the photodiode connected to the transistor, a ring-shaped wiring formed to surround the pixel region in a planar view, a wiring portion having a first portion connected to the transistor or the photodiode and a second portion connected to the ring-shaped wiring, the first portion and the second portion being electrically isolated from each other, a bias line formed in a layer above the photodiode, the bias line connected to the photodiode, a first insulating film formed in a layer above the bias line, the first insulating film being at least partially formed between the first portion and the second portion to insulate the first portion from the second portion, and a scintillator formed to cover the pixel region. Effect of the Invention

[0013] According to the above configuration, after the wirings are cut, the first insulating film can prevent the wirings from being exposed. Furthermore, the short ring and the transistor or photodiode can be electrically isolated without arranging components (e.g., fuses and heaters) for cutting the wirings in the photoelectric conversion panel (X-ray imaging panel). As a result, the number of components in the photoelectric conversion panel (X-ray imaging panel) can be reduced. Furthermore, since the process of arranging components for cutting the wirings is no longer necessary, the number of manufacturing processes for the photoelectric conversion panel can be reduced. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic diagram showing an X-ray imaging device 100 equipped with an X-ray imaging panel 10 including a photoelectric conversion panel 1. As shown in FIG. [Diagram 2] FIG. 2 is a plan view showing a schematic configuration of the photovoltaic conversion panel 1. As shown in FIG. [Diagram 3] FIG. 3 is a cross-sectional view showing a configuration within a pixel region R1 of the photoelectric conversion panel 1. As shown in FIG. [Figure 4]FIG. 4 is a cross-sectional view (1) showing the boundary portion between the pixel region R1 and the frame region R2. [Diagram 5] FIG. 5 is a cross-sectional view (2) showing the boundary portion between the pixel region R1 and the frame region R2. [Figure 6] FIG. 6 is a cross-sectional view (3) showing the boundary portion between the pixel region R1 and the frame region R2. [Figure 7] FIG. 7 is a cross-sectional view showing the configuration within the frame region R2 of the photoelectric conversion panel 1. As shown in FIG. [Figure 8] FIG. 8 is a flow diagram for explaining the manufacturing process of the photoelectric conversion panel 1 and the X-ray imaging panel 10. As shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view (1) for explaining the manufacturing process of the photoelectric conversion panel 1 and the X-ray imaging panel 10. As shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view (2) for explaining the manufacturing process of the photoelectric conversion panel 1 and the X-ray imaging panel 10. As shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view (3) for explaining the manufacturing process of the photoelectric conversion panel 1 and the X-ray imaging panel 10. As shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view (4) for explaining the manufacturing process of the photoelectric conversion panel 1 and the X-ray imaging panel 10. As shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view (5) for explaining the manufacturing process of the photoelectric conversion panel 1 and the X-ray imaging panel 10. As shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view (6) for explaining the manufacturing process of the photoelectric conversion panel 1 and the X-ray imaging panel 10. As shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view (7) for explaining the manufacturing process of the photoelectric conversion panel 1 and the X-ray imaging panel 10. As shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present disclosure will be described based on the drawings. Note that the present disclosure is not limited to the following embodiment, and appropriate design changes can be made within the scope of satisfying the configuration of the present disclosure. In addition, in the following description, the same parts or parts having similar functions are commonly used with the same reference numerals in different drawings, and repeated description thereof will be omitted. In addition, each configuration described in the embodiment and the modified example may be appropriately combined or changed within the scope of the gist of the present disclosure. In addition, in order to make the description easier to understand, in the drawings referred to below, the configuration is shown in a simplified or schematic manner, and some components are omitted. In addition, the dimensional ratio between the components shown in each figure does not necessarily indicate the actual dimensional ratio.

[0016] [Configuration of X-ray imaging device 100] 1 is a schematic diagram showing an X-ray imaging device 100 equipped with an X-ray imaging panel 10 including a photoelectric conversion panel 1 in this embodiment. The X-ray imaging device 100 includes the X-ray imaging panel 10 including the photoelectric conversion panel 1 and a scintillator 2, a control unit 3, and an X-ray source 4.

[0017] 1, the control unit 3 includes a gate control circuit 3a, a signal readout circuit 3b, and a bias voltage supply circuit 3c. The gate control circuit 3a is connected to a gate terminal 31 of the photoelectric conversion panel 1. The signal readout circuit 3b is connected to a data terminal 32. The bias voltage supply circuit 3c is connected to a bias terminal 33.

[0018] The X-ray source 4 irradiates the subject S with X-rays. The X-rays transmitted through the subject S are converted into fluorescence (hereinafter, scintillation light) in the scintillator 2 arranged on the upper part of the photoelectric conversion panel 1. The X-ray imaging device 100 generates an X-ray image by capturing the scintillation light on the X-ray imaging panel 10.

[0019] 2 is a plan schematic diagram showing a schematic configuration of the photoelectric conversion panel 1. A plurality of gate terminals 31, a plurality of data terminals 32, a bias terminal 33, a plurality of photodiodes 14, and a plurality of thin film transistors (TFTs: Thin Film Transistors) 15 are formed on a substrate 101 of the photoelectric conversion panel 1. In addition, a plurality of gate lines 11, a plurality of data lines 12, a bias line 13, and a short ring 53 are formed on the substrate 101 of the photoelectric conversion panel 1.

[0020] The gate lines 11 include a first conductive portion 11a connecting the gate electrodes 15a of the TFTs 15 to the gate terminal 31, and a second conductive portion 11b connected to the short ring 53. The first conductive portion 11a and the second conductive portion 11b are electrically isolated from each other at a blocking portion 41. The data lines 12 include a first conductive portion 12a connecting the source electrodes 15c of the TFTs 15 to the data terminal 32, and a second conductive portion 12b connected to the short ring 53. The first conductive portion 12a and the second conductive portion 12b are electrically isolated from each other at a blocking portion 42. The bias line 13 includes a first conductive portion 13a connecting the photodiodes 14 to the bias terminal 33, and a second conductive portion 13b connected to the short ring 53. The first conductive portion 13a and the second conductive portion 13b are electrically isolated from each other at a blocking portion 43.

[0021] As shown in Fig. 2, the photoelectric conversion panel 1 is provided with a pixel region R1 (active region) and a frame region R2. The pixel region R1 has, for example, a rectangular shape in a plan view. The pixel region R1 is a region in which a plurality of pixels 20 are formed. The pixels 20 are regions partitioned by gate lines 11 and data lines 12. The first conductive portions 11a, 12a, and 13a are each formed on the substrate 101, extending from the pixel region R1 to the frame region R2.

[0022] As shown in Fig. 2, in the pixel region R1, a plurality of gate lines 11 and a plurality of data lines 12 are formed so as to intersect with each other. As a result, a plurality of pixels 20 are formed in a matrix shape in a plan view. The photoelectric conversion panel 1 includes an active matrix substrate. In addition, the bias lines 13 are formed, for example, along the data lines 12. Each of the pixels 20 is provided with a photodiode 14 and a TFT 15.

[0023] As shown in FIG. 2, the frame region R2 is provided on the substrate 101 outside the pixel region R1. In the frame region R2, the gate terminal 31, the data terminal 32, the bias terminal 33, and the short ring 53 are arranged. The short ring 53 is formed in a rectangular frame shape so as to surround the pixel region R1. The short ring 53 is a ring-shaped wiring. The short ring 53 is formed outside (closer to the outer end) of the substrate 101 than the gate terminal 31, the data terminal 32, and the bias terminal 33. In the frame region R2, the gate terminals 31 are arranged side by side in the Y direction. In the frame region R2, the data terminals 32 and the bias terminals 33 are arranged side by side in the X direction. The gate terminals 31 transmit gate signals from the gate control circuit 3a to the gate lines 11. The data terminals 32 apply read voltages from the signal read circuit 3b to the data lines 12. Further, the plurality of data terminals 32 acquire data signals from the photodiodes 14 via the data lines 12 and the TFTs 15, and transmit the data signals to the signal read circuit 3b. The bias terminal 33 supplies a bias voltage from the bias voltage supply circuit 3c to the bias line 13.

[0024] The interrupter 41 is formed in the frame region R2 between the gate terminal 31 and the short ring 53 in a planar view. The interrupter 42 is formed in the frame region R2 between the data terminal 32 and the short ring 53 in a planar view. The interrupter 43 is formed in the frame region R2 between the bias terminal 33 and the short ring 53 in a planar view.

[0025] The control unit 3 shown in FIG. 1 irradiates X-rays from the X-ray source 4 and generates an X-ray image based on a data signal acquired by the signal readout circuit 3b. The photodiode 14 converts the X-rays transmitted through the subject S into charges corresponding to the amount of scintillation light converted by the scintillator while a bias voltage is applied from the bias line 13, and transmits a signal (data signal) corresponding to the charges to the TFT 15. Then, the control unit 3 causes the gate control circuit 3a to sequentially and selectively supply gate signals to each gate line 11. The TFT 15 to which the gate signal is supplied is turned on. A readout voltage is applied to the data line 12 by the signal readout circuit 3b, and when the TFT 15 is turned on, a signal (data signal) corresponding to the charges converted in the photodiode 14 is applied to the readout voltage. Then, the signal readout circuit 3b acquires the data signal. The control unit 3 generates an X-ray image based on the data signals of each pixel 20 in the pixel region R1.

[0026] (Details of the configuration of photovoltaic conversion panel 1) The configuration of the photoelectric conversion panel 1 will be described in detail with reference to Fig. 3 to Fig. 7. Fig. 3 is a cross-sectional view showing the configuration within pixel region R1 of the photoelectric conversion panel 1. Figs. 4 to 6 are cross-sectional views showing the boundary between pixel region R1 and frame region R2. Fig. 7 is a cross-sectional view showing the configuration within frame region R2 of the photoelectric conversion panel 1.

[0027] Gate lines, data lines, and bias lines 4 to 7, in the frame region R2, the first conductive portions 11a, 12a, and 13a are formed in the same layer as the layer in which the source electrode 15c and the drain electrode 15d are formed (see FIG. 3). As shown in FIG. 7, the second conductive portions 11b, 12b, and 13b are each formed in the frame region R2 on the substrate 101. In addition, the second conductive portions 11b, 12b, and 13b are formed in the same layer as the layer in which the source electrode 15c and the drain electrode 15d are formed (see FIG. 3).

[0028] Here, the part of the first conductive portion 11a formed in the same layer as the layer in which the gate electrode 15a is formed is called the first conductive portion 11aa, and the part formed in the same layer as the layer in which the source electrode 15c and the drain electrode 15d are formed is called the first conductive portion 11ab. Also, the part of the first conductive portion 12a formed in a layer above the layer in which the photodiode 14 is formed is called the first conductive portion 12aa, and the part formed in the same layer as the layer in which the source electrode 15c and the drain electrode 15d are formed is called the first conductive portion 12ab. Also, the part of the first conductive portion 12a formed in a layer above the layer in which the photodiode 14 is formed is called the first conductive portion 12aa, and the part formed in the same layer as the layer in which the source electrode 15c and the drain electrode 15d are formed is called the first conductive portion 12ab.

[0029] <Configuration of pixel region R1> As shown in FIG. 3, the TFT 15 has a gate electrode 15a connected to the gate line 11 (see FIG. 2), a semiconductor active layer 15b, a source electrode 15c connected to the data line 12, and a drain electrode 15d connected to the photodiode 14. The photodiode 14 is formed in a layer above the layer in which the TFT 15 is formed. The photodiode 14 also includes a photoelectric conversion layer 16, a cathode 14b, and an anode 14c. The photoelectric conversion layer 16 is provided between the cathode 14b and the anode 14c. The drain electrode 15d and the cathode 14b are connected via a cathode connection electrode 14a provided in a contact hole CH1.

[0030] The photoelectric conversion panel 1 also includes a connection electrode 12d that connects the source electrode 15c and the data line 12. A part of the connection electrode 12d is disposed in a contact hole CH2 and is connected to a first conductive portion 12aa of the data line 12 via the contact hole CH2. A part of the first conductive portion 13aa of the bias line 13 is formed in a contact hole CH3. In the pixel region R1, the bias line 13 is formed in a layer above the layer in which the photodiode 14 is formed.

[0031] As shown in FIG. 3, the gate electrode 15a is formed on a substrate 101. The substrate 101 is, for example, a glass substrate having insulating properties. The gate electrode 15a is configured as a laminated film containing, for example, tungsten (W) and tantalum nitride (TaN) as materials. A gate insulating film 102 is provided so as to cover the gate electrode 15a. The gate insulating film 102 is, for example, an insulating film made of silicon oxide (SiO2) in an upper layer and a silicon nitride (SiN x 4 is made of the same material as the gate electrode 15a.

[0032] The semiconductor active layer 15b and the source electrode 15c and the drain electrode 15d connected to the semiconductor active layer 15b are formed on the gate electrode 15a with a gate insulating film 102 interposed therebetween. The semiconductor active layer 15b is made of an oxide semiconductor. The oxide semiconductor is, for example, an amorphous oxide semiconductor containing indium (In), gallium (Ga) and zinc (Zn) in a predetermined ratio. With this configuration, the off-leak current of the thin film transistor 15 can be reduced compared to amorphous silicon (a-Si). If the off-leak current of the thin film transistor 15 is small, a highly sensitive sensor panel can be obtained, and a photoelectric conversion panel 1 with low exposure can be obtained. The semiconductor active layer 15b is not limited to this, and may be made of InGaO3 (ZnO)5, magnesium zinc oxide (Mg x Zinc 1-x O), cadmium zinc oxide (Cd x Zinc 1-x O), cadmium oxide (CdO), InSnZnO (containing In (indium), Sn (tin), and Zn (zinc)), In (indium)-Al (aluminum)-Zn (zinc)-O (oxygen)-based amorphous oxide semiconductors, etc. may also be used. In addition, "amorphous" and "crystalline (including polycrystalline, microcrystalline, and c-axis oriented)" materials are also applicable as oxide semiconductors.

[0033] The source electrode 15c and the drain electrode 15d are disposed on the gate insulating film 102 so as to be in contact with a part of the semiconductor active layer 15b. The source electrode 15c and the drain electrode 15d are formed in the same layer. The source electrode 15c and the drain electrode 15d have a three-layer structure in which a metal film made of aluminum (Al) is sandwiched between two metal films made of titanium (Ti), for example.

[0034] 3, a protective film 103 is provided on the gate insulating film 102 so as to cover the source electrode 15c and the drain electrode 15d. The protective film 103 is made of, for example, silicon oxide (SiO2). A planarizing film 104 is provided on the upper layer of the protective film 103. That is, the planarizing film 104 planarizes the upper part of the thin film transistor 15. The planarizing film 104 is made of an organic insulating film containing a resin material (organic material).

[0035] The cathode connection electrode 14a is formed on the upper layer of the planarization film 104. The connection electrode 12d is formed on the upper layer of the planarization film 104 and in the same layer as the cathode connection electrode 14a. The cathode connection electrode 14a is formed in the contact hole CH1 and connects the drain electrode 15d and the cathode 14b. The connection electrode 12d is formed in the contact hole CH2 and connects the source electrode 15c and the first conductive portion 12a. The cathode connection electrode 14a and the connection electrode 12d have a three-layer structure in which, for example, two metal films made of titanium (Ti) are laminated to sandwich a metal film made of aluminum (Al). Here, since aluminum is contained in the cathode connection electrode 14a and the connection electrode 12d, the electric resistance value of the cathode connection electrode 14a and the connection electrode 12d is low because aluminum has a smaller electric resistance value than ITO.

[0036] An inorganic insulating film 105a is formed on the cathode connecting electrode 14a and the connecting electrode 12d. A contact hole CH4 is provided in the inorganic insulating film 105a on the connecting electrode 12d, and a part of the first conductive portion 12a is provided in the contact hole CH4. The inorganic insulating film 105a is made of, for example, silicon nitride (SiN x ) or silicon dioxide (SiO2).

[0037] The cathode 14b of the photodiode 14 is formed above the cathode connecting electrode 14a so as to cover a part of the inorganic insulating film 105a. The cathode 14b and the cathode connecting electrode 14a are in contact with each other. The cathode 14b is made of, for example, titanium (Ti).

[0038] The photoelectric conversion layer 16 is formed on the cathode 14b. The photoelectric conversion layer 16 is configured by sequentially stacking an n-type amorphous semiconductor layer 161, an intrinsic amorphous semiconductor layer 162, and a p-type amorphous semiconductor layer 163. The n-type amorphous semiconductor layer 161 is made of amorphous silicon doped with an n-type impurity (e.g., phosphorus). The intrinsic amorphous semiconductor layer 162 is made of intrinsic amorphous silicon. The intrinsic amorphous semiconductor layer 162 is formed in contact with the n-type amorphous semiconductor layer 161. The p-type amorphous semiconductor layer 163 is made of amorphous silicon doped with a p-type impurity (e.g., boron). The p-type amorphous semiconductor layer 163 is formed in contact with the intrinsic amorphous semiconductor layer 162. The anode 14c is formed on the photoelectric conversion layer 16. The anode 14c is made of, for example, ITO (Indium Tin Oxide).

[0039] The inorganic insulating film 105b is formed so as to cover at least a portion of the photodiode 14 and the inorganic insulating film 105a. A contact hole CH3 in which a portion of the bias line 13 is provided is formed in the inorganic insulating film 105b. The inorganic insulating film 105b also covers a portion of the upper surface of the photodiode 14 and the side surface of the photodiode 14. The inorganic insulating film 105b also has contact holes CH3 and CH4 formed therein. The inorganic insulating film 105b is configured as an inorganic insulating film, for example, and is made of silicon nitride (SiN x ) or silicon dioxide (SiO2).

[0040] The planarization film 106 is formed in a layer above the photodiode 14, and is formed so as to cover the inorganic insulating film 105b. The planarization film 106 also covers the photodiode 14, and planarizes a step portion formed by the photodiode 14. The planarization film 106 is made of, for example, the same material (organic insulating film) as the planarization film 104. In addition, contact holes CH3 and CH4 are formed in the planarization film 106.

[0041] The inorganic insulating film 107a is formed on the planarizing film 106. Contact holes CH3 and CH4 are formed in the inorganic insulating film 107a. A first conductive portion 12aa of the data line 12 and a first conductive portion 13aa of the bias line 13 are formed on the inorganic insulating film 107a.

[0042] In the contact hole CH4, the first conductive portion 12aa and the connection electrode 12d are connected. In the contact hole CH3, the first conductive portion 13aa and the anode 14c of the photodiode 14 are connected. The first conductive portion 12a and the first conductive portion 13aa each have a layer having a three-layer structure in which two metal films made of titanium (Ti) are stacked to sandwich a metal film made of aluminum (Al), and a layer made of ITO.

[0043] The inorganic insulating film 107b is formed so as to cover the inorganic insulating film 107a, the first conductive portion 12a, and the bias line 13. The inorganic insulating films 107a and 107b are passivation films (protective films). The inorganic insulating films 107a and 107b are made of, for example, silicon nitride (SiN x ) or silicon dioxide (SiO2).

[0044] The planarization film 108 is formed so as to cover the inorganic insulating film 107b. The planarization film 108 planarizes the portion above the first conductive portion 12aa and the first conductive portion 13aa. The planarization film 108 is made of, for example, the same material as the planarization film 104 (an organic insulating film).

[0045] Configuration of frame region R2 As shown in FIG. 4, the first conductive portion 11aa and the first conductive portion 11ab of the gate line 11 are connected via a contact hole CH5a formed in the gate insulating film 102. The gate terminal 31 is disposed on the first conductive portion 11ab. The photoelectric conversion panel 1 includes terminal connection electrodes 31a, 31b, and 31c that connect the gate terminal 31 and the first conductive portion 11ab. The terminal connection electrodes 31a and 31b are formed in the same layer as the layer in which the cathode connection electrode 14a is formed. The terminal connection electrodes 31a and 31b are made of the same material as the cathode connection electrode 14a. The terminal connection electrode 31c is formed in the same layer as the layer in which the first conductive portion 13aa of the bias line 13 is formed. The terminal connection electrode 31c is made of the same material as the first conductive portion 13aa of the bias line 13. The first conductive portion 11ab is made of the same material as the source electrode 15c and the drain electrode 15d. The gate terminal 31 is made of, for example, ITO.

[0046] As shown in FIG. 5, the first conductive portion 12aa and the first conductive portion 12ab of the data line 12 are connected via the connection electrode 12e. The first conductive portion 12aa and the connection electrode 12e are connected via a contact hole CH5b formed in the planarization film 106. The connection electrode 12e and the first conductive portion 12ab are connected via a contact hole CH5c formed in the protective film 103. The data terminal 32 is disposed on the first conductive portion 12ab. The photoelectric conversion panel 1 includes terminal connection electrodes 32a, 32b, and 32c that connect the data terminal 32 and the first conductive portion 12ab. The terminal connection electrodes 32a and 32b are formed in the same layer as the layer in which the cathode connection electrode 14a is formed. The terminal connection electrodes 32a and 32b are made of the same material as the cathode connection electrode 14a. The terminal connection electrode 32c is formed in the same layer as the layer in which the first conductive portion 13aa of the bias line 13 is formed. The terminal connection electrode 32c is made of the same material as the first conductive portion 13aa of the bias line 13. The first conductive portion 12ab is made of the same material as the source electrode 15c and the drain electrode 15d. The data terminal 32 is made of, for example, ITO.

[0047] As shown in FIG. 6, the first conductive portion 13aa and the first conductive portion 13ab of the bias line 13 are connected via the connection electrode 13e. The first conductive portion 13aa and the connection electrode 13e are connected via a contact hole CH5d formed in the planarization film 106. The connection electrode 13e and the first conductive portion 13ab are connected via a contact hole CH5e formed in the protective film 103. The bias terminal 33 is disposed on the first conductive portion 13ab. The photoelectric conversion panel 1 includes terminal connection electrodes 33a, 33b, and 33c that connect the bias terminal 33 and the first conductive portion 13ab. The terminal connection electrodes 33a and 33b are formed in the same layer as the layer in which the cathode connection electrode 14a is formed. The terminal connection electrodes 33a and 33b are made of the same material as the cathode connection electrode 14a. The terminal connection electrode 33c is formed in the same layer as the layer in which the first conductive portion 13aa of the bias line 13 is formed. The terminal connection electrode 33c is made of the same material as the first conductive portion 13aa of the bias line 13. The first conductive portion 13ab is made of the same material as the source electrode 15c and the drain electrode 15d. The bias terminal 33 is made of, for example, ITO.

[0048] As shown in FIG. 7, in the frame region R2, a short ring 53 is formed on the substrate 101. The short ring 53 is formed in the same layer as the layer in which the gate electrode 15a is formed. The short ring 53 is made of the same material as the material of the gate electrode 15a. In the frame region R2, a contact hole CH6 is formed in the gate insulating film 102. The contact hole CH6 is formed on the short ring 53. The second conductive portion 12b of the data line 12 is disposed in the contact hole CH6. The short ring 53 is connected to the second conductive portion 12b in the contact hole CH6.

[0049] The data line 12 is arranged such that the first conductive portion 12a (first conductive portion 12ab) and the second conductive portion 12b are separated by the interrupting portion 42 in the frame region R2. As a result, the first conductive portion 12a and the second conductive portion 12b are electrically isolated. The interrupting portion 42 is formed in a concave shape recessed toward the substrate 101. A part 107c of the inorganic insulating film 107b is arranged in the interrupting portion 42. Note that the portion of the frame region R2 in which the gate line 11 and the interrupting portion 41 are arranged, and the portion of the frame region R2 in which the bias line 13 and the interrupting portion 43 are arranged have the same configuration as the portion of the frame region R2 in which the data line 12 and the interrupting portion 42 are arranged shown in FIG. 7. For this reason, the description of the portion of the frame region R2 in which the gate line 11 and the interrupting portion 41 are arranged, and the portion of the frame region R2 in which the bias line 13 and the interrupting portion 43 are arranged will be omitted.

[0050] According to the above configuration, the first conductive portion 12a and the second conductive portion 12b are covered with the inorganic insulating film 107b, so that it is possible to prevent the data line 12 from being exposed. It is possible to electrically isolate the short ring 53 from the TFT 15 or the photodiode 14 without arranging components (e.g., fuses and heaters) for disconnecting the first conductive portion 12a and the second conductive portion 12b in the photoelectric conversion panel 1. As a result, it is possible to reduce the number of components in the photoelectric conversion panel 1.

[0051] [Method of manufacturing photoelectric conversion panel 1] Next, a method for manufacturing the photoelectric conversion panel 1 according to this embodiment will be described with reference to Fig. 3 to Fig. 14. Fig. 8 is a flow chart for explaining the manufacturing process of the photoelectric conversion panel 1.

[0052] The manufacturing method of the portion where the data lines 12 and the blocking portion 42 are arranged in the frame region R2 of the photoelectric conversion panel 1 will be described below. The manufacturing method of the portion where the gate lines 11 and the blocking portion 41 in the frame region R2 are arranged and the portion where the bias lines 13 and the blocking portion 43 in the frame region R2 are arranged is the same as that of the portion where the data lines 12 and the blocking portion 42 in the frame region R2, so that the description thereof will be omitted.

[0053] 8, in step S1, in the pixel region R1, the gate electrode 15a (see FIG. 3) and the first conductive portion 11aa (see FIG. 4) of the gate line 11 are deposited and patterned on the substrate 101. Also, in this step S1, in the frame region R2, as shown in FIG. 6, the short ring 53 is deposited and patterned on the substrate 101.

[0054] In step S2, a gate insulating film 102 is formed and patterned so as to cover the gate electrode 15a, the first conductive portion 11aa, and the short ring 53. During the patterning in step S2, a contact hole CH6 is formed in the frame region R2. Then, in step S3, a semiconductor active layer 15b (see FIG. 3) is formed on the gate insulating film 102 in the pixel region R1 and patterned.

[0055] In step S4, in the pixel region R1, a source electrode 15c and a drain electrode 15d are formed and patterned on the gate insulating film 102. This forms a thin film transistor 15. Also, in this step S4, as shown in FIG. 6, in the frame region R2, a first conductive portion 12ab, a second conductive portion 12b, and a third conductive portion 12c constituting a data line 121 are formed on the gate insulating film 102. The third conductive portion 12c connects the first conductive portion 12ab and the second conductive portion 12b. The data line in the state before the first conductive portion 12ab and the second conductive portion 12b are disconnected is called the "data line 121", and the data line in the state after the first conductive portion 12ab and the second conductive portion 12b are disconnected is called the "data line 12".

[0056] 9, a part of the first conductive portion 12ab is disposed in the contact hole CH6. The short ring 53 is connected to the data line 121. The short ring 53 is also connected to the multiple data lines 121. The short ring 53 is also connected to the multiple TFTs 15 and the multiple data terminals 32 via the multiple data lines 121. As a result, the short ring 53 short-circuits the multiple data lines 121 and also short-circuits the multiple TFTs 15 and the multiple data terminals 32. As a result, even if the photodiode 14 or the TFT 15 in the pixel region R1 becomes charged during the manufacturing process of the photoelectric conversion panel 1, the short ring 53 can diffuse the static electricity, and the TFT 15 and the photodiode 14 can be protected against the static electricity.

[0057] In step S5, as shown in Fig. 3, in the pixel region R1, a protective film 103 is formed and patterned on the gate insulating film 102 so as to cover the source electrode 15c and the drain electrode 15d. Also, as shown in Fig. 9, in the frame region R2, a protective film 103 is formed and patterned on the gate insulating film 102 so as to cover the data line 121. As shown in Fig. 9, during this patterning, a portion 103b of the protective film 103 that overlaps with the portion of the data line 121 to be cut (the third conductive portion 12c) in a plan view is removed to expose the third conductive portion 12c.

[0058] In step S6, a heat treatment (annealing treatment) is performed on the exposed third conductive portion 12c of the data line 121. This causes SiO2 (silicon dioxide) of the protective film 103 to bond with aluminum of the third conductive portion 12c, changing the third conductive portion 12c into a state containing an aluminum-silicon alloy. As a result, in the frame region R2, when dry etching is performed on the cathode connecting electrode 14a and when dry etching is performed on the bias line 13 (first conductive portion 13aa), it is possible to prevent the third conductive portion 12c from being removed.

[0059] In step S7, as shown in FIG. 3, the planarizing film 104 is formed on the protective film 103 in the pixel region R1.

[0060] In step S8, the cathode connection electrode 14a and the connection electrode 12d are formed in the pixel region R1. Also, as shown in FIG. 10, in step S8, the conductive layer 14aa is formed in the frame region R2 so as to cover the protective film 103. In step S8, the connection electrode 12e (see FIG. 5), the connection electrode 13e (see FIG. 6), the terminal connection electrodes 32a and 32b (see FIG. 5), and the terminal connection electrodes 33a and 33b (see FIG. 6) are formed. Then, as shown in FIG. 11, the cathode connection electrode 14a, the connection electrode 12d, the conductive layer 14aa, the connection electrode 12e, the connection electrode 13e, the terminal connection electrodes 32a and 32b, and the terminal connection electrodes 33a and 33b are patterned by dry etching. In addition, the conductive layer 14aa is entirely removed. Furthermore, as shown in FIG. 11, the third conductive portion 12c remains even after step S8 is performed.

[0061] In step S9, the inorganic insulating film 105a is formed and patterned. Then, in step S10, in the pixel region R1, the cathode 14b (see FIG. 3) of the photodiode 14 is formed and patterned on a part of the inorganic insulating film 105a and the cathode connecting electrode 14a. Also in this step S10, in the frame region R2, the terminal connecting electrodes 32c and 33c (see FIGS. 5 and 6) are formed and patterned.

[0062] In step S11, the photoelectric conversion layer 16 (see FIG. 3) is formed in the pixel region R1. Specifically, an n-type amorphous semiconductor layer 161, an intrinsic amorphous semiconductor layer 162, and a p-type amorphous semiconductor layer 163 are laminated in this order. In step S12, the anode 14c is formed on the p-type amorphous semiconductor layer 163 in the pixel region R1.

[0063] In step S13, the inorganic insulating film 105b is formed and patterned. In step S14, the planarizing film 106 is formed in the pixel region R1, as shown in FIG.

[0064] In step S15, inorganic insulating film 107a is formed and patterned. In this step S15, as shown in Fig. 13, inorganic insulating film 105a, inorganic insulating film 105b, and a part of the inorganic insulating film 107a that overlaps with third conductive portion 12c in a plan view are removed by dry etching. Note that third conductive portion 12c is not removed by dry etching, so that a part of third conductive portion 12c is exposed. As a result, recess 105c is formed with third conductive portion 12c as a bottom surface.

[0065] In step S16, the first conductive portion 12aa of the data line 12 in the pixel region R1 and the first conductive portion 13aa of the bias line 13 are formed and patterned. As shown in FIG. 14, the first conductive portion 13aa of the bias line 13 is also formed in the frame region R2. When the first conductive portion 13ab of the bias line 13 is patterned, dry etching is performed. Here, the third conductive portion 12c is not removed by dry etching, so that the third conductive portion 12c remains as shown in FIG. 14. As a result, while all the electrodes (conductive layers) of the photoelectric conversion panel 1 are formed, the third conductive portion 12c remains, and thus the short ring 53 can disperse static electricity of the TFT 15 and the photodiode 14.

[0066] In step S17, as shown in FIG. 15, the data line 121 is cut. Specifically, the third conductive portion 12c of the data line 121 is removed by wet etching to cut off (sever) the first conductive portion 12a and the second conductive portion 12b. This forms a cutoff portion 42. The cutoff portion 42 electrically cuts off the first conductive portion 12a and the second conductive portion 12b, and electrically cuts off the short ring 53 and the TFT 15 or the photodiode 14. The cutoff portion 42 is a recess in which the third conductive portion 12c of the recess 105c is removed and the gate insulating film 102 becomes the bottom surface. Note that the etching of the first conductive portion 13aa is not completely completed in step S16 and the remaining portion is removed by wet etching in step S17. This makes it possible to prevent current leakage caused by the remaining portion.

[0067] Then, in step S18, an inorganic insulating film 107b is formed on the planarizing film 106 so as to cover the first conductive portions 12aa and 13aa, and is patterned so as to expose the terminal connection electrode 32c. As shown in FIG. 7, in step S18, a portion 107c of the inorganic insulating film 107b is formed in the blocking portion 42 (recess). As a result, the first conductive portion 12a and the second conductive portion 12b are blocked by the inorganic insulating film 107b. Since the first conductive portion 12a and the second conductive portion 12b are covered by the inorganic insulating film 107b, it is possible to prevent the data line 12 from being exposed.

[0068] In step S19, as shown in FIGS. 4 to 6, the gate terminal 31, the data terminal 32, and the bias terminal 33 are formed and patterned. In step S20, the planarization film 108 is formed and patterned. In this way, the photoelectric conversion panel 1 is completed.

[0069] Then, in step S21, the scintillator 2 is disposed so as to cover the pixel region R1, thereby completing the X-ray imaging panel 10. In this state, it is possible to carry out an imaging inspection of the X-ray imaging panel 10.

[0070] According to the above manufacturing method, it is possible to electrically isolate the short ring 53 from the TFT 15 or the photodiode 14 without arranging components (e.g., fuses and heaters) for disconnecting the gate lines 11, data lines 12, and bias lines 13 in the photoelectric conversion panel 1. As a result, it is possible to reduce the number of components in the photoelectric conversion panel 1. In addition, since the process of arranging components for disconnecting the above wiring is no longer necessary, it is possible to reduce the number of manufacturing processes for the photoelectric conversion panel 1.

[0071] Furthermore, according to the above manufacturing method, even after the first conductive portion 12a and the second conductive portion 12b are cut, the first conductive portion 12a can be used as a wiring for connecting the data terminal 32 and the TFT 15. As a result, the number of components of the photoelectric conversion panel 1 can be reduced compared to the case where a separate wiring for connecting the data terminal 32 and the TFT 15 is provided.

[0072] [Variations] Although the embodiments have been described above, the above-described embodiments are merely examples for implementing the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and can be implemented by appropriately modifying the above-described embodiments within the scope of the present disclosure.

[0073] (1) In the above embodiment, the first conductive portions 11ab, 12ab, and 13ab and the second conductive portions 11b, 12b, and 13b are formed in a layer above the layer in which the short ring 53 is formed, but the present disclosure is not limited to this. That is, the first conductive portions 11ab, 12ab, and 13ab and the second conductive portions 11b, 12b, and 13b may be formed in the same layer as the layer in which the short ring 53 is formed, or in a layer below the layer in which the short ring 53 is formed.

[0074] (2) In the above embodiment, the first conductive portion and the second conductive portion are cut by wet etching, but the present disclosure is not limited to this. For example, the first conductive portion and the second conductive portion may be cut by dry etching, or the first conductive portion and the second conductive portion may be cut by cutting with a blade.

[0075] (3) In the above embodiment, the first conductive portion is configured to include a conductive material containing aluminum, but the present disclosure is not limited to this. For example, the first conductive portion may be configured from a conductive material that does not contain aluminum (such as copper, silver, gold, or ITO).

[0076] (4) In the above embodiment, the first conductive portions 11ab, 12ab, and 13ab are formed in the same layer as the layer in which the source electrode 15c and the drain electrode 15d are formed, but the present disclosure is not limited to this. That is, the first conductive portions 11ab, 12ab, and 13ab may be formed in a layer above or below the layer in which the source electrode 15c and the drain electrode 15d are formed.

[0077] (5) In the above embodiment, examples of materials for the layers (films) constituting the photovoltaic conversion panel are shown, but the present disclosure is not limited to these examples. That is, the layers (films) constituting the photovoltaic conversion panel may be made of materials other than the above examples.

[0078] The above-mentioned configuration can also be explained as follows.

[0079] A manufacturing method for a photoelectric conversion panel according to a first configuration includes forming a transistor in a pixel region on a substrate, forming a photodiode connected to the transistor in the pixel region, forming a short ring so as to surround the pixel region in a planar view, forming a plurality of wirings short-circuited by the short ring and connected to the transistor or the photodiode and the short ring, forming a bias line connected to the photodiode above the photodiode, and after forming the bias line, cutting the plurality of wirings to electrically isolate the short ring from the transistor or the photodiode, and forming a first insulating film in a recess created by cutting the plurality of wirings (first configuration).

[0080] According to the first configuration, after the wirings are cut, the first insulating film can prevent the wirings from being exposed. Furthermore, the short ring and the transistor or photodiode can be electrically isolated without arranging components (e.g., fuses and heaters) for cutting the wiring in the photoelectric conversion panel (X-ray imaging panel). As a result, the number of components in the photoelectric conversion panel (X-ray imaging panel) can be reduced. Furthermore, since the process of arranging components for cutting the wiring is no longer necessary, the number of manufacturing processes for the photoelectric conversion panel can be reduced.

[0081] In the first configuration, forming the multiple wirings may include forming a conductive layer above the layer in which the short ring is formed, forming a second insulating film to cover the conductive layer, and removing portions of the second insulating film that overlap in a planar view with portions of the multiple wirings to be cut, to expose the conductive layer (second configuration).

[0082] According to the second configuration, the first insulating portion that overlaps the portion of the plurality of wirings to be cut in a plan view is removed, so that the plurality of wirings can be easily cut after this step.

[0083] In the second configuration, forming the conductive layer may include forming the conductive layer from a conductive material containing aluminum. Forming the second insulating film may include forming the second insulating film from an insulating material containing silicon dioxide. Forming the plurality of wirings may include, after forming the second insulating film, subjecting at least exposed portions of the conductive layer to a heat treatment, thereby changing the exposed portions to a state containing an aluminum silicon alloy. Forming the bias line may include performing dry etching. Cutting the plurality of wirings may include performing wet etching (third configuration).

[0084] According to the third configuration, since the aluminum silicon alloy is not removed by dry etching, even if a part of the wirings is exposed, the wirings can be prevented from being removed by dry etching when forming the bias line. Moreover, since the aluminum silicon alloy can be removed by wet etching, the wirings can be cut by performing wet etching.

[0085] In any one of the first to third configurations, the method for manufacturing a photoelectric conversion panel may further include forming a plurality of terminals on the plurality of wirings outside the pixel region and inside the short ring. Cutting the plurality of wirings may include cutting a portion of the plurality of wirings that connects the plurality of terminals and the short ring (fourth configuration).

[0086] According to the fourth configuration, even after the wirings are cut, some of the wirings can be used as wirings for connecting the terminals to the transistors or photodiodes. As a result, the number of components of the photoelectric conversion panel can be reduced compared to the case where wirings for connecting the terminals to the transistors or photodiodes are separately provided.

[0087] In any one of the first to fourth configurations, forming the transistor may include forming a gate electrode and forming a source electrode or a drain electrode in a layer above the gate electrode. Forming the short ring may include forming the short ring in the same layer as the layer in which the gate electrode is formed. Forming the plurality of wirings may include forming the plurality of wirings in the same layer as the layer in which the source electrode or the drain electrode is formed (fifth configuration).

[0088] According to the fifth configuration, the short ring and the multiple wirings can be formed in the same process as the process for forming the transistors, thereby reducing the number of manufacturing processes for the photoelectric conversion panel.

[0089] A photoelectric conversion panel according to a sixth configuration includes a transistor formed in a pixel region on a substrate, a photodiode formed in the pixel region, the photodiode connected to the transistor, a ring-shaped wiring formed to surround the pixel region in a planar view, a wiring section having a first conductive portion connected to the transistor or the photodiode and a second conductive portion connected to the ring-shaped wiring, the first conductive portion and the second conductive portion being electrically isolated from each other, a bias line formed in a layer above the photodiode, the bias line connected to the photodiode, and a first insulating film formed in a layer above the bias line, the first insulating film being at least partially formed between the first conductive portion and the second conductive portion to insulate the first conductive portion from the second conductive portion (sixth configuration).

[0090] According to the sixth configuration, it is possible to provide a photoelectric conversion panel that enables the number of parts to be reduced and the number of manufacturing steps to be reduced.

[0091] An X-ray imaging panel of a seventh configuration includes a transistor formed in a pixel region on a substrate, a photodiode formed in the pixel region, the photodiode connected to the transistor, a ring-shaped wiring formed to surround the pixel region in a planar view, a wiring section having a first portion connected to the transistor or the photodiode and a second portion connected to the ring-shaped wiring, the first portion and the second portion being electrically isolated from each other, a bias line formed in a layer above the photodiode, the bias line connected to the photodiode, a first insulating film formed in a layer above the bias line, the first insulating film being at least partially formed between the first portion and the second portion to insulate the first portion from the second portion, and a scintillator formed to cover the pixel region (seventh configuration).

[0092] According to the seventh configuration, it is possible to provide an X-ray imaging panel that can reduce the number of parts and the number of manufacturing steps. [Explanation of symbols]

[0093] 1: photoelectric conversion panel, 2: scintillator, 10: X-ray imaging panel, 11: gate line, 11a, 11aa, 11ab, 12a, 12aa, 12ab, 13a, 13aa, 13ab: first conductive portion, 11b, 12b, 13b: second conductive portion, 12: data line, 12c: third conductive portion, 13: bias line, 14: photodiode, 14aa: conductive layer, 15: TFT, 15a: gate electrode, 15c: source electrode, 15d: drain electrode, 20: pixel, 31: gate terminal, 32: data terminal, 33: bias terminal, 41, 42, 43: blocking portion (recess), 53: short ring, 100: X-ray imaging device, 101: substrate, 103: protective film, 103b: portion, 104: planarizing film, 105a, 105b, 107a, 107b: inorganic insulating film, R1: pixel region, R2: frame region

Claims

1. forming a transistor in a pixel region on a substrate; forming a photodiode connected to the transistor in the pixel region; A short ring is formed so as to surround the pixel region in a plan view; forming a plurality of wirings that are short-circuited by the short ring and are connected to the transistor or the photodiode and the short ring; forming a bias line connected to the photodiode in a layer above the photodiode; After forming the bias line, the plurality of wirings are cut to electrically isolate the short ring from the transistor or the photodiode; forming a first insulating film in a recess formed by cutting the plurality of wirings.

2. Forming the plurality of wirings includes: forming a conductive layer above the layer in which the short ring is formed; forming a second insulating film so as to cover the conductive layer; 2 . The method for manufacturing a photovoltaic conversion panel according to claim 1 , further comprising removing a portion of the second insulating film that overlaps in a planar view with a portion of the plurality of wirings to be cut, thereby exposing the conductive layer.

3. forming the conductive layer includes forming the conductive layer from a conductive material including aluminum; forming the second insulating film includes forming the second insulating film from an insulating material including silicon dioxide; forming the plurality of wirings includes, after forming the second insulating film, subjecting at least an exposed portion of the conductive layer to a heat treatment to change the exposed portion to a state containing an aluminum silicon alloy; forming the bias line includes performing dry etching; The method for producing a photovoltaic conversion panel according to claim 2 , wherein cutting the plurality of wirings includes performing wet etching.

4. Further forming a plurality of terminals on the plurality of wirings outside the pixel region and inside the short ring; 4. The method for manufacturing a photoelectric conversion panel according to claim 1, wherein cutting the plurality of wirings includes cutting portions of the plurality of wirings that connect the plurality of terminals and the short ring.

5. forming the transistor includes forming a gate electrode and forming a source electrode or a drain electrode above the gate electrode; forming the short ring includes forming the short ring in the same layer as the layer in which the gate electrode is formed, 4. The method for manufacturing a photoelectric conversion panel according to claim 1, wherein forming the plurality of wirings includes forming the plurality of wirings in the same layer as a layer in which the source electrode or the drain electrode is formed.

6. A transistor formed in a pixel region on a substrate; a photodiode formed in the pixel region and connected to the transistor; a ring-shaped wiring formed so as to surround the pixel region in a plan view; a wiring section having a first conductive portion connected to the transistor or the photodiode and a second conductive portion connected to the ring-shaped wiring, the first conductive portion and the second conductive portion being electrically isolated from each other; a bias line formed in a layer above the photodiode and connected to the photodiode; A photoelectric conversion panel comprising: a first insulating film formed above the bias line, the first insulating film being at least partially formed between the first conductive portion and the second conductive portion, thereby insulating the first conductive portion from the second conductive portion.

7. A transistor formed in a pixel region on a substrate; a photodiode formed in the pixel region and connected to the transistor; a ring-shaped wiring formed so as to surround the pixel region in a plan view; a wiring section having a first portion connected to the transistor or the photodiode and a second portion connected to the ring-shaped wiring, the first portion and the second portion being electrically isolated from each other; a bias line formed in a layer above the photodiode and connected to the photodiode; a first insulating film formed in a layer above the bias line, the first insulating film being at least partially formed between the first portion and the second portion to insulate the first portion from the second portion; a scintillator formed so as to cover the pixel region.

Images