Radiation detector and detection system

Abstract

To provide a radiation detector in which, even when a dummy pattern is disposed in an intermediate region between a pixel region and a peripheral circuit region, dielectric breakdown of an insulating layer caused by charge-up of the dummy pattern is suppressed.SOLUTION: A radiation detector has a pixel region, a peripheral circuit region, and a first intermediate region arranged between the pixel region and the peripheral circuit region, and is configured such that a predetermined potential is supplied to a first conductive layer arranged on an insulating layer in the first intermediate region with the insulating layer sandwiched therebetween.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to radiation detectors and detection systems. [Background technology]

[0002] As a detector capable of detecting radiation (energy rays) such as visible light and X-rays, a detector having a pixel structure similar to that of a CMOS image sensor in a detection element is known. For example, a radiation detector has been proposed in which a shielding member having an opening is provided so that radiation is not irradiated to the peripheral circuit region but radiation is irradiated to the pixel region.

[0003] In a CMOS image sensor, the pixel region and the peripheral circuit region are integrally formed on a single semiconductor chip, and in recent years, chip sizes have been reduced and the number of pixels has increased. This has led to the need to miniaturize the wiring, and the interlayer insulating film is planarized by CMP (Chemical Mechanical Polishing). At this time, if the pattern density of the conductive layer in the pixel region and the peripheral circuit region differs, the polishing rate of the CMP for the interlayer insulating layer disposed on top of it may differ. This causes a difference in the thickness of the interlayer insulating film between the pixel region and the peripheral circuit region, which affects the characteristics of the CMOS image sensor.

[0004] In response to this, Patent Document 1 discloses a technique for reducing the height difference in the thickness of an interlayer insulating film by arranging a dummy pattern in a conductive layer that forms a gate electrode. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2008-98373 A Summary of the Invention [Problem to be solved by the invention]

[0006] In the radiation detector, a buffer region may be provided between the pixel region and the peripheral circuit region, taking into consideration variations in the alignment between the opening in the shielding member and the pixel region having the detection element, the spread of radiation that circulates from the opening in the shielding member into the peripheral circuit region, etc. In this case, as described above, in order to planarize the interlayer insulating film by CMP, it is also possible to arrange a dummy pattern in this buffer region, as in Patent Document 1.

[0007] However, the dummy pattern in Patent Document 1 is not electrically connected to any of the surrounding patterns and is floating. Since the buffer region may be irradiated with radiation depending on the position of the shielding member, the floating dummy pattern may be charged up when exposed to radiation. If the dummy pattern is charged up, dielectric breakdown may occur in the insulating layer adjacent to the dummy pattern, which may cause the radiation detector to malfunction.

[0008] One aspect of the present invention has been made in consideration of the above, and aims to provide a radiation detector in which, even if a dummy pattern is placed in a buffer region between a pixel region and a peripheral circuit region, dielectric breakdown of an insulating layer due to charging up of the dummy pattern is suppressed. [Means for solving the problem]

[0009] One aspect of the present invention relates to a radiation detector comprising: a pixel region in which a plurality of pixels are arranged; a peripheral circuit region in which a signal processing circuit is provided for processing signals from the plurality of pixels; and a first intermediate region arranged between the pixel region and the peripheral circuit region, each of the plurality of pixels comprising a radiation detection element provided on a semiconductor substrate and a transistor for outputting a signal corresponding to charge accumulated in the radiation detection element, wherein in the pixel region, the first intermediate region, and the peripheral circuit region, an insulating layer is arranged on the semiconductor substrate and an interlayer insulating layer is arranged on the insulating layer, the transistor has a gate electrode provided on the insulating layer, the first intermediate region has a first conductive layer arranged in contact with the insulating layer, and a first potential is supplied to the first conductive layer.

[0010] Another aspect of the present invention relates to a radiation detector comprising: a pixel region in which a plurality of pixels are arranged; a peripheral circuit region in which a signal processing circuit is provided for processing signals from the plurality of pixels; and a first intermediate region arranged between the pixel region and the peripheral circuit region, each of the plurality of pixels comprising a radiation detection element provided on a semiconductor substrate, and a transistor having a gate electrode and outputting a signal according to a charge accumulated in the radiation detection element, the first intermediate region comprising an insulating layer arranged on the semiconductor substrate, and a first conductive layer having polysilicon arranged on the insulating layer, an interlayer insulating layer being arranged on the discharge detection element, the transistor, and the first conductive layer, and a first potential being supplied to the first conductive layer. Effect of the Invention

[0011] According to the configuration described in the present disclosure, a radiation detector can be provided in which, even if a dummy pattern formed of a conductive layer is placed on an insulating layer in an intermediate region between a pixel region and a peripheral circuit region, destruction of the insulating layer due to charging up of the dummy pattern is suppressed. [Brief description of the drawings]

[0012] [Figure 1]1A is a diagram showing an example of a radiation detector in accordance with embodiment 1. FIG. 1B is a diagram for explaining the electrical configuration of the radiation detector in accordance with embodiment 1. [Diagram 2] 2 is a diagram showing an example of a pixel configuration of the radiation detector in the first embodiment. FIG. [Diagram 3] 1 is a cross-sectional view of a portion of a radiation detector in accordance with a first embodiment. [Figure 4] 4(a) is a diagram showing an example of a first buffer region in embodiment 1. (b) is a plan view showing a first wiring layer 17 in the configuration of FIG. 4(a). (c) is a cross-sectional view taken along line A-A' in FIG. 4(b). [Diagram 5] 5(a) is a diagram showing an example of a first buffer region in embodiment 2. (b) is a plan view showing a first wiring layer 17 in the configuration of FIG. 5(a). (c) is a cross-sectional view taken along line BB' in FIG. 5(b). [Figure 6] 6(a) is a diagram showing an example of a first buffer region in embodiment 3. (b) is a plan view showing a first wiring layer 17 in the configuration of FIG. 6(a). (c) is a cross-sectional view taken along line CC' in FIG. 6(b). [Figure 7] FIG. 11 is a diagram showing an example of a radiation detector according to a fourth embodiment. [Figure 8] FIG. 13 is a diagram illustrating an example of a radiation detector according to a fifth embodiment. [Figure 9] 9(a) is a diagram showing an example of a first buffer region and a second buffer region in embodiment 5. (b) is a plan view showing a first wiring layer 17 in the configuration of FIG. 9(a). (c) is a cross-sectional view taken along line D-D' in FIG. 9(b). [Figure 10] 10(a) is a diagram showing an example of the pixel region 2, the first buffer region, and the second buffer region of the radiation detector 1 in embodiment 5. FIG. 10(b) is a cross-sectional view taken along line EE' in FIG. [Figure 11] 13 is a diagram showing an example of a pixel region 2, a first buffer region, and a second buffer region of a radiation detector 11 in embodiment 6. FIG. [Figure 12] FIG. 13 is a diagram showing an example of a radiation detector 1 according to a seventh embodiment. [Figure 13]FIG. 13 is a diagram showing an example of a radiation detector 1 according to an eighth embodiment. [Figure 14] FIG. 13 is a diagram for explaining a radiation imaging system according to a ninth embodiment. [Figure 15] FIG. 23 is a diagram illustrating a detection system including a radiation detector according to a tenth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. Note that the present invention is not limited to the following embodiment, and can be modified as appropriate without departing from the gist of the present invention. In addition, in the drawings described below, parts having the same functions are given the same reference numerals, and their description may be omitted or simplified.

[0014] In the following embodiments, electrons are used as signal charges, but the radiation detector may use holes as signal charges. When holes are used as signal charges, the P-type semiconductor region may be replaced with an N-type semiconductor region, and the N-type semiconductor region may be replaced with a P-type semiconductor region.

[0015] [Embodiment 1] A radiation detector according to a first embodiment will be described with reference to Fig. 1 to Fig. 3. Fig. 1(a) is a diagram showing an example of a radiation detector in this embodiment. The radiation detector 1 uses a semiconductor substrate such as silicon as a substrate, and has a pixel region 2, a peripheral circuit region 3, and a first buffer region (first intermediate region) 4 disposed adjacent to the peripheral circuit region 3 and between the pixel region 2 and the peripheral circuit region 3. The pixel region 2 has a plurality of pixels, and the peripheral circuit region 3 has a signal processing circuit that processes signals from the plurality of pixels.

[0016] In this embodiment, the first buffer region 4 is disposed so as to surround the periphery of the pixel region 2. For example, a large number of pixels are arranged two-dimensionally in the pixel region 2. Each pixel accumulates electric charges generated by irradiated radiation, and outputs a pixel signal corresponding to the amount of accumulated electric charges.

[0017] Fig. 1(b) is a block diagram showing an example of the configuration of a portion of the radiation detector 1. The portion of the radiation detector 1 has a pixel array 501 in which the pixels shown in Fig. 1 are arranged in a two-dimensional matrix, a vertical scanning circuit 502, vertical signal lines VL, a column circuit 504, a DFE 505, and a timing generator 506. Here, DFE is an abbreviation for Digital Front End.

[0018] The vertical scanning circuit 502 selects pixel rows from which signals are to be output from the pixel array 501 and sequentially operates the pixel rows by controlling the SEL voltage or the RES voltage. A signal (pixel signal) is input from a pixel selected by the vertical scanning circuit 502 to a vertical signal line VL. The readout circuit 504 processes a signal input from a vertical signal line 503. The DFE 505 outputs the signal input from the readout circuit 504 to the outside of the radiation detector 1. The timing generator 506 controls the timing of the circuit operations of the vertical scanning circuit 502 and the readout circuit 504.

[0019] Although FIG. 1(b) shows a radiation detector 1 having a pixel array 501 arranged in a two-dimensional matrix, the radiation detector of this embodiment may have a pixel region in which a plurality of pixels 1C are arranged in a one-dimensional straight line, depending on the application.

[0020] In this embodiment, the pixel region 2 may include only effective pixels, and if the radiation detector 1 has ineffective pixels and dummy pixels in addition to effective pixels, the pixel region 2 is deemed to include all of these pixels.

[0021] The peripheral circuit region 3 has a signal processing circuit that processes signals from the pixels. The signal processing circuit has at least one of a vertical scanning circuit 502, a readout circuit 504, a DFD 505 which is a signal output circuit, and a timing generator 506.

[0022] The vertical scanning circuit 502 outputs control signals to sequentially drive the pixels in the pixel region 2 row by row. The readout circuit 504 may include a column amplifier, a correlated double sampling (CDS) circuit, an adder circuit, an A / D conversion circuit, etc. Pixel signals are read out from the pixels in the row selected by the vertical scanning circuit 502 via vertical signal lines and input to the A / D conversion circuit of the readout circuit.

[0023] The pixel signal input to the A / D conversion circuit is converted from an analog signal to a digital signal.

[0024] The signal output circuit transmits the digital signal output from the A / D conversion circuit as an image signal to an external device in a predetermined manner. The timing generator 506 receives a control signal from the external device and transmits timing signals to the vertical scanning circuit 502, the readout circuit 504, and the DFD 505 (signal output circuit) to control the operation of each circuit.

[0025] A shielding member (not shown) is provided in the radiation detector 1, and radiation is irradiated to the pixel region 2 through an opening provided in the shielding member. The peripheral circuit region 3 is shielded from radiation by the shielding member. The first buffer region 4 is a region that is arranged between the pixel region 2 and the peripheral circuit region 3, taking into consideration variations in the positioning of the shielding member and the spread of radiation that may wrap around from the opening in the shielding member into the peripheral circuit region 3.

[0026] Considering the scattering of radiation within the semiconductor substrate 10, the distance between the pixel region 2 and the peripheral circuit region 3 is preferably 200 um or more. Also, considering the transmission speed of pixel signals and control signals between the pixel region 2 and the peripheral circuit region 3, the distance is preferably 2000 um or less. A more detailed configuration of the first buffer region 4 will be described later.

[0027] An example of each pixel in the pixel region 2 is shown in Fig. 2. Each pixel has a detection diode D1, which is a radiation detection element, and a transistor that outputs a signal according to the charge accumulated in the radiation detection element. In the following, an example is shown in which the charge accumulated in the detection diode D1, which is a radiation detection element, is electrons. In addition, in this embodiment, an example is shown in which all the transistors provided in the pixel are N-type transistors.

[0028] On the other hand, the charge accumulated by the detection diode D1 may be a hole, in which case the pixel transistor may be a P-type transistor. In other words, the definition of the conductivity type used in the following description can be changed depending on the polarity of the charge treated as a signal.

[0029] 2, a detection diode D1, which is a photoelectric conversion unit, is provided in a semiconductor substrate 10, and the cathode of the detection diode D1 is connected to the source of the reset transistor TR1 and the gate of the amplification transistor TR2. The anode of the detection diode D1 is connected to an impurity region in the semiconductor substrate 10 to which a GND potential is supplied.

[0030] The drain of the reset transistor TR1 is connected to a power supply voltage VRES, and the power supply voltage VRES can be written to the cathode of the detection diode D1 via the reset transistor TR1. The drain of the amplification transistor TR2 is connected to a power supply voltage VDD. The potential of the power supply voltage VRES and the potential of the power supply voltage VDD may be the same potential.

[0031] The source of the amplification transistor TR2 is connected to the vertical signal line VL via the selection transistor TR3. A reset signal PRES is input to the gate of the reset transistor TR1, and a selection signal PSEL is input to the gate of the selection transistor TR3.

[0032] A current source (not shown) is connected to the vertical signal line VL. When the selection signal PSEL becomes active, the selection transistor TR3 is turned on. This causes a current to be supplied from the current source to the amplification transistor TR2. A source follower circuit is formed by the power supply voltage VDD, the amplification transistor TR2, and the current source (not shown) connected to the vertical signal line VL.

[0033] By forming this source follower circuit, the amplifying transistor TR2 outputs a signal based on the potential of the cathode of the detection diode D1, that is, a signal corresponding to the charge accumulated in the detection diode D1, to the vertical signal line VL via the transistor TR3.

[0034] The pixel of the present embodiment may be a pixel having three transistors as shown in Fig. 2. Alternatively, the pixel may have four transistors, with a transfer transistor provided in the electrical path between the detection diode D1 and the gate of the amplification transistor TR2. Furthermore, the pixel may have a so-called global shutter structure, further including a memory and a second transfer transistor for transfer between the transfer transistor and the gate of the amplification transistor RR2.

[0035] Fig. 3 is a cross-sectional view of the pixel region 2, the peripheral circuit region 3, and a part of the first buffer region 4 in this embodiment taken along the line P-P' in Fig. 1. In this embodiment, an example is shown in which an insulating layer 16 is disposed on the semiconductor substrate 10 in the pixel region 2, the peripheral circuit region 3, and the first buffer region 14. In this example, the insulating layer 16 is in contact with the semiconductor substrate 10.

[0036] The pixel region 2 has a detection diode D1 which is a radiation detection element, and a transistor 22 configured to output a signal according to the charge accumulated in the detection diode D1. The transistor 22 has an insulating layer 16 arranged on a semiconductor substrate 10 as a gate insulating film, and a conductive layer 11A having polysilicon arranged on the insulating layer 16 as a gate electrode. The detection diode D1 is composed of a second impurity region 24 of a first conductivity type which is a so-called pixel well, and a third impurity region 23 arranged in the second impurity region 24 and having a second conductivity type different from the first conductivity type.

[0037] The peripheral circuit region 3 has transistors that configure a signal processing circuit, such as the transistor 25 shown in Fig. 3. The transistor 25 is also disposed on the insulating layer 16, with the insulating layer 16 serving as a gate insulating film, and has a conductive layer 11B having polysilicon as a gate electrode.

[0038] The first buffer region 4 has a first conductivity type first impurity region 18, and a conductive layer 11 that is arranged on the semiconductor substrate 10 in contact with the insulating layer 16 and is formed from the same layer as the conductive layers 11A and 11B. The conductive layer 11 is arranged in the first buffer region 4 as a dummy conductive layer, not for applying a voltage or supplying a current to other elements, but for improving the flatness of an interlayer insulating layer arranged on the conductive layer 11.

[0039] Fig. 4 is a diagram illustrating the first buffer region 4 in this embodiment. Fig. 4(a) is a plan view of an example of the radiation detector 1, and for convenience of explanation, the first wiring layer 17 is not shown. Fig. 4(b) is a plan view illustrating the first wiring layer 17 in the configuration of Fig. 4(a), and Fig. 4(c) is a cross-sectional view taken along line A-A' in Fig. 4(b).

[0040] In the first buffer region 4 shown in Figures 4(a) and 4(c), a first impurity region 18, which is a first well, is formed in a semiconductor substrate 10, and insulators 12 are arranged in a lattice pattern on the first impurity region 18. The insulators 12 are formed, for example, using silicon oxide, and can be fabricated in the same process as the insulator element isolation portion of the transistor using LOCOS or STI. In this embodiment, the insulators 12 may be at least one of LOCOS and STI, and therefore the first buffer region 4 may have both the LOCOS insulators 12 and the LTI insulators 12.

[0041] Here, LOCOS is an abbreviation for Local Oxidation of Silicon, and STI is an abbreviation for shallow trench isolation.

[0042] Since the insulator isolation parts of the transistors in the pixel region 2 and the peripheral circuit region 3 are also generally arranged in a lattice pattern, the insulators and the insulator isolation parts can be arranged in a lattice pattern throughout the radiation detector. This stabilizes the manufacturing conditions within the surface of the semiconductor substrate 10, making it possible to suppress formation defects of LOCOS and STI. This ensures the flatness of the interlayer insulating layer 14 when the interlayer insulating layer 14 is flattened by CMP, making it possible to suppress a decrease in manufacturing yield.

[0043] When the insulator 12 is formed by STI, the insulator is planarized by CMP, so that the area density of the insulator 12 is preferably 75% or less. The thickness of the insulator 12 is preferably 100 nm to 500 nm.

[0044] Moreover, the conductive layer 11, which is a dummy conductive layer (dummy pattern), is disposed in a region above the first impurity region 18 in a portion where there is no insulator 12. As described above, the conductive layer 11 is in the same layer as the gate electrode of the transistor, and is formed in the same process using, for example, polysilicon.

[0045] An insulating layer 16 that functions as a gate insulating film for transistors in the pixel region 2 and the peripheral circuit region 3 is disposed between the conductive layer 11 and the first impurity region 18. The thickness of the insulating layer 16 is preferably less than 100 nm. By forming the conductive layer 11 into a small pattern arranged in an island shape, antenna damage caused by charge-up during etching in the manufacturing process can be suppressed.

[0046] By setting the area of ​​the conductive layer 11 to the desired area density, when performing CMP on the interlayer insulating layer 14 on the conductive layer 11, the difference in thickness between the interlayer insulating layer in the pixel region 2 and the interlayer insulating layer in the peripheral circuit region 3 can be reduced, improving the manufacturing yield.

[0047] Here, the area density of the conductive layer 11 refers to the ratio of the area of ​​the conductive layer 11 to the area of ​​one repeat unit of the region having the conductive layer 11 in the plan view shown in Fig. 4(a). For example, Fig. 4(a) shows a region having 12 repeat units, and the area density of the conductive layer 11 is the ratio of the area of ​​one of the conductive layers 11 to the area of ​​the region of this one repeat unit. In the present disclosure, the area density of the member A refers to the ratio of the area of ​​the member A to the area of ​​one unit of the repeat unit of the region including the member A in the plan view.

[0048] The conductive layer 11 and the gate electrode of the transistor disposed in the pixel region 2 do not need to have the same shape and size, and may have different shapes and sizes according to the requirements of each.

[0049] In the pixel region 2, the volume of the detection diode D1 per pixel can be increased and the sensitivity can be improved by reducing the area occupied by the transistor. In this case, the gate electrode of the transistor also becomes smaller, and the area density of the gate electrode in the pixel region 2 becomes low.

[0050] On the other hand, since the detection diode D1 is not arranged in the first buffer region 4, there is no restriction on the size of the conductive layer 11 (first conductive layer). On the other hand, when the area density of the gate electrodes in the pixel region 2 is small, the area density of the first conductive layer 4 in the first buffer region 4 is increased, so that the flatness of the interlayer insulating layer 14 can be further improved in the CMP process for forming the interlayer insulating layer 14.

[0051] Therefore, in a plan view from a direction perpendicular to the surface of the semiconductor substrate 10 on which the conductive layer 11 is disposed, it is preferable that the area of ​​the conductive layer 11 disposed in the first buffer region 4 is larger than the area of ​​the gate electrode of the transistor in the pixel region 3. For example, it is preferable that the area of ​​the conductive layer 11 is at least twice the area of ​​the gate electrode of the transistor. In this embodiment, the area of ​​the conductive layer 11 is about 36 times the area of ​​the gate electrode of the transistor 22 disposed in the pixel region 3. This can improve the flatness of the conductive layer 11 and the interlayer insulating layer 14 disposed on the transistor in the pixel region 2.

[0052] The area density of the conductive layer 11 is preferably 5% to 70%. Also, in a cross-sectional view, the insulator 12 tends to be higher than the upper surface of the semiconductor substrate 10. Therefore, by disposing the conductive layer 11 in a portion of the semiconductor substrate 10 that is not covered with the insulator 12, it is possible to advantageously reduce unevenness of the base of the interlayer insulating layer 14 when the interlayer insulating layer 14 is planarized by CMP.

[0053] A first wiring layer 17 is disposed on the conductive layer 11 via an interlayer insulating layer 14, and the conductive layer 11 and the first wiring layer 17 are connected via a plug 13. The first wiring layer 17 is given a potential such as a ground potential or a potential of a power source used in the pixel region 2 or the peripheral circuit region 3, and therefore the conductive layer 11 is also given a potential. Therefore, even if the conductive layer 11 is irradiated with radiation and charges up, the charges can be discharged. This makes it possible to suppress breakdown of the insulating layer 16 due to charging up of the conductive layer 11 and a decrease in radiation detection performance due to an increase in dark current.

[0054] The potential applied to the first impurity region 18 may be any potential, such as the ground or the power supply used in the pixel region 2 or the peripheral circuit region 3, so long as it is a predetermined potential. In the first buffer region, the insulating layer 16 is sandwiched between the first impurity region 18 and the conductive layer 11. Therefore, when the conductive layer 11 is in a floating state, that is, when it is not connected to anything and no potential is supplied, if radiation hits the conductive layer 11 and the conductive layer 11 charges up, an unexpected electric field is applied to the insulating layer 16 by the first impurity region 18 and the conductive layer 11. Furthermore, the strength of the electric field is not constant and is difficult to predict.

[0055] Therefore, when radiation hits the conductive layer 11 in a floating state, the conductive layer 11 may be charged up, causing a dielectric breakdown of the insulating layer 16 .

[0056] However, by configuring the radiation detector 1 so that a predetermined potential (potential I) is supplied to the conductive layer 11, it is possible to prevent the conductive layer 11 from being charged up by radiation, and therefore it is possible to prevent the insulation layer 16 from being broken down.

[0057] Furthermore, by supplying the same potential to the conductive layer 11 as to the first impurity region 18, the electric field applied to the insulating layer 16 in the first buffer region 4 is relaxed and theoretically becomes zero. Therefore, the generation of dark current due to charge accumulation in the insulating layer 16 can be more effectively suppressed, and as a result, noise signals due to the dark current can be suppressed.

[0058] Furthermore, when the potential of the first impurity region 18 in the first buffer region 4 is set to the ground potential, holes generated in the insulating film 16 and the semiconductor substrate 10 due to radiation can be discharged. This further reduces the effect of dark current on detection performance. Also, the potential of the impurity region (well) arranged in the adjacent pixel region 2 can be stabilized.

[0059] On the other hand, when the potential of the first impurity region 18 in the first buffer region 4 is set to the potential of the power supply, it is possible to collect electrons generated by radiation irradiation. This makes it possible to suppress the effect of noise on the pixel signals in the pixel region 2 and to suppress malfunctions and latch-ups in the peripheral circuit region 3 caused by electrons sneaking in.

[0060] When the first impurity region 18 is a P-type semiconductor, it is preferable to apply a ground potential to the first impurity region 18. When the first impurity region 18 is an N-type semiconductor, it is preferable to apply a power supply potential higher than the ground potential to the first impurity region 18.

[0061] In order to make the first impurity region 18 and the conductive layer 11 have the same potential, the first wiring layer 17 and the first impurity region 18 may be connected by a plug. By implanting impurity ions having the same conductivity type as the first impurity region 18 into the surface of the first impurity region 18 to which the plug is connected, the connection resistance can be reduced and noise due to potential fluctuations can be suppressed.

[0062] Also, a configuration may be adopted in which a wiring (not shown) is connected to the first impurity region 18 to share a predetermined potential, and the first wiring layer 17 is connected to another wiring that supplies the same potential.

[0063] 3(b), the first wiring layer 17 is arranged in a lattice pattern. The desired area density can be set by adjusting the wiring width, so that when CMP is performed on the interlayer insulating layer on the first wiring layer 17, the difference in film thickness between the interlayer insulating layer in the pixel region 2 and the peripheral circuit region 3 can be reduced, improving the manufacturing yield. The area density of the first wiring layer 17 is preferably 10% to 85%.

[0064] The material constituting the interlayer insulating layer 14 may be, for example, silicon oxide or BPSG (Boro-Phospho-Silicate Glass). In addition, PSG (Phosphorous Silicate Glass), BSG (Boro-Silicate Glass), silicon nitride, or silicon carbide may be used. The material constituting the wiring layer or plug may be, for example, a conductive material such as copper, aluminum, tungsten, tantalum, titanium, polysilicon, or an alloy thereof.

[0065] If one or more wiring layers are disposed on the first wiring layer 17 and any of the wirings is floating, the floating wiring will be charged up when irradiated with radiation. Then, an electric field will be generated between the floating wiring and the wiring adjacent to it, which may cause dielectric breakdown of the interlayer insulating layer between them.

[0066] Therefore, it is preferable to configure the floating wiring so that a ground potential or a potential of a power source used in the pixel region 2 or the peripheral circuit region 3 is supplied to the floating wiring. With this configuration, even if the wiring is irradiated with radiation, the generated charge can be discharged. Therefore, the destruction of the interlayer insulating layer due to charge-up can be suppressed.

[0067] Furthermore, vertical signal lines VL connected to the pixel region 2 and control signal lines such as a reset signal PRES and a selection signal PSEL may extend through the first buffer region 4. The vertical signal lines VL and the control signal lines may be formed in the first wiring layer 17 or an upper wiring layer thereof.

[0068] Note that the conductive layer 11 can be formed from, for example, the same conductive film as the gate electrode of the transistor 22 in the pixel region 2 and can have the same material. With this configuration, the number of formation steps and materials used can be reduced compared to forming the gate electrode of the transistor 22 and the conductive layer 11 in separate steps, and productivity can be improved. However, the radiation detector 1 of the present disclosure is not limited to this configuration. The transistor 22 and the conductive layer 11 in the pixel region 2 may each be formed in separate steps.

[0069] In the present embodiment, the conductive layer 11 is configured to be disposed on the first impurity region 18 via the insulating layer 16, but a part of the conductive layer 11 may be disposed on the insulator 12. Even in this case, it is possible to suppress the dielectric breakdown of the insulating layer 16 due to charge-up and the generation of dark current due to charge accumulation in the insulating film, as described in the present embodiment.

[0070] As described above, the radiation detector 1 of this embodiment includes the first buffer region 4, and can ensure a margin for aligning the shielding member. Furthermore, since the first buffer region 4 includes the conductive layer 11 as a dummy conductive layer, the difference in height of the interlayer insulating layer between the pixel region 2 and the peripheral circuit region 3 and the first buffer region 4 can be reduced, and flatness can be improved.

[0071] The conductive layer 11 in the first buffer region 4 is connected to the first wiring layer 17 via the plug 13, and is given a predetermined potential. Therefore, even if radiation is irradiated, charge in the conductive layer 11 can be discharged, so that destruction of the insulating layer 16 due to charge-up can be suppressed. In addition, a decrease in radiation detection performance due to an increase in dark current can be prevented.

[0072] Furthermore, when the conductive layer 11 and the first impurity region 18 are at the same potential, the electric field applied to the insulating layer 16 is relaxed, so that it is possible to more effectively suppress the dielectric breakdown of the insulating layer 16. Also, it is possible to effectively suppress the generation of dark current caused by charge accumulation in the insulating layer 16 due to deterioration of the insulating layer 16, and as a result, it is possible to suppress noise signals due to dark current.

[0073] [Embodiment 2] The radiation detector 1 according to the second embodiment will be described with reference to Figures 5(a) to 5(c). Note that a description of the same configuration as in the first embodiment will be omitted.

[0074] 1 in the first embodiment, the radiation detector 1 in the present embodiment includes a pixel region 2, a peripheral circuit region 3, and a first buffer region 4 disposed between the pixel region 2 and the peripheral circuit region 3. The first buffer region 4 is disposed so as to surround the periphery of the pixel region 2.

[0075] Figures 5(a) to (c) are diagrams for explaining the first buffer region 4 in this embodiment. Figure 5(a) is a plan view of an example of the radiation detector 1, and for convenience of explanation, the first wiring layer 17 is not shown. Figure 5(b) is a plan view illustrating the first wiring layer 17 in the configuration of Figure 5(a), and Figure 5(c) is a cross-sectional view taken along line B-B' in Figure 5(b).

[0076] 5(a) and 5(c), a first impurity region 18 is formed in a semiconductor substrate 10, and a plurality of insulators 12, which are formed simultaneously with the insulator element isolation portions of the pixel region 2 and the peripheral circuit region 3, are arranged in an island shape on the first impurity region 18. In addition, a conductive layer 11 is arranged on the insulator 12. FIG. 5(c) shows an example of a configuration in which an insulating layer 16 is arranged between the conductive layer 11 and the insulator 12, but the insulating layer 16 may be omitted.

[0077] In FIG. 5(b), similarly to the first embodiment, the first wiring layer 17 is arranged in a lattice pattern, and the planarization of CMP can be ensured by adjusting the wiring width to adjust the desired area density.

[0078] As in the first embodiment, the area density of the insulator 12 and the conductive layer 11 can be adjusted to ensure flatness in CMP.

[0079] Also, similar to the first embodiment, a first wiring layer 17 is disposed on the conductive layer 11 via an interlayer insulating layer 14, and the conductive layer 11 and the first wiring layer 17 are connected via a plug 13. A potential is applied to the first wiring layer 17, and therefore a potential is also applied to the conductive layer 11. Therefore, similar to the first embodiment, even if radiation is irradiated, charge can be discharged, and therefore it is possible to suppress the destruction of the insulator 12 and the insulating layer 16 due to charge-up and the deterioration of imaging performance due to an increase in dark current. Also, the generation of dark current can be suppressed.

[0080] Furthermore, by supplying the same potential to the first impurity region 18 and the conductive layer 11, the electric field applied to the insulator 12 and the insulating layer 16 in the first buffer region 4 is relaxed. This makes it possible to suppress the generation of dark current caused by charge accumulation in the insulator 12 and the insulating layer 16, and as a result, makes it possible to suppress noise signals caused by the dark current.

[0081] As described above, the radiation detector 1 of this embodiment includes the first buffer region 4, and provides the effect of improving flatness, similar to embodiment 1. In addition, a predetermined potential (first potential) is supplied to the conductive layer 11 of the first buffer region 4, which provides the effects of suppressing dielectric breakdown of the insulator 12 and the insulating layer 16, and suppressing dark current.

[0082] Furthermore, in this embodiment, an insulator 12 is disposed between the conductive layer 11 and the first impurity region 18. Since the insulator 12 is thicker than the insulating layer 16, the electric field applied between the conductive layer 11 and the first impurity region 18 is relaxed more than in the configuration of the first embodiment, and noise signals caused by dark current due to the deterioration of the insulator 12 and the insulating layer 16 can be further suppressed.

[0083] [Embodiment 3] The radiation detector 1 according to the third embodiment will be described with reference to Fig. 6. Note that the description of the same configuration as in the first embodiment will be omitted as appropriate.

[0084] The radiation detector 1 in this embodiment, similar to FIG. 1 in embodiment 1, comprises a pixel region 2, a peripheral circuit region 3, and a first buffer region 4 arranged between the pixel region 2 and the peripheral circuit region 3, and the first buffer region 4 is arranged to surround the pixel region 2.

[0085] Figures 6(a) to (c) are diagrams for explaining the first buffer region 4 in this embodiment. Figure 6(a) is a plan view of an example of the radiation detector 1, and for convenience of explanation, the first wiring layer 17 is not shown. Figure 6(b) is a plan view illustrating the first wiring layer 17 in the configuration of Figure 6(a). Figure 6(c) is a cross-sectional view taken along line CC' in Figure 6(b).

[0086] 6(a) and 6(c), similarly to the first embodiment, a first impurity region 18 is formed in a semiconductor substrate 10, and an insulator 12 is arranged in a lattice pattern on the first impurity region 18. Also, similarly to the second embodiment, a conductive layer 11 is arranged on the insulator 12.

[0087] This embodiment differs from the first and second embodiments in that the conductive layer 11 is arranged such that the longitudinal direction of the conductive layer 11 is aligned along both the first direction of the lattice of the insulator 12 and the second direction intersecting with the first direction. By arranging the conductive layer 11 so as to surround the first impurity region 18 surrounded by the insulator 12 in this manner, the area of ​​the conductive layer 11 can be secured, and the area density can be easily adjusted.

[0088] Also in this embodiment, in plan view from a direction perpendicular to the surface of the semiconductor substrate 10 on which the conductive layer 11 is disposed, the area of ​​the conductive layer 11 disposed in the first buffer region 4 is preferably larger than the area of ​​the gate electrode of the transistor in the pixel region 3. In this embodiment, the area of ​​the conductive layer 11 is about 10 times larger than the area of ​​the gate electrode of the transistor 22 disposed in the pixel region 3. Here, the area of ​​one conductive layer 11 is compared with the area of ​​the gate electrode of the transistor 22 in plan view.

[0089] 6, the first buffer region 4 has a configuration in which regions of repeating units having substantially the same configuration are repeatedly arranged. In such a configuration, when a plurality of conductive layers 11 are arranged in one repeating unit region, it is preferable that the area of ​​one of the conductive layers 11 arranged in the first buffer region 4 is larger than the area of ​​the gate electrode of the transistor in the pixel region 3 in the plan view. This can improve the flatness of the interlayer insulating layer 14 arranged on the conductive layer 11 and the transistor in the pixel region 2.

[0090] 6(c) shows a configuration in which a wiring layer 17A is disposed on the first wiring layer 17 with an interlayer insulating layer sandwiched therebetween, and a wiring layer 17B is disposed on top of that with an interlayer insulating layer sandwiched therebetween. A configuration can be used in which a potential (second potential) such as a ground or a power supply used in the pixel region 2 or the peripheral circuit region 3 is supplied to the wiring layer 17A and the wiring layer 17B. Even if the wiring layer 17A and the wiring layer 17B have island-shaped parts, they can be connected to other wiring via the plug 13A so that the island-shaped wiring layer 17A and the wiring layer 17B do not become floating.

[0091] In this way, even when island-shaped wiring layers 17A and 17B are present on the first wiring layer 17, a configuration in which a potential is supplied to the wiring layers can be used to discharge the charges generated even when the wiring layers are irradiated with radiation. This makes it possible to suppress the destruction of the interlayer insulating layer due to charge-up. Although not illustrated in the first and second embodiments, when an island-shaped wiring layer is similarly present, a similar effect can be obtained by configuring the wiring layers to be supplied with a potential.

[0092] [Embodiment 4] The radiation detector 1 according to the fourth embodiment will be described with reference to Fig. 7. Note that a description of the same configuration as in the first embodiment will be omitted.

[0093] In the radiation detector 1 of embodiment 1, as shown in Fig. 1, the first buffer region 4 is disposed so as to surround the periphery of the pixel region 2, but it does not necessarily have to surround all sides of the pixel region 2. As in the radiation detector 1 of this embodiment shown in Fig. 7, the first buffer region 4 may be disposed partially between the pixel region 2 and the peripheral circuit region 3, and the structure thereof can be appropriately selected and combined from the configurations shown in the above-mentioned embodiments 1 to 3. Even in this case, it is possible to obtain the effect of fixing the potential of the dummy conductive layer in the buffer region, which is an effect of this embodiment.

[0094] In this embodiment, it is preferable to dispose circuits and components that are insensitive to radiation exposure in the portions where the first buffer regions 4 are not connected, that is, in the peripheral circuit regions 3 near the four corners of the pixel region 2 in FIG.

[0095] [Embodiment 5] The radiation detector 1 according to the fifth embodiment will be described with reference to Fig. 8, Fig. 9(a), Fig. 9(b), Fig. 9(c), Fig. 10(a), and Fig. 10(b). Note that a description of the same configuration as that of the first embodiment will be omitted.

[0096] 8 is a diagram showing an example of a radiation detector 1 in this embodiment. The radiation detector 1 includes a pixel region 2, a peripheral circuit region 3, and a first buffer region (first intermediate region) 4 and a second buffer region (second intermediate region) 5 arranged between the pixel region 2 and the peripheral circuit region 3. The first buffer region 4 is arranged so as to surround the periphery of the pixel region 2, and the second buffer region 5 is arranged so as to surround the periphery of the first buffer region 4.

[0097] 9(a) to 9(c) are diagrams illustrating the boundary between the first buffer region 4 and the second buffer region 5 in this embodiment. The radiation detector 1 of this embodiment has a semiconductor substrate 10 made of silicon or the like. FIG. 9(a) is a plan view of an example of a portion of the radiation detector 1, and for ease of explanation, the first wiring layer 17 and the second wiring layer 20 are not shown. FIG. 9(b) is a plan view illustrating the first wiring layer 17 and the second wiring layer 20 in the configuration of FIG. 9(a). FIG. 9(c) is a cross-sectional view taken along line DD' in FIG. 9(b).

[0098] 9(a) and 9(c), insulators 12 are arranged in a lattice pattern as in the first embodiment, but are different in that wells (conductivity types of impurity regions) are separated between the first buffer region 4 and the second buffer region 5. In the semiconductor substrate 10, a first impurity region 18 is arranged in the first buffer region 4, and a second impurity region 21 is arranged in the second buffer region 5.

[0099] The conductive layer 11 is disposed on the first impurity region 18 in a region where the insulator 12 is not disposed. In addition, the conductive layer 19 (second conductive layer) functioning as a second dummy conductive layer (second dummy pattern) is disposed on the second impurity region 21 in a region where the insulator 12 is not disposed.

[0100] A first wiring layer 17 is disposed on the conductive layer 11 with an interlayer insulating layer 14 interposed therebetween, and the conductive layer 11 and the first wiring layer 17 are connected via a plug 13. A second wiring layer 20 is disposed on the conductive layer 19 with an interlayer insulating layer 14 interposed therebetween, and the conductive layer 19 and the second wiring layer 20 are connected via the plug 13.

[0101] The conductive layer 11 and the conductive layer 19 can be formed from the same conductive film and have the same material as, for example, the gate electrode of the transistor 22 in the pixel region 2. With this configuration, the number of formation steps and materials used can be reduced compared to forming the gate electrode of the transistor 22, and the conductive layer 11 and the conductive layer 19 in separate steps, thereby improving productivity.

[0102] However, the radiation detector 1 of the present disclosure is not limited to this configuration. The gate electrode of the transistor 22 in the pixel region 2 and the conductive layer 11 and conductive layer 19 may be formed in separate processes, or any two of them may be formed in the same process and any one of them may be formed in a different process. Similarly, the other wiring layers may be formed from the same conductive film, or may be formed in a different process. By forming them from the same conductive film, the number of processes and the amount of material used can be reduced, and productivity can be improved.

[0103] Similarly, the interlayer insulating layer 14 arranged in the first buffer region 4 and the interlayer insulating layer 14 arranged in the second buffer region 5 may be formed in the same process or in different processes.

[0104] By setting the potential of the first impurity region 18 in the first buffer region 4 to ground, holes generated in the insulating layer 16 and the semiconductor substrate 10 due to radiation can be discharged, and the effect of dark current on detection performance can be suppressed.

[0105] Moreover, by setting the potential of the second impurity region 21 in the second buffer region 5 to the power supply potential, it is possible to collect electrons generated by radiation irradiation. This has the effect of suppressing the influence of noise on the detection signal of the pixel region 2. In addition, it is possible to suppress malfunctions such as latch-up of the peripheral circuit caused by electrons generated in the pixel region 2 leaking into the peripheral circuit region 3.

[0106] Conversely, the potential of the first impurity region 18 in the first buffer region 4 may be the power supply potential, and the potential of the second impurity region 21 in the second buffer region 5 may be the ground potential.

[0107] When the first impurity region 18 is a P-type semiconductor and the second impurity region 21 is an N-type semiconductor, it is preferable to supply the first impurity region 18 with a ground potential and to supply a power supply potential higher than the ground potential to the second impurity region 21. When the first impurity region 18 is an N-type semiconductor and the second impurity region 21 is a P-type semiconductor, it is preferable to supply the first impurity region 18 with a power supply potential higher than the ground potential and to supply the second impurity region 21 with the ground potential.

[0108] By supplying such a potential, even if an unexpected charge is generated in the semiconductor substrate 10, it can be quickly discharged. Therefore, it is possible to suppress the influence of noise on the detection signal of the pixel region 2. In addition, it is possible to suppress malfunctions such as latch-up of the peripheral circuit caused by electrons generated in the pixel region 2 leaking into the peripheral circuit region 3.

[0109] 10(a) and 10(b) are diagrams for explaining the pixel region 2, the first buffer region 4, and the second buffer region 5. FIG. 10(a) is a plan view of an example of a portion of the radiation detector 1, and for ease of explanation, the first wiring layer 17, the second wiring layer 20, and the wiring layer of the pixel region 2 are not shown. FIG. 10(b) is a cross-sectional view taken along line EE' in FIG. 10(a). Here, an example is shown in which the first buffer region 4 and the second buffer region 5 have the same configuration as those shown in FIG. 8.

[0110] 10(a) and 10(b), a transistor 22 and a detection diode D1 are disposed in the pixel region 2. The detection diode D1 is constituted by a second impurity region 24 and a third impurity region 23.

[0111] 10(b), a third impurity region 23 for configuring a detection diode D1 can be disposed under the transistor 22. In addition, by forming the second impurity region 24, which is a pixel well, deeply in the pixel region 2, the dimension of the detection diode D1 in the depth direction can be increased. With these configurations, the volume of the detection diode D1 can be increased, thereby increasing the sensitivity of the radiation detector 1.

[0112] 10(a), the upper surface of the second impurity region 24 of the pixel region 2 has a region where the insulator 12 is not disposed. Impurity ions are implanted into the region where the insulator 12 is not disposed, and a third impurity region 23 that constitutes the detection diode D1 is formed.

[0113] By forming the second impurity region 24 and the first impurity region 18 as semiconductor layers of the same conductivity type, the second impurity region 24 and the first impurity region 18 can be at the same potential. In this case, the first impurity region 18 can be formed in the same process as the well (impurity region) used in the peripheral circuit region 3.

[0114] As a result, the first impurity region 18 is shallower from the surface of the semiconductor substrate 10 than the second impurity region 24, and has a higher concentration of impurity ions than the second impurity region 24. A high concentration of impurity ions results in low resistance, so that unnecessary electrons generated in the first impurity region 18 by radiation irradiation can be collected more quickly. Therefore, potential fluctuations in the first impurity region 18 can be suppressed, and the potential of the second impurity region 24 can be kept more stable.

[0115] Furthermore, when the transistor 22 arranged in the pixel region 2 is an N-type transistor as shown in FIG. 2, the second impurity region 24, which is the well of the pixel region 2, and the first impurity region 18 of the first buffer region 4 are P-type semiconductor regions and are supplied with a ground potential.

[0116] By making the first impurity region 18 a P-type semiconductor region and setting it to ground potential, even if holes are generated in the insulating layer 16 of the first buffer region 4 or in the semiconductor substrate 10 due to radiation, these holes can be discharged. This makes it possible to prevent noise due to hole-induced dark current from flowing into the detection diode D1, and suppresses the effect on the detection performance of the radiation detector 1.

[0117] On the other hand, the second impurity region 21 in the second buffer region 5 is an N-type semiconductor region, and is supplied with a power supply potential higher than the ground potential. The second impurity region 21 to which the power supply potential is applied can collect electrons even if they are generated in the insulating layer 16 or the semiconductor substrate 20 in the peripheral circuit region 3 due to irradiation with radiation. This makes it possible to prevent noise signals from being mixed into pixel signals read out from pixels in the readout circuit in the peripheral circuit region 3, and to prevent malfunctions such as latch-up in the vertical scanning circuit.

[0118] The gate electrode in the pixel region 2 may have a low gate electrode area density of 0.5% to 4% due to restrictions imposed by the arrangement of the transistor 22. Therefore, by increasing the area density of the conductive layer 11 or the conductive layer 19 to 10% to 80%, it is possible to adjust the area of ​​the gate electrode over the entire semiconductor substrate, compensating for the low gate electrode area density in the pixel region 2. This makes it possible to stably perform the etching process of the gate electrode, improve the patterning accuracy of the gate electrode, and suppress variations in the characteristics of the transistor.

[0119] In this embodiment, the first buffer region 4 and the second buffer region 5 have different well (impurity region) configurations, and the insulator 12, the conductive layer functioning as a dummy conductive layer, and the like have the configuration shown in Fig. 4 in embodiment 1. In addition to this configuration, the insulator 12, the conductive layer, and the like can also have the configuration shown in Fig. 5 in embodiment 2 or the configuration shown in Fig. 6 in embodiment 3.

[0120] In the present embodiment, the conductive layer 11, the conductive layer 19, the plug 13, the insulating layer 16, and the insulator 12 have the same shapes and arrangements in the first buffer region 4 and the second buffer region 5, but they do not necessarily have to be the same. For example, the first buffer region 4 may have the configuration shown in FIG. 4 in the first embodiment, and the second buffer region 5 may have the configuration shown in FIG. 5 in the second embodiment, and the combinations may be appropriately different.

[0121] As described above, the radiation detector 1 of this embodiment has the first buffer region 4 and the second buffer region 5, and provides the same effects as those of embodiment 1. Furthermore, by supplying different potentials to the first buffer region 4 and the second buffer region 5, it is possible to suppress both defects such as noise signals and latch-up caused by electrons, and defects such as dark current caused by holes.

[0122] For example, by supplying a ground potential to an impurity region corresponding to one of the wells of the first buffer region 4 and the second buffer region 5, holes generated in the insulating film 16 and the semiconductor substrate 10 by radiation can be discharged, and the effect of dark current on detection performance can be suppressed. In addition, the potential of the well (impurity region) arranged in the pixel region 2 can be stabilized.

[0123] At the same time, it is possible to collect electrons generated by radiation irradiation by setting the impurity region corresponding to the other well of the first buffer region 4 and the second buffer region 5 to a power supply potential higher than the ground potential. This makes it possible to suppress the effect of noise on pixel signals caused by electrons flowing into the pixel region 2, and to suppress the introduction of noise signals and malfunctions such as latch-up caused by electrons generated in the pixel region 2 leaking into the peripheral circuit region 3.

[0124] In the present embodiment, the second impurity region 24 in the pixel region 2 and the first impurity region 18 in the first buffer region 4 have the same conductivity type, but they may have different conductivity types. Also, the second impurity region 24 in the pixel region 2 and the second impurity region 21 in the second buffer region 5 may have the same conductivity type. With this configuration, it is possible to obtain the effects of suppressing the intrusion of noise signals and suppressing circuit malfunctions, similar to the fifth embodiment.

[0125] [Embodiment 6] A radiation detector 1 according to the sixth embodiment will be described with reference to Fig. 11. This embodiment is a modified example of the configuration shown in Fig. 10 of the fifth embodiment, and a description of the same configuration will be omitted.

[0126] 11, the first impurity region 18 (well) in the first buffer region 4 is formed in the same process as the second impurity region 24 in the pixel region 2. Therefore, the first impurity region 18 in the first buffer region 4 can be said to be a region in which the second impurity region 24 in the pixel region 2 extends to the first buffer region 4.

[0127] As described above, in this embodiment, the first impurity region 18, which is the first well of the first buffer region 4, is disposed to a deeper position in the semiconductor substrate 10 compared to the first impurity region 18 of the fifth embodiment. Such a configuration is effective when it is particularly desired to suppress the influence of hole generation deep in the semiconductor substrate 10. In addition, since the deep portion of the first buffer region 4 can be made to have the same potential as the second impurity region 24, it is possible to reduce the potential fluctuation of the second impurity region 24 and suppress noise.

[0128] [Embodiment 7] The radiation detector 1 according to the seventh embodiment will be described with reference to Fig. 12. Note that a description of the same configuration as in the fifth embodiment will be omitted.

[0129] In the radiation detector 1 of the fifth embodiment, as shown in Fig. 8, the first buffer region 4 and the second buffer region 5 are arranged to surround the periphery of the pixel region 2, but it is not necessary to surround all sides of the pixel region 2. In this embodiment, the first buffer region 4 and the second buffer region 5 are not arranged at the four corners of the pixel region 2. In this way, as long as the first buffer region 4 and the second buffer region 5 are arranged between the pixel region 2 and the peripheral circuit region 3 even if only partially, the same effect as in the fifth embodiment can be obtained.

[0130] [Embodiment 8] The radiation detector 1 according to the eighth embodiment will be described with reference to Fig. 13. Note that a description of the same configuration as in the fifth embodiment will be omitted.

[0131] 13 shows a configuration in which the first buffer region 4 is disposed so as to surround the pixel region 2, and the second buffer region 5 is disposed in a portion between the pixel region 2 and the peripheral circuit region 3. In FIG.

[0132] This arrangement can efficiently suppress noise or malfunction while preventing an increase in chip area. For example, if a readout circuit is provided in the peripheral circuit region 3 adjacent to the second buffer region 5, it can prevent noise signals from being mixed into pixel signals read out from the pixels, and if a vertical scanning circuit is provided, it can prevent malfunctions such as latch-up.

[0133] In the radiation detector 1 of the present disclosure, the first buffer region 4 or the second buffer region 5 may be disposed between the pixel region 2 and the peripheral circuit region 3, and is preferably disposed in a position that provides the effect of suppressing noise and malfunction of the peripheral circuits.

[0134] Additionally, other buffer regions such as a third buffer region and a fourth buffer region may be provided in addition to the first buffer region 4 and the second buffer region 5. The potential applied to the conductive layer or well (impurity region) functioning as a dummy conductive layer in such other buffer regions may be the same as or different from the potential applied to the first buffer region 4 and the second buffer region 5. This makes it possible to efficiently obtain the effect of suppressing noise and malfunction.

[0135] [Embodiment 9] In the above embodiments, a configuration example of the radiation detector 1 has been described. In the present embodiment, a radiation imaging system will be described as an example of a detection system including the radiation detector 1 of any of embodiments 1 to 8. The detection system of the present embodiment detects energy rays by irradiating an object with energy rays from an irradiation unit and detecting the energy rays emitted from the object by the irradiation with the radiation detector 1.

[0136] 14 is a detection system including an imaging unit 1101, an exposure control unit 1102, a radiation source 1103 as an energy ray irradiation unit, and a computer 1104. The imaging unit 1101 has an imaging panel 100P equipped with a pixel array. Any of the radiation detectors 1 described in the first to eighth embodiments can be used as the imaging unit 1101.

[0137] The radiation source 1103 starts irradiating radiation in accordance with an exposure command from the exposure control unit 1102. The radiation irradiated from the radiation source 1103 passes through the imaging target (subject) and enters the imaging panel 100P of the imaging unit 1101. The radiation source 1103 stops irradiating radiation in accordance with a stop command from the exposure control unit 1102.

[0138] The imaging unit 1101 is, for example, a flat panel detector used for radiography in medical image diagnosis, non-destructive testing, and the like. The imaging panel 100P of the imaging unit 1101 can be a plate-like shape with a size that matches the size of the imaging target. For example, the imaging panel 100P has 3300×2800 pixels arranged on a substrate of 550 mm×445 mm. The imaging unit 1101 may be of a direct conversion type in which radiation is converted into signal charges by detection diodes provided in a pixel array of the imaging panel 100P.

[0139] The imaging unit 1101 can use the radiation detector 1 described in any one of the embodiments 1 to 8. Here, the imaging unit 1101 includes the imaging panel 100P described above, a control unit 1105 for controlling the imaging panel 100P, and a signal processing unit 1106 for processing a signal output from the imaging panel 100P.

[0140] The imaging panel 100P has a plurality of pixels arranged in the pixel region 2 described in any one of the first to eighth embodiments. The signal processing unit 1106 may be a signal processing circuit in the peripheral circuit region 3 described in any one of the first to eighth embodiments. Although not shown here, the first buffer region 4 described in any one of the first to eighth embodiments is provided between the pixel panel 100P and the signal processing unit 1106. The imaging unit 1101 may further have a second buffer region 5.

[0141] The signal processing unit 1106 may, for example, perform A / D conversion on the signal output from the imaging panel 100P and output the signal as digital image data to the computer 1104. Furthermore, the signal processing unit 1106 may, for example, generate a stop signal for stopping the irradiation of radiation from the radiation source 1103 based on the signal output from the imaging panel 100P. The stop signal is supplied to the exposure control unit 1102 via the computer 1104, and the exposure control unit 1102 sends a stop command to the radiation source 1103 in response to the stop signal.

[0142] The control unit 1105 can be configured, for example, by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit), or a general-purpose computer with a built-in program, or a combination of all or part of these.

[0143] In the present embodiment, the signal processing unit 1106 is shown as being disposed in the control unit 1105 or as a part of the function of the control unit 1105, but is not limited thereto. The control unit 1105 and the signal processing unit 1106 may each have a different configuration. Furthermore, the signal processing unit 1106 may be disposed separately from the imaging unit 1101. For example, the computer 1104 may have the function of the signal processing unit 1106. For this reason, the signal processing unit 1106 may be included in the radiation imaging system 1100 as a signal processing device that processes a signal output from the imaging unit 1101.

[0144] The computer 1104 can control the imaging unit 1101 and the exposure control unit 1102, receive radiation image data from the imaging unit 1101, and perform processing for displaying the data as a radiation image. The computer 1104 can also function as an input unit for a user to input conditions for capturing a radiation image.

[0145] As an example, the exposure control unit 1102 has an exposure switch, and when the exposure switch is turned on by a user, it sends an exposure command to the radiation source 1103 and also sends a start notification indicating the start of radiation emission to the computer 1104. In response to the start notification, the computer 1104 notifies the control unit 1105 of the imaging unit 1101 of the start of radiation irradiation. In response to this, the control unit 1105 outputs a signal corresponding to the incident radiation in the imaging panel 100P.

[0146] [Embodiment 10] In this embodiment, a description will be given of another example of a detection system including the radiation detector 1 according to any one of embodiments 1 to 8. In this embodiment as well, in the detection system, an energy ray is irradiated from an irradiation unit to a target, and the radiation detector 1 detects the energy ray emitted from the target in response to the irradiation, thereby detecting the energy ray.

[0147] 15 shows an apparatus EQP as a detection system including a radiation detector 1200. As the radiation detector 1200, any of the radiation detectors 1 according to the first to eighth embodiments can be used.

[0148] The radiation detector 1200 has a pixel array 103 in which pixels are arranged in a matrix and a peripheral circuit region PR around the pixel array 103. Peripheral circuits (for example, a vertical scanning circuit and a column circuit section) can be provided in the peripheral circuit region PR.

[0149] The pixel array 103 can be implemented by using a plurality of pixels arranged in the pixel region 2 of any one of the first to eighth embodiments. Similarly, the peripheral circuit region PR can be implemented by using the peripheral circuit region 3 described in any one of the first to eighth embodiments. Thus, although not shown, the first buffer region 4 described in any one of the first to eighth embodiments is provided between the pixel array 103 and the peripheral circuit region PR. The radiation detector 1200 may further include a second buffer region 5.

[0150] The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical system OPT forms an image of radiation on the radiation detector 1200, and is, for example, a lens, a shutter, or a mirror. The optical system OPT may form an image of a particle beam, such as an electron beam or a proton beam, on the radiation detector 1200 depending on the type of radiation to be handled.

[0151] The control device CTRL controls the radiation detector 1200 and is, for example, an ASIC. The processing device PRCS processes signals output from the radiation detector 1200 and is a device such as a CPU or ASIC for configuring an AFE (analog front end) or DFE (digital front end). The display device DSPL is an EL display device or liquid crystal display device that displays information obtained by the radiation detector 1200 in the form of a visible image or the like.

[0152] The memory device MMRY is a magnetic device or a semiconductor device that stores information obtained by the radiation detector 1200. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine.

[0153] The device EQP displays the signal output from the radiation detector 1200 on the display device DSPL, and transmits the signal to the outside by a communication device (not shown) included in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit and arithmetic circuit included in the radiation detector 1200. The mechanical device MCHN may be controlled based on the signal output from the radiation detector 1200.

[0154] The device EQP shown in FIG. 15 may be a medical device such as an endoscope or a radiological diagnostic device, a measuring device such as a distance measuring sensor, or an analytical device such as an electron microscope.

[0155] The detection systems described above in the ninth and tenth embodiments are merely examples, and the radiation detector 1 described in the first to eighth embodiments may be applied to other detection systems.

[0156] [Other embodiments] The present invention is not limited to the above-described embodiment, and many modifications are possible within the technical spirit of the present invention. For example, the above-described different embodiments may be combined in part or in whole.

[0157] The radiation detector 1 to which the present invention can be applied is not limited to a specific type, and for example, the light receiving section that receives radiation may be either a front-illuminated type or a back-illuminated type. Also, the radiation detector may be a stacked type in which a semiconductor chip including a light receiving section and a semiconductor chip including a logic section are stacked.

[0158] The present invention includes, for example, the following configurations.

[0159] (Configuration 1) A radiation detector according to one embodiment includes a pixel region in which a plurality of pixels are arranged, a peripheral circuit region in which a signal processing circuit for processing signals from the plurality of pixels is provided, and a first intermediate region arranged between the pixel region and the peripheral circuit region. Each of the plurality of pixels includes a radiation detection element provided on a semiconductor substrate, and a transistor for outputting a signal according to charges accumulated in the radiation detection element. In the pixel region, the first intermediate region, and the peripheral circuit region, an insulating layer is arranged on the semiconductor substrate, and an interlayer insulating layer is arranged on the insulating layer. The transistor has a gate electrode provided on the insulating layer, and the first intermediate region has a first conductive layer arranged in contact with the insulating layer. The radiation detector according to one embodiment is configured such that a first potential is supplied to the first conductive layer.

[0160] (Configuration 2) The radiation detector according to configuration 1, wherein the first conductive layer comprises polysilicon.

[0161] (Configuration 3) A radiation detector according to one embodiment includes a pixel region in which a plurality of pixels are arranged, a peripheral circuit region in which a signal processing circuit for processing signals from the plurality of pixels is provided, and a first intermediate region arranged between the pixel region and the peripheral circuit region. Each of the plurality of pixels includes a radiation detection element provided on a semiconductor substrate, and a transistor having a gate electrode and outputting a signal according to charges accumulated in the radiation detection element. The first intermediate region also includes an insulating layer arranged on the semiconductor substrate, and a first conductive layer having polysilicon arranged on the insulating layer. An interlayer insulating layer is arranged on the radiation detection element, the transistor, and the first conductive layer. The radiation detector according to one embodiment is configured such that a first potential is supplied to the first conductive layer.

[0162] (Configuration 4) In the radiation detector of configuration 3, in a planar view from a direction perpendicular to the surface of the semiconductor substrate on which the first conductive layer is arranged, the area of ​​the first conductive layer is different from the area of ​​the gate electrode in one of the multiple pixels.

[0163] (Configuration 5) The radiation detector according to configuration 4, wherein, in the plan view, the area of ​​the first conductive layer is larger than the area of ​​the gate electrode of the one pixel.

[0164] (Configuration 6) The radiation detector according to configuration 4 or 5, wherein, in the plan view, the area of ​​the first conductive layer is at least twice the area of ​​the gate electrode of the one pixel.

[0165] (Configuration 7) The radiation detection device according to any one of configurations 1 to 6, further comprising a first wiring disposed on the interlayer insulating layer, the first conductive layer being connected to the first wiring.

[0166] (Configuration 8) The radiation detector according to any one of configurations 1 to 7, wherein the semiconductor substrate has a first impurity region having a first conductivity type, the first impurity region being disposed in contact with the insulating layer, and the first potential is supplied to the first impurity region.

[0167] (Configuration 9) The radiation detector of configuration 8, wherein the semiconductor substrate has a second impurity region of the first conductivity type and is disposed within the second impurity region in the pixel region. The radiation detector of this configuration has a third impurity region having a second conductivity type different from the first conductivity type, and is configured such that the first potential is supplied to the second impurity region.

[0168] (Configuration 10) In any one of configurations 1 to 9, the radiation detector according to the present invention, wherein the first potential is a ground potential.

[0169] (Configuration 11) The radiation detector according to configuration 3, wherein an insulating layer is disposed on the semiconductor substrate in the pixel region, the first intermediate region, and the peripheral circuit region. Also, in the first intermediate region, the first conductive layer is disposed on the semiconductor substrate with the insulating layer sandwiched therebetween.

[0170] (Configuration 12) In any one of configurations 1 to 9, the first intermediate region has an insulator disposed on the semiconductor substrate, and the first conductive layer is disposed on the insulator.

[0171] (Configuration 13) In configuration 12, the radiation detector wherein the insulator is at least one of local oxidation of silicon and shallow trench isolation.

[0172] (Configuration 14) A radiation detector according to any one of configurations 1 to 13, further comprising a second intermediate region between the peripheral circuit region and the first intermediate region, the second intermediate region having a second conductive layer disposed on the insulating layer, the second conductive layer being covered by the interlayer insulating layer, the second conductive layer being configured to be supplied with a second potential different from the first potential.

[0173] (Configuration 15) A radiation detector according to configuration 14, wherein the second potential is higher than the first potential.

[0174] (Configuration 16) A radiation detector according to any one of configurations 1 to 15, wherein the second potential is a power supply potential input to any one of the wirings of the signal processing circuit.

[0175] (Configuration 17) In any one of configurations 14 to 16, the radiation detector is configured such that the second intermediate region is disposed between the peripheral circuit region and the first intermediate region.

[0176] (Configuration 18) A radiation detector according to any one of configurations 1 to 17, wherein the distance between the pixel region and the peripheral circuit region is 200 μm or more.

[0177] (Configuration 19) A radiation detector according to configuration 9, wherein the first impurity region and the second impurity region are electrically connected to each other.

[0178] (Configuration 20) A detection system comprising an irradiation means for irradiating an object with an energy ray, and a radiation detector according to any one of configurations 1 to 19, wherein the radiation detector detects the energy ray traveling from the object to the radiation detector. [Explanation of symbols]

[0179] 1. Radiation detector 2 Pixel Area 3 Peripheral circuit area 4 First buffer area 10. Semiconductor Substrate 11 Conductive layer 14 Interlayer insulation layer 16 Insulating layer 22 Transistor D1 Detector diode

Claims

1. a pixel region in which a plurality of pixels are arranged; a peripheral circuit region provided with a signal processing circuit for processing signals from the plurality of pixels; a first intermediate region disposed between the pixel region and the peripheral circuit region; Each of the plurality of pixels is A radiation detection element provided on a semiconductor substrate; a transistor that outputs a signal corresponding to the charge accumulated in the radiation detection element, an insulating layer is disposed on the semiconductor substrate in the pixel region, the first intermediate region, and the peripheral circuit region, and an interlayer insulating layer is disposed on the insulating layer; the transistor has a gate electrode provided on the insulating layer; the first intermediate region has a first conductive layer disposed in contact with the insulating layer; A radiation detector, characterized in that a first potential is supplied to the first conductive layer.

2. The radiation detector of claim 1 , wherein the first conductive layer comprises polysilicon.

3. a pixel region in which a plurality of pixels are arranged; a peripheral circuit region provided with a signal processing circuit for processing signals from the plurality of pixels; a first intermediate region disposed between the pixel region and the peripheral circuit region; Each of the plurality of pixels is A radiation detection element provided on a semiconductor substrate; a transistor having a gate electrode and outputting a signal corresponding to the charge accumulated in the radiation detection element; the first intermediate region includes an insulating layer disposed on the semiconductor substrate, and a first conductive layer disposed on the insulating layer and having polysilicon; an interlayer insulating layer is disposed on the radiation detection element, the transistor, and the first conductive layer; A radiation detector, characterized in that a first potential is supplied to the first conductive layer.

4. 4. The radiation detector according to claim 1, wherein, in a plan view from a direction perpendicular to a surface of the semiconductor substrate on which the first conductive layer is disposed, an area of ​​the first conductive layer is different from an area of ​​the gate electrode in one pixel of the plurality of pixels.

5. The radiation detector according to claim 4 , wherein, in the plan view, an area of ​​the first conductive layer is larger than an area of ​​the gate electrode of the one pixel.

6. The radiation detector according to claim 4 , wherein an area of ​​the first conductive layer is equal to or larger than twice an area of ​​the gate electrode of the one pixel in the plan view.

7. The radiation detection device according to claim 1 , further comprising: a first wiring disposed on the interlayer insulating layer; and the first conductive layer being connected to the first wiring.

8. In the first intermediate region, the semiconductor substrate has a first impurity region having a first conductivity type, the first impurity region being disposed in contact with the insulating layer; 4. The radiation detector according to claim 1, wherein the first potential is supplied to the first impurity region.

9. In the pixel region, the semiconductor substrate has a second impurity region of the first conductivity type, and a third impurity region disposed in the second impurity region and having a second conductivity type different from the first conductivity type; The radiation detector according to claim 8 , wherein the second impurity region is configured to be supplied with the first potential.

10. 4. The radiation detector according to claim 1, wherein the first potential is a ground potential.

11. an insulating layer is disposed on the semiconductor substrate in the pixel region, the first intermediate region, and the peripheral circuit region; 4. The radiation detector according to claim 3, wherein in the first intermediate region, the first conductive layer is disposed on the semiconductor substrate with the insulating layer interposed therebetween.

12. 4. The radiation detector according to claim 1, wherein the first intermediate region has an insulator disposed on the semiconductor substrate, and the first conductive layer is disposed on the insulator.

13. 13. The radiation detector according to claim 12, wherein the insulator is at least one of local oxidation of silicon and shallow trench isolation.

14. a second intermediate region between the peripheral circuit region and the first intermediate region; the second intermediate region includes a second conductive layer disposed on the insulating layer; the second conductive layer is covered with the interlayer insulating layer; The radiation detector according to claim 1 , wherein the second conductive layer is configured to be supplied with a second potential different from the first potential.

15. The radiation detector of claim 14 , wherein the second potential is higher than the first potential.

16. The radiation detector according to claim 14 , wherein the second potential is a power supply potential input to any one of the wirings of the signal processing circuit.

17. The radiation detector of claim 14 , wherein the second intermediate region is disposed between the peripheral circuit region and the first intermediate region.

18. 4. The radiation detector according to claim 1, wherein a distance between the pixel region and the peripheral circuit region is 200 um or more.

19. The radiation detector according to claim 9 , wherein the first impurity region and the second impurity region are electrically connected to each other.

20. An irradiation means for irradiating an energy beam to a target; A radiation detector according to any one of claims 1 to 3, and detecting an energy ray traveling from the object to the radiation detector using the radiation detector.

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