Semiconductor device

Abstract

To provide a semiconductor device capable of reducing noise.SOLUTION: A semiconductor device 100 has a semiconductor substrate 1, an insulating layer 2 on the semiconductor substrate 1, and a resistor layer 3 buried within the insulating layer 2. A first surface region TR facing the resistor layer 3 of the semiconductor substrate 1 has a plurality of trenches 1T. If the shortest distance between the resistor layer 3 and a surface region (bottom electrode) of the semiconductor substrate 1 is d, and the area of the surface of the resistor layer 3 facing the semiconductor substrate 1 is S, and if the average dielectric constant of an insulating region is ε, the capacitor C between the resistor layer 3 and the semiconductor substrate 1 is C≤0.8×(ε×S / d).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a resistive film formed on a silicon substrate via an insulating layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 149371

[0004] [overview] The present disclosure provides a semiconductor device capable of reducing noise.

[0005] The semiconductor device disclosed herein comprises an insulating layer provided on a semiconductor substrate and a resistive layer embedded in the insulating layer, and a first surface region of the semiconductor substrate facing the resistive layer has a plurality of trenches. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing a vertical cross-sectional configuration of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a graph showing the relationship between trench depth ΔD (μm) and the rate of change in capacitance (C / C0). [Diagram 3] FIG. 3 is a diagram showing a vertical cross-sectional configuration of the trench structure. [Figure 4] FIG. 4 is a diagram showing a vertical cross-sectional configuration of the trench structure. [Diagram 5] FIG. 5 is a diagram showing the positional relationship between a plurality of resistors and a plurality of trenches (FIGS. 5(A), 5(B), 5(C), and 5(D)). [Figure 6] FIG. 6 is a diagram showing a planar configuration of the resistor chip. [Figure 7]FIG. 7 is an enlarged view of a portion of the resistor chip (the second region S2 in FIG. 6). [Figure 8] FIG. 8 is a diagram showing a vertical cross-sectional configuration of a portion taken along line AA in FIG. [Figure 9] FIG. 9 is a diagram showing a vertical cross-sectional configuration of a portion taken along line BB in FIG. [Figure 10] FIG. 10 is a diagram showing a vertical cross-sectional configuration of a portion taken along line CC in FIG. [Figure 11] 11 is a diagram showing a vertical cross-sectional configuration of a semiconductor device according to an embodiment.

[0007] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or corresponding parts in each drawing are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0008] FIG. 1 is a diagram showing a vertical cross-sectional configuration of a semiconductor device according to an embodiment.

[0009] The semiconductor device 100 includes a semiconductor substrate 1. An XYZ three-dimensional orthogonal coordinate system is set. The thickness direction of the semiconductor substrate 1 is defined as the Z-axis direction, the direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The positive direction of the Z-axis is defined as the depth direction (downward) of the semiconductor substrate 1.

[0010] The semiconductor device 100 includes an insulating layer 2 provided on a semiconductor substrate 1 and a resistive layer 3 embedded in the insulating layer 2. A first surface region TR facing the resistive layer 3 of the semiconductor substrate 1 has a plurality of trenches 1T. A capacitor (parasitic capacitor) is formed between the resistive layer 3 and the first surface region TR, sandwiching an insulating region that is a part of the insulating layer 2. The capacitance C (parasitic capacitance) of this capacitor decreases as the average distance between the resistive layer 3 and the first surface region TR increases. Since the first surface region TR has a plurality of trenches 1T, the average distance is larger compared to a case where there is no trench. Therefore, the capacitance C of the capacitor decreases. When the capacitance C of the capacitor decreases, noise caused by the capacitance C, for example, noise superimposed on the resistive layer 3, can be reduced. In addition, in the case of a circuit that transmits a signal via the resistive layer 3, when the capacitance C decreases, the signal delay caused by the capacitance C can be reduced.

[0011] A first wiring E1 (electrode) is provided on the insulating layer 2. A lower surface of the first wiring E1 is connected to an upper surface of a first embedded wiring B1 through a first via electrode V1. An upper surface of the first embedded wiring B1 is connected to a lower surface of one end of the resistance layer 3 through a second via electrode V2.

[0012] A second wiring E2 (electrode) is provided on the insulating layer 2. The lower surface of the second wiring E2 is connected to the upper surface of the second embedded wiring B2 through a third via electrode V3. The upper surface of the second embedded wiring B2 is connected to the lower surface of the other end of the resistance layer 3 through a fourth via electrode V4.

[0013] The first via electrode V1, the second via electrode V2, the third via electrode V3, the fourth via electrode V4, the first embedded wiring B1, the second embedded wiring B2, and the resistance layer 3 are embedded in an insulating layer 2. A protective film 4 is provided on the insulating layer 2 to cover the first wiring E1 and the second wiring E2.

[0014] The insulating layer 2 includes a plurality of laminated dielectric layers (first dielectric layer 2A, second dielectric layer 2B). The material of at least one layer (first dielectric layer 2A) of the plurality of dielectric layers includes silicon oxide. The material of at least one layer (second dielectric layer 2B) of the plurality of dielectric layers includes silicon nitride. In this example, the first dielectric layer 2A and the second dielectric layer 2B are alternately laminated. The silicon oxide in this example is SiO2, but the element composition ratio may be changed and other elements may be included as necessary. The silicon nitride in this example is Si3N4, but the element composition ratio may be changed and other elements may be included as necessary. In this example, the same dielectric material 2A1 as the bottom first dielectric layer 2A is buried in the trench 1T.

[0015] The interface position between the first wiring E1 and the insulating layer 2 is defined as the reference position Z0 on the substrate surface. The lower surface position of the resistive layer 3 is defined as the first position Z1. The upper surface position of the first buried wiring B1 is defined as the second position Z2. The surface position of the semiconductor substrate 1 is defined as the third position Z3. The bottom surface position of the trench 1T is defined as the fourth position Z4. The depth ΔD of the trench 1T is given by the Z-axis distance between the third position Z3 and the fourth position Z4. A parasitic capacitor without the trench 1T is composed of a lower electrode (surface region of the semiconductor substrate 1), an upper electrode (resistive layer 3), and an insulating region located between them. The reference distance d between the electrodes of this capacitor (the shortest distance between the first surface region TR and the resistive layer 3) is given by the Z-axis distance between the first position Z1 and the third position Z3. The thickness d2 of the insulating layer 2 excluding the portion embedded in the trench is given by the Z-axis distance between the reference position Z0 and the third position Z3.

[0016] The first surface region TR in which the plurality of trenches 1T are formed has a width in the X-axis direction defined by a third distance ΔX3. The width in the Y-axis direction of the first surface region TR is defined as a fourth distance ΔY4. The total area S of the first surface region TR in the XY plane TR is S TR = ΔX3 × ΔY4. The total area S of the openings of all trenches 1T in the XY plane SUM is S SUM TR ​The total area S TR Total area S for SUM The occupancy rate α of is α=S SUM / S TR In other words, S SUM = α × S TR The area of ​​the surface (XY plane) of the resistance layer 3 facing the surface of the semiconductor substrate 1 is S R The capacitance C is the area S of the resistive layer 3. R The larger it is, the greater the increase.

[0017] The material of the resistive layer 3 in this example is a resistive material having a resistivity higher than that of polysilicon. Specifically, the material of the resistive layer 3 is a material containing chromium (Cr) and silicon (Si), and is CrSi, CrSiC, or CrSiN. The resistive layer 3 can be formed by a sputtering method using a target containing a resistive material. Other materials having a high resistivity can also be used. A plating method can also be used depending on the type of material of the resistive layer 3. The material of the resistive layer 3 may be composed of a single resistive material, or a combination of multiple resistive materials. The thickness Rd of the resistive layer 3 can be 1 nm≦Rd≦5 nm. When the thickness Rd is equal to or less than the upper limit, the resistance value can be sufficiently increased, and when the thickness Rd is equal to or more than the lower limit, the resistance and strength of the resistive layer can be maintained.

[0018] When the semiconductor device 100 has a plurality of trenches 1T, after the trenches 1T are formed, a dielectric material is filled into the trenches 1T, and then the dielectric material is subjected to chemical mechanical polishing (CMP) to flatten the surface of the dielectric material 2A1. Then, an insulating layer 2 is formed thereon. The trenches 1T can be formed by etching, and the dielectric material and the insulating layer can be formed by using a sputtering method or a chemical vapor deposition (CVD) method. The structure having a plurality of trenches 1T has the advantage that the amount of dielectric material and the amount of polishing by CMP can be smaller than the case of a structure having a single recess shown in FIG. 11 described later.

[0019] The semiconductor substrate 1 may be conductive. For example, the impurity concentration of the semiconductor substrate 1 may be 5×1013 ( / cm 3 ) or more 5×10 14 ( / cm 3 ) or less. The thickness of the semiconductor substrate 1 may be 50 μm or more and 800 μm or less. The material of the semiconductor substrate 1 may be silicon (Si), but it is also possible to use a compound semiconductor such as SiC or SiGe.

[0020] The insulating layer 2 and the protective film 4 may be made of an inorganic insulator such as silicon oxide or silicon nitride.

[0021] The first wiring E1, the second wiring E2, the first embedded wiring B1, the second embedded wiring B2, and the third embedded wiring B3 described below can be made of an aluminum alloy (such as AlCu), but other electrode materials can also be used.

[0022] The first via electrode V1 and the second via electrode V2 can be made of a high melting point metal such as tungsten (W), but other electrode materials can also be used. The second via electrode V2 is located on the lower surface side of the resistance layer 3. Although the resistance layer 3 is thin, they can be easily contacted by forming the resistance layer 3 after forming the second via electrode V2.

[0023] A method for manufacturing the semiconductor device 100 will now be described.

[0024] First, a mask having openings for forming trenches is formed on the surface of the semiconductor substrate 1, and the semiconductor material in the openings is etched using the mask. A plurality of trenches 1T are formed by etching. A dielectric material is filled into the trenches 1T, and the surface is subjected to chemical mechanical polishing (CMP), and an insulating layer 2 is formed on the planarized surface. The insulating layer 2 includes a plurality of types of insulating layers. In the process of forming the first dielectric layer 2A on the upper part of the insulating layer 2, a first embedded wiring B1 and a second embedded wiring B2 are formed on the exposed insulating region by a method such as sputtering.

[0025] An insulating layer is further formed on the first buried wiring B1 and the second buried wiring B2. Then, vias (holes) of the via electrodes reaching the first and second buried wirings from the exposed surface of the insulating layer are formed by etching or the like, and the material of the via electrodes is filled in these holes. Then, a resistive layer 3 is formed by sputtering or the like so as to contact the exposed surfaces of the second via electrode V2 and the fourth via electrode V4. An insulating layer is further formed on the resistive layer 3, and vias (holes) for the first via electrode V1 and the third via electrode V3 extending downward from the exposed surface of the insulating layer are formed by etching or the like, and the material of the via electrodes is filled in these holes. The first wiring E1 and the second wiring E2 are formed on the exposed surfaces of the first via electrode V1 and the third via electrode V3, respectively. Finally, a protective film 4 is formed on the first wiring E1 and the second wiring E2 by sputtering or CVD or the like.

[0026] The structure of the trench 1T will be further explained.

[0027] FIG. 2 is a graph showing the relationship between the depth ΔD (μm) of the trench 1T and the rate of change in capacitance (C / C0).

[0028] As an example, the area S of the resistive layer 3 R and the total area S of the first surface region TR TR are equal and completely overlapped when viewed from the Z-axis direction (in a plan view). The reference distance between the electrodes of the capacitor is d=14 (μm). Regarding the capacitance C of the capacitor formed between the resistive layer 3 and the first surface region TR in the absence of a trench, the reference capacitance in the absence of a trench is C0. The rate of change (C / C0) of the capacitance C with respect to the reference capacitance C0, in other words, the capacitance (C / C0) normalized by the reference capacitance C0, decreases when a trench is formed. The graph shows the cases of trench occupancy α=0.1 (=10%), α=0.25 (=25%), α=0.5 (=50%), and α=0.75 (=75%). The normalized capacitance (C / C0) decreases as the trench occupancy α increases and as the trench depth ΔD increases.

[0029] The reference capacitance C0 of the capacitor is determined by the reference distance d (=the shortest distance between the first surface region TR and the resistive layer 3), the area S of the surface (XY plane) of the resistive layer 3 facing the surface of the semiconductor substrate 1, R , where ε is the average dielectric constant of the insulating region between the first surface region TR and the resistive layer 3, C0=ε×S R / d. As an example, the capacitance C is C = ε × S R It is given by {((1-α) / d)+(α / (d+ΔD))}.

[0030] When ΔD is 10 μm or more and the occupancy rate α is 0.5 or more, the capacitance C is 80% or less of the reference capacitance C0. That is, the relationship (C≦0.8×C0=0.8×(ε×S R / d)). Furthermore, when ΔD is 30 μm or more and the occupancy rate α is 0.75 or more, the capacitance C is 50% or less of the reference capacitance C0. In other words, the capacitance C of the capacitor satisfies the relationship (C≦0.5×C0=0.5×(ε×S R / d)) is satisfied.

[0031] As shown in the graph, the capacitance C can be 0.9×C0 or less, 0.8×C0 or less, 0.7×C0 or less, 0.6×C0 or less, or 0.5×C0 or less. If the trench is too deep, manufacturing becomes difficult, so for example, ΔD can be set to 40 (μm) or less. In this case, the capacitance C can be 0.4×C0 or more, 0.5×C0 or more, or 0.6×C0 or more. It is also possible to determine a suitable range using other data shown in the graph. Also, the reference distance d does not need to be 14 (μm), and can be, for example, 6 μm≦d≦17 μm.

[0032] 3 is a diagram showing a vertical cross-sectional configuration (XZ cross-section) of the trench structure, which shows an enlarged view of the structure in the first region S1 of FIG.

[0033] The opening width of the trench 1T in the X-axis direction is a first distance ΔX1. The width of the trench 1T can be made smaller in the depth direction (positive direction of the Z-axis). The trench 1T is filled with a dielectric material 2A1. In this example, the dielectric material 2A1 is the same as the material of the first dielectric layer 2A, which is the bottom layer. The structure of the first surface region having a plurality of trenches 1T can be modified in various ways. For example, the opening width of the trench 1T (first distance ΔX1), the interval between adjacent trenches 1T (second distance ΔX2), or the depth ΔD of the trench 1T can be changed.

[0034] An exemplary range of the first distance ΔX1 may be 0.5 μm≦ΔX1≦5 μm. If the first distance ΔX1 is smaller than the lower limit, the depth of the trench cannot be made sufficiently large, and if it is larger than the upper limit, the amount of dielectric material required for filling increases.

[0035] An exemplary range of the second distance ΔX2 may be 0.5 μm≦ΔX2≦50 μm. If the second distance ΔX2 is smaller than the lower limit, it is difficult to form a mask and perform etching, and if it is larger than the upper limit, the occupancy rate α of the trench cannot be increased sufficiently.

[0036] An exemplary range of the depth ΔD may be 5 μm≦ΔD≦40 μm. If the depth ΔD is smaller than the lower limit, a large capacitance reduction effect cannot be obtained, and if it is larger than the upper limit, it becomes difficult to manufacture the trench.

[0037] 4 is a diagram showing a vertical cross-sectional configuration (XZ cross-section) of the trench structure, which shows an enlarged view of the structure in the first region S1 of FIG.

[0038] 3, the trench 1T is different in that a second dielectric material G, such as an air gap (gas), is provided inside the dielectric material 2A1. The second dielectric material G extends along the Z-axis direction. Since the dielectric constant of the second dielectric material G, such as air, is smaller than the dielectric constant of the dielectric material 2A1, the capacitance C of the capacitor can be further reduced.

[0039] FIG. 5 is a diagram (FIG. 5(A), FIG. 5(B), FIG. 5(C), FIG. 5(D)) showing the positional relationship between multiple resistive layers (resistors) and multiple trenches. The diagram shows the positional relationship of each element in a plan view (as viewed from the Z-axis direction). In order to clarify the positional relationship, elements located above the resistive layer 3 are omitted. In either structure, the total area S of the first surface region TR (see FIG. 1) serving as the trench formation region is TR is defined by the product of the third distance ΔX3 and the fourth distance ΔY4. In this case, the occupancy rate α of the trench may satisfy, for example, the above-mentioned range of 0.1≦α≦0.7. The occupancy rate α may satisfy the range of 0.2≦α≦0.7. The occupancy rate α may satisfy the range of 0.5≦α≦0.7.

[0040] 5A shows a case where the longitudinal direction (X-axis direction) of the resistance layer 3 and the longitudinal direction (Y-axis direction) of the trenches 1T are perpendicular to each other. In a plan view, each trench 1T traverses a plurality of resistance layers 3.

[0041] The structure in Fig. 5(B) is obtained by dividing each trench 1T in Fig. 5(A) into multiple trenches. The longitudinal direction (X-axis direction) of the resistance layer 3 and the longitudinal direction (Y-axis direction) of the trenches 1T are perpendicular to each other. In a plan view, each trench 1T crosses each resistance layer 3.

[0042] 5(C) shows a case where the longitudinal direction (X-axis direction) of the resistance layer 3 coincides with the longitudinal direction (X-axis direction) of the trenches 1T. In a plan view, each trench 1T extends along each resistance layer 3.

[0043] The structure in Fig. 5(D) is obtained by dividing each trench 1T in Fig. 5(C) into multiple trenches. The longitudinal direction (X-axis direction) of the resistance layer 3 and the longitudinal direction (X-axis direction) of the trenches 1T coincide with each other. In a plan view, multiple trenches 1T overlap each resistance layer 3.

[0044] FIG. 6 is a diagram showing a planar configuration of a resistor chip that constitutes the semiconductor device 100. As shown in FIG.

[0045] The resistor chip uses a semiconductor device having the resistor described above. The resistor chip includes a resistor region RM embedded in a surface region of a substrate 10. The resistor region RM includes a plurality of resistor regions. That is, the resistor region RM includes a first resistor region RM1, a second resistor region RM2, a third resistor region RM3, and a fourth resistor region RM4. The resistor layer 3 described above (see FIG. 1) is formed in each resistor region. The planar shape of each resistor layer 3 in each resistor region can be various resistor patterns such as a spiral shape, an interdigital shape, a meandering shape, a square wave shape, a triangular wave shape, etc.

[0046] One end of the resistor pattern formed in the first resistor region RM1 is electrically connected to the first electrode pad P1 and the second electrode pad P2, and the other end is electrically connected to the third electrode pad P3 and the fourth electrode pad P4.

[0047] One end of the resistor pattern formed in the second resistor region RM2 is electrically connected to the third electrode pad P3 and the fourth electrode pad P4, and the other end is electrically connected to the fifth electrode pad P5 and the sixth electrode pad P6.

[0048] One end of the resistor pattern formed in the third resistor region RM3 is electrically connected to the fifth electrode pad P5 and the sixth electrode pad P6, and the other end is electrically connected to the seventh electrode pad P7 and the eighth electrode pad P8.

[0049] One end of the resistor pattern formed in the fourth resistor region RM4 is electrically connected to the seventh electrode pad P7 and the eighth electrode pad P8, and the other end is electrically connected to the ninth electrode pad P9 and the tenth electrode pad P10.

[0050] By selecting two desired electrode pads from each set, a resistance value according to the selection can be obtained.

[0051] FIG. 7 is an enlarged view of a portion of the resistor chip (the second region S2 in FIG. 6).

[0052] In this example, in each resistance region, a plurality of rectangular resistance layers 3 extending in the X-axis direction are aligned along the Y-axis direction, and one end of the first resistance layer 3 from the left end is electrically connected to one end of the second resistance layer 3 adjacent thereto. Similarly, one end of the third resistance layer 3 is electrically connected to one end of the fourth resistance layer 3 adjacent thereto. In other words, one end of the odd-numbered resistance layer 3 is electrically connected to one end of the even-numbered resistance layer 3 adjacent thereto. This electrical connection can be made by the third embedded wiring B3.

[0053] Similarly, although not shown in the drawing, the other end of the even-numbered resistive layer 3 can be electrically connected to the other end of the adjacent odd-numbered resistive layer 3, forming a square waveform resistive pattern as a whole in a plan view. One end of this resistive pattern is connected to the third wiring E3 (electrode).

[0054] FIG. 8 is a diagram showing a longitudinal sectional configuration (YZ cross section) of a portion taken along line AA in FIG.

[0055] The substrate 10 includes a semiconductor substrate 1 and an insulating layer 2 formed on the semiconductor substrate 1. A protective film 4 is formed on the insulating layer 2. A plurality of resistive layers 3 are embedded in the insulating layer 2. Each resistive layer 3 is connected to a third embedded wiring B3 through one or more second via electrodes V2. The third embedded wiring B3 electrically connects adjacent resistive layers 3 through the second via electrodes V2. The structures of the semiconductor substrate 1, the insulating layer 2, the resistive layer 3, and the protective film 4 are as described in FIG. 1. The first surface region TR of the semiconductor substrate 1 may include a plurality of trenches. As the structure of the trenches, for example, various structures as shown in FIG. 5 may be adopted.

[0056] FIG. 9 is a diagram showing a longitudinal sectional configuration (YZ cross section) of a portion taken along line BB in FIG.

[0057] The resistive layer 3 extends along the X-axis direction, but does not have a third buried interconnect for connection. Even in a vertical cross section in which no buried interconnect exists directly below the resistive layer 3, the first surface region TR is located directly below the resistive layer 3.

[0058] FIG. 10 is a diagram showing a longitudinal sectional configuration (XZ cross section) of a portion taken along line CC in FIG.

[0059] The resistive layer 3 extends along the X-axis direction, and an end of the resistive layer 3 is connected to the third embedded wiring B3 through one or more second via electrodes V2. A ninth electrode pad P9 is located at a position away from the end of the resistive layer 3 along the X-axis direction. The ninth electrode pad P9 is formed on the insulating layer 2, and a surface region thereof is exposed.

[0060] FIG. 11 is a diagram showing a vertical cross-sectional configuration of the semiconductor device according to the embodiment.

[0061] This semiconductor device 100 is the same as the semiconductor device shown in Fig. 1 except that a single recess 1R is formed in the first surface region TR instead of the multiple trenches in the semiconductor device shown in Fig. 1. The rest of the structure is the same as the semiconductor device shown in Fig. 1.

[0062] That is, the semiconductor device 100 includes an insulating layer 2 provided on a semiconductor substrate 1 and a resistive layer 3 embedded in the insulating layer 2, and a first surface region TR facing the resistive layer 3 of the semiconductor substrate 1 has a recess 1R. With respect to reducing the capacitance C of the parasitic capacitor, the function of the recess 1R is similar to that of the multiple trenches. With this structure as well, it is possible to reduce the capacitance C of the parasitic capacitor formed between the resistive layer 3 and the first surface region TR.

[0063] When the semiconductor device has a single recess 1R, after the dielectric material 2A1 is filled in the recess 1R, chemical mechanical polishing (CMP) is performed to planarize the surface of the dielectric material 2A1. Then, the insulating layer 2 is laminated on the dielectric material 2A1.

[0064] The configuration, materials, and numerical ranges of the above-mentioned elements can be appropriately selected and combined. Furthermore, the semiconductor device 100 having the resistive layer 3 can be applied to integrated circuits and the like in addition to the above-mentioned resistor chip.

[0065] As described above, according to the above-mentioned semiconductor device, the parasitic capacitance can be reduced, and therefore the noise can be reduced. Various embodiments of the present disclosure can be defined as the following supplementary notes [A1] to [A7].

[0066] [A1] A semiconductor device comprising: a semiconductor substrate 1; an insulating layer 2 provided on the semiconductor substrate 1; and a resistive layer 3 embedded in the insulating layer 2, wherein a first surface region TR of the semiconductor substrate 1 facing the resistive layer 3 has a plurality of trenches 1T.

[0067] [A2] A semiconductor device comprising: a semiconductor substrate 1; an insulating layer 2 provided on the semiconductor substrate 1; and a resistive layer 3 embedded in the insulating layer 2, wherein a first surface region TR of the semiconductor substrate 1 facing the resistive layer 3 has a recess 1R.

[0068] [A3] The semiconductor device according to A1 or A2, wherein a capacitor (the above-mentioned parasitic capacitor) is formed between the resistive layer 3 and the first surface region TR.

[0069] [A4] The semiconductor device according to A3, wherein a capacitance C of the capacitor satisfies the following relationship, C≦0.8×(ε×S / d), where d is the shortest distance between the first surface region TR and the resistive layer 3, S is the area of ​​the surface of the resistive layer 3 facing the semiconductor substrate 1, and ε is the average dielectric constant of an insulating region (insulating layer 2) between the first surface region TR and the resistive layer 3.

[0070] [A5] The semiconductor device according to A4, wherein a capacitance C of the capacitor satisfies the following relationship: C≦0.5×(ε×S / d).

[0071] [A6] The semiconductor device according to any one of A1 to A5, wherein a material of the resistance layer 3 contains Cr and Si.

[0072] [A7] The semiconductor device according to any one of A1 to A6, wherein the insulating layer 2 comprises a plurality of stacked dielectric layers, and at least one of the plurality of dielectric layers (first dielectric layer 2A) is made of a material containing silicon oxide, and at least one of the plurality of dielectric layers (second dielectric layer 2B) is made of a material containing silicon nitride.

[0073] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Elements in different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims. [Explanation of symbols]

[0074] 1...semiconductor substrate, 1T...trench, 2...insulating layer, 3...resistance layer, 4...protective film, 100...semiconductor device, TR...first surface region, 2A...first dielectric layer, 2A1...dielectric material, 2B...second dielectric layer, B1...first buried wiring, B2...second buried wiring, B3...third buried wiring, d...reference distance, E1...first wiring, E2...second wiring, E3...third wiring, G...second dielectric material, P1...first electrode pad, P2...second electrode pad, P3...third electrode pad, P4...fourth electrode pad, P5...fifth electrode pad, P6...sixth electrode pad, P7...7th electrode pad, P8...8th electrode pad, P9...9th electrode pad, P10...10th electrode pad, RM...resistance area, RM1...first resistance area, RM2...second resistance area, RM3...third resistance area, RM4...fourth resistance area, S1...first area, V1...first via electrode, V2...second via electrode, V3...third via electrode, V4...fourth via electrode, Z0...reference position, Z1...first position, Z2...second position, Z3...third position, Z4...fourth position, ΔX1...first distance, ΔX2...second distance, ΔX3...third distance, ΔY4...fourth distance.

Claims

1. A semiconductor substrate; an insulating layer provided on the semiconductor substrate; a resistive layer embedded within the insulating layer; Equipped with a first surface region of the semiconductor substrate facing the resistive layer having a plurality of trenches; Semiconductor device.

2. A semiconductor substrate; an insulating layer provided on the semiconductor substrate; a resistive layer embedded within the insulating layer; Equipped with a first surface region of the semiconductor substrate facing the resistive layer having a recess; Semiconductor device.

3. a capacitor is formed between the resistive layer and the first surface region; The semiconductor device according to claim 1 .

4. The capacitance C of the capacitor is The shortest distance between the first surface region and the resistive layer is d; The area of ​​the surface of the resistance layer facing the semiconductor substrate is S, The average dielectric constant of the insulating region between the first surface region and the resistive layer is ε; As the following relationship, C≦0.8×(ε×S / d), Fulfilling The semiconductor device according to claim 3 .

5. The capacitance C of the capacitor is expressed by the following relationship: C≦0.5×(ε×S / d), Fulfilling The semiconductor device according to claim 4.

6. The material of the resistance layer includes Cr and Si. The semiconductor device according to claim 1 .

7. The insulating layer comprises a plurality of dielectric layers stacked together; a material of at least one of the plurality of dielectric layers includes silicon oxide; a material of at least one of the plurality of dielectric layers includes silicon nitride; The semiconductor device according to claim 1 .

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