Semiconductor device for switching power supply and switching power supply device

Abstract

To reduce conduction noise in an insulated switching power supply device that can switch PWM control and quasi-resonance control.SOLUTION: There is provided a semiconductor device for a switching power supply, which generates a driving signal for performing on / off control of a switching element connected in series to a primary winding of a transformer. The semiconductor device includes: a resonance monitor circuit that monitors a resonance state of a secondary winding; a timer circuit that generates a period signal giving a minimum switching period; a circuit that generates a turn-on signal on the basis of the period signal and a signal from the resonance monitor circuit; a turn-off circuit that generates a turn-off signal in response to detecting that a current flowing through the switching element reaches a predetermined current value; a circuit that generates an on / off control signal on the basis of the turn-on circuit and the turn-off circuit; and a circuit that generates a first jitter signal for giving jitter to a period of the period signal and a second jitter signal for giving jitter to the predetermined current value. The first and second jitter signals have a predetermined phase difference.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device for switching power supplies (power supply control ICs) and switching power supplies, and in particular to a power supply control IC that controls the switching elements on the primary side of a DC power supply device equipped with a voltage conversion transformer, and a switching power supply device that uses the power supply control IC. [Background technology]

[0002] DC power supplies include isolated switching power supplies that are composed of a diode bridge circuit that rectifies AC power, and a DC-DC converter that converts the DC voltage rectified by the circuit into a DC voltage of a desired voltage. For example, a switching power supply device that controls the current flowing through the primary winding by driving a switching element connected in series with the primary winding of a voltage conversion transformer on and off using a PWM (pulse width modulation) control method or a pseudo-resonant control method to control the voltage induced in the secondary winding is known as an isolated switching power supply device.

[0003] PWM control and quasi-resonant control each have their advantages and disadvantages. For example, PWM control has the disadvantage of relatively poor power efficiency due to large switching losses and conduction noise, but has the advantage of low acoustic noise, the ability to operate in continuous current mode and suppress transformer current peaks, allowing the transformer size to be small. On the other hand, quasi-resonant control has the disadvantages of acoustic noise due to bottom skip and operating only in discontinuous current mode, which results in large component sizes for the transformer and output capacitor, but has the advantage of low switching loss and conduction noise and good power efficiency because it performs soft switching (soft turn-on) that turns on at the bottom of the zero-current resonant voltage when turned on.

[0004] Conventional isolated switching power supplies employing a quasi-resonant control method are generally configured to operate only under quasi-resonant control (see, for example, Patent Document 1). In order to make the most of the advantages of both, the applicant has invented and previously filed applications for an isolated switching power supply device that switches between PWM control and quasi-resonant control depending on the feedback voltage of the output voltage from the secondary side (Patent Documents 2 and 3). The invention of Patent Document 3 was made to solve the problem with the invention of Patent Document 2. The problem with the invention of Patent Document 2 is that when the invention of Patent Document 2 is applied to a power supply device having a function capable of switching the output voltage, when the output voltage is switched to a low voltage, the switching period fluctuates significantly, causing large ripples in the output voltage and generating audible noise. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2014-124038 A [Patent Document 2] JP 2020-58196 A [Patent Document 3] JP 2021-103931 A Summary of the Invention [Problem to be solved by the invention]

[0006] Furthermore, the applicant has developed a technique for adding jitter to a periodic pulse signal that provides a switching period in order to reduce the spectrum peak of conducted noise in a switching power supply device to which the invention of Patent Document 3 is applied. However, when jitter is added to a periodic pulse signal that gives a switching cycle, a sufficient reduction effect in the frequency spectrum peak of the conducted noise can be obtained during PWM operation, but during quasi-resonant operation, the switching cycle is concentrated in a specific cycle, as shown in Figure 14(A). Therefore, it became clear that there was a problem in that the reduction effect in the spectrum peak of the conducted noise could not be obtained or was quite limited.

[0007] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to enable a peak in the frequency spectrum of conducted noise to be reduced both during PWM operation and during quasi-resonant operation in an isolated switching power supply device that switches between PWM control and quasi-resonant control during normal operation. Another object of the present invention is to provide a semiconductor device for a switching power supply, and a switching power supply device that can suppress conductive noise emitted during execution of either PWM control or quasi-resonant control. [Means for solving the problem]

[0008] In order to achieve the above object, the present invention relates to 2. A semiconductor device for a switching power supply that generates a drive signal for controlling on / off of a switching element connected in series with a primary winding of a voltage conversion transformer having an auxiliary winding, a resonance monitoring circuit for monitoring a resonance state in a secondary winding of the transformer based on a voltage of the auxiliary winding; a timer circuit for generating a periodic signal that defines a switching period of the switching element; a turn-on circuit that outputs a turn-on signal for turning on the switching element based on the periodic signal and a signal from the resonance monitoring circuit; a turn-off circuit that detects when a current flowing through the switching element reaches a predetermined current value and outputs a turn-off signal to turn off the switching element; a jitter generating circuit that generates a first jitter signal for imparting a fluctuation to a section of the periodic signal and a second jitter signal for imparting a fluctuation to the predetermined current value at which the turn-off circuit outputs the turn-off signal; wherein the first jitter signal and the second jitter signal have a predetermined phase difference.

[0009] According to the above-described configuration, it is possible to impart fluctuation to the periodic signal that provides the minimum switching period, and also to impart fluctuation to the on-timing of the switching element, thereby reducing the peak of the frequency spectrum of the conducted noise. As a result, in a switching power supply device capable of switching between PWM control and quasi-resonant control, the conducted noise emitted from the power supply device can be suppressed in both PWM operation and quasi-resonant operation. Effect of the Invention

[0010] According to the present invention, in an isolated switching power supply device that switches between PWM control and quasi-resonant control during normal operation, it is possible to reduce the peak of the frequency spectrum of conducted noise both during PWM operation and during quasi-resonant operation, thereby achieving the effect of suppressing conducted noise. [Brief description of the drawings]

[0011] [Figure 1] 1 is a circuit configuration diagram showing an embodiment of a DC-DC converter as a DC power supply device to which the semiconductor device for switching power supply according to the present invention is effectively applied; [Diagram 2] 2 is a functional block diagram showing an embodiment of a semiconductor device for a switching power supply according to the present invention, which is provided on the primary side of a transformer in the DC-DC converter of FIG. 1. FIG. [Diagram 3] 1A is a circuit diagram showing a specific example of a resonance start detection circuit constituting a switching power supply semiconductor device according to an embodiment of the present invention, and FIG. 1B is a circuit diagram showing a specific example of a resonance phase detection circuit. [Figure 4] 1 is a circuit diagram showing a specific example of a turn-on circuit constituting a switching power supply semiconductor device according to an embodiment of the present invention; [Diagram 5] 1 is a circuit diagram showing a specific example of a minimum period timer circuit constituting a switching power supply semiconductor device according to an embodiment of the present invention; [Figure 6]FIG. 1A is a circuit diagram showing a specific example of a jitter circuit constituting a semiconductor device for a switching power supply according to an embodiment of the present invention; FIG. 1B is a circuit diagram showing a specific example of a data generation circuit constituting the jitter circuit; and FIG. 1C is a circuit diagram showing a specific example of a jitter conversion circuit constituting the jitter circuit. [Figure 7] 2 is a circuit diagram showing a specific example of a turn-off circuit (current detection circuit) constituting the switching power supply semiconductor device of the embodiment; FIG. [Figure 8] Graph (A) is a graph showing the relationship between the voltage of the FB terminal and the time measured by the minimum period timer circuit in a switching power supply semiconductor device according to an embodiment, and graph (B) is a graph showing the relationship between the voltage of the FB terminal and a reference voltage as the threshold of Vcs of a turn-off circuit (current detection circuit). [Figure 9] 1A is a timing chart showing changes in the period jitter signal and the section of the minimum period signal in a semiconductor device for a switching power supply according to an embodiment, and FIG. 1B is a timing chart showing changes in the current jitter signal and the reference voltage of a turn-off circuit (current detection circuit). [Figure 10] 11 is a timing chart showing changes in signals at various parts when a power supply control IC in which only a periodic jitter signal is generated by a jitter circuit operates in PWM mode. [Figure 11] 11 is a timing chart showing changes in signals at various parts when a power supply control IC in which a jitter circuit generates a period jitter signal and a current jitter signal operates in PWM mode. [Figure 12] 11 is a timing chart showing changes in signals at various parts when a power supply control IC in which only a periodic jitter signal is generated by a jitter circuit operates in a quasi-resonant mode. [Figure 13] 11 is a timing chart showing changes in signals at various parts when a power supply control IC in which a jitter circuit generates a period jitter signal and a current jitter signal operates in a quasi-resonant mode. [Figure 14]Graph (A) shows the fluctuation of the switching period in a switching power supply using a power supply control IC that applies only period jitter, and graph (B) shows the fluctuation of the switching period in a switching power supply using a power supply control IC that applies period jitter and current jitter. [Figure 15] 1 is a graph showing the noise spectrum distribution in a switching power supply device using the power supply control IC of the embodiment, with the noise intensity plotted against the frequency on the horizontal axis. [Figure 16] 11 is a graph showing the relationship between the phase difference between period jitter and current jitter and the spectrum peak in a switching power supply device using the power supply control IC of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of an isolated DC-DC converter as a DC power supply device to which a power supply control semiconductor device according to the present invention is applied. The isolated DC-DC converter of this embodiment has a pair of voltage input terminals 11 to which a DC voltage is input, a voltage conversion transformer 12 having a primary winding Np, a secondary winding Ns and an auxiliary winding Nb, a switching transistor SW1 connected in series with the primary winding Np of the transformer 12, and a switching power supply semiconductor device (hereinafter referred to as a power supply control IC) 13 that drives the switching transistor SW1 on and off. When configuring a switching power supply device (AC-DC converter), a diode bridge circuit that rectifies the AC voltage from an AC power supply and a smoothing capacitor are connected in front of the input terminals 11.

[0013] In this embodiment, the switching transistor SW1 is configured as a discrete component using an N-channel MOSFET (insulated gate field effect transistor). The power supply control IC 13 is provided with an output terminal GATE for a gate drive signal that drives the gate of the transistor SW1. Furthermore, in the DC-DC converter of this embodiment, a rectifying and smoothing circuit is provided on the primary side of the transformer 12, the rectifying diode D1 being connected in series with the auxiliary winding Nb, and a smoothing capacitor C1 being connected between the cathode terminal of the diode D1 and the ground point GND, and a voltage rectified and smoothed by the rectifying and smoothing circuit is applied to a power supply voltage terminal VDD of the power supply control IC 13. Furthermore, the power supply control IC 13 is provided with an external terminal DMG to which a voltage VDMG obtained by dividing the voltage induced in the auxiliary winding Nb by resistors R1 and R2 is applied.

[0014] Furthermore, the power supply control IC 13 is provided with an external terminal FB to which a phototransistor (light receiving element) PT constituting a photocoupler for transmitting an output detection signal on the secondary side to the primary side as a feedback voltage VFB is connected. The power supply control IC 13 is also provided with an external terminal CS as a current detection terminal to which a voltage Vcs converted from current to voltage by a current detection resistor Rs connected between the source terminal of the switching transistor SW1 and a ground point GND is input.

[0015] On the other hand, a rectifier diode D2 connected in series with the secondary winding Ns and a smoothing capacitor C2 connected between the cathode terminal of this diode D2 and the other terminal of the secondary winding Ns are provided on the secondary side of the transformer 12, and a DC voltage Vout is generated and output by rectifying and smoothing the AC voltage induced in the secondary winding Ns by intermittently passing a current through the primary winding Np. The primary winding Np and secondary winding Ns of the transformer 12 have opposite polarities, and this is a flyback type converter.

[0016] Furthermore, on the secondary side of the transformer 12, there are provided a constant voltage control circuit (shunt regulator) 14 constituting an output voltage detection circuit that detects the output voltage Vout, and a light emitting diode (light emitting element) PD constituting a photocoupler for transmitting an output voltage detection signal corresponding to the detection voltage of the constant voltage control circuit 14 to the primary side. A current corresponding to the detection voltage is passed through the light-emitting diode PD by the constant voltage control circuit 14, and this is transmitted to the primary side as an optical signal having an intensity corresponding to the detection voltage, so that a current corresponding to the optical intensity flows through the phototransistor PT and is converted to a feedback voltage VFB by a pull-up resistor (Rp in FIG. 2) or the like inside the power supply control IC 13 and input.

[0017] The constant voltage control circuit 14 includes a bipolar transistor TR1 connected in series with the light emitting diode PD, resistors R3 and R4 for dividing the secondary side output voltage Vout, an error amplifier AMP0 for comparing the divided voltage with a reference voltage Vref0 and outputting a voltage according to the potential difference, and a phase compensation circuit 14a, and is configured so that the output voltage of the error amplifier AMP0 is applied to the base terminal of the transistor TR1, and a current according to the output voltage Vout flows. In this embodiment, the higher the secondary side output voltage Vout, the more the current flows through the light emitting diode PD, which in turn increases the current flowing through the phototransistor PT, and the voltage VFB at the external terminal FB of the power supply control IC 13 decreases. In this embodiment, the rectifier diode D2 is used in the secondary circuit, but a synchronous rectification method may be used in which the rectifier diode D2 is replaced with a switch.

[0018] Next, a functional block configuration of one embodiment of the power supply control IC 13 on the primary side in the power supply device of FIG. 1 and the function of each block will be described with reference to FIGS. The power supply control IC 13 of this embodiment is configured to be able to switch between operation by pseudo-resonant control (hereinafter, pseudo-resonant mode) and operation by PWM control (hereinafter, PWM mode), as shown in Fig. 2. To make this possible, the power supply control IC 13 of this embodiment includes a resonance start detection circuit 31 that monitors the voltage VDMG of the external terminal DMG, detects the start of zero current resonance that starts immediately after the current of the secondary winding Ns of the transformer 12 becomes zero, and outputs a resonance start detection signal RSD, and a resonance phase detection circuit 32 that detects a predetermined phase of the zero current resonance and outputs a resonance phase detection signal RPD, as shown in Fig. 2.

[0019] The power supply control IC 13 also includes a timer circuit 33 that generates a minimum period signal which provides a minimum switching period, and a turn-on circuit 34 that receives as input the output signals of the resonance start detection circuit 31, the resonance phase detection circuit 32, and the timer circuit 33 and generates a timing signal TON for turning on the switching element SW1. Of these, the timer circuit 33 is configured to measure a time corresponding to the voltage VFB of the external terminal FB to which a feedback signal from the secondary side is input. In order to reduce the conductive noise emitted from the power supply in the PWM mode, a jitter circuit 35 is provided to impart jitter to the section of the minimum period signal generated by this timer circuit 33.

[0020] The power supply control IC 13 further includes a turn-off circuit 36 ​​consisting of a current detection circuit which receives as input the voltage VFB of the external terminal FB and the voltage Vcs of the current detection terminal CS and generates a timing signal for turning off the switching element SW1. The power supply control IC 13 also includes a latch circuit 37 consisting of an RS flip-flop or the like which receives as input the output signal TON of the turn-on circuit 34 and the output signal TOFF of the turn-off circuit 36, and a driver circuit 38 which generates a gate drive signal for driving the switching element SW1 in response to a gate control signal GCS output from the latch circuit 37 and outputs the gate drive signal from the external terminal GATE. The gate control signal GCS is supplied to the timer circuit 33 as a signal for enabling the timer circuit 33, and is also supplied to the resonance start detection circuit 31 and the turn-on circuit 34 as a signal for resetting the resonance start detection circuit 31 and the turn-on circuit 34. The power supply control IC 13 is also provided with an internal power supply circuit 39 consisting of a voltage regulator such as a series regulator for providing operating voltages to the above-mentioned functional circuits.

[0021] Furthermore, in the power supply control IC 13 of this embodiment, the jitter circuit 35 is provided with a function of generating a current jitter signal JTi for adding jitter to the peak current of the switching element SW1 determined by the turn-off signal by changing the input voltage of the turn-off circuit 36. The current jitter signal JTi generated by the jitter circuit 35 is input to the turn-off circuit 36. Hereinafter, specific examples and operations of the above-mentioned functional blocks 31 to 36 will be described.

[0022] 3A, the resonance start detection circuit 31 of the functional blocks 31 to 36 constituting the power supply control IC 13 is composed of a comparator (voltage comparison circuit) CMP1 that compares the voltage VDMG of the external terminal DMG with a predetermined reference voltage VDMGREF1 and changes its output to a high level when VDMG becomes lower than VDMGREF1, and a D-type flip-flop FF1 that latches data "1" based on the output of the comparator CMP1. The output of this flip-flop is supplied to a turn-on circuit 34 as a resonance start detection signal RSD. On the other hand, the resonance phase detection circuit 32 is configured to detect a predetermined phase point (for example, 180°) from the zero current resonance starting point and output the resonance phase detection signal RPD. Specifically, as shown in Fig. 3B, it can be configured by a comparator CMP2 that compares the voltage VDMG of the external terminal DMG with a predetermined reference voltage VDMGREF2 and changes its output to a high level when VDMG becomes lower than VDMGREF2. Here, VDMGREF1 and VDMGREF2 are set to have a relationship of VDMGREF1 ≥ VDMGREF2.

[0023] The resonance start detection circuit 31 and the resonance phase detection circuit 32 are circuits provided to detect the timing to turn on the switching element SW1 in the quasi-resonant mode. Therefore, it is possible to configure the circuit to monitor and detect the drain voltage VD of the switching element SW1. However, the drain voltage VD of SW1 may exceed 500V depending on the specifications of the power supply device, and even if the voltage is divided, the loss and components may become large, and the voltage at the zero current resonance start point (timing t2 in FIG. 13) also depends on the input voltage. Therefore, in this embodiment, an external terminal DMG is provided to which a voltage obtained by dividing the voltage appearing in the auxiliary winding Nb of the transformer 12 by resistors R1 and R2 is input, and the voltage VDMG is monitored.

[0024] 4, the turn-on circuit 34 includes an AND gate G1 that receives as inputs the minimum period signal MPS from the timer circuit 33 and the detection signal RSD from the resonance start detection circuit 31, and a D-type flip-flop FF2 whose data terminal receives the output of the AND gate G1. The turn-on circuit 34 further includes an AND gate G2 that receives as inputs the minimum period signal MPS from the timer circuit 33 and a signal obtained by inverting the detection signal RSD from the resonance start detection circuit 31 by an inverter INV1, and an OR gate G3 that receives as inputs the output signal of the AND gate G2 and the output signal of the D-type flip-flop FF2. The output of the OR gate G3 is output as a turn-on signal TON. The D-type flip-flop FF2 is configured to take in the output of the AND gate G1 in synchronization with the rising edge of the resonance phase detection signal RPD from the resonance phase detection circuit 32. The D-type flip-flop FF2 is also configured to be cleared by a signal obtained by inverting the gate control signal GCS output from the latch circuit 37 by an inverter INV2.

[0025] 5, the timer circuit 33 includes an AND gate G4 that receives as input a gate control signal GCS output from the latch circuit 37 and a signal obtained by delaying and inverting the control signal GCS through a delay circuit DLY consisting of a series inverter.The timer circuit 33 also includes a variable current source VCS1 that supplies a current according to the voltage VFB of the external terminal FB, a capacitor C3 that is charged by the current from the current source VCS1, and a discharging switch transistor SW2 that discharges the charge of the capacitor C3, and the output of the AND gate G4 is applied to the gate terminal of the switch transistor SW2. Furthermore, the timer circuit 33 includes a comparator CMP3 that compares the charging voltage of the capacitor C3 with a predetermined reference voltage Vref3, and a second variable current source VCS2 connected in parallel with the variable current source VCS1. The second variable current source VCS2 is configured so that the current it supplies is increased or decreased according to the period jitter signal JTp from the jitter circuit 35. The timer circuit 33 may be a digital timer circuit that operates to measure time according to a clock signal.

[0026] In the timer circuit 33 of Fig. 5, when the gate control signal GCS changes from low level to high level, the output of the AND gate G4 changes to high level for a predetermined time (delay time of the delay circuit DLY), the switch transistor SW2 turns on, and the charge of the capacitor C3 is discharged. When the gate control signal GCS changes to low level and the switch transistor SW2 turns off, charging of the capacitor C3 begins, and when a predetermined time determined by the capacitance value of the capacitor C3 and the current values ​​of the variable current sources VCS1 and VCS2 has elapsed, the charging voltage of the capacitor C3 reaches Vref3, and the output of the comparator CMP3 changes from low level to high level. As a result, the minimum period signal MPS having a period according to the voltage VFB is output from the period timer circuit 33, and jitter (fluctuation) is added to the section of the minimum period signal MPS according to the period jitter signal JTp input at that time.

[0027] In this embodiment, the timer circuit 33 is set so that the higher the voltage VFB at the external terminal FB (the larger the secondary load), the larger the current of the variable current source VCS1 is, the shorter the time it measures, and the shorter the section tMIN of the minimum period signal MPS it outputs becomes. Note that Fig. 8(A) shows an example of setting the section tMIN of the minimum period signal MPS and the voltage VFB at the FB terminal. Fig. 9(A) also shows the period jitter signal JTp and the fluctuation of the section tMIN of the minimum period signal MPS that is changed by this signal. Incidentally, in this embodiment, the period of the minimum period signal MPS is used as the switching period in PWM mode (continuous current mode) and as the detection period of the zero current resonant phase in quasi-resonant mode (discontinuous current mode). Therefore, in a switching power supply device using the power supply control IC 13 of this embodiment, the switching period is determined based on the period of the minimum period signal MPS output from the timer circuit 33 (time counting of the timer circuit 33), and in PWM mode, the reciprocal of the period of the minimum period signal MPS is the switching frequency. In quasi-resonant mode, the reciprocal of (time counting of the minimum period signal MPS + detection delay time until the rising edge of the next phase detection signal) is the switching frequency.

[0028] Fig. 6(A) shows a specific circuit configuration example of the jitter circuit 35. As shown in Fig. 6(A), the jitter circuit 35 includes a data generation circuit 51 that generates first data FDT, a jitter conversion circuit 52A that generates a period jitter signal JTp based on the first data FDT generated by the data generation circuit 51, an addition circuit 53 that generates second data SDT by adding a predetermined addition value (fixed value) ADT to the first data FDT, and a jitter conversion circuit 52B that generates a current jitter signal JTi based on the second data SDT generated by the addition circuit 53.

[0029] As shown in FIG. 6B, the data generation circuit 51 is composed of a counter circuit CNT in which trigger flip-flops T-FF0 to T-FF3 are cascaded, and a clock generator CG that generates a clock signal CLK for operating the counter circuit. The counter circuit CNT performs a coefficient operation by the clock signal CLK, and repeatedly outputs a value to be incremented (+1). The number of stages of the counter circuit CNT is not limited to four stages as shown in the figure, and can be set arbitrarily. The period of the clock signal CLK for operating the counter circuit CNT is set so that the period of the generated first data has a period sufficiently longer (100 to several hundreds times longer) than the switching period of the switching element SW1.

[0030] 6C, the jitter conversion circuits 52A, 52B include inverters IV1-IV3 which invert the outputs Q0-Q2 of the trigger flip-flops T-FF0-T-FF2, and multiplexers MPX1-MPX3 which receive the outputs Q0-Q2 of the flip-flops T-FF0-T-FF2 and their inverted signals as inputs and select and output one of the signals. The output Q3 of the final-stage flip-flop T-FF3 of the counter circuit CNT is applied to the control terminals of the multiplexers MPX1-MPX3. As a result, the jitter conversion circuits 52A, 52B output the increment (+1) value supplied from the counter circuit as is while the output Q3 is at a low level, and when the output Q3 changes to a high level, they operate as a circuit that converts data consisting of the increment (+1) value supplied from the counter circuit CNT (ascending data) into data consisting of the decrement (-1) value (descending data) and outputs it.

[0031] As a result, the outputs of the jitter conversion circuits 52A and 52B can be regarded as data that repeats ups and downs, that is, pseudo triangular wave signals having a predetermined period. The pseudo triangular wave signal (JTi) output from the jitter conversion circuit 52B is a signal that has a phase difference corresponding to the addition data ADT with respect to the pseudo triangular wave signal (JTp) output from the jitter conversion circuit 52A, as shown in Fig. 9(B). Therefore, the addition data ADT is information (phase shift signal) that indicates the amount of phase shift, and the addition circuit 53 can be regarded as a phase shift circuit. In the jitter circuit of this embodiment, the periodic jitter signal JTp is generated based on the first data FDT, and the current jitter signal JTi is generated based on the second data SDT obtained by adding a predetermined addition value ADT to the first data FDT, but the periodic jitter signal JTp and the current jitter signal JTi may be reversed.

[0032] 7 shows a specific circuit configuration example of the turn-off circuit 36 ​​consisting of a current detection circuit. As shown in FIG. 7, the turn-off circuit 36 ​​includes a voltage divider circuit consisting of a resistor R5 and a variable resistor R6 connected in series between the external terminal FB and the ground point, which divides the voltage VFB of the terminal FB, and a comparator CMP4 that uses the voltage divided by the resistors R5 and R6 as a threshold voltage VREF to determine the voltage Vcs of the external terminal CS. When the voltage Vcs of the external terminal CS exceeds VREF, the output of the comparator CMP4 changes from a low level to a high level. This output is supplied to the latch circuit 37 as a turn-off signal TOFF, and the switching element SW1 is turned off.

[0033] In the power supply control IC 13 of this embodiment, the resistance value of the variable resistor R6 of the turn-off circuit 36 ​​is configured to change according to the current jitter signal JTi output from the jitter circuit 35. As a result, the timing of the signal TOFF output from the turn-off circuit 36 ​​fluctuates, and jitter is added to the turn-off signal of the switching element SW1. Then, at the timing when the switching element SW1 is turned off, the drain current of SW1 becomes a peak current. Therefore, when jitter is added to the turn-off signal TOFF as described above, the peak current changes. In other words, the current jitter signal JTi acts as a signal that adds jitter (fluctuation) to the peak current of the drain current of SW1.

[0034] 8B shows an example of setting the voltage VFB at the terminal FB and the threshold voltage VREF of the comparator CMP3 of the turn-off circuit (current detection circuit) 36. In this embodiment, the resistance value of the variable resistor R6 is configured to change in proportion to the voltage VFB at the terminal FB, and thus the threshold voltage VREF is set to change linearly with respect to the voltage VFB, as shown in FIG. Also, Fig. 9(B) shows the current jitter signal JTi and the fluctuation of the threshold voltage VREF changed by this signal. As can be seen from Fig. 9(B), the period and phase of the current jitter signal JTi and the threshold voltage VREF are the same. However, as can be seen by comparing Fig. 9(A) and (B), the current jitter signal JTi has a predetermined phase difference PD with respect to the period jitter signal JTp. This phase difference PD is given by the addition data ADT in the addition circuit 52 constituting the jitter circuit 35 shown in Fig. 6. Although not shown, in the case of only period jitter, the fluctuation of the section tMIN of the minimum period signal MPS is the same as in Fig. 9(A), but since no current jitter is added, the threshold voltage VREF does not change and remains constant.

[0035] Next, the features of the operation of the power supply control IC 13 of this embodiment having the above-mentioned configuration will be described with reference to FIGS. FIG. 10 shows a timing chart when the power supply control IC in which the jitter circuit 35 generates only the periodic jitter signal JTp operates in PWM mode, and FIG. 11 shows a timing chart when the power supply control IC 13 of this embodiment in which the jitter circuit 35 generates both the periodic jitter signal JTp and the current jitter signal JTi operates in PWM mode.

[0036] 10 and 11, the switching period with neither period jitter nor current jitter is tSW, the switching period with no current jitter (only period jitter in Figure 10) is tSWJ, the switching period with both period jitter and current jitter (Figure 11) is tSWJ', the interval of the minimum period signal MPS is tMIN, and the time changed by the period jitter is Δt. Then, when there is neither period jitter nor current jitter, tSW = tMIN. When there is only period jitter, tSWJ = tMIN + Δt, and when there are both period jitter and current jitter, tSWJ' = tMIN + Δt. From this, we can see that in PWM mode, the effect of dispersing the switching period due to jitter can be obtained in both cases where there is only period jitter and where there are both period jitter and current jitter.

[0037] FIG. 12 shows a timing chart of the power supply control IC in which the jitter circuit 35 generates only the periodic jitter signal JTp when operating in the quasi-resonant mode, and FIG. 13 shows a timing chart of the power supply control IC 13 in this embodiment in which the jitter circuit 35 generates both the periodic jitter signal JTp and the current jitter signal JTi when operating in the quasi-resonant mode. 12, the switching period tSW is until the next phase detection timing tZ2 of the section tMIN of the minimum period signal MPS. Therefore, when the timing of turning on the switching element SW1 is set as the reference time 0, the zero current resonance start time is t2, the zero current resonance period is tZP, the added amount of period jitter is Δt, and the switching period when the period jitter is effective is tSWJ, then tSW and tSWJ are expressed by the following equation: tSW(N) = t2 + (N + X) * tZP tSWJ(NJ) = t2 + (NJ + X) * tZP Here, N and NJ are natural numbers, and X is a constant between 0 and 1.

[0038] In addition, the relationship between tSW and tMIN, and the relationship between tSWJ and tMIN+Δt are expressed by the following equations. tSW(N-1) < tMIN ≦ tSW(N) tSWJ(NJ-1) < tMIN+Δt ≦ tSWJ(NJ) Here, Δt is tSW(N-1) < tMIN + Δt ≦ tSW(N) If the switching period falls within the range tSWJ(NJ) = tSW(N) Therefore, the switching period is the same regardless of the presence or absence of period jitter. Therefore, in the case of only period jitter, the effect of dispersing the switching period due to period jitter cannot be obtained in the quasi-resonant mode.

[0039] On the other hand, when the power supply control IC operates in quasi-resonant mode with the period jitter and current jitter of Figure 13, the reference voltage of the current detection circuit that detects the turn-off timing is VREF, the amount of addition due to the current jitter is ΔV, and the time to turn off when the timing of turning on the switch is the reference time 0 is t1', and the zero current resonance start time is t2'. Then, t1' = t1 * (1 + ΔV / VREF) t2' = t2 * (1 + ΔV / VREF) It becomes. Moreover, the switching period tSW' has a value determined by the phase detection timing tZ2' next to the section tMIN of the minimum period signal MPS.

[0040] Here, if the switching period when both period jitter and current jitter exist is tSWJ', tSW and tSWJ' are expressed by the following formula. tSW(N) = t2+(N+X) * tZP tSWJ'(NJ') ​​= t2'+(NJ'+X) * tZP =t2 * (1+ΔV / VREF) +(NJ'+X) * tZP It is determined by the following: N and NJ are natural numbers, and X is a constant between 0 and 1. Then, the difference in switching period between the cases with and without jitter is expressed as follows: tSWJ'(NJ')-tSW(N) =t2+(N+X) * tZP-t2 * (1+ΔV / VREF)+(NJ'+ X)* tZP = t2 * ΔV / VREF+(N-NJ')* tZP Even if N=NJ', the switching period fluctuates by t2*ΔV / VREF. Therefore, when there is period jitter and current jitter, the effect of dispersing the switching period can be obtained even in the quasi-resonant mode.

[0041] Fig. 14(A) shows a graph representing the fluctuation of the switching period in a switching power supply using a power supply control IC that applies only period jitter, with the horizontal axis representing the feedback voltage VFB and the vertical axis representing the ratio tsw' / tsw of the switching period when jitter is enabled and disabled. Similarly, Fig. 14(B) shows a graph representing the fluctuation of the switching period in a switching power supply using a power supply control IC that applies period jitter and current jitter, with the horizontal axis representing the feedback voltage VFB and the vertical axis representing the ratio tsw' / tsw of the switching period when jitter is enabled and disabled.

[0042] Comparing the graphs in Figure 14 (A) and (B), in the quasi-resonant operation region, in the case of only period jitter in (A), the switching period is concentrated at three specific discrete points, which causes the peak of the frequency spectrum of the conducted noise to become higher. The reason that the switching period is concentrated at a specific discrete period in this way is that under quasi-resonant operation, the resonance period Tr of the zero current resonance is "Tr = tZP x (0.5 + N)" (N is an integer), where tZP is the resonance period.

[0043] In contrast, in the case of the period jitter and current jitter in Figure 14(B), although the switching periods are concentrated in a specific period range under quasi-resonant operation, they also appear to be dispersed around a specific period. The reason why the switching periods are dispersed under quasi-resonant operation in this way is because the time t2 (Figure 13) from turn-on to the start of zero current resonance varies with the current jitter. As a result, the case of the period jitter and current jitter in Figure 14(B) provides a better noise reduction effect under quasi-resonant operation than the case of only period jitter in Figure 14(A).

[0044] Fig. 15 shows a graph with frequency on the horizontal axis and noise intensity on the vertical axis. In Fig. 15, the dashed line represents the frequency spectrum of noise intensity in the case of period jitter only, and the solid line represents the frequency spectrum of noise intensity in the case of period jitter and current jitter. Fig. 15 also shows that the peak is lower in the case of period jitter and current jitter (solid line) than in the case of period jitter only (dashed line), and a better noise reduction effect can be obtained.

[0045] Furthermore, the present inventors have found that in a switching power supply device using the power supply control IC of the above embodiment, the spectrum peak differs depending on the phase difference between the period jitter and the current jitter, as shown in Fig. 16. In the example graph of Fig. 16, the spectrum peak is smallest when the phase difference is -45 degrees compared to when the phase difference is 0 degrees, and the effect of noise spectrum dispersion is expected. However, the magnitude relationship of the spectral peak with respect to the phase difference also varies depending on the configuration of the switching power supply device and the magnitudes of the input voltage, output voltage, and output current. Therefore, it is most effective from the viewpoint of noise reduction to set the phase shift amount according to the conditions under which the conduction noise is particularly desired to be reduced, that is, to set the phase shift amount so that the spectral peak is minimized under the conditions that are the bottleneck of the spectrum peak of the conduction noise. For example, once the conditions other than the phase difference are determined, the phase difference that minimizes the spectrum peak under those conditions may be found, and the addition data (addition value) in the jitter circuit 35 may be set.

[0046] Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment. For example, in the above embodiment, the voltage obtained by dividing the voltage of the auxiliary winding by resistors R1 and R2 as external elements is input to the external terminal DMG, but the voltage of the auxiliary winding may be input directly to the external terminal DMG, or a voltage divided by a resistor element provided inside the power supply control IC or a voltage divided by a resistor element provided inside the power supply control IC and an external resistor element may be input to the external terminal DMG.

[0047] Also, in the above embodiment, the switching transistor SW1 and the current sense resistor Rs are separate elements from the power supply control IC 13, but the switching transistor SW1 may be incorporated into the power supply control IC 13 to configure it as one semiconductor integrated circuit (the current sense resistor Rs is an external element), or the switching transistor SW1 and the current sense resistor Rs may be incorporated into the power supply control IC 13. Also, instead of providing the current sense resistor Rs to generate and detect the voltage Vcs, the magnitude of the drain current may be detected from the drain voltage of the internal switching transistor SW1. [Explanation of symbols]

[0048] 12... transformer, 13... switching power supply semiconductor device (power supply control IC), 14... constant voltage control circuit, 31... resonance start detection circuit, 32... resonance phase detection circuit, 33... timer circuit, 34... turn-on circuit, 35... jitter circuit, 36... turn-off circuit (current detection circuit), 37... latch circuit (gate control signal generation circuit), 38... driver circuit, 39... internal power supply circuit, 51... data generation circuit, 52A, 52B... jitter conversion circuit, 53... adder circuit (phase shift circuit)

Claims

1. A semiconductor device for a switching power supply that generates a drive signal for controlling on / off of a switching element connected in series with a primary winding of a voltage conversion transformer having an auxiliary winding, a resonance monitoring circuit for monitoring a resonance state in a secondary winding of the transformer based on a voltage of the auxiliary winding; a timer circuit for generating a periodic signal that defines a switching period of the switching element; a turn-on circuit that outputs a turn-on signal for turning on the switching element based on the periodic signal and a signal from the resonance monitoring circuit; a turn-off circuit that detects when a current flowing through the switching element reaches a predetermined current value and outputs a turn-off signal to turn off the switching element; a jitter generating circuit that generates a first jitter signal for imparting a fluctuation to a section of the periodic signal and a second jitter signal for imparting a fluctuation to the predetermined current value at which the turn-off circuit outputs the turn-off signal; wherein the first jitter signal and the second jitter signal are generated so as to have a predetermined phase difference.

2. The jitter generation circuit includes: a data generating circuit that generates first data that is a source of the first jitter signal; a first jitter signal generating circuit that generates the first jitter signal based on the first data; a second jitter signal generating circuit that generates the second jitter signal by phase-shifting the first jitter signal; Equipped with a period of the first jitter signal and a period of the second jitter signal are longer than a switching period of the switching element, the timer circuit fluctuates a section of the periodic signal based on the first jitter signal output from the first jitter signal generating circuit; 2. The semiconductor device for a switching power supply according to claim 1, wherein the turn-off circuit is configured to give a fluctuation to the turn-off signal based on the second jitter signal output from the second jitter signal generating circuit.

3. The jitter generation circuit includes: a counter circuit for generating first data that is a basis of the first jitter signal; an adder circuit that adds a predetermined addend value to the first data to generate second data that is a source of the second jitter signal; a first data conversion circuit that converts the first data, which is ascending data, into descending data and outputs the ascending and then descending data; a second data conversion circuit that converts the second data, which is ascending data, into descending data and outputs the data in ascending order and then descending order; Equipped with the timer circuit fluctuates the periodic signal based on the data output from the first data conversion circuit; 2. The semiconductor device for a switching power supply according to claim 1, wherein the turn-off circuit is configured to give a fluctuation to the turn-off signal based on the data output from the second data conversion circuit.

4. 4. The semiconductor device for a switching power supply according to claim 3, wherein the additional value is set so as to minimize a peak in the frequency spectrum of the conduction noise emitted by the power supply device.

5. a third external terminal to which a voltage induced in the auxiliary winding or a voltage proportional to the voltage is input; The resonance monitoring circuit includes: a resonance start detection circuit that detects, based on a voltage of the third external terminal, that a zero current resonance that starts immediately after a current in a secondary winding of the transformer becomes zero after the switching element is turned off and outputs a resonance start detection signal; a resonance phase detection circuit that detects a predetermined phase of the zero current resonance based on a voltage of the third external terminal and outputs a resonance phase detection signal, 2. The semiconductor device for a switching power supply according to claim 1, wherein the turn-on circuit generates the turn-on signal when the periodic signal is received before the resonance start detection signal is received, or at the rising edge of the resonance phase detection signal following the reception of the periodic signal, based on the periodic signal, the resonance start detection signal, and the resonance phase detection signal.

6. a first external terminal to which a feedback voltage corresponding to a voltage output from a secondary side of the transformer is input; a second external terminal to which a voltage proportional to a current flowing through the switching element is input; Equipped with the turn-off circuit detects whether a current flowing through the switching element reaches a predetermined current value based on a voltage at the first external terminal and a voltage at the second external terminal, 6. The semiconductor device for a switching power supply according to claim 5, wherein the second jitter signal causes a fluctuation in the predetermined current value by varying a voltage derived from a voltage at the second external terminal.

7. a voltage divider circuit having a fixed resistor and a variable resistor connected in series between the first external terminal and a reference potential point, the voltage divider circuit dividing a voltage of the first external terminal; the turn-off circuit detects that a current flowing through the switching element has reached a predetermined current value by comparing a voltage divided by the voltage divider circuit with a voltage at the second external terminal; 7. The semiconductor device for a switching power supply according to claim 6, wherein the second jitter signal is generated by varying a resistance value of the variable resistor to vary a divided voltage by the voltage divider circuit, thereby causing a fluctuation in the predetermined current value.

8. 8. A switching power supply device comprising: a semiconductor device for a switching power supply according to claim 1; a transformer having an auxiliary winding, in which a voltage obtained by rectifying an AC voltage is applied to a primary winding; and a switching element connected to the primary winding, wherein the switching power supply device is configured to output a predetermined voltage to a secondary winding by controlling the switching element using the semiconductor device for a switching power supply.

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