Method of manufacturing semiconductor device and semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device, with which a semiconductor element can be bonded to pads via a solder without using a dedicated positioning jig even if an interval between adjacent pads is narrow.SOLUTION: There is provided a method of manufacturing a semiconductor device 1, with which a plurality of semiconductor elements 5 are bonded, via a solder 4, on a substrate 2 including a plurality of pads 3. The method includes: an arrangement step of disposing the solder 4 and the plurality of semiconductor elements 5 on the plurality of pads 3, respectively, while shifting the center position of each pad 3 and the center position of the semiconductor element 5 corresponding to the pad so as to satisfy a12<c12 where a12 represents the center distance between a first pad 3A and a second pad 3B, and c12 represents the center distance between a first electrode included in a first semiconductor element 5A and a second electrode included in a second semiconductor element 5B; and a solder melting step of melting the solder 4 after the arrangement step.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] An example of a semiconductor device in which a semiconductor element is bonded to a pad of a substrate via solder is disclosed in Patent Document 1.

[0003] Figure 1 and the abstract of Patent Document 1 state that "The semiconductor device 101 comprises an insulating substrate 4 and a semiconductor element 6. The insulating substrate comprises an insulating layer 2 and a metal circuit pattern 3a provided on the upper surface of the insulating layer. The semiconductor element is solder-joined to the upper surface of the metal circuit pattern, and an oxide film 7a or a nitride film is provided on the area of ​​the upper surface of the metal circuit pattern to which the semiconductor element is not solder-joined."

[0004] Furthermore, paragraph 0037 of Patent Document 1 states, "The oxide film 7a suppresses the spreading of the solder material 5a, thereby preventing the solder material 5a from flowing to unnecessary areas. Therefore, when soldering the semiconductor element 6 to the metal circuit pattern 3a, the semiconductor element 6 and the solder material 5a can be positioned without using a dedicated positioning jig." [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2022-137686 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, even if the technology of Patent Document 1 is used, if the spacing between adjacent pads is narrowed in order to mount semiconductor elements at a high density, there is a problem that the semiconductor elements may shift and overlap with adjacent semiconductor elements when the solder is melted.

[0007] FIG. 10 is a top view for explaining problems in a conventional method of manufacturing a semiconductor device.

[0008] In FIG. 10, the substrate 2 of the semiconductor device 1 is covered with an insulating film except at the pads 3. Solder (not shown) is disposed on the pads 3, and a semiconductor element 5 is disposed on the solder, and the solder is melted. At this time, in a place where the interval between adjacent pads 3 is narrow, the semiconductor element 5 may shift, and two adjacent semiconductor elements 5 may overlap.

[0009] The problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device capable of joining a semiconductor element to a pad via solder without using a dedicated positioning jig even when the interval between adjacent pads is narrow.

Means for Solving the Problem

[0010] In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a plurality of semiconductor elements are joined via solder on a substrate having a plurality of pads, wherein the plurality of pads include a first pad and a second pad adjacent to the first pad, the solder includes a first solder disposed corresponding to the first pad and a second solder disposed corresponding to the second pad, the plurality of semiconductor elements include a first semiconductor element having a first electrode joined to the first pad and a second semiconductor element having a second electrode joined to the second pad, and when a center-to-center distance between the first pad and the second pad is a12 and a center-to-center distance between the first electrode and the second electrode is c12, an arranging step of shifting center positions of the plurality of pads and the plurality of semiconductor elements so as to satisfy a12 < c12 and arranging the solder and the plurality of semiconductor elements on the plurality of pads; and a solder melting step of melting the solder after the arranging step.

[0011] In addition, the semiconductor device of the present invention is a semiconductor device having a substrate having a plurality of pads, a plurality of semiconductor elements, and solder joining the pads and the semiconductor elements, and is characterized in that the distribution of the Cu6Sn5 phase of the solder is more uniform at the outer periphery of the solder between adjacent semiconductor elements than at the outer periphery of the solder on the opposite side. Effect of the Invention

[0012] According to the present invention, even when the space between adjacent pads is narrow, a semiconductor element can be bonded to the pads via solder without using a dedicated positioning jig. [Brief description of the drawings]

[0013] [Figure 1] 1A to 1C are top views illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Diagram 2] 4 is a top view illustrating a placement process in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Diagram 3] 4 is a top view illustrating a placement process in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 4] 4 is a top view illustrating a placement process in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Diagram 5] FIG. 2 is a top view of the semiconductor device of the first embodiment. [Figure 6] 3A and 3B are cross-sectional views illustrating a state before and after a solder melting step in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] 6A and 6B are cross-sectional views illustrating a state before and after a solder melting step in a manufacturing method of a semiconductor device according to a comparative example. [Figure 8] 4A to 4C are top views for explaining the amount of misalignment in the placement process in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 9] 11A to 11C are top views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 10] 1 is a top view illustrating a problem in a conventional method for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted. EXAMPLES

[0015] FIG. 1 is a top view illustrating a method for manufacturing a semiconductor device according to a first embodiment.

[0016] The semiconductor device 1 of this embodiment includes a substrate 2 having a plurality of pads 3, a plurality of semiconductor elements 5, and solder 4 that bonds the pads 3 and the semiconductor elements 5 together.

[0017] The substrate 2 is an insulating substrate such as a ceramic substrate, on which a wiring layer is formed of a metal such as copper. Part of this wiring layer serves as the pad 3. The insulating substrate and the wiring layer are covered with an insulating film (see insulating film 6 in FIG. 6) so that the area of ​​the pad 3 is exposed.

[0018] The semiconductor element 5 may be, for example, a semiconductor chip such as a switching element or a diode.

[0019] The solder 4 may be, but is not limited to, a solder containing Sn as a main component and 3 to 10% by weight of Cu. In this embodiment, a solder paste is used as the solder 4, but the present invention is not limited to this and a solder sheet may be used as the solder 4.

[0020] The manufacturing method of the semiconductor device 1 of this embodiment is a method of manufacturing the semiconductor device 1 in which a plurality of semiconductor elements 5 are bonded via solder 4 onto a substrate 2 having a plurality of pads 3, and includes an arrangement step of arranging the solder 4 and the plurality of semiconductor elements 5 on the plurality of pads 3, and a solder melting step of melting the solder 4 after the arrangement step. Fig. 1 shows the state after the arrangement step and before the solder melting step. First, the details of the arrangement step will be described.

[0021] FIG. 2 is a top view illustrating a placement process in the manufacturing method of the semiconductor device according to the first embodiment.

[0022] 2 shows the state immediately before the placement process is started. The substrate 2 used is covered with an insulating film so that the area of ​​the pads 3 is exposed. The pads 3 include a first pad 3A and a second pad 3B adjacent to the first pad 3A. Here, the center-to-center distance between the first pad 3A and the second pad 3B is a12.

[0023] FIG. 3 is a top view illustrating the arrangement process in the manufacturing method of the semiconductor device according to the first embodiment.

[0024] The process of Fig. 3 is a part of the arrangement process, and is the next process after Fig. 2. As shown in Fig. 3, the solder 4 is arranged on the pad 3 with the center position of the solder 4 shifted from the center position of the pad 3. The solder 4 includes a first solder 4A arranged corresponding to the first pad 3A, and a second solder 4B arranged corresponding to the second pad 3B. Here, the center distance between the first solder 4A and the second solder 4B is b12.

[0025] FIG. 4 is a top view illustrating the arrangement process in the manufacturing method of the semiconductor device according to the first embodiment.

[0026] The step in Fig. 4 is a part of the arrangement step, and is the next step after Fig. 3. As shown in Fig. 4, the semiconductor element 5 is arranged on the pad 3 with the center position of the semiconductor element 5 shifted from the center position of the pad 3. The multiple semiconductor elements 5 include a first semiconductor element 5A having a first electrode bonded to the first pad 3A, and a second semiconductor element 5B having a second electrode bonded to the second pad 3B. Here, the center-to-center distance between the first electrode and the second electrode is c12.

[0027] Figure 1 shows the state after the process of Figure 4, and the center-to-center distances a12, b12, and c12 are shown superimposed. In the placement process of this embodiment, the center positions of the plurality of pads 3 and the plurality of semiconductor elements 5 are shifted so as to satisfy a12 < c12, and the solder 4 and the plurality of semiconductor elements 5 are placed on the plurality of pads 3. Regarding the solder 4 as well, it is desirable to shift the center positions of the plurality of pads 3, the solder 4, and the plurality of semiconductor elements 5 so as to satisfy a12 < b12 < c12. However, it is not limited to this, and the center position of the solder 4 may be made to coincide with the center position of the pad 3 or the center position of the semiconductor element 5 and arranged so as to satisfy a12 ≤ b12 ≤ c12. However, even in this case, a12 < c12 should be satisfied.

[0028] And after the placement process, a solder melting process for melting the solder 4 is performed. In the solder melting process, heating is performed so that the solder 4 is in a temperature range of the solidus temperature or higher and 300°C or lower. For Sn-3 to 10Cu solder, since 85% or more of the solder volume melts at a solidus temperature of 227°C or higher, connection is possible at a temperature equal to or higher than the solidus temperature. Note that when the connection temperature is high, there is a high possibility of thermal damage to the components, and it is also inferior in energy saving, so 300°C or lower is desirable.

[0029] When the solder 4 melts, the self-alignment effect acts, and the solder 4 and the semiconductor element 5 arranged with the center positions shifted as shown in Figure 1 move in a direction in which the deviation becomes smaller.

[0030] Figure 5 is a top view of the semiconductor device of Example 1.

[0031] Figure 5 shows the state in which the solder 4 has solidified after the solder melting process. When the center-to-center distance between the first electrode and the second electrode in this state is c12', the deviation between the pad 3 and the semiconductor element 5 becomes smaller due to the self-alignment effect, so c12' < c12.

[0032] As in the prior art, when the pads 3 and the semiconductor elements 5 are arranged without shifting their central positions and the solder 4 is melted, if the interval between adjacent pads 3 is narrow, the semiconductor elements 5 may shift, and as shown in FIG. 10, two adjacent semiconductor elements 5 may overlap each other.

[0033] On the other hand, as in this embodiment, after shifting the central positions of the plurality of pads 3 and the plurality of semiconductor elements 5 so as to satisfy a12 < c12 and arranging the solder 4 and the plurality of semiconductor elements 5 on the plurality of pads, and then melting the solder 4, even when the interval between adjacent pads 3 is narrow, the semiconductor elements 5 can be joined to the pads 3 via the solder 4 without using a dedicated positioning jig.

[0034] In the description so far, the relationship between the first semiconductor element 5A and the second semiconductor element 5B has been described, but the same applies to other semiconductor elements 5. For example, the plurality of pads 3 may include a third pad 3C adjacent to the first pad 3A, the solder 4 may include a third solder 4C arranged corresponding to the third pad 3C, and the plurality of semiconductor elements 5 may include a third semiconductor element 5C having a third electrode joined to the third pad 3C. At this time, in the arranging step, when the center-to-center distance between the first pad 3A and the third pad 3C is a13 and the center-to-center distance between the first electrode and the third electrode is c13, it may be arranged so as to satisfy a13 < c13. At this time, when the center-to-center distance between the first solder 4A and the third solder 4C is b13, it is desirable to satisfy a13 < b13 < c13, but it may also be such that a13 ≤ b13 ≤ c13 and a13 < c13 are satisfied. Further, when the center-to-center distance between the first electrode and the third electrode in the state where the solder 4 has solidified after the solder melting step is c13', it may be arranged so as to satisfy c13' < c13.

[0035] In addition, when the interval between adjacent pads 3 is narrow, the semiconductor elements 5 may be shifted in a direction in which the interval between the corresponding adjacent semiconductor elements 5 is wider than when the semiconductor elements 5 are not shifted. This makes it possible to prevent two adjacent semiconductor elements 5 from overlapping. In addition, when the interval between adjacent pads 3 is wide and there is a low possibility that two adjacent semiconductor elements 5 will overlap, it is not necessary to shift the semiconductor elements 5 in a direction in which the interval between the adjacent semiconductor elements 5 is wider.

[0036] Next, the features of the semiconductor device 1 manufactured according to this embodiment will be described.

[0037] FIG. 6 is a cross-sectional view illustrating a state before and after a solder melting step in the method for manufacturing a semiconductor device according to the first embodiment.

[0038] Before the solder melting process, the solder 4 and the semiconductor element 5 are arranged offset from the pad 3 as shown in the upper left of Fig. 6, but after the solder melting process, the self-alignment effect works and the offset between the solder 4 and the semiconductor element 5 becomes smaller as shown in the upper right of Fig. 6. In the solder melting process, the solder 4 is exposed to the outside air less on the side of the outer periphery of the solder where the semiconductor element 5 protrudes and the outer periphery of the solder 4 is located under the semiconductor element 5, so that after the solder melting process, the Cu6Sn5 phase of the solder 4 is distributed separately at the connection interface with the pad 3 and the connection interface with the semiconductor element 5 as shown in the lower right of Fig. 6. On the other hand, on the side where the outer periphery of the solder 4 is exposed out of the semiconductor element 5, the outer periphery of the solder 4 is exposed to the outside air more, so that the distribution of the Cu6Sn5 phase of the solder 4 is nearly uniform as shown in the lower left of Fig. 6.

[0039] FIG. 7 is a cross-sectional view illustrating a state before and after a solder melting step in a manufacturing method for a semiconductor device according to a comparative example.

[0040] In the semiconductor device 1 of the comparative example, before the solder melting process, the solder 4 and the semiconductor element 5 are not displaced from the positions of the pads 3 as shown in the upper left of Fig. 7, and even after the solder melting process, the solder 4 and the semiconductor element 5 are not displaced from the positions of the pads 3 as shown in the upper right of Fig. 7. Therefore, in the solder melting process, the outer periphery of the solder 4 is exposed to the outside air, and as shown in the lower left and lower right of Fig. 7, the distribution of the Cu6Sn5 phase of the solder 4 is nearly uniform everywhere on the outer periphery of the solder 4.

[0041] 6 and 7 and the arrangement described in Fig. 1 and 5, the semiconductor device 1 manufactured in this embodiment is a semiconductor device 1 having a substrate 2 with a plurality of pads 3, a plurality of semiconductor elements 5, and solder 4 joining the pads 3 and the semiconductor elements 5, and the distribution of the Cu6Sn5 phase of the solder 4 is more uniform in the solder periphery between the adjacent semiconductor elements 5 than in the solder periphery on the opposite side. Here, in the solder periphery on the opposite side described above, the Cu6Sn5 phase of the solder 4 is distributed separately at the connection interface with the pad 3 and the connection interface with the semiconductor element 5.

[0042] Next, the placement process in this embodiment will be described in detail.

[0043] FIG. 8 is a top view for explaining the amount of misalignment in the placement process in the manufacturing method of the semiconductor device according to the first embodiment.

[0044] In this embodiment, in the placement step, it is desirable to place the pads 3, the solder 4, and the semiconductor elements 5 such that the amount of misalignment does not exceed an allowable threshold value.

[0045] To explain one example, the above-mentioned allowable threshold value can be calculated based on, for example, the length W of the short side of the pad 3 and a correction coefficient D, for example, by W×D.

[0046] The molten solder 4 flows toward the center of the pad 3 due to the self-alignment effect. At this time, the semiconductor element 5 placed on the solder 4 also flows together with the solder 4. Here, the magnitude of the self-alignment effect is largely dependent on the composition of the solder 4, the solder form, and the connection temperature. The lower the connection temperature, the greater the volume ratio of the Cu6Sn5 phase in the molten solder 4, and therefore the higher the viscosity becomes, and the higher the viscosity becomes, the smaller the correction coefficient D becomes. Therefore, this correction coefficient D may be determined based on, for example, the solder composition, the solder form (solder paste or solder sheet), and the temperature of the solder 4 in the solder melting process.

[0047] Then, for example, the solder 4 is arranged within a range that satisfies the allowable threshold value W×D>d1+d2 using the amount of deviation d1 of the solder 4 in the short side direction of the pad 3 and the amount of deviation d2 of the solder 4 in the long side direction of the pad 3. Furthermore, for example, the semiconductor element 5 is arranged within a range that satisfies the allowable threshold value W×D>e1+e2 using the amount of deviation e1 of the semiconductor element 5 from the solder 4 in the short side direction of the pad 3 and the amount of deviation e2 of the semiconductor element 5 from the solder 4 in the long side direction of the pad 3.

[0048] The above example is merely an example, and the method of setting the allowable threshold value, the method of setting the deviation amount, and the concept of the correction coefficient are not limited to the above example. Also, for example, the length L of the long side of the pad 3 may be taken into consideration. EXAMPLES

[0049] FIG. 9 is a top view illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0050] In the second embodiment, a solder sheet is placed as the solder 4 after the flux 7 is applied to the pads 3 in the placement step.

[0051] The flux 7 is also called a soldering promoter. By applying the flux 7 to the pads 3, the oxide film that inhibits the wetting of the solder 4 can be removed.

[0052] When a solder paste is used as the solder 4, the solder paste usually contains the flux 7, so there is no need to provide a separate step of applying the flux 7 to the pads 3.

[0053] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0054] 1 Semiconductor device 2. Board 3 Pad 3A 1st Pad 3B 2nd pad 3C 3rd Pad 4. Solder 4A 1st solder 4B Second solder 4C 3rd solder 5. Semiconductor elements 5A First Semiconductor Element 5B Second semiconductor element 5C Third Semiconductor Element 6. Insulating film 7. Flux

Claims

1. A method for manufacturing a semiconductor device in which a plurality of semiconductor elements are bonded via solder onto a substrate having a plurality of pads, the method comprising the steps of: the plurality of pads includes a first pad and a second pad adjacent to the first pad; the solder includes a first solder arranged corresponding to the first pad and a second solder arranged corresponding to the second pad; the plurality of semiconductor elements include a first semiconductor element having a first electrode bonded to the first pad and a second semiconductor element having a second electrode bonded to the second pad; a placement step of placing the solder and the semiconductor elements on the pads by shifting the center positions of the pads and the semiconductor elements so that a12<c12 is satisfied, where a12 is a center distance between the first pad and the second pad, and c12 is a center distance between the first electrode and the second electrode; a solder melting step of melting the solder after the placing step.

2. In claim 1, A method for manufacturing a semiconductor device, characterized in that when the center-to-center distance between the first electrode and the second electrode in a state in which the solder is solidified after the solder melting step is c12', c12' < c12.

3. In claim 1, The method for manufacturing a semiconductor device, wherein the arrangement step is a step of arranging the first solder and the second solder so as to satisfy a12≦b12≦c12, where b12 is a center-to-center distance between the first solder and the second solder.

4. In claim 1, a first solder layer and a second solder layer, the second solder layer being spaced apart from each other by a distance of about 100 μm from the first solder layer and about 100 μm from the second solder layer;

5. In claim 1, The method for manufacturing a semiconductor device is characterized in that the solder contains Sn as a main component and 3 to 10 wt % Cu.

6. In claim 5, 4. The method for manufacturing a semiconductor device, wherein the solder melting step is a step of heating the solder to a temperature in the range of not less than the solidus temperature but not more than 300°C.

7. In claim 1, 4. The method for manufacturing a semiconductor device, wherein the solder is a solder paste.

8. In claim 1, 4. The method for manufacturing a semiconductor device, wherein the solder is a solder sheet.

9. In claim 8, 4. A method for manufacturing a semiconductor device, comprising the steps of: applying flux to the plurality of pads; and then arranging the solder sheet.

10. In claim 1, 4. A method for manufacturing a semiconductor device, comprising the steps of: placing the semiconductor elements on the substrate; and forming a first semiconductor element on the substrate;

11. In claim 10, 4. A method for manufacturing a semiconductor device, comprising the steps of: calculating the permissible threshold value based on lengths of the short sides of the plurality of pads and a correction coefficient;

12. In claim 11, 4. A method for manufacturing a semiconductor device, comprising the steps of: determining the correction coefficient based on a solder composition, a solder form, and a temperature of the solder in the solder melting step;

13. In claim 1, the plurality of pads includes a third pad adjacent to the first pad; the solder includes a third solder arranged corresponding to the third pad; the plurality of semiconductor elements includes a third semiconductor element having a third electrode bonded to the third pad; a13 is a center-to-center distance between the first pad and the third pad, and c13 is a center-to-center distance between the first electrode and the third electrode.

14. A semiconductor device comprising: a substrate having a plurality of pads; a plurality of semiconductor elements; and solder for joining the pads and the semiconductor elements, A semiconductor device, characterized in that the distribution of the Cu6Sn5 phase of the solder is more uniform in the outer periphery of the solder between the adjacent semiconductor elements than in the outer periphery of the solder on the opposite side.

15. In claim 14, A semiconductor device, characterized in that, in the outer periphery of the solder on the opposite side, the Cu6Sn5 phase of the solder is distributed separately at the connection interface with the pad and the connection interface with the semiconductor element.

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