Semiconductor device, semiconductor system, and switching power source device

Abstract

To make it possible to set a mode without requiring an exclusive terminal.SOLUTION: A semiconductor device includes: a synchronous input terminal (S_IN); a synchronous output terminal (S_OUT); a functional circuit (20) including a circuit for generating a reference clock signal (CLKa); a signal output circuit (40); and a mode setting circuit (60) for setting an operation mode of the functional circuit and the signal output circuit at a first mode or a second mode through mode determination processing. The functional circuit performs a predetermined functional operation in synchronization with the reference clock signal in the first mode, and performs the functional operation in synchronization with an input clock signal supplied from another semiconductor device to the synchronous input terminal in the second mode. The signal output circuit outputs a clock signal based on the reference clock signal from the synchronous output terminal in the first mode. In mode determination processing, the mode setting circuit determines whether or not a specific voltage satisfying predetermined conditions is supplied to the synchronous output terminal from the outside of the semiconductor device.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a semiconductor system, and a switching power supply device. [Background technology]

[0002] A configuration in which multiple semiconductor devices are synchronized is sometimes adopted. For example, a method is known in which a multi-phase DC / DC converter is configured by synchronizing multiple channels of DC / DC converters (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-6829

[0004] [overview] When configuring a system including multiple semiconductor devices, the multiple semiconductor devices are often operated in different operation modes. The operation mode can be set by providing each semiconductor device with a dedicated terminal for setting the operation mode, but providing the dedicated terminal hinders miniaturization and cost reduction of the semiconductor device.

[0005] A semiconductor device according to one embodiment of the present disclosure comprises a functional circuit having a synchronous input terminal, a synchronous output terminal, and a reference clock signal generation circuit configured to generate a reference clock signal, a signal output circuit connected to the synchronous output terminal, and a mode setting circuit configured to perform a mode determination process and then set an operation mode of the functional circuit and the signal output circuit to a first mode or a second mode based on a result of the mode determination process, wherein in the first mode, the functional circuit performs a predetermined functional operation in synchronization with the reference clock signal, and in the second mode, the functional circuit performs the functional operation in synchronization with an input clock signal supplied to the synchronous input terminal from another semiconductor device, and in the first mode, the signal output circuit outputs a clock signal based on the reference clock signal from the synchronous output terminal, and in the mode determination process, the mode setting circuit determines whether a specific voltage satisfying predetermined conditions is supplied to the synchronous output terminal from outside the semiconductor device. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is an overall configuration diagram of a switching power supply device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of the power supply control device according to the embodiment of the present disclosure. [Diagram 3] FIG. 3 is an overall configuration diagram of a switching power supply device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating an internal configuration of a power supply control device according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is an operation flowchart of the power supply control device according to the embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating an internal configuration of the first power supply control device according to the embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating an internal configuration of a second power supply control device according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a waveform diagram of some signals in the first power control device according to an embodiment of the present disclosure. [Figure 9]FIG. 9 is a waveform diagram of some signals in the second power control device according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a relationship diagram of two clock signals according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a circuit diagram of a synchronization management circuit according to a first example of an embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram illustrating one DFF according to a first example belonging to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a timing chart at the start-up of the first power supply control device according to a first example belonging to an embodiment of the present disclosure. [Figure 14] FIG. 14 is an explanatory diagram of signal states at the time of start-up of the first power supply control device according to the first example belonging to the embodiment of the present disclosure. [Figure 15] FIG. 15 is an explanatory diagram of signal states at the time of start-up of the first power supply control device according to the first example belonging to the embodiment of the present disclosure. [Figure 16] FIG. 16 is an explanatory diagram of signal states at the time of start-up of the first power supply control device according to the first example belonging to the embodiment of the present disclosure. [Figure 17] FIG. 17 relates to a first example belonging to an embodiment of the present disclosure and is an explanatory diagram of signal states at the time of start-up of the first power supply control device. [Figure 18] FIG. 18 is an explanatory diagram of signal states at the time of start-up of the first power supply control device according to the first example belonging to the embodiment of the present disclosure. [Figure 19] FIG. 19 is an explanatory diagram of signal states at the time of start-up of the second power supply control device according to the first example belonging to the embodiment of the present disclosure. [Figure 20] FIG. 20 is an explanatory diagram of signal states at the time of start-up of the second power supply control device according to the first example belonging to the embodiment of the present disclosure. [Figure 21] FIG. 21 is a circuit diagram of a synchronization management circuit according to a second embodiment of the present disclosure. [Figure 22]FIG. 22 is a modified configuration diagram of a switching power supply device according to a fourth example of an embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from ground.

[0009] A level refers to a level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. For any signal of interest, when the signal has a high level, the inverted signal of the signal has a low level, and when the signal has a low level, the inverted signal of the signal has a high level.

[0010] In any signal or voltage of interest, a transition from a low level to a high level may be referred to as a rising edge, and a transition from a high level to a low level may be referred to as a falling edge.

[0011] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." In addition, unless otherwise specified, the backgate of any MOSFET can be considered to be shorted to the source.

[0012] Hereinafter, the on and off states of any transistor may be simply expressed as on and off. For any transistor, switching from the off state to the on state is expressed as turning on, and switching from the on state to the off state is expressed as turning off. Also, for any transistor, the period during which the transistor is in the on state is referred to as the on period, and the period during which the transistor is in the off state is referred to as the off period.

[0013] For any signal that takes a high or low signal level, the period during which the signal level is high is called a high-level period, and the period during which the signal level is low is called a low-level period. The same applies to any voltage that takes a high or low voltage level.

[0014] Unless otherwise specified, the connection between multiple parts that form a circuit, such as any circuit elements, wiring, nodes, etc., may be understood to refer to an electrical connection.

[0015] FIG. 1 shows the overall configuration of a switching power supply device 1 according to an embodiment of the present disclosure. The switching power supply device 1 receives a positive input voltage Vin from a voltage source (not shown) and generates a positive output voltage Vout by stepping down the input voltage Vin. Therefore, the output voltage Vout is lower than the input voltage Vin. The switching power supply device 1 stabilizes the output voltage Vout at a predetermined target voltage. That is, in a steady state, the output voltage Vout substantially coincides with the target voltage. Hereinafter, the target voltage will be referred to by the symbol "Vtg". The switching power supply device 1 includes two power supply control devices 10. Wiring provided outside the two power supply control devices 10 may be specifically referred to as external wiring.

[0016] The switching power supply device 1 may be mounted on a vehicle such as an automobile. In this case, the input voltage Vin may be the output voltage of a battery mounted on the vehicle. In addition, the switching power supply device 1 may be provided in any device (for example, a smartphone, a portable information terminal, a computer device, a game device, a television device, or an air conditioner).

[0017] FIG. 2 is an external perspective view of one power supply control device 10. The power supply control device 10 is an electronic component (semiconductor device) including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the power supply control device 10. The power supply control device 10 is formed by sealing the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply control device 10 and the type of housing of the power supply control device 10 shown in FIG. 2 are merely examples, and they can be designed arbitrarily. The plurality of external terminals provided in the power supply control device 10 include an input terminal IN, a switch terminal SW, a ground terminal GND, a feedback terminal FB, an error sharing terminal CMPOUT, a synchronization input terminal S_IN, a synchronization output terminal S_OUT, and an internal power supply output terminal REG. External terminals other than these may also be provided in the power supply control device 10. Note that the synchronization input terminal can be read as a synchronization clock input terminal, and the synchronization output terminal can be read as a synchronization clock output terminal.

[0018] In the switching power supply 1, a coil L is provided for each power supply control device 10. The coil L is provided outside the power supply control device 10. A first end of the coil L associated with a certain power supply control device 10 is connected to a switch terminal SW of the certain power supply control device 10. Second ends of all the coils L are commonly connected to an output terminal OUT. In each coil L, a current flowing through the coil L is referred to as a coil current IL. In principle, the coil current IL flows from the switch terminal SW to the output terminal OUT (only the principle will be considered below).

[0019] The switching power supply device 1 is further provided with an output capacitor Cout and feedback resistors R1 and R2. The output capacitor Cout is inserted between the output terminal OUT and ground. That is, a first end of the output capacitor Cout is connected to the output terminal OUT, and a second end of the output capacitor Cout is connected to ground. The voltage at the output terminal OUT is the output voltage Vout. That is, the output terminal OUT is the application terminal of the output voltage Vout. A load LD is connected to the output terminal OUT. The load LD is any load that is driven based on the output voltage Vout.

[0020] A first end of the feedback resistor R1 is connected to the output terminal OUT, a second end of the feedback resistor R1 is connected to a first end of the feedback resistor R2, and a second end of the feedback resistor R2 is connected to ground. A feedback voltage Vfb according to the output voltage Vout is generated at a connection node between the feedback resistors R1 and R2. The feedback voltage Vfb is a divided voltage of the output voltage Vout, and is therefore proportional to the output voltage Vout. The feedback resistors R1 and R2 form a feedback voltage generating circuit that generates the feedback voltage Vfb. The feedback terminal FB of each power supply control device 10 is connected to the connection node between the feedback resistors R1 and R2 and receives the feedback voltage Vfb. The output voltage Vout itself may be used as the feedback voltage Vfb. In any case, the feedback voltage Vfb is a voltage according to the output voltage Vout.

[0021] The two power supply control devices 10 can be referred to as the first and second power supply control devices 10. Of the first and second power supply control devices 10, the first power supply control device 10 operates in a first mode (leader mode), and the second power supply control device 10 operates in a second mode (follower mode), as will be described in detail later. The feedback voltage Vfb may be applied only to the feedback terminal FB of the first power supply control device 10 operating in the first mode.

[0022] An input voltage Vin is supplied to the input terminal IN of each power supply control device 10. The ground terminal GND of each power supply control device 10 is connected to ground. The two error sharing terminals CMPOUT of the two power supply control devices 10 are connected to each other via external wiring Wc. The synchronous output terminal S_OUT of the first power supply control device 10 and the synchronous input terminal S_IN of the second power supply control device 10 are connected to each other via external wiring Ws.

[0023] Each power supply control device 10 has an internal power supply circuit (internal power supply circuit 80 described below; see FIG. 4) that generates an internal power supply voltage Vreg based on an input voltage Vin, and outputs the generated internal power supply voltage Vreg from an internal power supply output terminal REG. A capacitor Creg is provided outside the power supply control device 10 for each power supply control device 10. The capacitor Creg for each power supply control device 10 is inserted between the internal power supply output terminal REG and ground.

[0024] A set of one power supply control device 10 and one coil L cooperates with an output capacitor Cout to form a DC / DC converter for one channel that performs current mode control. Therefore, a two-channel DC / DC converter is formed in the switching power supply device 1. The output capacitor Cout is shared by the two-channel DC / DC converter. However, an output capacitor Cout may be provided for each channel. In the switching power supply device 1, a signal corresponding to the feedback voltage Vfb (an error signal, described later) is shared by the power supply control devices 10 of all channels, and multi-phase control can be performed by shifting the switching phase between multiple channels.

[0025] In the following, in order to clearly distinguish the first and second power supply control devices 10, as necessary, the first power supply control device 10 may be referred to as "10[1]" and the second power supply control device 10 may be referred to as "10[2]" as shown in FIG. 3. In addition, the coils L associated with the power supply control devices 10[1] and 10[2] are referred to as coils L[1] and L[2], respectively. That is, the switch terminal SW of the power supply control device 10[i] is connected to the first end of the coil L[i], and the second end of the coil L[i] is connected to the output terminal OUT. The coil current IL flowing through the coil L[i] may be specifically referred to as the coil current IL[i]. i represents any integer.

[0026] Furthermore, the synchronous input terminal S_IN and the synchronous output terminal S_OUT in the power supply control device 10[i] may be specifically referred to as the synchronous input terminal S_IN[i] and the synchronous output terminal S_OUT[i], respectively. In the switching power supply device 1, the synchronous input terminal S_IN[1] is open. The synchronous input terminal S_IN[1] may be connected to ground. In the switching power supply device 1, the synchronous output terminal S_OUT[1] is connected to the synchronous input terminal S_IN[2] via the external wiring Ws. In the switching power supply device 1, the synchronous output terminal S_OUT[2] is connected to the internal power output terminal REG of the power supply control device 10[2] via the external wiring Wr, and is therefore supplied with the internal power supply voltage Vreg.

[0027] FIG. 4 shows the internal configuration of one power supply control device 10. The internal configurations of the power supply control devices 10[1] and 10[2] are the same. Therefore, the internal configuration of the power supply control device 10 will be described by focusing on one power supply control device 10. However, there are some parts in which the operation of the power supply control devices 10[1] and 10[2] differs, and such parts will be explained as appropriate. The power supply control device 10 includes an output stage MM and a switching control circuit 20 for switching control of the output stage MM, as well as a synchronization management circuit 30 and an internal power supply circuit 80. The synchronization management circuit 30 includes a signal output circuit 40 connected to the synchronization output terminal S_OUT, and a mode setting circuit 60. Hereinafter, for the sake of simplicity, the power supply control devices 10, 10[i] are often abbreviated to device 10, 10[i].

[0028] The output stage MM is provided between an application end (input terminal IN) of the input voltage Vin and an application end (output terminal OUT) of the output voltage Vout, and generates the output voltage Vout in cooperation with the coil L and the output capacitor Cout through switching of the input voltage Vin. The output stage MM includes transistors MH and ML configured as N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, ground). When they are switched (switched) controlled (switched driven), the input voltage Vin is switched and a square-wave switch voltage appears at the switch terminal SW. The transistor MH is provided on a higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input terminal IN, which is the application end of the input voltage Vin, and is supplied with the input voltage Vin. The source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW. The source of the transistor ML is connected to the ground terminal GND (and therefore to ground). However, a resistor for current detection may be inserted between the source of the transistor ML and the ground terminal GND.

[0029] The transistor MH functions as an output element (output transistor), and the transistor ML functions as a rectifier element (synchronous rectifier transistor). In the switching control of the output stage MM, the output element (MH) and the rectifier element (ML) are alternately turned on and off. The coil L and output capacitor Cout connected to the switch terminal SW form a rectifying and smoothing circuit that rectifies and smoothes the square-wave-shaped switch voltage that appears at the switch terminal SW (see also Figure 1).

[0030] Gate signals GH and GL are supplied to the gates of the transistors MH and ML as drive signals, respectively, and the transistors MH and ML are turned on and off in response to the gate signals GH and GL. When the gate signal GH is at a high level, the transistor MH is turned on, and when the gate signal GH is at a low level, the transistor MH is turned off. Similarly, when the gate signal GL is at a high level, the transistor ML is turned on, and when the gate signal GL is at a low level, the transistor ML is turned off. Basically, the transistors MH and ML are turned on and off alternately, but both the transistors MH and ML may be maintained in an off state. The transistors MH and ML are never turned on at the same time. At least one of the output element (MH) and the rectifier element (ML) may be provided outside the device 10. The entire output stage MM may be provided outside the device 10.

[0031] During the ON period of the transistor MH, the coil current IL flows through the channel (between the drain and source) of the transistor MH, and during the OFF period of the transistor MH, the coil current IL flows through the channel of the transistor ML or the parasitic diode of the transistor ML.

[0032] The input voltage Vin is power-converted into the output voltage Vout by controlling the switching of the output stage MM. A switching control circuit 20 is responsible for controlling the switching of the output stage MM, and converts the input voltage Vin into the output voltage Vout by controlling the switching of the output stage MM. In the switching control, the switching control circuit 20 controls the on / off states of the transistors MH and ML through level control of the gate signals GH and GL, thereby generating a desired output voltage Vout at the output terminal OUT. When the two switching control circuits 20 in the two devices 10 simultaneously perform switching control, the input voltage Vin is converted into the output voltage Vout by the cooperation of the two devices 10.

[0033] The gate signal GL is a signal based on the ground potential, whereas the gate signal GH is a signal based on the potential of the switch terminal SW. A low-level gate signal GH has the potential of the switch terminal SW, and a high-level gate signal GH is a predetermined voltage higher than the potential of the switch terminal SW. The predetermined voltage here is higher than the gate threshold voltage of the transistor MH. A well-known bootstrap circuit (not shown) can be used to generate a boost power supply for generating the gate signal GH. The transistor MH may be configured as a P-channel MOSFET, in which case a boost power supply is not required.

[0034] As a modification, a diode rectification method may be adopted in the device 10. In this case, a synchronous rectification diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW is used as the rectification element instead of the transistor ML. In this case, only the output element (MH) is turned on and off in the switching control of the output stage MM. In either case, the output element (MH) is switched between on and off in the switching control of the output stage MM, and an output voltage Vout is generated based on the current (IL) flowing through the coil L.

[0035] Prior to a detailed description of the operation of the switching control circuit 20, the mode setting circuit 60 provided in the device 10 will be described with reference to FIG. 5. FIG. 5 is an operation flowchart of the device 10. When the supply of the input voltage Vin to the device 10 starts in step STP1, the device 10 executes an initial setting process in step STP2. The period during which the initial setting process is executed is called the initial setting period. In the initial setting process, initialization of each signal in the device 10 is performed. The initial setting process includes a mode determination process. Therefore, the mode determination process is executed in the initial setting period. After the initial setting process is completed, the device 10 executes a normal operation in step STP3. The period during which the normal operation is executed is called the normal operation period. After the start of the normal operation, the normal operation is basically executed continuously until the supply of the input voltage Vin is interrupted.

[0036] In the device 10[i], the mode setting circuit 60 executes a mode determination process and sets the operation mode of the device 10[i] to the first mode or the second mode based on the result of the mode determination process. In the switching power supply device 1, the operation mode of the device 10[1] is set to the first mode, and the operation mode of the device 10[2] is set to the second mode, and the method of setting the operation mode will be described later.

[0037] The mode setting circuit 60 supplies a mode setting signal MODE indicating the setting result of the operation mode to each circuit in the device 10. Specifically, when the mode setting circuit 60 of the device 10[i] sets the operation mode of the device 10[i] to the first mode, it supplies a first mode setting signal MODE indicating that to each circuit in the device 10[i]. When the mode setting circuit 60 of the device 10[i] sets the operation mode of the device 10[i] to the second mode, it supplies a second mode setting signal MODE indicating that to each circuit in the device 10[i]. In the switching power supply device 1, after the mode determination process, the first mode setting signal MODE is supplied to each circuit in the device 10[1], while the second mode setting signal MODE is supplied to each circuit in the device 10[2]. Hereinafter, the device 10 in the first mode refers to the device 10 in which the first mode is set as the operation mode, and the device 10 in the second mode refers to the device 10 in which the second mode is set as the operation mode.

[0038] Among the operations of the device 10, the operations of the switching control circuit 20 and the signal output circuit 40 in particular depend greatly on the setting of the operation mode. For this reason, the operation mode of the device 10 (which may hereinafter be simply referred to as the operation mode) can be understood as the operation mode of the switching control circuit 20 and the signal output circuit 40 among the components of the device 10. As shown in FIG. 4, a mode setting signal MODE is supplied to the switching control circuit 20 and the signal output circuit 40.

[0039] The internal configuration of the switching control circuit 20 and the operation of each part in the switching control circuit 20 during the normal operation period will be described below. The normal operation (see FIG. 5) includes the operation of each part in the switching control circuit 20 as follows. The switching control circuit 20 includes an error amplifier 21, a sense circuit 22, a reset circuit 23, a switch circuit 24, a set circuit 25, and a controller 26.

[0040] The error amplifier 21 is a current output type transconductance amplifier. The error amplifier 21 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 21 is connected to a feedback terminal FB. A predetermined reference voltage Vref is supplied to the non-inverting input terminal of the error amplifier 21. The reference voltage Vref is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the device 10. The output terminal of the error amplifier 21 is connected to a wiring WR1.

[0041] The error amplifier 21 operates only in the device 10 in the first mode, and the error amplifier 21 in the device 10 in the second mode is inactive (does not operate). In the device 10[i], the first or second mode setting signal MODE from the mode setting circuit 60 is supplied to the switching control circuit 20. When the first mode setting signal MODE is supplied to the switching control circuit 20, the switching control circuit 20 operates the error amplifier 21, and when the second mode setting signal MODE is supplied to the switching control circuit 20, the switching control circuit 20 deactivates the error amplifier 21 (stops the operation of the error amplifier 21). Therefore, of the error amplifiers 21 of the devices 10[1] and 10[2], only the error amplifier 21 of the device 10[1] operates. Note that, when the device 10[1] is started, a soft start control may be performed to gradually increase the value of the reference voltage Vref from 0V to a positive predetermined voltage value, but the existence of the soft start control will be ignored below.

[0042] In device 10[1], a feedback voltage Vfb is input to the inverting input terminal of error amplifier 21. The error amplifier 21 outputs a current signal corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref from its output terminal, thereby generating an error signal CMP corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref on wiring WR1. The error signal CMP and the signals Isns, SET, and RST described later are all voltage signals. In any voltage signal, the rise and fall of the voltage signal mean the rise and fall of the potential of the voltage signal. The same applies to other similar expressions.

[0043] In device 10[1], when "Vfb < Vref" holds, the error amplifier 21 outputs a current from its output terminal toward wiring WR1 so that the potential of the error signal CMP rises, and when "Vfb > Vref" holds, it draws a current from wiring WR1 toward its output terminal so that the potential of the error signal CMP falls. Although not particularly shown, a phase compensation circuit including a capacitor may be connected between wiring WR1 and ground.

[0044] The sense circuit 22 detects the coil current IL and generates a sense signal Isns representing the detection result of the coil current IL. As the coil current IL increases, the potential of the sense signal Isns rises, and as the coil current IL decreases, the potential of the sense signal Isns falls. The coil current IL detected by the sense circuit 22 of device 10[i] is the coil current IL[i].

[0045] The sense circuit 22 can generate the sense signal Isns by detecting the current flowing through the transistor MH (therefore the coil current IL) during the on period of the transistor MH, or by detecting the current flowing through the transistor ML (therefore the coil current IL) during the on period of the transistor ML. Alternatively, a shunt resistor (not shown) can be inserted between the connection node between the transistors MH and ML and the coil L. At this time, the sense circuit 22 can generate the sense signal Isns based on the voltage drop of the shunt resistor. In addition, the sense signal Isns may be generated by detecting the voltage at any location where a voltage corresponding to the coil current IL is generated.

[0046] The reset circuit 23 has input terminals in1 and in2. A sense signal Isns is supplied to the input terminal in2 of the reset circuit 23. A switch circuit 24 is provided between the input terminal in1 of the reset circuit 23, the wiring WR1, and the error sharing terminal CMPOUT. The switch circuit 24 has either a first switch state or a second switch state. When a first mode setting signal MODE is supplied to the switching control circuit 20, the switching control circuit 20 sets the switch circuit 24 to the first switch state, and when a second mode setting signal MODE is supplied to the switching control circuit 20, the switching control circuit 20 sets the switch circuit 24 to the second switch state. Therefore, the switch circuit 24 of the device 10[1] is set to the first switch state, and the switch circuit 24 of the device 10[2] is set to the second switch state.

[0047] FIG. 6 shows the state in which the switch circuit 24 of the device 10[1] is set to the first switch state, and FIG. 7 shows the state in which the switch circuit 24 of the device 10[2] is set to the second switch state. In the device 10[1], as shown in FIG. 6, the switch circuit 24 in the first switch state connects the wiring WR1 to the input terminal in1 of the reset circuit 23 and the error sharing terminal CMPOUT. Therefore, the error signal CMP generated by the error amplifier 21 in the device 10[1] is input to the input terminal in1 of the reset circuit 23 in the device 10[1]. In the device 10[2], as shown in FIG. 7, the switch circuit 24 in the second switch state connects the error sharing terminal CMPOUT to the input terminal in1 of the reset circuit 23 while disconnecting the wiring WR1 from the input terminal in1 of the reset circuit 23. As described above, the error sharing terminals CMPOUT in devices 10[1] and 10[2] are connected to each other via external wiring Wc (see FIG. 3), and therefore the error signal CMP generated by the error amplifier 21 in device 10[1] is also input to the input terminal in1 of the reset circuit 23 in device 10[2].

[0048] In addition, Fig. 6 shows the state in which the device 10[1] outputs the clock signal CLKb from the synchronous output terminal S_OUT[1] during normal operation. Fig. 7 shows the state in which the clock signal CLKb is input to the synchronous input terminal S_IN[2] of the device 10[2] during normal operation. The contents of the clock signal CLKb will be described later.

[0049] The reset circuit 23 generates and outputs a signal RST using pulse width modulation based on the error signal CMP and the sense signal Isns supplied to the input terminals in1 and in2.

[0050] The set circuit 25 has an oscillator circuit 25a, and generates and outputs a signal SET. The signals SET and RST are binary signals having a high level or a low level. The oscillator circuit 25a is an example of a reference clock signal generating circuit that generates and outputs a reference clock signal CLKa. The reference clock signal CLKa is a clock signal having a predetermined frequency fpwm. Any clock signal has a high level and a low level alternately. A clock signal CLKb different from the reference clock signal CLKa may be input to the synchronization input terminal S_IN from outside the device 10. The set circuit 25 generates and outputs a binary signal based on the reference clock signal CLKa or a binary signal based on the clock signal CLKb as the signal SET.

[0051] FIG. 8 shows some signal waveforms in the device 10[1]. In the device 10[1] operating in the first mode, the set circuit 25 generates and outputs the signal SET based on the reference clock signal CLKa. The set circuit 25 in the device 10[1] sets the level of the signal SET to a low level as a rule, and sets the level of the signal SET to a high level for a very short period of time when a rising edge of the reference clock signal CLKa occurs. Therefore, in the device 10[1], a rising edge occurs in the signal SET at the timing of the rising edge of the reference clock signal CLKa. In the device 10[1], the reference clock signal CLKa itself may be used as the signal SET.

[0052] In the switching power supply device 1, during normal operation, the clock signal CLKb output from the synchronous output terminal S_OUT[1] is input to the synchronous input terminal S_IN[2] (see also Figures 6 and 7). The clock signal CLKb is an output clock signal for the device 10[1] and an input clock signal for the device 10[2].

[0053] FIG. 9 shows some signal waveforms in the device 10[2]. In the device 10[2] operating in the second mode, the set circuit 25 generates and outputs the signal SET based on the input clock signal CLKb. The set circuit 25 in the device 10[2] sets the level of the signal SET to a low level as a rule, and sets the level of the signal SET to a high level for a very short period of time when a rising edge of the input clock signal CLKb occurs. Therefore, in the device 10[2], a rising edge occurs in the signal SET at the timing of the rising edge of the input clock signal CLKb. In the device 10[2], the input clock signal CLKb itself may be used as the signal SET.

[0054] A signal SET from the set circuit 25 and a signal RST from the reset circuit 23 are input to a controller 26 (see FIG. 4). In response to a rising edge of the signal SET, the controller 26 generates a rising edge in the gate signal GH to turn on the transistor MH and generates a falling edge in the gate signal GL to turn off the transistor ML. Then, in response to a rising edge of the signal RST, the controller 26 generates a falling edge in the gate signal GH to turn off the transistor MH and generates a rising edge in the gate signal GL to turn on the transistor ML.

[0055] The signal SET in device 10[1] is synchronized with the reference clock signal CLKa generated within device 10[1]. Therefore, the controller 26 in device 10[1] will perform switching control of the output stage MM in synchronization with the reference clock signal CLKa generated within device 10[1]. In contrast, the signal SET in device 10[2] is synchronized with the input clock signal CLKb supplied to the synchronization input terminal S_IN[2]. Therefore, the controller 26 in device 10[2] will perform switching control of the output stage MM in synchronization with the input clock signal CLKb supplied to the synchronization input terminal S_IN[2].

[0056] When “Vout = Vtg”, “Vfb = Vref”. When “Vfb < Vref” due to an increase in the supply current to the load LD or the like, the error signal CMP rises. The reset circuit 23 generates the signal RST so that the on-duty of the output stage MM increases when “CMP > Isns” as the error signal CMP rises. The increase in the on-duty of the output stage MM results in an increase in the coil current IL, and the increase in the coil current IL raises the output voltage Vout and the sense signal Isns. Conversely, when “Vfb > Vref” due to a decrease in the supply current to the load LD or the like, the error signal CMP drops. The reset circuit 23 generates the signal RST so that the on-duty of the output stage MM decreases when “CMP < Isns” as the error signal CMP drops. The decrease in the on-duty of the output stage MM results in a decrease in the coil current IL, and the decrease in the coil current IL lowers the output voltage Vout and the sense signal Isns. Thus, in the switching power supply device 1 (in the device 10 where switching control is executed), control is performed to reduce the difference between the output voltage Vout and the target voltage Vtg.

[0057] The on-duty of the output stage MM represents the ratio of the on-period of the transistor MH to the sum of the on-period and off-period of the transistor MH. There are various configurations for performing switching control of the output stage MM based on the information (Vfb) of the output voltage Vout and the information (Isns) of the coil current IL, and any configuration for realizing such switching control may be adopted by the switching control circuit 20.

[0058] In the switching power supply device 1, during the normal operation period, current is supplied from the application terminal of the input voltage Vin to the application terminal of the output voltage Vout through each output stage MM of the devices 10[1] and 10[2]. At this time, since current mode control is performed using a common error signal CMP between the devices 10[1] and 10[2], the magnitudes of the coil currents IL[1] and IL[2] are approximately the same.

[0059] An explanation is added regarding the operation of the mode setting circuit 60. The mode setting circuit 60 in the device 10[i] determines, in the mode determination process, whether a specific voltage is supplied to the synchronous output terminal S_OUT[i] from the outside of the device 10[i]. A state in which a specific voltage is supplied to the synchronous output terminal S_OUT[i] is referred to as a specific voltage supply state, and a state in which no specific voltage is supplied to the synchronous output terminal S_OUT[i] is referred to as a specific voltage non-supply state.

[0060] The specific voltage is a voltage that satisfies a predetermined condition. The specific voltage that satisfies the predetermined condition is a voltage having a value equal to or higher than a predetermined upper threshold voltage Vth_H. In the synchronous management circuit 30, a level equal to or higher than the upper threshold voltage Vth_H belongs to the high level. That is, in each signal in the synchronous management circuit 30, the high level refers to a potential equal to or higher than a predetermined upper threshold voltage Vth_H. In each signal in the synchronous management circuit 30, the low level refers to a potential equal to or lower than a predetermined lower threshold voltage Vth_L. Here, "0 < Vth_L < Vth_H < Vreg" holds. Therefore, the internal power supply voltage Vreg corresponds to a specific voltage that satisfies the predetermined condition. For example, "Vth_L = Vreg × 0.3" and "Vth_H = Vreg × 0.7".

[0061] In the switching power supply device 1, the internal power supply voltage Vreg is supplied to the synchronous output terminal S_OUT[2] of the device 10[2] (see FIG. 3), so that the synchronous output terminal S_OUT[2] is in a state where a specific voltage is supplied.

[0062] When the mode setting circuit 60 in the device 10[i] determines that the synchronous output terminal S_OUT[i] is in a state where a specific voltage is being supplied (i.e., when a specific voltage is being supplied to the synchronous output terminal S_OUT[i]), it sets the operation mode of the device 10[i] (and therefore the operation modes of the switching control circuit 20 and the signal output circuit 40 in the device 10[i]) to the second mode. Therefore, the mode setting circuit 60 in the device 10[2] outputs a second mode setting signal MODE according to the result of the above determination, thereby setting the operation mode of the device 10[2] (and therefore the operation modes of the switching control circuit 20 and the signal output circuit 40 in the device 10[2]) to the second mode.

[0063] On the other hand, in the switching power supply device 1, no specific voltage is supplied from the outside to the synchronous output terminal S_OUT[1] of the device 10[1]. The synchronous output terminal S_OUT[1] is connected to the synchronous input terminal S_IN[2], but since the device 10[2] does not have the function of outputting a signal from the synchronous input terminal S_IN[2], the synchronous input terminal S_IN[1] is essentially in an open state.

[0064] When the mode setting circuit 60 in the device 10[i] determines that the specific voltage is not being supplied to the synchronous output terminal S_OUT[i] (i.e., when the specific voltage is not being supplied to the synchronous output terminal S_OUT[i]), it sets the operation mode of the device 10[i] (and therefore the operation modes of the switching control circuit 20 and the signal output circuit 40 in the device 10[i]) to the first mode. Therefore, the mode setting circuit 60 in the device 10[1] outputs a first mode setting signal MODE according to the result of the above determination, thereby setting the operation mode of the device 10[1] (and therefore the operation modes of the switching control circuit 20 and the signal output circuit 40 in the device 10[1]) to the first mode.

[0065] When the first mode setting signal MODE is supplied to the signal output circuit 40, the signal output circuit 40 outputs the clock signal CLKb based on the reference clock signal CLKa from the synchronous output terminal S_OUT during the normal operation period. Therefore, the signal output circuit 40 of the device 10[1] outputs the clock signal CLKb based on the reference clock signal CLKa from the synchronous output terminal S_OUT[1] during the normal operation period. FIG. 10 shows the waveforms of the clock signals CLKa and CLKb. The frequencies of the clock signals CLKa and CLKb are the same. The reference clock signal CLKa generated in the device 10[1] and the clock signal CLKb output by the signal output circuit 40 of the device 10[1] (in other words, the clock signal CLKb supplied to the device 10[2]) are out of phase with each other by 180°. However, the amount of phase shift may differ slightly from 180°.

[0066] When the second mode setting signal MODE is supplied to the signal output circuit 40, the signal output circuit 40 does not output the clock signal CLKb from the synchronous output terminal S_OUT during the normal operation period, and keeps the input impedance of the synchronous output terminal S_OUT in a sufficiently high state (at least compared to when the first mode setting signal MODE is supplied to the signal output circuit 40, the input impedance of the synchronous output terminal S_OUT is kept in a sufficiently high state). Therefore, the signal output circuit 40 of the device 10[2] does not output the clock signal CLKb from the synchronous output terminal S_OUT[2] during the normal operation period, and keeps the input impedance of the synchronous output terminal S_OUT[2] in a sufficiently high state.

[0067] The internal power supply circuit 80 generates one or more internal power supply voltages including the internal power supply voltage Vreg based on the input voltage Vin. The switching control circuit 20 and the synchronization management circuit 30 operate based on the internal power supply voltages generated by the internal power supply circuit 80 or based on the input voltage Vin.

[0068] Below, several specific configuration examples, operation examples, application techniques, and modified techniques related to the switching power supply device 1 or the power supply control device 10 will be described among several embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are matters in each embodiment that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the following embodiments can also be applied to any of the other embodiments (i.e., any two or more of the embodiments can be combined).

[0069] <<First Example>> A first embodiment will be described. Fig. 11 shows a circuit diagram of a synchronization management circuit 130 according to the first embodiment. The synchronization management circuit 130 includes a signal output circuit 140 and a mode setting circuit 160. In the first embodiment, the synchronization management circuit 130, the signal output circuit 140, and the mode setting circuit 160 are used as the synchronization management circuit 30, the signal output circuit 40, and the mode setting circuit 60 (see Fig. 4) in each device 10, respectively.

[0070] The signal output circuit 140 includes inverter circuits 141-144, AND circuits 145 and 146, OR circuits 147 and 148, transistors 149-151, and a resistor 152. The mode setting circuit 160 includes a synchronization circuit 161, an inverter circuit 162, and AND circuits 163-165. The synchronization management circuit 130 is further provided with a DFF 171 and an inverter circuit 172. The synchronization circuit 161 is composed of a plurality of DFFs and a plurality of inverter circuits. The transistor 149 is a P-channel MOSFET, and the transistors 150 and 151 are N-channel MOSFETs.

[0071] Any inverter circuit has an input end and an output end, and outputs from the output end an inverted signal of an input signal to the input end. For any inverter circuit, the input signal to the inverter circuit refers to a signal input to the input end of the inverter circuit, and the output signal of the inverter circuit refers to a signal output from the output end of the inverter circuit.

[0072] The AND circuits 145, 146, and 163 to 165 are each a two-input AND circuit (logical product circuit). The two-input AND circuit has a first input terminal, a second input terminal, and an output terminal, and outputs a logical product signal of an input signal to the first input terminal and an input signal to the second input terminal from the output terminal. For any AND circuit, the output signal of the AND circuit refers to a signal output from the output terminal of the AND circuit.

[0073] The OR circuits 147 and 148 are each a two-input OR circuit (logical sum circuit). The two-input OR circuit has a first input terminal, a second input terminal, and an output terminal, and outputs a logical sum signal of an input signal to the first input terminal and an input signal to the second input terminal from the output terminal. For any OR circuit, the output signal of the OR circuit refers to a signal output from the output terminal of the OR circuit.

[0074] DFF171 and each DFF in the synchronous circuit 161 are the same as DFF170 in FIG. 12. DFF170 is a positive-edge-triggered D-type flip-flop, and includes a data input end (D), a data output end (Q), a clock input end (CP), and a reset input end of negative logic. DFF170 stores a value of "0" or "1". When DFF170 stores a value of "0", it outputs a low-level signal from the data output end (Q), and when it stores a value of "1", it outputs a high-level signal from the data output end (Q). When the input signal to the reset input end has a low level, DFF170 is in a reset state, and in the reset state DFF170 always stores a value of "0". When a rising edge occurs in the input signal to the clock input terminal (CP) during a period in which the input signal to the reset input terminal has a high level, DFF170 captures and stores the value of the input signal to the data input terminal (D) at the timing of the rising edge. The value of the input signal to the data input terminal (D) is "1" when the input signal to the data input terminal (D) has a high level, and is "0" when the input signal to the data input terminal (D) has a low level. As long as no rising edge occurs in the input signal to the clock input terminal (CP) during a period in which the input signal to the reset input terminal has a high level, DFF170 holds the current stored value as it is. For any DFF, the output signal of DFF refers to the signal output from the data output terminal (Q) of DFF.

[0075] The connections of the elements in the synchronization management circuit 130 and the input / output relationships of signals will be described below. The reference clock signal CLKa is input to the input terminal of the inverter circuit 141. The output signal of the inverter circuit 141 is input to the input terminal of the inverter circuit 142. The signal POR is input to the data input terminal (D) and the reset input terminal of DFF171, and the signal JUDGE is input to the clock input terminal (CP) of DFF171. The data output terminal (Q) of DFF171 is connected to the input terminal of the inverter circuit 172. The signal POR is input to the first input terminal of the AND circuit 145, and the output signal of the inverter circuit 172 is input to the second input terminal of the AND circuit 145. The mode setting signal MODE is input to the input terminal of the inverter circuit 144. The output signal of the AND circuit 145 and the output signal of the inverter circuit 144 are input to the first and second input terminals of the OR circuit 148, respectively.

[0076] The output signal of the OR circuit 148 is input to a first input terminal of the OR circuit 147 and an input terminal of the inverter circuit 143. The output signal of the inverter circuit 142 is input to a second input terminal of the OR circuit 147. The output signal of the inverter circuit 142 is also input to a first input terminal of the AND circuit 146. The output signal of the inverter circuit 143 is input to a second input terminal of the AND circuit 146.

[0077] The source of the transistor 149 is connected to an application terminal of the internal power supply voltage Vreg and is supplied with the internal power supply voltage Vreg. The drains of the transistors 149 and 150 are connected to a synchronous output terminal S_OUT. The synchronous output terminal S_OUT is connected to a first terminal of a resistor 152, and a second terminal of the resistor 152 is connected to a drain of a transistor 151. The sources of the transistors 150 and 151 are connected to ground. A signal at the synchronous output terminal S_OUT is referred to as a signal CLKOUT. The output terminal of the OR circuit 147, the output terminal of the AND circuit 146, and the output terminal of the OR circuit 148 are connected to the gates of the transistors 149, 150, and 151, respectively. When the output signal of the OR circuit 147 has a low level, the transistor 149 is on, and when the output signal of the OR circuit 147 has a high level, the transistor 149 is off. When the output signal of the AND circuit 146 has a high level, the transistor 150 is on, and when the output signal of the AND circuit 146 has a low level, the transistor 150 is off. When the output signal of the OR circuit 148 has a high level, the transistor 151 is on, and when the output signal of the OR circuit 148 has a low level, the transistor 151 is off.

[0078] An input terminal of the inverter circuit 162 is connected to the synchronous output terminal S_OUT and therefore receives the signal CLKOUT. The output signal of the inverter circuit 162 is input to a first input terminal of the AND circuit 163, and the signal POR is input to a second input terminal of the AND circuit 163. The output signal of the inverter circuit 141 and the output signal of the AND circuit 163 are input to a first input terminal and a second input terminal of the AND circuit 164, respectively. The output signal of the AND circuit 164 will be particularly referred to as a signal S11. The output signal of DFF171 will be particularly referred to as S12.

[0079] Signals S11, S12, and POR are input to the synchronization circuit 161. Only during a period when the output signal of the AND circuit 163 has a high level, an inverted signal of the reference clock signal CLKa is input to the synchronization circuit 161 as the signal S11. When the signal S11 is an inverted signal of the reference clock signal CLKa, the signal S11 is particularly referred to as a clock signal S11. When the output signal of the AND circuit 163 has a low level, the clock signal S11 is not generated and the signal S11 is maintained at a low level. The synchronization circuit 161 outputs a signal S13 based on the signals S11, S12, and POR. The signals S13 and POR are input to a first input terminal and a second input terminal of the AND circuit 165, respectively. The output signal of the AND circuit 165 is a mode setting signal MODE.

[0080] The synchronous circuit 161 is a circuit that operates in synchronization with the clock signal S11. In principle, the synchronous circuit 161 sets the signal S13 to a low level. When a rising edge occurs in the clock signal S11 a predetermined number of times (here, five times) during a period in which the signals S12 and POR are both at a high level, the synchronous circuit 161 generates a rising edge in the signal S13, and thereafter maintains the signal S13 at a high level. When the input of the clock signal S11 to the synchronous circuit 161 is cut off (i.e., when the signal S11 is maintained at a low level), the signal S13 is maintained at an initial level, that is, a low level.

[0081] Specifically, the synchronous circuit 161 includes DFF161a to 161e and inverter circuits 161f and 161g. Of these, DFF161a to 161d and the inverter circuits 161f and 161g form a counter which operates in synchronization with the clock signal S11. DFF161e may also be considered to be included in the components of the counter. The signal S11 is supplied to the clock input terminals (CP) of DFF161a and 161d. The signal S12 is supplied to the reset input terminals of DFF161a to 161d.

[0082] The inverter circuit 161f inputs the inverted signal of the output signal of DFF161a to the data input terminal (D) of DFF161a and to the clock input terminal (CP) of DFF161b. The inverter circuit 161g inputs the inverted signal of the output signal of DFF161b to the data input terminal (D) of DFF161b and to the clock input terminal (CP) of DFF161c. The signal S12 is input to the data input terminal (D) of DFF161c. The output signal of DFF161c is input to the data input terminal (D) of DFF161d. The output signal of DFF161d is input to the clock input terminal (CP) of DFF161e. The signal POR is input to the data input terminal (D) and the reset input terminal of DFF161e. The output signal of DFF161e is the signal S13.

[0083] The mode determination process will be described with reference to FIG. 13. FIG. 13 is a timing chart at the time of startup of the apparatus 10. FIG. 13 shows the waveforms of the internal power supply voltage Vreg, the signal POR, OSC_EN, JUDGE, and MODE. The signal POR is a power-on reset signal. The signal OSC_EN is an enable signal for the oscillation circuit 25a. The signal JUDGE is a determination instruction signal for instructing the execution of the mode determination process.

[0084] When the supply of the input voltage Vin to the apparatus 10 is started, the internal power supply circuit 80 starts up, causing the internal power supply voltage Vreg to rise from 0V toward a predetermined voltage Vreg_tg. A power-on reset circuit (not shown) provided in the apparatus 10 generates a rising edge in the signal POR when the internal power supply voltage Vreg reaches a predetermined threshold voltage Vreg_th (<Vreg_tg) at time T1 during the rising process of the internal power supply voltage Vreg. At time T1, the signals OSC_EN, JUDGE, and MODE all have a low level, which is the initial level. The initial setting process starts from time T1 (see FIG. 5).

[0085] A start-up circuit (not shown) provided in the device 10 generates a rising edge in the signal OSC_EN at time T2, when a predetermined time Δt1 has elapsed since time T1, and generates a rising edge in the signal JUDGE at time T3, when a predetermined time Δt2 has elapsed since time T2. The oscillation circuit 25a performs an oscillation operation only during a high-level period of the signal OSC_EN, and generates and outputs the reference clock signal CLKa. During a low-level period of the signal OSC_EN, the input signal to the inverter circuit 141 is fixed at a low level.

[0086] Time T4 follows after time T3. Until just before time T4, the mode setting signal MODE has an initial level of low level. The high-level mode setting signal MODE is the first mode setting signal MODE having a first value. The low-level mode setting signal MODE is the second mode setting signal MODE having a second value. A mode determination process is executed between times T3 and T4 (see FIG. 5). In device 10[1], as a result of the mode determination process, the level of the mode setting signal MODE switches from low to high at time T4. In device 10[2], as a result of the mode determination process, the mode setting signal MODE is maintained at low level even after time T4, and the mode setting signal MODE never becomes high level.

[0087] The operation of the synchronization management circuit 130 in the device 10[1] will be described with reference to Figures 14 to 18. In Figures 14 to 18, "(L)" means that the corresponding signal has a low level, and "(H)" means that the corresponding signal has a high level (the same applies to Figures 19 and 20 described below). The synchronization management circuit 130 in the device 10[1] will be specifically referred to as the synchronization management circuit 130[1].

[0088] FIG. 14 shows the state of the synchronization management circuit 130[1] just before time T1. In the synchronization management circuit 130[1], the mode setting signal MODE has a low level during the low level period of the signal POR, so the output signal of the OR circuit 148 is at a high level, and therefore the transistors 149 and 150 are off and the transistor 151 is on. In the device 10[1], the synchronization output terminal S_OUT[1] is substantially in an open state. Therefore, when the transistors 149 and 150 are off and the transistor 151 is on in the device 10[1], the synchronization output terminal S_OUT[1] is pulled down to ground (and therefore pulled down to a low level) by the transistor 151 via the resistor 152, so that the signal CLKOUT has a low level. In addition, before time T1, the signals S11 to S13 are maintained at a low level.

[0089] 15 shows the state of the synchronization management circuit 130[1] from time T1 to just before time T2. At time T1, a rising edge occurs in the signal POR, so that some signals in the synchronization management circuit 130[1] other than the signal POR also change in level. However, just before time T2, the signals S11 and S12 were previously fixed to a low level, and therefore the signal S13 has a low level, so the mode setting signal MODE has a low level. If the mode setting signal MODE is at a low level, the transistors 149 and 150 are off and the transistor 151 is on based on the high level output signal from the OR circuit 148, and the signal CLKOUT has a low level.

[0090] 16 shows the state of the synchronization management circuit 130[1] from time T2 to immediately before time T3. During the period from time T2 to immediately before time T3, the input signals and output signals of the inverter circuits 141 and 142 and the signal S11 alternately transition between high and low levels, and the period from time T2 to immediately before time T3 differs from the period from time T1 to immediately before time T2 in that the transitions occur. However, before time T3, DFFs 161a to 161d are in the reset state, so the counter in the synchronization circuit 161 is not driven, and therefore the signal S13 has a low level. If the signal S13 is at a low level, the mode setting signal MODE is also at a low level. As described above, if the mode setting signal MODE is at a low level, the transistors 149 and 150 are off and the transistor 151 is on based on the high-level output signal from the OR circuit 148, and the signal CLKOUT has a low level.

[0091] 17 shows the state of the synchronization management circuit 130[1] from time T3 to just before time T4. In the synchronization management circuit 130[1], when the signal JUDGE switches to the high level at time T3, a rising edge occurs in the output signal of DFF171, and therefore a falling edge occurs in each output signal of the inverter circuit 172 and the AND circuit 145. However, the mode setting signal MODE is at the low level until time T4.

[0092] Meanwhile, since the rising edge of the output signal of DFF171 corresponds to the rising edge of the signal S12, DFF161a-161d are released from the reset state at time T3. Then, in the synchronization management circuit 130[1], the inverted signal of the reference clock signal CLKa is input as the clock signal S11 to the synchronization circuit 161 after time T3. As a result, in the synchronization management circuit 130[1], a rising edge appears in the input signal to the clock input terminal of DFF161e at time T4 due to the operation of the counter, which results in a rising edge in the signal S13 and, ultimately, in the mode setting signal MODE.

[0093] FIG. 18 shows the state of the synchronization management circuit 130[1] after time T4. In the synchronization management circuit 130[1], after time T4, the mode setting signal MODE is maintained at a high level based on the high-level signals S13 and POR. In addition, the rising edge of the signal JUDGE generated at time T3 triggers the output signal of the AND circuit 145 to have a low level after time T4. Therefore, in the synchronization management circuit 130[1], the output signal of the OR circuit 148 has a low level after time T4. When the output signal of the OR circuit 148 is at a low level, the transistor 151 is off, and a clock signal equivalent to the reference clock signal CLKa is supplied to the gates of the transistors 149 and 150 through the OR circuit 147 and the AND circuit 146. Therefore, the transistors 149 and 150 are alternately turned on and off in synchronization with the reference clock signal CLKa. Then, in the synchronization management circuit 130[1], after time T4, an inverted signal of the reference clock signal CLKa appears as the signal CLKOUT. The signal CLKOUT, which is equivalent to the inverted signal of the reference clock signal CLKa, is output from the synchronization output terminal S_OUT[1] and supplied to the synchronization input terminal S_IN[2].

[0094] The operation of the synchronization management circuit 130 in the device 10[2] will be described with reference to Figures 19 and 20. The synchronization management circuit 130 in the device 10[2] will be specifically referred to as the synchronization management circuit 130[2].

[0095] FIG. 19 shows the state of the synchronization management circuit 130[2] from time T1 to just before time T3. Just before time T3, the mode setting signal MODE in the synchronization management circuit 130[2] is at a low level, as described for the synchronization management circuit 130[1]. Therefore, in the synchronization management circuit 130[2], the transistors 149 and 150 are off and the transistor 151 is on based on the low-level mode setting signal MODE until time T3. However, the internal power supply voltage Vreg is always supplied to the synchronization output terminal S_OUT[2] of the device 10[2]. Therefore, in the synchronization management circuit 130[2], the signal CLKOUT is at a high level even if the transistor 151 is on. When the signal CLKOUT is at a high level, the signal S11 is maintained at a low level by the function of the circuits 162 to 164.

[0096] In the synchronization management circuit 130[2], a rising edge occurs in the signal JUDGE at time T3, but since the signal CLKOUT is fixed at a high level even after time T3, the signal S11 to the synchronization circuit 161 is fixed at a low level and the counter does not operate. Therefore, in the synchronization management circuit 130[2], the signal S13 remains unchanged at a low level after time T1, and as a result, the mode setting signal MODE also remains unchanged at a low level. Figure 20 shows the state of the synchronization management circuit 130[2] after time T4.

[0097] The period after time T4 is the normal operation period (FIG. 5), and after time T4, normal operation is performed in each of the devices 10[1] and 10[2]. The normal operation includes switching control of the output stage MM by the switching control circuit 20. At least before time T4, the transistors MH and ML in each device 10 are kept off.

[0098] In the device 10[1], the switching control circuit 20 generates a signal SET from the reference clock signal CLKa based on a high-level mode setting signal MODE (first mode setting signal MODE) during normal operation, and executes switching control of the output stage MM in synchronization with the generated signal SET (and therefore in synchronization with the reference clock signal CLKa). Also, during normal operation, in response to a high-level mode setting signal MODE, the signal output circuit 140 in the device 10[1] outputs the signal CLKOUT as a clock signal CLKb from the synchronous output terminal S_OUT[1]. The clock signal CLKb is input to the synchronous input terminal S_IN[2].

[0099] In the device 10[2], the switching control circuit 20 generates a signal SET from the input clock signal CLKb based on a low-level mode setting signal MODE (second mode setting signal MODE) during the normal operation period, and performs switching control of the output stage MM in synchronization with the generated signal SET (and therefore in synchronization with the input clock signal CLKb).

[0100] In this way, the signal output circuit 140 pulls down the synchronous output terminal S_OUT to a low level via the resistor 152 during the execution period of the mode determination process (from time T3 to immediately before time T4). Due to this pull-down, when a specific voltage (here, the internal power supply voltage Vreg) is not supplied to the synchronous output terminal S_OUT, the signal CLKOUT of the synchronous output terminal S_OUT has a low level during the execution period of the mode determination process. On the other hand, when a specific voltage is supplied to the synchronous output terminal S_OUT, the signal CLKOUT of the synchronous output terminal S_OUT has a high level. In the device 10[i], if the level of the signal CLKOUT during the execution period of the mode determination process is a low level, the mode setting circuit 160 generates a rising edge in the mode setting signal MODE to set the operation mode of the device 10[i] to the first mode, and if the level of the signal CLKOUT during the execution period of the mode determination process is a high level, the mode setting signal MODE is maintained at a low level to set the operation mode of the device 10[i] to the second mode.

[0101] As described above, the mode setting signal MODE at a high level has a first value, and the mode setting signal MODE has a second value. When the signal at the synchronous output terminal S_OUT has a low level during the execution period of the mode determination process, the mode setting circuit 160 sets the mode setting signal MODE to the first value by driving the synchronous circuit 161 using the reference clock signal CLKa. When the signal at the synchronous output terminal S_OUT has a high level during the execution period of the mode determination process, the mode setting circuit 160 maintains the value of the mode setting signal MODE at the second value, which is the initial value, even after that. Note that the relationship between the first value, the second value, and the high level and the low level may be reversed from that described above.

[0102] As a reference configuration, the following switching power supply is considered. In the switching power supply according to the reference configuration, a dedicated external terminal for mode setting is provided for each power supply control device, and the operating mode of each power supply control device is set based on the input voltage to the dedicated external terminal for mode setting. In the switching power supply according to the reference configuration, the dedicated external terminal is required, and the power supply control device becomes larger. The larger power supply control device also leads to increased costs. According to the switching power supply 1 according to the present embodiment, the operating mode of each device 10 can be set without the need for a dedicated external terminal, making it possible to reduce the size and cost of the device 10.

[0103] <<Second Example>> The second embodiment will be described. The second embodiment and the third to sixth embodiments described later are based on the first embodiment, and for matters not specifically mentioned in the second to sixth embodiments, the description of the first embodiment also applies to the second to sixth embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that contradict between the first and second embodiments (the same applies to the third to sixth embodiments described later). As long as there is no contradiction, any two or more of the first to sixth embodiments may be combined.

[0104] The signal output circuit 40 in the device 10[i] may be configured in any way so long as it pulls down the synchronous output terminal S_OUT[i] to a low level (e.g., ground) via a resistor during execution of the mode determination process. The mode setting circuit 60 in the device 10[i] may be configured in any way so long as it sets the operation mode of the device 10[i] to the first mode or the second mode based on the level of the signal at the synchronous output terminal S_OUT[i] during execution of the mode determination process.

[0105] Another configuration example of the mode setting circuit 60 is shown in Fig. 21. Fig. 21 is a circuit diagram of a synchronization management circuit 230 according to the second embodiment. The synchronization management circuit 230 includes a signal output circuit 140 and a mode setting circuit 260, as well as a DFF 171 and an inverter circuit 172. In the second embodiment, the synchronization management circuit 230, the signal output circuit 140, and the mode setting circuit 260 are used as the synchronization management circuit 30, the signal output circuit 40, and the mode setting circuit 60 (see Fig. 4) in each device 10, respectively.

[0106] 11, the synchronization management circuit 230 in Fig. 21 can be obtained by replacing the mode setting circuit 160 with a mode setting circuit 260. Except for this replacement and matters described later, the configuration and operation of the synchronization management circuit 230 in Fig. 21 are the same as the configuration and operation of the synchronization management circuit 130 in Fig. 11.

[0107] The mode setting circuit 260 includes a comparator 261, an inverter circuit 262, and DFF263. DFF263 has the same configuration as DFF170 in FIG.

[0108] Comparator 261 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The signal CLKOUT and the voltage Vjudge are input to the non-inverting input terminal and the inverting input terminal of comparator 261, respectively. The voltage Vjudge is a reference voltage for determination having a predetermined positive DC voltage value. The signal CLKOUT is the signal at the synchronous output terminal S_OUT as described above. Comparator 261 outputs a high-level signal from its output terminal when the voltage of signal CLKOUT is higher than the voltage Vjudge, and outputs a low-level signal from its output terminal when the voltage of signal CLKOUT is lower than the voltage Vjudge. The value of the voltage Vjudge is set such that a high-level signal is output from comparator 261 when signal CLKOUT has a high level, and a low-level signal is output from comparator 261 when signal CLKOUT has a low level. It is preferable that "Vth_L < Vjudge < Vth_H" holds. Note that hysteresis characteristics may be imparted to comparator 261.

[0109] Inverter circuit 262 outputs an inverted signal of the output signal of comparator 261. The output signal of inverter circuit 262 is input to the data input terminal (D) of DFF 263. The signal JUDGE and the POR are input to the clock input terminal (CP) and the reset input terminal of DFF 263, respectively. The mode setting signal MODE is output from the data output terminal (Q) of DFF 263.

[0110] In the second embodiment, the timing chart at the startup of device 10 is the same as that shown in FIG. 13. However, in the second embodiment, the time difference between times T3 and T4 is shorter than that in the first embodiment. The time difference corresponds to the propagation delay time from when a rising edge occurs in the signal JUDGE until the signal at the data input terminal (D) of DFF 263 is reflected in the signal at the data output terminal (Q) of DFF 263.

[0111] As described in the first embodiment, until immediately before time T4, the mode setting signal MODE has a low level which is the initial level.

[0112] In the device 10[1], as a result of the mode determination process, the level of the mode setting signal MODE switches from low to high at time T4. This is because, in the device 10[1], the signal CLKOUT is at low level immediately before the rising edge of the signal JUDGE occurs and at the timing when the rising edge occurs in the signal JUDGE, and therefore the input signal to the data input terminal (D) of DFF263 is at high level.

[0113] In contrast, in the device 10[2], as a result of the mode determination process, the mode setting signal MODE is kept at low level even after time T4, and the mode setting signal MODE never goes high. This is because in the device 10[1], the signal CLKOUT is at high level immediately before and at the timing when a rising edge occurs in the signal JUDGE, and therefore the input signal to the data input terminal (D) of DFF263 is at low level.

[0114] <<Third Example>> A third embodiment will now be described. As long as the specific voltage can be supplied to the synchronous output terminal S_OUT[2] from outside the device 10[2], the supply source of the specific voltage is arbitrary. Therefore, for example, the specific voltage may be supplied to the synchronous output terminal S_OUT[2] from a DC voltage source (not shown) provided outside the device 1010[2].

[0115] <<Fourth Example>> A fourth embodiment will be described. A switching power supply device can be configured using one device 10. That is, the switching power supply device 1a shown in FIG. 22 may be configured. The switching power supply device 1 in FIG. 1 has two sets of devices 10 and coils L, but by omitting one of the sets from the switching power supply device 1, the switching power supply device 1a is obtained. That is, by omitting the device 10[2] and coil L[2] from the switching power supply device 1 in FIG. 3, the switching power supply device 1a is obtained. In the switching power supply device 1a, the synchronous output terminal S_OUT of the device 10, which is the only one provided, is opened or connected to ground. As a result, the operation mode of the device 10 in the switching power supply device 1a is set to the first mode.

[0116] Although the switching power supply devices 1 and 1a are configured as step-down DC / DC converters in the above example, the switching power supply devices 1 and 1a may be configured as step-up or step-up / step-down DC / DC converters.

[0117] <<Fifth Example>> A fifth embodiment will now be described. A switching power supply device 1 in Fig. 1 is an example of a semiconductor system equipped with first and second semiconductor devices. Devices 10[1] and 10[2] are examples of the first and second semiconductor devices. Each semiconductor device is equipped with a functional circuit having a predetermined function. The functional circuit in device 10 has a switching control circuit 20 and an output stage MM, and performs an operation for converting an input voltage Vin to an output voltage Vout.

[0118] In the present disclosure, the semiconductor device is not limited to a power supply control device incorporated in a switching power supply device. The technology of the present disclosure can be widely applied to any semiconductor system that requires synchronization between a first and a second semiconductor device. For example, each semiconductor device may be a driver device that drives a specified load (such as a light-emitting element, a display device, or a motor), and in this case, the functional circuit of each semiconductor device performs control to drive the specified load as desired.

[0119] <<Sixth Example>> A sixth embodiment will now be described.

[0120] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0121] The channel types of FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel without departing from the spirit of the above.

[0122] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0123] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0124] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0125] A semiconductor device (10) according to one aspect of the present disclosure includes a functional circuit (20) having a synchronous input terminal (S_IN), a synchronous output terminal (S_OUT), and a reference clock signal generating circuit (25a) configured to generate a reference clock signal (CLKa), a signal output circuit (40) connected to the synchronous output terminal, and a mode setting circuit (60) configured to set an operation mode of the functional circuit and the signal output circuit to a first mode or a second mode based on a result of a mode determination process after the mode determination process is performed, wherein the functional circuit performs a predetermined functional operation in synchronization with the reference clock signal in the first mode, and performs the functional operation in synchronization with an input clock signal (CLKb) supplied from another semiconductor device to the synchronous input terminal in the second mode, the signal output circuit outputs a clock signal based on the reference clock signal from the synchronous output terminal in the first mode, and the mode setting circuit is configured to determine whether a specific voltage (e.g., Vreg) satisfying a predetermined condition is supplied to the synchronous output terminal from outside the semiconductor device in the mode determination process (first configuration).

[0126] According to the semiconductor device, the mode can be set using the synchronous input terminal and the synchronous output terminal that are originally provided for transmitting the clock signal. In other words, the dedicated terminal for mode setting can be omitted, which contributes to miniaturization and cost reduction of the semiconductor device.

[0127] In the semiconductor device of the first configuration described above, the mode setting circuit may be configured (second configuration) to set the operating mode to the second mode when it is determined in the mode determination process that the specific voltage is being supplied to the synchronous output terminal, and to set the operating mode to the first mode when it is determined that the specific voltage is not being supplied to the synchronous output terminal.

[0128] In the semiconductor device according to the second configuration (see FIG. 11 or FIG. 21), the signal output circuit may be configured (third configuration) to pull down the synchronous output terminal to a first level (low level) via a resistor (152) during the execution period of the mode determination process, and the pull-down causes the signal at the synchronous output terminal to have the first level during the execution period of the mode determination process when the specific voltage is not being supplied, and causes the signal at the synchronous output terminal to have a second level (high level) higher than the first level when the specific voltage is being supplied, and the mode setting circuit may be configured to set the operating mode to the first mode or the second mode based on the level of the signal at the synchronous output terminal during the execution period of the mode determination process.

[0129] In the semiconductor device according to the third configuration (see FIG. 11), the mode setting circuit (160) may generate a mode setting signal (MODE) according to a result of the mode determination process, the mode setting signal having a first value or a second value, and after the mode determination process, when the mode setting signal has the first value, the operation mode is the first mode, and when the mode setting signal has the second value, the operation mode is the second mode, the mode setting circuit has a synchronization circuit (161), and when a signal at the synchronous output terminal has the first level during an execution period of the mode determination process, the synchronization circuit sets the mode setting signal to the first value by driving the synchronization circuit using the reference clock signal, and when a signal at the synchronous output terminal has the second level during an execution period of the mode determination process, the mode setting signal may be maintained at the second value, which is an initial value (fourth configuration).

[0130] In the semiconductor device according to the third configuration (see FIG. 21), the mode setting circuit (260) may generate a mode setting signal (MODE) according to a result of the mode determination process, the mode setting signal having a first value or a second value, and after the mode determination process, when the mode setting signal has the first value, the operation mode is the first mode, and when the mode setting signal has the second value, the operation mode is the second mode, and the mode setting circuit may compare the voltage of the signal at the synchronous output terminal with a predetermined judgment reference voltage (Vjudge) in the mode determination process, and set the mode setting signal to the first value when the voltage of the signal at the synchronous output terminal is lower than the judgment reference voltage, and set the mode setting signal to the second value when the voltage of the signal at the synchronous output terminal is higher than the judgment reference voltage (fifth configuration).

[0131] In the semiconductor device according to any one of the first to fifth configurations, the semiconductor device may be a power supply control device (10) provided in a switching power supply device configured to generate an output voltage (Vout) from an input voltage (Vin), and the functional circuit may have an output stage (MM) provided between an application terminal of the input voltage and an application terminal of the output voltage, and a switching control circuit (20) configured to perform power conversion from the input voltage to the output voltage by performing switching control of the output stage, and may be configured (sixth configuration) in which the switching control is performed in synchronization with the reference clock signal in the first mode, and in the second mode, the switching control is performed in synchronization with the input clock signal.

[0132] A semiconductor system according to one aspect of the present disclosure is a semiconductor system including first and second semiconductor devices (10[1], 10[2]), each of which is a semiconductor device according to any of the first to fifth configurations described above, wherein the synchronous output terminal (S_OUT[1]) of the first semiconductor device is connected to the synchronous input terminal (S_IN[2]) of the second semiconductor device, and the specific voltage (Vreg) is supplied to the synchronous output terminal of the second semiconductor device through a wiring (Wr) provided outside the second semiconductor device, and the mode setting circuit in the first semiconductor device sets the operating mode to the first mode, and the mode setting circuit in the second semiconductor device sets the operating mode to the second mode (seventh configuration).

[0133] A switching power supply device according to one aspect of the present disclosure is a switching power supply device (1) configured to generate an output voltage (Vout) from an input voltage (Vin), and includes first and second power supply control devices (10[1], 10[2]), each of which is a semiconductor device according to the sixth configuration described above, wherein the synchronous output terminal (S_OUT[1]) of the first power supply control device is connected to the synchronous input terminal (S_IN[2]) of the second power supply control device, and the specific voltage (Vreg) is supplied to the synchronous output terminal of the second power supply control device through a wiring (Wr) provided outside the second power supply control device, the mode setting circuit in the first power supply control device sets the operating mode to the first mode, and the mode setting circuit in the second power supply control device sets the operating mode to the second mode, and a current is supplied from the application terminal (IN) of the input voltage to the application terminal (OUT) of the output voltage through an output stage of the first power supply control device and an output stage of the second power supply control device (eighth configuration). [Explanation of symbols]

[0134] 1, 1a switching power supply Vin Input voltage Vout Output voltage Vfb Feedback voltage Vreg Internal power supply voltage L, L[i] coil Cout Output capacitor R1, R2 Feedback resistors IN Input terminal SW Switch terminal GND Ground terminal FB Feedback pin CMPOUT Error sharing pin S_IN, S_IN[i] Synchronous input terminal S_OUT, S_OUT[i] Synchronous output terminal REG Internal power output terminal Creg Capacitor Wc, Ws, Wr External wiring 10, 10[i] Power supply control device 20 Switching control circuit 21 Error Amplifier 22 Sense Circuit 23 Reset Circuit 24 Switch Circuit 25 set circuits 25a Oscillator circuit 26 Controller 30 Synchronization management circuit 40 Signal output circuit 60 Mode setting circuit 80 Internal power circuit MM output stage MH, ML transistors GH, GL gate signals MODE Mode setting signal CLKa Reference clock signal CLKb Input clock signal 130, 130[i], 230 synchronization management circuit 140 Signal output circuit 141-144, 161f, 161g, 162, 172, 262 Inverter circuits 145, 145, 163~165 AND circuit 147, 148 OR circuit 149~151 Transistor 152 Resistance 160, 260 Mode setting circuit 161 Synchronous Circuit 161a-161e, 171, 263 DFF 261 Comparator

Claims

1. A sync input terminal; A synchronous output terminal; a functional circuit having a reference clock signal generating circuit configured to generate a reference clock signal; a signal output circuit connected to the synchronous output terminal; a mode setting circuit configured to set the operation modes of the functional circuit and the signal output circuit to a first mode or a second mode based on a result of a mode determination process after the mode determination process is performed; the functional circuit performs a predetermined functional operation in synchronization with the reference clock signal in the first mode, and performs the functional operation in synchronization with an input clock signal supplied to the synchronous input terminal from another semiconductor device in the second mode; the signal output circuit outputs a clock signal based on the reference clock signal from the synchronous output terminal in the first mode; The mode setting circuit determines whether a specific voltage that satisfies a predetermined condition is supplied to the synchronous output terminal from outside the semiconductor device in the mode determination process. , semiconductor device.

2. When it is determined in the mode determination process that the specific voltage is being supplied to the synchronous output terminal, the mode setting circuit sets the operation mode to the second mode, and when it is determined that the specific voltage is not being supplied to the synchronous output terminal, the mode setting circuit sets the operation mode to the first mode. The semiconductor device according to claim 1 .

3. the signal output circuit pulls down the synchronous output terminal to a first level via a resistor during an execution period of the mode determination process; When the specific voltage is not being supplied due to the pull-down, the signal at the synchronous output terminal has the first level during an execution period of the mode determination process; In the specific voltage supply state, the signal at the synchronous output terminal has a second level higher than the first level, The mode setting circuit sets the operation mode to the first mode or the second mode based on a level of a signal at the synchronous output terminal during an execution period of the mode determination process. The semiconductor device according to claim 2 .

4. the mode setting circuit generates a mode setting signal according to a result of the mode determination process; the mode setting signal has a first value or a second value; after the mode determination process, when the mode setting signal has the first value, the operation mode is the first mode, and when the mode setting signal has the second value, the operation mode is the second mode; The mode setting circuit has a synchronous circuit, and when the signal at the synchronous output terminal has the first level during the execution period of the mode determination process, the synchronous circuit is driven using the reference clock signal to set the mode setting signal to the first value, and when the signal at the synchronous output terminal has the second level during the execution period of the mode determination process, the mode setting signal is maintained at the second value, which is an initial value. The semiconductor device according to claim 3 .

5. the mode setting circuit generates a mode setting signal according to a result of the mode determination process; the mode setting signal has a first value or a second value; after the mode determination process, when the mode setting signal has the first value, the operation mode is the first mode, and when the mode setting signal has the second value, the operation mode is the second mode; In the mode determination process, the mode setting circuit compares the voltage of the signal at the synchronous output terminal with a predetermined reference voltage for determination using a comparator, and sets the mode setting signal to the first value when the voltage of the signal at the synchronous output terminal is lower than the reference voltage for determination, and sets the mode setting signal to the second value when the voltage of the signal at the synchronous output terminal is higher than the reference voltage for determination. The semiconductor device according to claim 3 .

6. The semiconductor device is a power supply control device provided in a switching power supply device configured to generate an output voltage from an input voltage, The functional circuit has an output stage provided between an application terminal of the input voltage and an application terminal of the output voltage, and a switching control circuit configured to perform power conversion of the input voltage to the output voltage by performing switching control of the output stage, and performs the switching control in synchronization with the reference clock signal in the first mode, and performs the switching control in synchronization with the input clock signal in the second mode.

6. The semiconductor device according to claim 1 .

7. A semiconductor system including first and second semiconductor devices, Each semiconductor device is a semiconductor device according to any one of claims 1 to 5, the synchronous output terminal of the first semiconductor device is connected to the synchronous input terminal of the second semiconductor device, and the specific voltage is supplied to the synchronous output terminal of the second semiconductor device through a wiring provided outside the second semiconductor device; In the first semiconductor device, the mode setting circuit sets the operation mode to the first mode, and in the second semiconductor device, the mode setting circuit sets the operation mode to the second mode. ,Semiconductor Systems.

8. 1. A switching power supply configured to generate an output voltage from an input voltage, comprising: The semiconductor device includes a first power supply control device and a second power supply control device, each of the first power supply control device and the second power supply control device being configured as described in claim 6. the synchronous output terminal of the first power supply control device is connected to the synchronous input terminal of the second power supply control device, and the specific voltage is supplied to the synchronous output terminal of the second power supply control device through a wiring provided outside the second power supply control device; In the first power supply control device, the mode setting circuit sets the operation mode to the first mode, and in the second power supply control device, the mode setting circuit sets the operation mode to the second mode; A current is supplied from the input voltage application terminal to the output voltage application terminal through the output stage of the first power supply control device and the output stage of the second power supply control device. , switching power supply.

Images