Semiconductor device

Abstract

To provide a semiconductor device in which resistance and inductance of a circuit pattern in an insulation circuit board can be reduced.SOLUTION: A semiconductor device according to an embodiment includes: an insulation circuit board 10; an insulation circuit board 20; and a semiconductor chip 30 and an inter-board space 70 between the insulation circuit board 10 and the insulation circuit board 20. A conductive pattern 11b in a conductive board 11 of the insulation circuit board 10 has a first side 14aa, a second side 14bb, a third side 14cc, and a fourth side 14dd arranged to surround the inter-board space 70. The first side 14aa extends in a Y-direction, the second side 14bb is arranged to continue to the first side and extends in an X-direction perpendicular to the Y-direction, the third side 14cc is arranged to continue to the second side and extends in the Y-direction, and the fourth side 14dd is arranged to continue to the third side and extends obliquely to the Y-direction and the X-direction.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices including insulating circuit boards on which semiconductor chips are mounted are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-146444 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of reducing the resistance and inductance of a circuit pattern on an insulating circuit board is provided. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a first insulating circuit board having a first conductive plate, a second conductive plate, and a first insulating substrate provided between the first conductive plate and the second conductive plate, a second insulating circuit board having a third conductive plate, a fourth conductive plate, and a second insulating substrate provided between the third conductive plate and the fourth conductive plate, a first semiconductor chip provided between the first insulating circuit board and the second insulating circuit board, and a first spacer provided between the first insulating circuit board and the second insulating circuit board. The first conductive plate has a first conductive pattern, and the first spacer is arranged on the first conductive pattern. The first conductive pattern has a first side, a second side, a third side, and a fourth side arranged to surround the first spacer, the first side extending in a first direction, the second side being arranged continuously with the first side and extending in a second direction perpendicular to the first direction, the third side being arranged continuously with the second side and extending in the first direction, and the fourth side being arranged continuously with the third side and extending diagonally with respect to the first direction and the second direction. [Brief description of the drawings]

[0006] [Figure 1] 1 is a perspective view showing the outer shape of a semiconductor device according to a first embodiment; [Diagram 2] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] 2 is an enlarged view of the periphery of an inter-substrate spacer in the semiconductor device according to the first embodiment. FIG. [Diagram 5] 11 is an enlarged view of the periphery of an inter-substrate spacer in a semiconductor device of a comparative example. [Figure 6] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a second embodiment. [Figure 7] 13 is an enlarged view of the periphery of an inter-substrate spacer in the semiconductor device according to the second embodiment. FIG. [Figure 8] FIG. 13 is a plan view showing a configuration of a semiconductor device according to a third embodiment. [Figure 9]13 is an enlarged view of the periphery of an inter-substrate spacer in the semiconductor device according to the third embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same functions and configurations are given the same reference numerals. Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas of the embodiments, and do not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0008] 1. First embodiment A description will now be given of a semiconductor device according to a first embodiment. The semiconductor device has a package structure including a semiconductor chip and two insulating circuit boards that sandwich the semiconductor chip from above and below, and that holds these in a molding material.

[0009] The configuration of the semiconductor device of the first embodiment will be described with reference to Figures 1, 2, and 3. Figure 1 is a perspective view showing the outer shape of the semiconductor device of the first embodiment. Figure 2 is a plan view showing the configuration of the semiconductor device of the first embodiment. Figure 3 is a cross-sectional view taken along line III-III in Figure 2.

[0010] The semiconductor device includes a main body 1, plate terminals 2, 3, and 4, and a plurality of lead terminals 5. The main body 1 includes a molding material 6, a lower insulating circuit board 10, an upper insulating circuit board 20, semiconductor chips 30 and 40, chip spacers 50 and 60, and inter-board spacers 70 and 80.

[0011] Plate terminals 2, 3, and 4 are each electrically connected to a conductive pattern (or a circuit pattern) of insulating circuit board 10. Lead terminal 5 is each electrically connected to semiconductor chips 30 and 40, or to the conductive pattern. Note that the plan view shown in FIG. 2 shows the configuration on insulating circuit board 10 when viewed through insulating circuit board 20 and molding material 6.

[0012] 2, a semiconductor chip 30 is provided at one end in the X direction of the insulating circuit board 10, and a semiconductor chip 40 is provided at the other end in the X direction of the insulating circuit board 10. Inter-board spacers 70 and 80 are provided in the Y direction between the semiconductor chips 30 and 40. Hereinafter, the side of the insulating circuit board 10 where the semiconductor chip 30 is provided will be referred to as one end in the X direction, and the side where the semiconductor chip 40 is provided will be referred to as the other end in the X direction.

[0013] As shown in Fig. 3, the insulating circuit board 10 includes a conductive plate 11, a conductive plate 12, and a ceramic substrate 13. The ceramic substrate 13 is provided between the conductive plates 11 and 12. That is, the conductive plate 11 is disposed on the upper surface of the ceramic substrate 13, and the conductive plate 12 is disposed on the lower surface of the ceramic substrate 13. The conductive plates 11 and 12 each have a thickness of, for example, about 0.4 mm. The conductive plates 11 and 12 include, for example, copper. The ceramic substrate 13 is formed from an insulating material and has electrical insulation properties.

[0014] Conductive plate 11 is provided with slits 14 formed by removing parts of conductive plate 11 in a certain pattern. In other words, slits 14 are grooves provided in conductive plate 11 by removing parts of conductive plate 11.

[0015] The conductive plate 11 is separated into three conductive patterns (or circuit patterns) 11a, 11b, and 11c by slits 14. The conductive patterns 11a, 11b, and 11c are electrically insulated from each other.

[0016] Similarly, the insulating circuit board 20 includes a conductive plate 21, a conductive plate 22, and a ceramic substrate 23. The ceramic substrate 23 is provided between the conductive plate 21 and the conductive plate 22. That is, the conductive plate 21 is disposed on the upper surface of the ceramic substrate 23, and the conductive plate 22 is disposed on the lower surface of the ceramic substrate 23. The conductive plates 21 and 22 each have a thickness of, for example, about 0.4 mm. The conductive plates 21 and 22 include, for example, copper. The ceramic substrate 23 is formed from an insulating material and has electrical insulation properties.

[0017] Although not shown, the conductive plate 22 is separated into a plurality of conductive patterns (or circuit patterns) that are electrically insulated from one another by slits.

[0018] A semiconductor chip 30 is provided on the conductive pattern 11a with a solder material 31 interposed therebetween. A chip spacer 50 is provided on the semiconductor chip 30 with a solder material 51 interposed therebetween. Furthermore, a conductive pattern of a conductive plate 22 is provided on the chip spacer 50 with a solder material 52 interposed therebetween.

[0019] The semiconductor chip 30 includes, for example, a MOS field effect transistor (i.e., a MOSFET) or an IGBT (insulated gate bipolar transistor). Here, the description will be continued assuming that the semiconductor chip 30 is a MOS field effect transistor. The semiconductor chip 30 has a gate, a source, and a drain as electrodes.

[0020] For example, the drain of the semiconductor chip 30 is electrically connected to the conductive pattern 11a via the solder material 31. The source of the semiconductor chip 30 is electrically connected to the chip spacer 50 via the solder material 51.

[0021] The chip spacer 50 contains a conductive material and has conductivity. Therefore, the source of the semiconductor chip 30 is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 51, the chip spacer 50, and the solder material 52. The chip spacer 50 also functions as a heat dissipation path that dissipates heat generated in the semiconductor chip 30 to the insulating circuit board 20.

[0022] An inter-board spacer 70 is provided on conductive pattern 11b with a solder material 71 interposed therebetween. A conductive pattern of conductive plate 22 is provided on inter-board spacer 70 with a solder material 72 interposed therebetween.

[0023] The inter-board spacer 70 has, for example, a circular shape when viewed from the Z direction and a cylindrical shape having a thickness in the Z direction. The inter-board spacer 70 contains a conductive material and is conductive. Therefore, the conductive pattern 11b is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 71, the inter-board spacer 70, and the solder material 72.

[0024] The semiconductor chip 40 is provided on the conductive pattern 11c with a solder material 41 interposed therebetween. The chip spacer 60 is provided on the semiconductor chip 40 with a solder material 61 interposed therebetween. Furthermore, the conductive pattern of the conductive plate 22 is provided on the chip spacer 60 with a solder material 62 interposed therebetween.

[0025] The semiconductor chip 40 includes, for example, a MOS field effect transistor or an IGBT. Here, the description will be continued assuming that the semiconductor chip 40 is a MOS field effect transistor. The semiconductor chip 40 has a gate, a source, and a drain as electrodes.

[0026] For example, the drain of the semiconductor chip 40 is electrically connected to the conductive pattern 11c via the solder material 41. The source of the semiconductor chip 40 is electrically connected to the chip spacer 60 via the solder material 61.

[0027] The chip spacer 60 contains a conductive material and has conductivity. Therefore, the source of the semiconductor chip 40 is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 61, the chip spacer 60, and the solder material 62. The chip spacer 60 also functions as a heat dissipation path that dissipates heat generated in the semiconductor chip 40 to the insulating circuit board 20.

[0028] An inter-board spacer 80 is provided on the conductive pattern 11c with a solder material interposed therebetween. A conductive pattern of a conductive plate 22 is provided on the inter-board spacer 80 with a solder material interposed therebetween.

[0029] The inter-board spacer 80 has, for example, a circular shape when viewed from the Z direction and a cylindrical shape having a thickness in the Z direction. The inter-board spacer 80 includes a conductive material and has conductivity. Therefore, the conductive pattern 11c is electrically connected to the conductive pattern of the conductive plate 22 via the solder material, the inter-board spacer 80, and the solder material.

[0030] 2, plate terminals 2 and 3 are provided at one end in the Y direction of insulating circuit board 10, and plate terminal 4 is provided at the other end in the Y direction of insulating circuit board 10. Hereinafter, the side of insulating circuit board 10 where plate terminals 2 and 3 are provided will be referred to as one end in the Y direction, and the side where plate terminal 4 is provided will be referred to as the other end in the Y direction.

[0031] A plate terminal 2 is arranged on one end in the Y direction of the conductive pattern 11a. The plate terminal 2 is joined to the conductive pattern 11a via a solder material. The plate terminal 2 is electrically connected to the conductive pattern 11a. A plate terminal 3 is arranged on one end in the Y direction of the conductive pattern 11b. The plate terminal 3 is joined to the conductive pattern 11b via a solder material. The plate terminal 3 is electrically connected to the conductive pattern 11b. Furthermore, a plate terminal 4 is arranged on the other end in the Y direction of the conductive pattern 11c. The plate terminal 4 is joined to the conductive pattern 11c via a solder material. The plate terminal 4 is electrically connected to the conductive pattern 11c.

[0032] A high voltage, for example, is supplied to plate terminal 2. Plate terminal 2 may also be referred to as a P terminal, for example. A low voltage lower than the high voltage supplied to plate terminal 2 is supplied to plate terminal 3. Plate terminal 3 may also be referred to as an N terminal, for example. Either the high voltage supplied to plate terminal 2 or the low voltage supplied to plate terminal 3 is output from plate terminal 4. Plate terminal 4 may also be referred to as an AC terminal, for example. The thickness of each of plate terminals 2, 3, and 4 is, for example, 0.8 mm.

[0033] Furthermore, a plurality of lead terminals 5 are provided on the other end side of the insulating circuit board 10 in the Y direction.

[0034] Conductive patterns 11d and 11e are disposed on the other end side in the Y direction of insulating circuit board 10 relative to semiconductor chip 30. Each of conductive patterns 11d and 11e is an island-shaped pattern.

[0035] For example, the lead terminal 5 is joined to the conductive pattern 11d via a solder material. The conductive pattern 11d is connected to a pad 33 of the semiconductor chip 30 by a bonding wire 32. The pad 33 is connected to the gate of the semiconductor chip 30. The lead terminal 5 is electrically connected to the gate of the semiconductor chip 30 via the conductive pattern 11d, the bonding wire 32, and the pad 33.

[0036] The other lead terminal 5 is joined to the conductive pattern 11e via a solder material. The lead terminal 5 is electrically connected to the conductive pattern 11e.

[0037] Moreover, conductive patterns 11f and 11g are arranged on the other end side in the Y direction with respect to the semiconductor chip 40. Each of the conductive patterns 11f and 11g is an island-shaped pattern.

[0038] For example, the lead terminal 5 is joined to the conductive pattern 11f via a solder material. The conductive pattern 11f is connected to a pad 43 of the semiconductor chip 40 by a bonding wire 42. The pad 43 is connected to the gate of the semiconductor chip 40. The lead terminal 5 is electrically connected to the gate of the semiconductor chip 40 via the conductive pattern 11f, the bonding wire 42, and the pad 43.

[0039] The other lead terminal 5 is joined to the conductive pattern 11g via a solder material. The lead terminal 5 is electrically connected to the conductive pattern 11g.

[0040] Next, conductive pattern 11b to which inter-board spacer 70 is joined by solder material 71 will be described with reference to Fig. 4. Fig. 4 is an enlarged view of the periphery of inter-board spacer 70 in the semiconductor device of the first embodiment.

[0041] 4, when viewed from the Z direction, i.e., when viewed from above (or from a direction perpendicular to) the surface of the conductive plate 11 of the insulating circuit board 10, a first side 14aa of the conductive pattern 11b is disposed on the right side (or the other end side) of the inter-board spacer 70 in the X direction. A second side 14bb of the conductive pattern 11b is disposed on the upper side (or the other end side) of the inter-board spacer 70 in the Y direction. A third side 14cc of the conductive pattern 11b is disposed on the left side (or one end side) of the inter-board spacer 70 in the X direction. Furthermore, a fourth side 14dd of the conductive pattern 11b is disposed on the lower side (or one end side) of the inter-board spacer 70 in the Y direction.

[0042] The first side 14aa, the second side 14bb, the third side 14cc, and the fourth side 14dd are continuous and uninterrupted, surrounding the inter-substrate spacer 70. The first side 14aa extends linearly in the Y direction. The second side 14bb extends linearly in the X direction. The third side 14cc extends linearly in the Y direction. Furthermore, the fourth side 14dd extends linearly at an angle to the X direction and the Y direction, in other words, so as to intersect with the X direction and the Y direction.

[0043] The first side 14aa and the fourth side 14dd are disposed such that the distance between the first side 14aa and the fourth side 14dd becomes narrower toward the lower side (or one end side) in the Y direction. In other words, the first side 14aa and the fourth side 14dd are disposed such that the distance between the first side 14aa and the fourth side 14dd becomes narrower in the direction away from the inter-substrate spacer 70. In this case, the distance between the first side 14aa and the fourth side 14dd is smaller than the diameter of the inter-substrate spacer 70.

[0044] Next, the slits 14 provided around the inter-substrate spacer 70 will be described with reference to FIG.

[0045] The inter-substrate spacer 70 has a circular shape. A slit 14 is provided around the periphery of the inter-substrate spacer 70. The slit 14 includes a first portion 14a, a second portion 14b, a third portion 14c, and a fourth portion 14d.

[0046] First portion 14a is provided between conductive pattern 11b and conductive pattern 11c. First portion 14a is disposed so as to be tangent to the circumference of inter-substrate spacer 70 when viewed from the Z direction, and extends linearly in the Y direction. Here, the circumference of inter-substrate spacer 70 refers to the curve that forms inter-substrate spacer 70 when viewed from the Z direction.

[0047] The second portion 14b is provided between the conductive patterns 11b and 11c, and is continuous with the first portion 14a. The second portion 14b is disposed so as to be in contact with the circumference of the inter-substrate spacer 70 when viewed from the Z direction, and extends linearly in the X direction.

[0048] The third portion 14c is provided between the conductive patterns 11b and 11a, and is continuous with the second portion 14b. The third portion 14c is disposed so as to be in contact with the circumference of the inter-substrate spacer 70 when viewed from the Z direction, and extends linearly in the Y direction.

[0049] The fourth portion 14d is provided between the conductive patterns 11b and 11a, and is continuous with the third portion 14c. The fourth portion 14d is disposed so as to be in contact with the circumference of the inter-substrate spacer 70 when viewed from the Z direction. The fourth portion 14d extends in a straight line obliquely with respect to the X direction and the Y direction, in other words, so as to intersect with the X direction and the Y direction.

[0050] The second portion 14b is disposed continuously with the first portion 14a without interruption. The third portion 14c is disposed continuously with the second portion 14b without interruption. Furthermore, the fourth portion 14d is disposed continuously with the third portion 14c without interruption. That is, the first portion 14a, the second portion 14b, the third portion 14c, and the fourth portion 14d are disposed so as to surround the inter-substrate spacer 70.

[0051] Inter-board spacer 70 is joined via a solder material onto a region of conductive pattern 11b surrounded by first portion 14a to fourth portion 14d.

[0052] In the first embodiment, a semiconductor device can be provided that allows for low resistance and low inductance of a conductive pattern (or a circuit pattern) in an insulating circuit board.

[0053] 5 is an enlarged view of the periphery of inter-substrate spacer 70 in the semiconductor device of the comparative example. In the comparative example, slit 100 corresponds to slit 14.

[0054] 5, in the semiconductor device of the comparative example, the first portion 100a, the second portion 100b, the third portion 100c, and the fourth portion 100d of the slit 100 are arranged to surround the inter-substrate spacer 70. In other words, the first side 100aa, the second side 100bb, the third side 100cc, and the fourth side 100dd of the conductive pattern 11b are arranged to surround the inter-substrate spacer 70. Then, the fifth portion 100e is arranged between the first portion 100a and the fourth portion 100d. This prevents the inter-substrate spacer 70 from being misaligned when the inter-substrate spacer 70 is soldered.

[0055] In this way, when the fourth portion 100d extending in the X direction is provided and the fifth portion 100e is provided between the first portion 100a and the fourth portion 100d, the conductive pattern 11b between the first portion 100a and the fourth portion 100d at the lower right side of the inter-substrate spacer 70 becomes narrow. This may cause the resistance and inductance of the conductive pattern 11b to increase. Furthermore, when the fourth portion 100d extending in the X direction is provided in the third portion 100c extending in the Y direction, the edge portion of the conductive pattern 11b, i.e., the third side 100cc and the fourth side 100dd are arranged so as to be perpendicular to each other. In this way, when the third side 100cc and the fourth side 100dd are perpendicular to each other, the high frequency component of the AC signal passes through the edge, which may cause the inductance to increase.

[0056] In contrast, in the first embodiment, the fourth side 14dd of the conductive pattern 11b is disposed obliquely with respect to the X and Y directions so as to contact the inter-substrate spacer 70, that is, disposed in a right-shouldered downward direction as viewed from the Z direction. In other words, the first side 14aa and the fourth side 14dd of the conductive pattern 11b are disposed such that the distance between the first side 14aa and the fourth side 14dd becomes narrower in the direction away from the inter-substrate spacer 70.

[0057] Moreover, focusing on the slit 14, the fourth portion 14d of the slit 14 is disposed obliquely with respect to the X and Y directions so as to be in contact with the inter-substrate spacer 70, i.e., disposed in a direction sloping to the right as viewed from the Z direction. In other words, the first portion 14a and the fourth portion 14d of the slit 14 are disposed such that the distance between the first portion 14a and the fourth portion 14d becomes narrower in the direction away from the inter-substrate spacer 70.

[0058] This eliminates the need to provide the fifth portion 100e between the first portion 14a and the fourth portion 14d of the slit 14, making it possible to prevent the inter-substrate spacer 70 from being misaligned and to reduce the resistance and inductance of the conductive pattern 11b. In addition, since the third side 14cc and the fourth side 14dd of the conductive pattern 11b are arranged at an angle greater than a right angle, the inductance due to the high-frequency component of the AC signal flowing through the conductive pattern 11b can be reduced compared to when the third side 14cc and the fourth side 14dd are arranged at a right angle.

[0059] In the configuration of the first embodiment, the insulating circuit boards 10 and 20 can dissipate heat generated from the semiconductor chips 30 and 40 and the conductive patterns to the outside. Specifically, heat generated from the semiconductor chips 30 and 40 and the conductive patterns during operation of the semiconductor device is dissipated to the outside from both sides of the semiconductor device, i.e., from the insulating circuit boards 10 and 20 arranged above and below the semiconductor chips 30 and 40.

[0060] As described above, according to the semiconductor device of the first embodiment, it is possible to reduce the resistance and inductance of the conductive pattern (or the circuit pattern) in the insulating circuit board.

[0061] 2. Second embodiment Next, a semiconductor device according to a second embodiment will be described. In the second embodiment, in addition to the configuration of the first embodiment, an example in which the shape of the plate terminal 3 (i.e., the N terminal) is improved will be described. In the second embodiment, differences from the first embodiment will be mainly described.

[0062] The configuration of the semiconductor device according to the second embodiment will be described with reference to FIGS.

[0063] In the semiconductor device of the second embodiment, the shape of the plate terminal 3A is different from that of the plate terminal 3 in the first embodiment. The other configurations are similar to those of the first embodiment.

[0064] Fig. 6 is a plan view showing the configuration of the semiconductor device of the second embodiment, and Fig. 7 is an enlarged view of the periphery of an inter-substrate spacer 70 in the semiconductor device of the second embodiment.

[0065] Plate terminal 3A is disposed on one end in the Y direction of conductive pattern 11b. Plate terminal 3A has a protruding portion A on one end side in the X direction. That is, plate terminal 3A has a rectangular shape, and has protruding portion A protruding from one end side in the X direction of the rectangular shape. In other words, plate terminal 3A has a rectangular portion having a rectangular shape, and protruding portion A protruding from one end in the X direction of the rectangular portion. In addition, the distance from one end in the X direction of the rectangular portion or protruding portion A to inter-board spacer 70 is shorter than the distance from the other end in the X direction of the rectangular portion to inter-board spacer 70.

[0066] The protrusion A overlaps with the conductive pattern 11b in the Z direction. The plate terminal 3A including the protrusion A is joined to the conductive pattern 11b via a solder material and is electrically connected to the conductive pattern 11b. The thickness of the plate terminal 3A is, for example, 0.8 mm.

[0067] In the second embodiment, a plate terminal 3A having a larger area than the plate terminal 3 is provided, and the plate terminal 3A is electrically connected to the conductive pattern 11b. That is, in the second embodiment, in addition to the plate terminal 3 shown in the first embodiment, the protruding portion A is also electrically connected to the conductive pattern 11b.

[0068] The conductive pattern 11b near one end side of the plate terminal 3A in the X direction is a current path through which current flows in a concentrated manner between the plate terminal 3A and the inter-board spacer 70. Since the protrusion A is provided on this current path, the path through which the current flows can be shortened by using only the conductive pattern 11b.

[0069] This makes it possible to further reduce the resistance and inductance in the plate terminal 3A and the conductive pattern 11b.

[0070] As described above, according to the semiconductor device of the second embodiment, in addition to the configuration of the first embodiment, by providing the plate terminal 3A with an increased area, it is possible to reduce the resistance and inductance of the conductive pattern (or the circuit pattern) in the insulating circuit board even more than in the first embodiment.

[0071] 3. Third embodiment Next, a semiconductor device according to a third embodiment will be described. In the third embodiment, an example in which the shape of the plate terminal 3A (i.e., the N terminal) is further improved compared to the second embodiment will be described. In the third embodiment, differences from the first embodiment will be mainly described.

[0072] The configuration of the semiconductor device of the third embodiment will be described with reference to Figures 8 and 9. In the semiconductor device of the third embodiment, the shape of the plate terminal 3B is different from that of the first and second embodiments. The other configurations are the same as those of the first and second embodiments.

[0073] Fig. 8 is a plan view showing the configuration of the semiconductor device of the third embodiment, and Fig. 9 is an enlarged view of the periphery of an inter-substrate spacer 70 in the semiconductor device of the third embodiment.

[0074] Plate terminal 3B is disposed on one end in the Y direction of conductive pattern 11b. Plate terminal 3B has a protrusion B on one end side in the X direction and the other end side in the Y direction. That is, plate terminal 3B has a rectangular shape, and has a protrusion B protruding from one end side in the X direction and the other end side in the Y direction of the rectangular shape. In other words, plate terminal 3B has a rectangular portion having a rectangular shape, and a protrusion B protruding from one end of the rectangular portion in the X direction and the other end of the rectangular portion in the Y direction. In addition, the distance from one end of the rectangular portion in the X direction or the protrusion B to inter-board spacer 70 is shorter than the distance from the other end of the rectangular portion in the X direction to inter-board spacer 70.

[0075] The protrusion B overlaps with the conductive pattern 11b in the Z direction. The plate terminal 3B including the protrusion B is joined to the conductive pattern 11b via a solder material and is electrically connected to the conductive pattern 11b. The thickness of the plate terminal 3B is, for example, 0.8 mm.

[0076] In the third embodiment, a plate terminal 3B having an area larger than that of the plate terminal 3 or 3A is provided, and the plate terminal 3B is electrically connected to the conductive pattern 11b. That is, in the third embodiment, in addition to the plate terminal 3 shown in the first embodiment, the protruding portion B is also electrically connected to the conductive pattern 11b.

[0077] The conductive pattern 11b near one end side in the X direction and the other end side in the Y direction of the plate terminal 3B constitutes a current path through which current flows in a concentrated manner between the plate terminal 3B and the board spacer 70. Since the protrusion B is provided on this current path, the path through which the current flows can be shortened by using only the conductive pattern 11b.

[0078] This makes it possible to further reduce the resistance and inductance in the plate terminal 3B and the conductive pattern 11b.

[0079] As described above, according to the semiconductor device of the third embodiment, in addition to the configuration of the first embodiment, by providing the plate terminal 3B with an increased area, it is possible to reduce the resistance and inductance of the conductive pattern (or the circuit pattern) in the insulating circuit board even more than in the first or second embodiment.

[0080] In the first to third embodiments described above, the semiconductor device constitutes a MOS field effect transistor (i.e., MOSFET), but the semiconductor device may constitute another switching element, for example, an IGBT (insulated gate bipolar transistor). When the semiconductor device constitutes an IGBT, the source corresponds to the emitter, and the drain corresponds to the collector.

[0081] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0082] 1...main body, 2...plate terminal, 3...plate terminal, 3A...plate terminal, 3B...plate terminal, 4...plate terminal, 5...lead terminal, 6...molding material, 10...insulated circuit board, 11...conductive plate, 11a...conductive pattern, 11b...conductive pattern, 11c...conductive pattern, 11d...conductive pattern, 11e...conductive pattern, 11f...conductive pattern, 11g...conductive pattern, 12...conductive plate, 13...ceramic substrate, 14...slit, 20...insulated circuit board, 21...conductive plate, 22...conductive plate, 23...ceramic substrate, 30...semiconductor chip, 31...solder material, 32...bonding wire, 33...pad, 40...semiconductor chip, 41...solder material, 42...bonding wire, 43...pad, 50...chip spacer, 51...solder material, 52...solder material, 60...chip spacer, 61...solder material, 62...solder material, 70...inter-board spacer, 71...solder material, 72...solder material, 80...inter-board spacer.

Claims

1. a first insulating circuit board having a first conductive plate, a second conductive plate, and a first insulating substrate provided between the first conductive plate and the second conductive plate; a second insulating circuit board having a third conductive plate, a fourth conductive plate, and a second insulating substrate provided between the third conductive plate and the fourth conductive plate; a first semiconductor chip provided between the first insulating circuit board and the second insulating circuit board; a first spacer provided between the first insulating circuit board and the second insulating circuit board; Equipped with the first conductive plate has a first conductive pattern; the first spacer is disposed on the first conductive pattern; the first conductive pattern has a first side, a second side, a third side, and a fourth side arranged to surround the first spacer; The first side extends in a first direction; The second side is disposed continuously with the first side and extends in a second direction perpendicular to the first direction; The third side is disposed continuously with the second side and extends in the first direction, The fourth side is disposed contiguous with the third side and extends obliquely with respect to the first direction and the second direction.

2. 2 . The semiconductor device according to claim 1 , wherein the first side and the fourth side are disposed such that a distance between the first side and the fourth side becomes narrower in a direction away from the first spacer.

3. The semiconductor device according to claim 2 , wherein the distance between the first side and the fourth side is smaller than a diameter of the first spacer.

4. The semiconductor device according to claim 1 , wherein each of the first side, the second side, the third side, and the fourth side extends linearly.

5. the first conductive plate has the first conductive pattern, a second conductive pattern, and a third conductive pattern; 2. The semiconductor device according to claim 1, wherein slits are provided around the first spacer, between the first conductive pattern and the second conductive pattern, and between the first conductive pattern and the third conductive pattern, where the first conductive plate is removed.

6. the slit has a first portion, a second portion, a third portion, and a fourth portion; The first portion extends in the first direction; the second portion is disposed contiguous with the first portion and extends in a second direction perpendicular to the first direction; the third portion is disposed contiguous with the second portion and extends in the first direction; The semiconductor device according to claim 5 , wherein the fourth portion is disposed contiguous with the third portion and extends obliquely with respect to the first direction and the second direction.

7. a second semiconductor chip provided between the first insulating circuit board and the second insulating circuit board; a second spacer provided between the first insulating circuit board and the second insulating circuit board; a third spacer provided between the first semiconductor chip and the second insulating circuit board; a fourth spacer provided between the second semiconductor chip and the second insulating circuit board; The semiconductor device according to claim 1 , further comprising:

8. a terminal provided on one end of the first conductive pattern in the first direction; The semiconductor device according to claim 1 , wherein the terminal has a rectangular portion having a rectangular shape and a protruding portion protruding from one end of the rectangular portion in the second direction.

9. a terminal provided on one end of the first conductive pattern in the first direction; The semiconductor device according to claim 8 , wherein the terminal has a rectangular portion having a rectangular shape, and a protruding portion protruding from one end of the rectangular portion in the second direction and from the other end of the rectangular portion in the first direction.

10. The semiconductor device according to claim 8 , wherein a distance from the protruding portion to the first spacer is shorter than a distance from the other end of the rectangular portion in the second direction to the first spacer.

11. The semiconductor device according to claim 1 , wherein the first semiconductor chip includes a MOS type field effect transistor.

12. The semiconductor device according to claim 1 , wherein the first semiconductor chip includes an insulated gate bipolar transistor (IGBT).

13. 2. The semiconductor device according to claim 1, wherein the first insulating substrate and the second insulating substrate are ceramic substrates.

14. a first insulating circuit board having a first conductive plate including a first conductive pattern, a second conductive plate, and a first insulating substrate provided between the first conductive plate and the second conductive plate; a second insulating circuit board having a third conductive plate, a fourth conductive plate, and a second insulating substrate provided between the third conductive plate and the fourth conductive plate; a first semiconductor chip provided between the first insulating circuit board and the second insulating circuit board; a first spacer provided between the first insulating circuit board and the second insulating circuit board and disposed on the first conductive pattern; a terminal provided on one end of the first conductive pattern in a first direction; Equipped with The terminal is a semiconductor device having a rectangular portion having a rectangular shape and a protruding portion protruding from one end of the rectangular portion in a second direction perpendicular to the first direction.

15. The semiconductor device according to claim 14 , wherein a distance from the protruding portion to the first spacer is shorter than a distance from the other end of the rectangular portion in the second direction to the first spacer.

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