Semiconductor device

Abstract

To improve heat release performance.SOLUTION: A semiconductor device according to an embodiment includes a first substrate 12, a second substrate 11, a chip 21, and a spacer 31. The second substrate 11 faces the first substrate 12. The chip 21 is located on the first substrate 12 and between the first substrate 12 and the second substrate 11. The spacer 31 is provided on the chip 21 and connects the chip 21 and the second substrate 11 to each other. The spacer 31 is in contact with the chip 21 in a first part and is in contact with the second substrate 11 in a second part and the second part is larger than the first part.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A power module is known as a semiconductor device, and a power module having a configuration in which heat is dissipated from both the top and bottom surfaces of the module is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-57425 [Patent Document 2] Patent Publication No. 2022-53057 [Patent Document 3] JP 2023-13148 A Summary of the Invention [Problem to be solved by the invention]

[0004] Improves heat dissipation performance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first substrate, a second substrate, a chip, and a spacer. The second substrate is disposed opposite the first substrate. The chip is disposed on the first substrate and between the first substrate and the second substrate. The spacer is disposed on the chip and connects the chip to the second substrate. The area of ​​the second portion of the spacer that contacts the second substrate is larger than the area of ​​the first portion that contacts the chip. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device according to an embodiment. [Diagram 2] 1 is a perspective view showing an example of an appearance of a semiconductor device according to an embodiment; [Diagram 3] 1 is a perspective view showing an example of an internal structure of a semiconductor device according to an embodiment; [Figure 4] 1 is a plan view showing an example of an internal structure of a semiconductor device according to an embodiment; [Diagram 5] 1 is a plan view showing an example of an internal structure of a semiconductor device according to an embodiment; [Figure 6] 1 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to an embodiment. [Figure 7] 1 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to an embodiment. [Figure 8] FIG. 11 is a plan view showing an example of an internal structure of a semiconductor device according to a first modified example. [Figure 9] FIG. 11 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to a first modified example. [Figure 10] FIG. 11 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to a second modified example. [Figure 11] FIG. 13 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to a third modified example. [Figure 12] FIG. 13 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to a fourth modified example. [Figure 13] FIG. 13 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to a fifth modified example. [Figure 14] FIG. 13 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to a sixth modified example. [Figure 15] FIG. 13 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to a seventh modification. [Figure 16] FIG. 13 is a cross-sectional view showing an example of an internal structure of a semiconductor device according to an eighth modification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the description, components having substantially the same functions and configurations are given the same reference numerals. The embodiments described below are merely examples of technical ideas. The materials, shapes, structures, arrangements, etc. of the components are not specified in the embodiments. Various modifications can be made to the embodiments.

[0008] <Embodiment> A semiconductor device according to an embodiment will be described. The semiconductor device 1 according to the embodiment is a power module. The semiconductor device 1 is used in, for example, a power conversion device for an electric vehicle.

[0009] <1> composition <1-1> Circuit configuration of semiconductor device 1 is a circuit diagram showing a configuration example of a semiconductor device according to an embodiment. The semiconductor device 1 according to the embodiment includes, for example, a half-bridge circuit. As shown in FIG. 1, the semiconductor device 1 includes terminals TP, TN, TOUT, TG1, TG2, TD1, TD2, TS1, and TS2, and transistors NM1 and NM2.

[0010] The terminals TP and TN are power supply terminals of the semiconductor device 1. A positive power supply voltage is applied to the terminal TP. A negative power supply voltage is applied to the terminal TN.

[0011] The terminal TOUT is an output terminal of the semiconductor device 1.

[0012] The terminals TG1 and TG2 are control terminals of the semiconductor device 1.

[0013] The terminals TD1, TD2, TS1, and TS2 are terminals for monitoring the operation of the semiconductor device 1, respectively.

[0014] Each of the transistors NM1 and NM2 is, for example, an N-type MOS transistor. The drain of the transistor NM1 is connected to the terminal TP. The source of the transistor NM1 is connected to the terminal TOUT. The gate of the transistor NM1 is connected to the terminal TG1. The drain of the transistor NM2 is connected to the terminal TOUT. The source of the transistor NM2 is connected to the terminal TN. The gate of the transistor NM2 is connected to the terminal TG2.

[0015] The drain of the transistor NM1 is connected to the terminal TD1. The source of the transistor NM1 is connected to the terminal TS1. The drain of the transistor NM2 is connected to the terminal TD2. The source of the transistor NM2 is connected to the terminal TS2.

[0016] <1-2> Package structure of semiconductor device 2 is a perspective view showing an example of the appearance of a semiconductor device according to an embodiment. The semiconductor device 1 has, for example, a thin rectangular parallelepiped shape. Hereinafter, the thickness direction of the semiconductor device 1 will be referred to as the up-down direction. In addition, when a component of the semiconductor device 1 has two surfaces that face each other in the up-down direction, the two surfaces will be referred to as the upper surface and the lower surface, respectively.

[0017] The semiconductor device 1 further includes substrates 11 and 12, and a sealing material 50. Each of the terminals TP, TN, TOUT, TG1, TG2, TD1, TD2, TS1, and TS2 has a portion exposed to the outside of the sealing material 50 as a terminal for electrical connection to the outside. Each of the substrates 11 and 12 has a portion exposed to the outside of the sealing material 50. In the following, the surface on which the substrate 11 is exposed is referred to as the upper surface, and the surface on which the substrate 12 is exposed is referred to as the lower surface.

[0018] The substrates 11 and 12 are insulating circuit boards in which conductors are attached to both sides of a plate-shaped insulator. The insulator is, for example, aluminum oxide. The conductor is, for example, copper. The substrates 11 and 12 are disposed opposite each other. Each of the substrates 11 and 12 has a circuit pattern disposed on the surface facing the inside of the semiconductor device 1. The substrate 11 is disposed so that a portion of it is exposed on the upper surface of the sealing material 50. The substrate 12 is disposed so that a portion of it is exposed on the lower surface of the sealing material 50. The substrate 11 exposed on the upper surface of the sealing material 50 and the substrate 12 exposed on the lower surface of the sealing material 50 each function as a heat sink that releases heat generated inside the semiconductor device 1 to the outside of the semiconductor device 1.

[0019] The terminals TP, TN, and TOUT are provided so as to be exposed on the side surface of the sealing material 50. For example, the terminals TP and TN protrude from a first surface which is a side surface of the sealing material 50. For example, the terminal TOUT protrudes from approximately the center of a second surface which is one of the side surfaces of the sealing material 50 and which faces the first surface from which the terminals TP and TN protrude. Each of the terminals TP, TN, and TOUT is bent into an L shape at the protruding end, and has a circular opening at the end of the L shape.

[0020] The terminals TG1, TD1, and TS1 are provided so as to be exposed on the side surfaces of the sealing material 50. For example, the terminals TG1, TD1, and TS1 are provided on a second surface among the side surfaces of the sealing material 50, side by side with the terminal TOUT, and between the terminal TOUT and an end of the second surface. The terminals TG1, TD1, and TS1 protrude from the side surfaces of the sealing material 50.

[0021] The terminals TG2, TD2, and TS2 are provided so as to be exposed on the side surface of the sealing material 50. For example, the terminals TG2, TD2, and TS2 are provided on the second surface among the side surfaces of the sealing material 50, side by side with the terminal TOUT, and between the terminal TOUT and the end of the second surface, on the opposite side to the portion where the terminals TG1, TD1, and TS1 are provided. The terminals TG2, TD2, and TS2 protrude from the side surface of the sealing material 50.

[0022] The sealing material 50 is an insulating member that physically and electrically protects the internal structure of the semiconductor device 1 from the outside. The sealing material 50 forms the outer shape of the semiconductor device 1.

[0023] <1-3> Internal structure of semiconductor device The internal structure of the semiconductor device 1 will be described with reference to Figs. 3 and 4. Fig. 3 is a perspective view showing an example of the internal structure of the semiconductor device according to the embodiment. Fig. 4 is a plan view showing an example of the internal structure of the semiconductor device according to the embodiment. In Figs. 3 and 4, the substrate 11 and the sealing material 50 are omitted. The semiconductor device 1 further includes chips 21 and 22, spacers 31 and 32, and inter-substrate spacers 41 and 42 as its internal structure. In addition, the substrate 12 includes circuit patterns 12a, 12b, 12c, 12d, 12e, 12f, and 12g.

[0024] Each of the circuit patterns 12a, 12b, 12c, 12d, 12e, 12f, and 12g is a conductor provided on the substrate 12, for example, copper. The circuit pattern 12a is connected to the terminals TP and TD1. The circuit pattern 12b is connected to the terminals TOUT and TD2. The circuit pattern 12c is connected to the terminal TN. The circuit pattern 12d is connected to the terminal TS1. The circuit pattern 12e is connected to the terminal TG1. The circuit pattern 12f is connected to the terminal TS2. The circuit pattern 12g is connected to the terminal TG2.

[0025] Each of the chips 21 and 22 is a power semiconductor chip. Specifically, for example, each of the chips 21 and 22 includes an N-type MOS transistor. The transistor included in the chip 21 corresponds to the transistor NM1 described with reference to FIG. 1. The transistor included in the chip 22 corresponds to the transistor NM2 described with reference to FIG. 1. Each of the chips 21 and 22 has, for example, a rectangular flat plate shape. The lower surface of each of the chips 21 and 22 is used as an electrode corresponding to the drain.

[0026] On the top surface of the chip 21, pads PSL1 and PSS1 corresponding to the source and a pad PG1 corresponding to the gate are provided. The pad PSL1 is a large pad that occupies most of the top surface of the chip 21. The pad PSL1 is provided in the center of the top surface of the chip 21. The pads PSS1 and PG1 are small pads. The pads PSS1 and PG1 are provided side by side along one side on the top surface of the chip 21.

[0027] The top surface of chip 22 is similar to the top surface of chip 21. That is, on the top surface of chip 22, pads PSL2 and PSS2 corresponding to the source and pad PG2 corresponding to the gate are provided. Pad PSL2 is a large pad that occupies most of the top surface of chip 22. Pad PSL2 is provided in the center of the top surface of chip 22. Pads PSS2 and PG2 are small pads. Pads PSS2 and PG2 are provided side by side along one side on the top surface of chip 22.

[0028] The chip 21 is provided on the circuit pattern 12a. Specifically, the chip 21 is provided so that the side along which the pads PSS1 and PG1 are arranged faces the direction in which the terminals TG1, TD1, and TS1 are arranged. The drain electrode provided on the lower surface of the chip 21 is electrically connected to the circuit pattern 12a. As a result, the drain electrode provided on the lower surface of the chip 21 is electrically connected to the terminals TP and TD1. The pad PSS1 provided on the upper surface of the chip 21 is electrically connected to the circuit pattern 12d by the bonding wire BW1. As a result, the pad PSS1 is electrically connected to the terminal TS1. The pad PG1 provided on the upper surface of the chip 21 is electrically connected to the circuit pattern 12e by the bonding wire BW2. As a result, the pad PG1 is electrically connected to the terminal TG1.

[0029] The chip 22 is provided on the circuit pattern 12b. Specifically, the chip 22 is provided so that the side along which the pads PSS2 and PG2 are arranged faces the direction in which the terminals TG2, TD2, and TS2 are arranged. The drain electrode provided on the lower surface of the chip 22 is electrically connected to the circuit pattern 12b. As a result, the drain electrode provided on the lower surface of the chip 22 is electrically connected to the terminals TOUT and TD2. The pad PSS2 provided on the upper surface of the chip 22 is electrically connected to the circuit pattern 12f by the bonding wire BW3. As a result, the pad PSS2 is electrically connected to the terminal TS2. The pad PG2 provided on the upper surface of the chip 22 is electrically connected to the circuit pattern 12g by the bonding wire BW4. As a result, the pad PG2 is electrically connected to the terminal TG2.

[0030] A spacer 31 is provided on a pad PSL1 provided on the upper surface of the chip 21. A spacer 32 is provided on a pad PSL2 provided on the upper surface of the chip 22. Each of the spacers 31 and 32 is a conductor. Each of the spacers 31 and 32 is, for example, a composite material of aluminum and silicon carbide. Each of the spacers 31 and 32 has a structure in which the area of ​​the upper surface is larger than the area of ​​the lower surface. The area of ​​the lower surface of the spacer 31 is smaller than the area of ​​the upper surface of the chip 21. The area of ​​the lower surface of the spacer 32 is smaller than the area of ​​the upper surface of the chip 22.

[0031] For example, the spacer 31 includes spacers 31a and 31b. Each of the spacers 31a and 31b is a rectangular flat plate with an area of ​​the upper surface and an area of ​​the lower surface being approximately equal. The spacer 31a has an upper surface and a lower surface that can be included in the upper surface of the chip 21 in a top view. The long sides of the upper surface and the lower surface of the spacer 31b are longer than the long sides of the upper surface and the lower surface of the spacer 31a. The short sides of the upper surface and the lower surface of the spacer 31b are longer than the short sides of the upper surface and the lower surface of the spacer 31a. The spacer 31 has a structure in which the spacer 31b is overlapped on the spacer 31a so that one side is aligned. The spacer 31 is provided so that the side of the spacers 31a and 31b that are overlapped so that one side is aligned faces the side along which the pads PSS1 and PG1 of the chip 21 are provided side by side. The spacer 31 is electrically connected to the pad PSL1.

[0032] The same is true for the spacer 32. That is, the spacer 32 includes spacers 32a and 32b. Each of the spacers 32a and 32b is a rectangular flat plate with an upper surface area and a lower surface area that are approximately equal. The spacer 32a has an upper surface and a lower surface that can be included in the upper surface of the chip 22 when viewed from above. The long sides of the upper surface and the lower surface of the spacer 32b are longer than the long sides of the upper surface and the lower surface of the spacer 32a. The short sides of the upper surface and the lower surface of the spacer 32b are longer than the short sides of the upper surface and the lower surface of the spacer 32a. The spacer 32 has a structure in which the spacer 32b is overlapped on the spacer 32a so that one side is aligned. The spacer 32 is provided so that the side of the spacers 32a and 32b that are overlapped so that one side is aligned faces the side along which the pads PSS2 and PG2 of the chip 22 are provided side by side. The spacer 32 is electrically connected to the pad PSL2.

[0033] An inter-substrate spacer 41 is provided on the circuit pattern 12c and between the chips 21 and 22. An inter-substrate spacer 42 is provided on the circuit pattern 12b and between the chips 21 and 22. Each of the inter-substrate spacers 41 and 42 is a conductor. Each of the inter-substrate spacers 41 and 42 is, for example, a composite material of aluminum and silicon carbide. Each of the inter-substrate spacers 41 and 42 has, for example, a cylindrical shape. The lower surface of the inter-substrate spacer 41 is electrically connected to the circuit pattern 12c. As a result, the inter-substrate spacer 41 is electrically connected to the terminal TN. The lower surface of the inter-substrate spacer 42 is electrically connected to the circuit pattern 12b. As a result, the inter-substrate spacer 42 is electrically connected to the terminals TOUT and TD2 and the drain electrode provided on the lower surface of the chip 22. The height of the upper surface of each of the inter-substrate spacers 41 and 42 is approximately equal to the height of the upper surface of each of the spacers 31 and 32.

[0034] FIG. 5 is a plan view showing an example of the internal structure of the semiconductor device according to the embodiment. In FIG. 5, the sealing material 50 is omitted. As shown in FIG. 5, the circuit pattern 11a provided on the lower surface of the substrate 11 electrically connects the upper surface of the spacer 31 and the upper surface of the inter-substrate spacer 42. As a result, the pad PSL1 of the chip 21 is electrically connected to the terminals TOUT and TD2 and the drain electrode provided on the lower surface of the chip 22. The circuit pattern 11b provided on the lower surface of the substrate 11 electrically connects the upper surface of the spacer 32 and the upper surface of the inter-substrate spacer 41. As a result, the pad PSL2 of the chip 22 is electrically connected to the terminal TN.

[0035] FIG. 6 is a cross-sectional view showing an example of the internal structure of the semiconductor device according to the embodiment. FIG. 6 shows a cross section corresponding to the line VI-VI in FIG. 5. In FIG. 6, the sealant 50 is omitted. The circuit pattern 12a on the substrate 12 and the drain electrode PD1 provided on the lower surface of the chip 21 are bonded by a bonding layer 60. The pad PSL1 provided on the upper surface of the chip 21 and the lower surface of the spacer 31 are bonded by a bonding layer 60. The upper surface of the spacer 31a and the lower surface of the spacer 31b are bonded by a bonding layer 60. The upper surface of the spacer 31 and the circuit pattern 11a provided on the substrate 11 are bonded by a bonding layer 60. The lower surface of the inter-substrate spacer 42 and the circuit pattern 12b on the substrate 12 are bonded by a bonding layer 60. The upper surface of the inter-substrate spacer 42 and the circuit pattern 11a provided on the substrate 11 are bonded by a bonding layer 60. The bonding layer 60 is, for example, solder.

[0036] The same is true for the chip 22, the spacer 32, and the inter-substrate spacer 41. That is, the circuit pattern 12b on the substrate 12 and the drain electrode provided on the lower surface of the chip 22 are joined by a bonding layer. The pad PSL2 provided on the upper surface of the chip 22 and the lower surface of the spacer 32 are joined by a bonding layer. The upper surface of the spacer 32a and the lower surface of the spacer 32b are joined by a bonding layer. The upper surface of the spacer 32 and the circuit pattern 11b provided on the substrate 11 are joined by a bonding layer. The lower surface of the inter-substrate spacer 41 and the circuit pattern 12c on the substrate 12 are joined by a bonding layer. The upper surface of the inter-substrate spacer 41 and the circuit pattern 11b provided on the substrate 11 are joined by a bonding layer. The bonding layer is, for example, solder.

[0037] Fig. 7 is a cross-sectional view showing an example of the internal structure of the semiconductor device according to the embodiment. Fig. 7 shows a cross section corresponding to line VII-VII in Fig. 5. In Fig. 7, the sealing material 50 is omitted. A pad PG1 provided on the upper surface of the chip 21 and a circuit pattern 12e are electrically connected by a bonding wire BW2. In the semiconductor device 1 according to the embodiment, a spacer 31 is not provided above the pad PG1.

[0038] Similarly, no spacer 31 is provided above the pad PSS1. In this manner, in the semiconductor device 1 according to the embodiment, the pad on which wire bonding is performed and the spacer are arranged so as not to overlap each other in a top view.

[0039] The thermal expansion coefficients of the elements used in the semiconductor device 1 according to the embodiment are as follows. The chips 21 and 22, which are mainly made of silicon, have a thermal expansion coefficient of, for example, 2×10 -6 / K~5×10 -6 / K. The copper of the circuit patterns of the substrates 11 and 12 is, for example, 17×10 -6 The aluminum-silicon carbide composite material contained in the spacers 31 and 32 and the inter-substrate spacers 41 and 42 has a thickness of, for example, 10×10 -6 / K. Thus, the thermal expansion coefficient of the aluminum-silicon carbide composite material contained in the spacers 31 and 32 is greater than that of the chips 21 and 22 and is smaller than that of the copper contained in the substrates 11 and 12.

[0040] According to the semiconductor device 1 according to the embodiment, the heat dissipation performance can be improved.

[0041] The spacer provided on the chip is part of the current path that connects the source of the transistor included in the chip to the external connection terminal, and is also one of the heat dissipation paths that transfers heat generated in the chip to the substrate 11.

[0042] According to an embodiment, the spacer provided on the chip is provided so that the area of ​​the upper surface bonded to the substrate is larger than the area of ​​the lower surface bonded to the chip, so that when heat is transferred from the chip to the substrate via the spacer, the heat spreads over a larger area, improving heat dissipation performance.

[0043] In the semiconductor device 1 according to the embodiment, the thermal expansion coefficient of the spacer provided on the chip is larger than that of the chip and smaller than that of the copper contained in the substrate, which prevents the bonding between the chip and the spacer and between the spacer and the substrate from coming apart even if the temperature of the semiconductor device 1 according to the embodiment is repeatedly increased and decreased.

[0044] [2] Modifications, etc. In the above embodiment, a structure in which a flat plate with a small area and a flat plate with a large area are overlapped with one side aligned is shown as an example of the spacers 31 and 32. The spacers 31 and 32 are not limited to this. Several modified examples will be described below.

[0045] FIG. 8 is a plan view showing an example of the internal structure of a semiconductor device according to a first modification. FIG. 8 corresponds to FIG. 4 of the above embodiment. In FIG. 8, the substrate 11 and the sealing material 50 are omitted. In the first modification, the spacer 31 is replaced with a spacer 33, and the spacer 32 is replaced with a spacer 34, as compared to the above embodiment. The spacer 33 includes spacers 33a and 33b. Each of the spacers 33a and 33b is a rectangular flat plate having an approximately equal area of ​​the upper surface and the lower surface. The spacer 33a has an upper surface and a lower surface that can be included in the upper surface of the chip 21 in a top view. The spacer 33b has an upper surface and a lower surface that can include the upper surface of the spacer 33a in a top view. The spacer 33 has a configuration in which the spacer 33b is overlapped on the spacer 33a. More specifically, the spacers 33a and 33b are provided so as to overlap each other, such that the upper surface of the spacer 33a is included in the lower surface of the spacer 33b, and the lower surface of the spacer 33b protrudes from the four sides of the upper surface of the spacer 33a.

[0046] The spacer 34 has a similar configuration to the spacer 33. That is, the spacer 34 includes spacers 34a and 34b. The spacers 34a and 34b are rectangular flat plates with approximately equal areas of the upper and lower surfaces. The spacer 34a has an upper surface and a lower surface that can be included in the upper surface of the chip 22 when viewed from above. The spacer 34b has an upper surface and a lower surface that can include the upper surface of the spacer 34a when viewed from above. The spacer 34 has a configuration in which the spacer 34b is overlapped on the spacer 34a. More specifically, the spacers 34a and 34b are provided overlapping each other so that the upper surface of the spacer 34a is included in the lower surface of the spacer 34b and the lower surface of the spacer 34b protrudes from the four sides of the upper surface of the spacer 34a.

[0047] Fig. 9 is a cross-sectional view showing an example of the internal structure of the semiconductor device according to the first modification. Fig. 9 corresponds to Fig. 7 of the above embodiment. In Fig. 9, the sealing material 50 is omitted. As shown in Fig. 9, in the semiconductor device according to the first modification, a spacer 33b protrudes above the pad PG1.

[0048] The spacers 33 and 34 thus configured have a shape in which the spacer 33b protrudes from the top of the spacer 33a, and the spacer 34b protrudes from the top of the spacer 34a from all four sides. The spacers may be configured in this manner. When the spacers are configured as in the first modified example, the spacers 33 and 34 are provided on the chips 21 and 22, respectively, after the wire bonding process is completed. Also, the spacers are provided so that the bonding wires and the spacers do not come into contact with each other.

[0049] FIG. 10 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to the second modification. FIG. 10 corresponds to FIG. 6 of the above embodiment. In FIG. 10, the sealing material 50 is omitted. In the second modification, the spacer 31 is replaced with a spacer 35 in the above embodiment. The spacer 35 includes spacers 35a and 35b. The spacer 35a is a quadrangular pyramid whose upper and lower surfaces are rectangular and parallel, and whose upper surface area is larger than that of the lower surface. The lower surface of the spacer 35a can be included in the upper surface of the chip 21. The spacer 35b is a quadrangular flat plate whose upper surface area and lower surface area are approximately equal. The lower surface of the spacer 35b can include the upper surface of the spacer 35a. The spacer 35 has a configuration in which the spacer 35b is overlapped on the spacer 35a. More specifically, the spacers 35a and 35b are provided overlapping each other so that the upper surface of the spacer 35a is included in the lower surface of the spacer 35b. The spacers 35a and 35b are bonded to each other via a bonding layer 60. The bonding layer 60 is, for example, solder.

[0050] The spacer 35 thus configured has an inclined portion such that the sidewall of the spacer widens from the bottom to the top. In this manner, the spacer may be configured so that the sidewall of the spacer is inclined.

[0051] Fig. 11 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a third modified example. Fig. 11 corresponds to Fig. 6 of the above embodiment. In Fig. 11, the sealing material 50 is omitted. In the third modified example, the spacer 31 in the above embodiment is replaced with a spacer 36. The spacer 36 is a quadrangular pyramid whose upper and lower surfaces are each rectangular and parallel, and whose area is larger than that of the lower surface. The lower surface of the spacer 36 can be included in the upper surface of the chip 21.

[0052] In this manner, the spacer may be formed only from a part having an inclined side wall, or the spacer may be formed from a single part.

[0053] The configuration of the spacer 36 can also be expressed as a cross-sectional area of ​​the spacer 36 in a plane parallel to the substrates 11 and 12 that increases continuously from the bottom surface to the top surface.

[0054] FIG. 12 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a fourth modification. FIG. 12 corresponds to FIG. 6 of the above embodiment. In FIG. 12, the sealing material 50 is omitted. In the fourth modification, the spacer 31 in the above embodiment is replaced with a spacer 37. The spacer 37 includes spacers 37a, 37b, and 37c. Each of the spacers 37a, 37b, and 37c is a rectangular flat plate with an approximately equal area of ​​the upper surface and the lower surface. The spacer 37a has an upper surface and a lower surface that can be included in the upper surface of the chip 21 in a top view. The spacer 37b has an upper surface and a lower surface that can include the upper surface of the spacer 37a in a top view. The spacer 37c has an upper surface and a lower surface that can include the upper surface of the spacer 37b in a top view. The spacer 37 has a configuration in which the spacer 37b overlaps the spacer 37a, and the spacer 37c overlaps the spacer 37b. More specifically, the spacers 37a, 37b, and 37c are provided so as to overlap each other, such that the upper surface of the spacer 37a is included in the lower surface of the spacer 37b, and the upper surface of the spacer 37b is included in the lower surface of the spacer 37c. The spacers 37a and 37b, and the spacers 37b and 37c are bonded together by a bonding layer 60. The bonding layer 60 is, for example, solder.

[0055] In this way, the number of parts constituting the spacer may be one or more, and is not limited to one or two. The spacer may be composed of any number of parts.

[0056] Fig. 13 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a fifth modified example. Fig. 13 corresponds to Fig. 7 of the above embodiment. In Fig. 13, the sealing material 50 is omitted. In the fifth modified example, unlike the first modified example, the spacer 33 made up of multiple parts is replaced with a spacer 38 made up of a single part. The spacer 38 has a shape similar to the structure in which the spacers 33a and 33b are stacked in the first modified example.

[0057] Fig. 14 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to the sixth modified example. Fig. 14 corresponds to Fig. 6 of the above embodiment. In Fig. 14, the sealing material 50 is omitted. In the sixth modified example, the spacer 35, which is made up of multiple parts in the second modified example, is replaced with a spacer 39 made up of a single part. The spacer 39 has a shape similar to that of the spacers 35a and 35b stacked together in the second modified example.

[0058] In this manner, the spacer constituted by a plurality of parts as described in the above embodiment and modified examples may be constituted by a single part having a similar shape.

[0059] Fig. 15 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a seventh modification. Fig. 15 corresponds to Fig. 7 of the above embodiment. In Fig. 15, the sealing material 50 is omitted. The seventh modification is different from the first modification in that the spacer 33a and the spacer 33b constituting the spacer 33 are directly connected to each other without the bonding layer 60 therebetween.

[0060] Fig. 16 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to an eighth modification. Fig. 16 corresponds to Fig. 6 of the above embodiment. In Fig. 16, the sealing material 50 is omitted. The eighth modification is different from the second modification in that the spacer 35a and the spacer 35b constituting the spacer 35 are directly connected to each other without the bonding layer 60 therebetween.

[0061] In this manner, the spacer constituted by a plurality of parts as described in the above embodiment and modified examples may be configured such that the spacer parts are directly connected to each other.

[0062] In the above embodiment and modified example, when the spacer includes a plurality of components, the bonding layer that bonds the spacer components to each other is solder. The bonding layer that bonds the spacer components to each other may be, for example, a sintered silver material.

[0063] In the above embodiment and modified example, a case where two transistors are included in a power module has been described as an example. The number of transistors included in a power module is not limited to two. The number of transistors included in a power module may be, for example, one, four, or six.

[0064] In this specification, "one end of a current path of a transistor" corresponds to the source or drain of a MOS transistor, and "the other end of a current path of a transistor" corresponds to the drain or source of a MOS transistor.

[0065] In this specification, "connection" refers to being electrically connected, and does not exclude, for example, the interposition of another element. Furthermore, "electrically connected" may be performed through an insulator as long as it is possible for the device to function in the same manner as an electrically connected device.

[0066] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0067] 1...semiconductor device, 11, 12...substrate, 11a, 11b, 12a, 12b, 12c, 12d, 12e, 12f, 12g...circuit pattern, 21, 22...chip, 31, 31a, 31b, 32, 32a, 32b, 33, 33a, 33b, 34, 34a, 34b, 35, 35a, 35b, 36, 37, 37a, 37b, 37c, 38, 39...space , 41, 42...inter-substrate spacer, 50...encapsulant, 60...bonding layer, BW1, BW2, BW3, BW4...bonding wires, NM1, NM2...transistor, PD1...drain electrode, PG1, PG2, PSL1, PSL2, PSS1, PSS2...pads, TD1, TD2, TG1, TG2, TN, TOUT, TP, TS1, TS2...terminals.

Claims

1. A first substrate; a second substrate provided opposite to the first substrate; a chip provided on the first substrate and between the first substrate and the second substrate; a spacer provided on the chip and connecting the chip and the second substrate; Including, A semiconductor device, wherein an area of ​​a second portion of the spacer in contact with the second substrate is larger than an area of ​​a first portion of the spacer in contact with the chip.

2. The semiconductor device according to claim 1 , wherein the first portion of the spacer is includeable on a surface of the chip that contacts the spacer.

3. 2 . The semiconductor device according to claim 1 , wherein the spacer has a thermal expansion coefficient larger than that of the chip and smaller than that of copper contained in the first substrate and the second substrate.

4. the chip includes a transistor; 2. The semiconductor device according to claim 1, wherein said spacer electrically connects one end of a current path of said transistor to said second substrate.

5. The semiconductor device according to claim 1 , wherein said spacer has a portion whose sidewall is inclined from said first portion toward said second portion.

6. The semiconductor device according to claim 1 , wherein a cross-sectional area of ​​said spacer in a plane parallel to said first substrate increases continuously from said first portion toward said second portion.

7. 2 . The semiconductor device according to claim 1 , wherein the spacer includes a first component including the first portion and a second component including the second portion, the first component and the second component being bonded to each other via a bonding layer.

8. The semiconductor device according to claim 7 , wherein the bonding layer includes solder.

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