Semiconductor device and method for supporting design of semiconductor device

Abstract

To provide a semiconductor device which can downsize a circuit and can increase the degree of freedom of designing the circuit in a semiconductor circuit having a MOM capacity.SOLUTION: A semiconductor device 1 includes: a MOM (metal oxide metal) capacity 2 formed by alternately laminating a first electrode 3 and a second electrode 4; and a first shield part 5 and a second shield part 6 provided on both sides of the MOM capacity to hold the MOS capacity in a second direction perpendicular to the first direction in which the first electrode and the second electrode are alternately arranged. The first shield part and the second shield part are electrically insulated from each other in the region between both sides.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a design support device for the semiconductor device. [Background technology]

[0002] Conventionally, there is known a semiconductor device including a MOM (Metal Oxide Metal) capacitor consisting of an electrode group in which a plurality of electrodes face each other, and a pair of shield parts provided facing each other across the MOM capacitor (see, for example, Patent Document 1). In such a semiconductor device, each shield part is connected to ground (earth potential), and the MOM capacitor is surrounded by the shield parts, thereby making it possible to suppress noise that the MOM capacitor receives from surrounding signal lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-2247 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a conventional semiconductor device, for example, a pair of shield parts are metal-bonded to both ends of the MOM capacitor so as to surround the MOM capacitor, as shown in Fig. 12. This causes a problem of an increased circuit size.

[0005] In addition, while it was previously common technical knowledge that the pair of shield parts facing each other across the MOM capacitor should have the same potential, design tools for such devices generally represented the pair of shield parts as one terminal, and as a result, only two-terminal or three-terminal symbols were available for connection symbols for a circuit consisting of an MOM capacitor and a pair of shield parts, as shown in Figure 8.

[0006] The present disclosure has been made in consideration of the above circumstances, and aims to provide a semiconductor device that can reduce the size of a semiconductor circuit having a MOM capacitance and increase the freedom of circuit design. [Means for solving the problem]

[0007] A semiconductor device according to some embodiments of the present disclosure includes a MOM (metal oxide metal) capacitor formed by alternating first electrodes and second electrodes, and a first shielding portion and a second shielding portion provided on either side of the MOM capacitor in a second direction perpendicular to a first direction in which the first electrodes and the second electrodes are alternately arranged, and the first shielding portion and the second shielding portion are electrically insulated in a region between the either side.

[0008] A design support device for a semiconductor device according to some embodiments of the present disclosure is a design support device for a semiconductor device having a first shield portion and a second shield portion arranged on either side of a MOM (metal oxide metal) capacitor formed by alternatingly arranging first electrodes and second electrodes, and is equipped with a symbol memory means in which a plurality of symbols indicating the connection states of a plurality of elements constituting the semiconductor device, including a four-terminal connection symbol representing the connection states of the first electrode, the second electrode, the first shield portion, and the second shield portion, are stored, and a circuit diagram design support means for designing a circuit diagram of the semiconductor device using the symbols stored in the symbol memory means. Effect of the Invention

[0009] According to the present disclosure, in a semiconductor circuit having a MOM capacitor, it is possible to reduce the size of the circuit and increase the degree of freedom in circuit design. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic diagram of an electronic device circuit including a semiconductor device according to an embodiment of the present disclosure. [Diagram 2]1 is a cross-sectional view of a four-terminal semiconductor device including a MOM capacitor according to an embodiment of the present disclosure. [Diagram 3] 1 is a plan view of a four-terminal semiconductor device including a MOM capacitor according to an embodiment of the present disclosure. [Figure 4] 4 is a schematic diagram illustrating a connection relationship between a first shield part and a second shield part and each ground terminal of the semiconductor device according to the embodiment of the present disclosure. FIG. [Diagram 5] FIG. 1 is a schematic configuration diagram illustrating an example of a hardware configuration of a design support apparatus according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a functional block diagram illustrating an example of functions of a design support apparatus according to an embodiment of the present disclosure. [Figure 7] 13 is a diagram showing parasitic capacitance in a MOM capacitor when a first shield part and a second shield part are metallically joined and connected to a ground terminal. FIG. [Figure 8] 13 is a diagram showing an example of a connection symbol in a MOM capacitor in which a first shield portion and a second shield portion are metallically joined and connected to a ground terminal. FIG. [Figure 9] 11 is a diagram showing parasitic capacitance in a MOM capacitor when a first shield part and a second shield part are connected to different ground terminals. FIG. [Figure 10] 13 is a diagram showing an example of a connection symbol when a first shield portion and a second shield portion are connected to different ground terminals in a MOM capacitor. FIG. [Figure 11] FIG. 1 is a flowchart illustrating an overview of LVS verification according to an embodiment of the present disclosure. [Figure 12] FIG. 1 is a cross-sectional view of a conventional three-terminal semiconductor device having a MOM capacitor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of a semiconductor device and a design support device thereof according to the present disclosure will be described with reference to the drawings.

[0012] 1 is a schematic diagram of an electronic device circuit including a semiconductor device 1. The electronic device circuit 8 includes terminals for different supply voltages V1 and V2, ground terminals GND1 and GND2 having different ground potentials, and a semiconductor device 1. The electronic device circuit 8 is a device in which single-function (discrete) semiconductors such as diodes, transistors, resistors, and capacitors are assembled on one chip. In this embodiment, the semiconductor device 1 included in the electronic device circuit 8 is a MOM capacitor.

[0013] 2 is a cross-sectional view of a four-terminal semiconductor device including a MOM capacitor according to this embodiment. In this embodiment, as shown in FIG. 2, the direction in which A electrodes (first electrodes) 3 and B electrodes (second electrodes) 4 are alternately arranged is defined as a first direction. Also, as shown in FIG. 2, the direction perpendicular to the first direction is defined as a second direction. As for the depth direction perpendicular to each of the first and second directions, a cross section as shown in FIG. 2 is assumed to be formed continuously over a predetermined range, and a description thereof will be omitted. FIG. 3 is a plan view of the semiconductor device shown in FIG.

[0014] 2 and 3, the semiconductor device 1 according to this embodiment includes an A electrode 3, a B electrode 4 arranged alternately with the A electrode 3, a first shield section 5 located above the A electrode 3 and the B electrode 4 in the stacking direction (second direction) of the semiconductor device 1, and a second shield section 6 located below the A electrode 3 and the B electrode 4 in the stacking direction (second direction) of the semiconductor device 1. The MOM capacitor 2 is formed by the A electrode 3 and the B electrode 4. The A electrode 3 has one or more main lines 31, and the B electrode 4 has one or more main lines 41 similar to the A electrode.

[0015] The MOM capacitor 2 is a capacitance element that utilizes coupling capacitance between wirings. Specifically, the MOM capacitor 2 is composed of an A electrode 3, a B electrode 4, one or more main lines 31 of the A electrode 3, and one or more main lines 41 of the B electrode 4. Specifically, one or more main lines 31, 41 are alternately arranged in a predetermined first direction (for example, the horizontal direction on the paper in FIG. 2). One or more main lines 31, 41 are wired close to each other along a line segment l-l' (the vertical direction on the paper in FIG. 3) connecting the A electrode 3 and the B electrode 4. With this configuration, a coupling capacitance (parasitic capacitance) is generated between the main lines 31, 41.

[0016] The first shield section 5 is provided on one side of the MOM capacitance 2 in a second direction (e.g., the vertical direction of the paper in FIG. 2) perpendicular to the first direction so as to sandwich the MOM capacitance 2 together with the second shield section 6 described later. The first shield section 5 is provided so as to cover the MOM capacitance 2, and suppresses coupling capacitance occurring between the MOM capacitance 2 and a signal line (not shown) wired near the MOM capacitance 2. This suppresses noise that the MOM capacitance 2 receives from the signal line. In addition, the first shield section 5 can suppress coupling capacitance occurring between, for example, a signal line wired in a layer above the first shield section 5 and the MOM capacitance 2. In this way, noise that the MOM capacitance 2 receives from the signal line can be suppressed.

[0017] Similarly, the second shield part 6 is provided on the opposite side of the first shield part 5 in a second direction perpendicular to the first direction so as to sandwich the MOM capacitance 2. The second shield part 6 is provided so as to cover the MOM capacitance 2, and suppresses coupling capacitance occurring between the MOM capacitance 2 and a signal line wired in the vicinity of the MOM capacitance 2. This suppresses noise received by the MOM capacitance 2 from the signal line. In addition, the second shield part 6 can suppress coupling capacitance occurring between, for example, a signal line wired in a layer below the second shield part 6 and the MOM capacitance 2. In this way, noise received by the MOM capacitance 2 from the signal line can be suppressed.

[0018] Here, Fig. 12 is a cross-sectional view of a conventional three-terminal semiconductor device having a MOM capacitor. In Fig. 12, in the semiconductor device 1', the first shield section 5' and the second shield section 6' are metal-joined in the stacking direction (second direction) of the semiconductor device 1' in the wiring spaces S' on the left and right of the MOM capacitor 2'. In other words, the first shield section 5' and the second shield section 6' are at the same potential and can be regarded as a single electrical configuration. As a result, the semiconductor device 1' is a three-terminal semiconductor device consisting of the A electrode 3', the B electrode 4', the first shield section 5', and the second shield section 6'.

[0019] 2, in the semiconductor device 1 of this embodiment, the first shield part 5 and the second shield part 6 are not metal-joined in the second direction in the wiring spaces S on the left and right of the MOM capacitor 2, compared to the three-terminal semiconductor device 1' shown in Fig. 12, and therefore it is possible to reduce the number of wiring connections and the wiring space S in the semiconductor device 1. In other words, it is possible to reduce the size of the semiconductor device 1.

[0020] As described above, in the four-terminal semiconductor device 1, the first shield section 5 and the second shield section 6 can each have a different terminal. Fig. 4 is a schematic diagram showing the connection relationship between the first shield section and the second shield section of the semiconductor device according to this embodiment and each ground terminal. In the example of Figs. 4(a) and (b), the first shield section 5 and the second shield section 6 are each connected to a different ground terminal.

[0021] For example, in Fig. 4(a), the first shield part 5 is connected to a ground terminal GND1 having a predetermined potential, and the second shield part 6 is connected to a ground terminal GND2 having a potential different from that of the ground terminal GND1. Also, in Fig. 4(b), the first shield part 5 is connected to the ground terminal GND2, and the second shield part 6 is connected to the ground terminal GND1. Thus, in the four-terminal semiconductor device 1 of this embodiment, the first shield part 5 and the second shield part 6 are not metallically joined to each other in the stacking direction (second direction) of the semiconductor device 1. This allows them to be connected to different ground terminals in consideration of the wiring of the circuit, and improves the degree of freedom in designing the wiring of the semiconductor device 1.

[0022] Fig. 5 is a schematic diagram showing an example of a hardware configuration of a design support device according to an embodiment of the present disclosure. As shown in Fig. 5, the design support device 10 (design support device for semiconductor device) has a computer (computer system), and includes, for example, a CPU 11, an auxiliary storage device 12 for storing programs executed by the CPU 11 and data referenced by the programs, a main storage device 13 that functions as a work area when each program is executed, a communication interface 14 for connecting to a network, an input unit 15 including a keyboard, a mouse, and the like, and a display unit 16 including a liquid crystal display device for displaying data. These units are connected via, for example, a bus 18. Examples of the auxiliary storage device 12 include a magnetic disk, a magneto-optical disk, and a semiconductor memory.

[0023] A series of processes for realizing various functions described below is stored in the auxiliary storage device 12 in the form of a program (e.g., a design support program), for example, and the CPU 11 reads this program into the main storage device 13 and executes information processing and arithmetic processing to realize various functions. Note that the program may be pre-installed in the auxiliary storage device 12, provided in a state stored in another computer-readable storage medium, or distributed via wired or wireless communication means. Examples of computer-readable storage media include magnetic disks, magneto-optical disks, CD-ROMs, DVD-ROMs, and semiconductor memories.

[0024] 6 is a functional block diagram showing an example of functions of a design support device according to an embodiment of the present disclosure. As shown in FIG. 6, the design support device 10 includes a storage unit (symbol storage means) 101, a circuit diagram design support unit 102a, a layout diagram design support unit 102b, and a verification unit 103.

[0025] The storage unit 101 stores symbol data sym and physical property values ​​of elements used when creating design drawings of the semiconductor device 1, for example, circuit diagrams. The stored element symbols are, for example, symbols corresponding to semiconductor elements such as resistor elements, capacitor elements, and transistors. The elements stored in the storage unit 101 may also include symbols of various elements not used in the semiconductor device 1 according to the present disclosure, such as power supply elements and control ICs. The storage unit 101 also stores a plurality of symbols indicating the connection states of a plurality of elements required for designing an electronic device circuit, including a four-terminal connection symbol indicating the connection states of the A electrode, the B electrode, the first shielding part, and the second shielding part corresponding to the semiconductor device 1 of the present embodiment.

[0026] For example, Fig. 7 is a diagram showing parasitic capacitance in a MOM capacitance when the first and second shielding parts are metallically joined and connected to a ground terminal. Fig. 8 is a diagram showing an example of a connection symbol in a MOM capacitance when the first and second shielding parts are metallically joined and connected to a ground terminal. In this way, when the first and second shielding parts are at the same potential, the connection symbol is expressed as a three-terminal connection symbol (hereinafter referred to as a "three-terminal connection symbol") consisting of a terminal of the A electrode, a terminal of the B electrode, and one ground terminal, as shown in Fig. 8.

[0027] For example, Fig. 9 is a diagram showing parasitic capacitance in a case where the first shield part and the second shield part are connected to different ground terminals in a MOM capacitance. Fig. 10 is a diagram showing an example of a connection symbol in a case where the first shield part and the second shield part are connected to different ground terminals in a MOM capacitance. In this way, when the first shield part and the second shield part are at different potentials, the connection symbol is expressed as a four-terminal connection symbol (hereinafter referred to as a "four-terminal connection symbol") consisting of a terminal of the A electrode, a terminal of the B electrode, and two ground terminals GND1 and GND2, as shown in Fig. 10. In addition, the four-terminal connection symbol can also be used as a three-terminal connection symbol by indicating that the two ground terminals GND1 and GND2 are a shared ground terminal.

[0028] In the memory unit 101 shown in Figure 6, the above-mentioned three-terminal connection symbol and four-terminal connection symbol are stored as symbol data sym as symbols indicating the connection state of the MOM capacitance and the first shield part and second shield part provided on both sides of the MOM capacitance.

[0029] Furthermore, information on wiring connections between elements in a circuit diagram and a layout diagram created by an operation by a designer (described later) is stored in the storage unit 101. For example, the storage unit 101 stores circuit diagram data SD including connection information (netlist) between elements in a circuit diagram, and layout data LD including connection information (netlist) between elements in a layout diagram.

[0030] The circuit diagram design support unit (circuit diagram design support means) 102a supports the circuit design of the semiconductor device. The circuit diagram design support unit 102a accepts input operations by the designer via the input unit, and is connected to the storage unit 101 so as to be capable of two-way communication. The designer uses the circuit diagram design support unit 102a to create a circuit diagram of an electronic device circuit to be designed, using the symbol data sym stored in the storage unit 101. The circuit diagram data SD created using the circuit diagram design support unit 102a is stored in the storage unit 101. As described above, the inclusion of a four-terminal connection symbol is novel, but other circuit design support techniques for semiconductor devices are known techniques, and the circuit diagram design support unit 102a according to this embodiment may employ these known techniques as appropriate.

[0031] The layout diagram design support unit 102b supports the design of a layout diagram of a semiconductor device. The layout diagram design support unit 102b accepts input operations by a designer via an input unit, and is connected to the storage unit 101 for two-way communication. By using the layout diagram design support unit 102b, the designer creates a layout diagram of an electronic device circuit, which is a design target, using the symbol data sym stored in the storage unit 101. In addition, the layout data LD created by using the layout diagram design support unit 102b is stored in the storage unit 101. Note that the design support technology for layout diagrams of semiconductor devices is a publicly known technology, and such a publicly known technology may be appropriately adopted.

[0032] The verification unit 103 verifies whether the connection information between elements shown in the layout diagram and the circuit diagram of the semiconductor device is consistent. Specifically, based on the circuit diagram data SD and the layout data LD stored in the storage unit 101, the verification unit 103 compares the connection information (netlist) between each element in the circuit diagram data SD with the connection information (netlist) between each element in the layout data LD, and verifies whether each piece of connection information is consistent. In addition, the verification unit 103 includes, for example, a netlist extraction unit 103a and a comparison unit 103b in order to perform the LVS verification described later.

[0033] The netlist extraction unit 103a receives as input the circuit diagram data SD of the electronic device circuit stored in the storage unit 101 and the layout data LD of the electronic device circuit, and extracts netlists from each of them.

[0034] The comparison unit 103b compares, for the electronic device circuit, a netlist extracted from the circuit diagram data SD with a netlist extracted from the layout data LD, and determines whether they are equivalent.

[0035] The verification unit 103 displays the comparison result of the comparison unit 103b on the display unit, thereby evaluating whether the connection information of the circuit diagram and the layout diagram is consistent, i.e., whether they are equivalent, and notifies the designer of the evaluation result.

[0036] 11 is a flow chart diagram for explaining an overview of LVS verification according to an embodiment of the present disclosure. In the LVS verification, it is verified whether elements and connection information between elements created in the logic / circuit design stage are properly realized in the layout design. In the example of FIG. 11, specifically, in the LVS verification, a netlist extracted from the circuit diagram data SD is compared with a netlist extracted from the layout data (layout drawing) LD of the electronic device circuit 8 to verify whether they are equivalent.

[0037] First, the netlist extraction unit 103a included in the verification unit 103 extracts a netlist including connection information between elements obtained from the circuit diagram data SD (step S11). The netlist extraction unit 103a included in the verification unit 103 also extracts a netlist from the layout data LD by restoring the connection information between elements in the layout data LD (step S12).

[0038] Next, the verification unit 103 performs LVS verification. Specifically, the comparison unit 103b included in the verification unit 103 compares the netlist extracted from the circuit diagram data SD with the netlist extracted from the layout data LD (step S13). As a result, if the netlist extracted from the circuit diagram data SD and the netlist extracted from the layout data LD match ("YES" in step S14), the verification unit 103 performs a normal judgment (step S15). On the other hand, if the netlist extracted from the circuit diagram data SD and the netlist extracted from the layout data LD do not match ("NO" in step S14), the verification unit 103 performs an error judgment (step S16).

[0039] As described above, the semiconductor device and the semiconductor device design support device according to this embodiment provide the following advantageous effects. For example, according to the semiconductor device design support device of this embodiment, a semiconductor device having an MOM capacitance has a four-terminal connection symbol that indicates that the first shield part and the second shield part are connected to different ground terminals. This makes it possible to design a semiconductor device in which the first shield part and the second shield part are connected to different ground terminals. That is, in the design of a conventional MOM capacitance, it is assumed that the first shield part and the second shield part are directly connected, and there was no idea of ​​connecting the first shield part and the second shield part to different ground terminals. Even if a designer wanted to connect the first shield part and the second shield part to different ground terminals, there was no connection symbol that represents such a circuit, so the designer could not design it. In addition, it is possible to use a conventional three-terminal connection symbol as a connection mode for connecting the first shield part and the second shield part to different ground terminals, but in that case, the netlist extracted from the circuit diagram data SD and the netlist extracted from the layout data LD will not match, and an error will be determined in the LVS verification.

[0040] For these reasons, it has not been possible to design a semiconductor device in which the first shield part and the second shield part are connected to different ground terminals, and as a result, no such semiconductor device has existed. In contrast, the design support device for a semiconductor device according to this embodiment has a four-terminal connection symbol (see FIG. 10) as one of the connection symbols, and by using this four-terminal connection symbol during circuit design, it is possible to increase the degree of freedom in designing the semiconductor device. Furthermore, by using the design support device for a semiconductor device according to this embodiment, it is possible to connect the first shield part and the second shield part to different ground terminals, and therefore it is not necessary to connect the shield metals at both ends to surround the MOM capacitor, as in the conventional MOM capacitor shown in FIG. 12. This allows for freedom in wiring arrangement for the connection between the first shield part and the second shield part, increasing the degree of freedom in circuit design and enabling the miniaturization of the semiconductor device to be realized. Furthermore, by using symbols corresponding to the actual circuits when creating design drawings, it is possible to reduce error outputs related to connection information in LVS verification, thereby making design work more efficient.

[0041] Although the present disclosure has been described above using the embodiments, the technical scope of the present disclosure is not limited to the scope described in the above embodiments. Various modifications or improvements can be made to the above embodiments without departing from the gist of the present disclosure, and the forms in which such modifications or improvements are made are also included in the technical scope of the present disclosure. In addition, the above embodiments may be appropriately combined. For example, in the above embodiment, the design support device 10 is described as having the layout diagram design support unit 102b and the verification unit 103, but the layout diagram design support unit 102b and the verification unit 103 do not necessarily need to be provided in the design support device 10. For example, the layout diagram design support unit 102b may be performed using another computer system. In addition, the LVS verification performed by the verification unit 103 may be performed in another computer system by acquiring circuit diagram data designed by the design support device 10 and layout data designed by the other computer system via a communication medium and using these data.

[0042] <Additional Notes> The semiconductor device and the design support device according to the above-described embodiments can be understood, for example, as follows. A semiconductor device 1 according to a first aspect of the present disclosure comprises a MOM (Metal oxide Metal) capacitor 2 formed by alternating first electrodes 3 and second electrodes 4, and a first shielding portion 5 and a second shielding portion 6 provided on either side of the MOM capacitor in a second direction perpendicular to the first direction in which the first electrodes and the second electrodes are alternately arranged, and the first shielding portion and the second shielding portion are electrically insulated in the region between the either side.

[0043] According to the semiconductor device disclosed herein, it is possible to reduce the space in which the first shield section and the second shield section were metal-connected in a direction perpendicular to the direction in which the electrodes that make up the MOM capacitance are alternately arranged, thereby achieving the effect of miniaturization.

[0044] A second aspect of the present disclosure relates to a semiconductor device in accordance with the first aspect, wherein the first shield portion and the second shield portion are connected to ground terminals GND1 and GND2 having different potentials.

[0045] According to the semiconductor device of the present disclosure, the first shield part and the second shield part each have a terminal independent of each other and are connected to a ground terminal having a different potential. That is, the terminal of the first shield part and the terminal of the second shield part can be at different potentials. This improves the degree of freedom in wiring each terminal of the semiconductor device.

[0046] A design support device 10 for a semiconductor device according to a third aspect of the present disclosure is a design support device for a semiconductor device 1 having a first shield portion 5 and a second shield portion 6 arranged on both sides of a MOM (Metal Oxide Metal) capacitor 2 formed by alternatingly arranging first electrodes 3 and second electrodes 4, and is equipped with a symbol storage means 101 in which a plurality of symbols indicating the connection states of a plurality of elements constituting the semiconductor device are stored, including a four-terminal connection symbol representing the connection states of the first electrode, the second electrode, the first shield portion, and the second shield portion, and a circuit diagram design support means 102a for designing a circuit diagram of the semiconductor device using the symbols stored in the symbol storage means.

[0047] According to the design support device for a semiconductor device according to some aspects of the present disclosure, a designer can use a four-terminal connection symbol corresponding to a four-terminal semiconductor device when creating a circuit diagram. In this way, if the circuit diagram is created using the four-terminal connection symbol corresponding to a four-terminal semiconductor device, when performing LVS (layout versus schematic) verification using a layout diagram corresponding to the circuit diagram, it is possible to suppress errors in LVS verification, and it is possible to improve the efficiency of design work. [Explanation of symbols]

[0048] 1,1' Semiconductor device 2,2' MOM capacity 3,3' A electrode 4,4' B electrode 5,5' 1st shield part 6,6' Second shield section 8 Electronic Device Circuits 10 Design support equipment 11 CPU 12 Auxiliary storage 13 Main memory 14 Communication Interface 15 Input section 16 Display 18 Bus 31,41 Main Line 101 Storage section 102a Circuit Diagram Design Support Department 102b Layout Design Support Department 103 Verification Department 103a Netlist Extraction Unit 103b Comparison section GND1, GND2 Ground terminals LD layout data S,S' Wiring space SD circuit diagram data sym symbol data V1, V2 supply voltage

Claims

1. A MOM (Metal Oxide Metal) capacitor formed by alternately arranging first electrodes and second electrodes; a first shield portion and a second shield portion provided on both sides of the MOM capacitor in a second direction perpendicular to a first direction in which the first electrodes and the second electrodes are alternately arranged; Equipped with The semiconductor device, wherein the first shield portion and the second shield portion are electrically insulated in a region between the two sides.

2. The semiconductor device according to claim 1 , wherein the first shield portion and the second shield portion are connected to ground terminals having different potentials.

3. A design support device for a semiconductor device including a first shield section and a second shield section provided on both sides of a MOM (Metal Oxide Metal) capacitor formed by alternately arranging first electrodes and second electrodes, the device comprising: a symbol storage means for storing a plurality of symbols including a four-terminal connection symbol representing a connection state of the first electrode, the second electrode, the first shield portion, and the second shield portion, the plurality of symbols representing a connection state of a plurality of elements constituting a semiconductor device; a circuit diagram design support means for designing a circuit diagram of a semiconductor device using the symbols stored in the symbol storage means; A design support device for a semiconductor device comprising:

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