Power conversion device

Abstract

To highly accurately estimate a current flowing through a switching element provided in a power conversion device.SOLUTION: A power conversion device 1 includes: a switching element 101; an integration circuit 106 outputting an integrated value (output voltage Vout) of a voltage that is generated in an inductance component 103 and a parasitic resistance 104 connected in series to a source electrode that is a main electrode of the switching element 101; and a first current detection circuit 21 obtaining a current IS flowing through the source electrode of the switching element 101, based on the output voltage Vout output from the integration circuit 106. The first current detection circuit 21 calculates a first current value representing a magnitude of a current flowing through the source electrode based on a first integrated value output from the integration circuit 106 in an interval before and after the switching element 101 is turned off and a second integrated value output from the integration circuit 106 in an interval before and after the switching element 101 is turned on.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] With growing social awareness of protecting the global environment and using resources efficiently, and with the economic rationality of household finances as a backdrop, it is predicted that new services such as car sharing, autonomous driving, and MaaS (Mobility as a Service) will become more widespread in the future, leading to a significant increase in the operating rate of automobiles. In order to accommodate this increase in operating time for various devices installed in automobiles, it is necessary to either extend the lifespan of components or maintain their functionality through appropriate maintenance. There are many constraints, such as cost and performance, in order to extend the lifespan of parts, and it is expected that significant improvements will take time. For this reason, it is considered effective to carry out maintenance in conjunction with predictive diagnosis technology that detects abnormalities in parts before they break down, and to replace parts at the appropriate time.

[0003] For example, the techniques of Patent Documents 1 and 2 are known for detecting abnormalities in components in on-board devices. Patent Document 1 discloses a technique for estimating the current value of a current sensor provided in each phase of a three-phase AC motor mounted on an electric vehicle based on measurements by current sensors of the other two phases, and determining the presence or absence of a failure in the current sensor in each phase by comparing the estimated result with the measurement value in each phase. Patent Document 2 discloses a technique for detecting a potential difference in wiring connected to each terminal of a switching element constituting an upper arm or a lower arm of a power module in a power conversion device mounted on an electric vehicle, and estimating the current value of each wiring based on the detected potential difference, thereby independently detecting a short circuit and an overcurrent in the switching element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2000-116176 A [Patent Document 2] JP 2017-92789 A Summary of the Invention [Problem to be solved by the invention]

[0005] The technology of Patent Document 1 can detect a failure of a current sensor in one of three phases, but cannot detect a failure of a current sensor in two or more phases because it cannot estimate the current value of each phase. On the other hand, the technology of Patent Document 2 can detect a short circuit and an overcurrent in each phase arm, but does not consider the temperature change of the parasitic resistance component, and the accuracy of the current estimation is low.

[0006] SUMMARY OF THE PRESENT EMBODIMENTS In view of the above, an object of the present invention is to accurately estimate a current flowing through a switching element provided in a power conversion device. [Means for solving the problem]

[0007] A power conversion device according to the present invention comprises a switching element, an integrating circuit that outputs an integral value of a voltage generated in an inductance component and a parasitic resistance connected in series to a main electrode of the switching element, and a first current detection circuit that determines a current flowing in the main electrode of the switching element based on the integral value output from the integrating circuit, and the first current detection circuit calculates a first current value indicating the magnitude of the current flowing in the main electrode based on a first integral value output from the integrating circuit in a period before and after the switching element is turned off and a second integral value output from the integrating circuit in a period before and after the switching element is turned on. Effect of the Invention

[0008] According to the present invention, it is possible to accurately estimate a current flowing through a switching element provided in a power conversion device. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of the configuration of a power conversion device according to a first embodiment of the present invention. [Diagram 2] FIG. 13 is a diagram illustrating an apparent source current estimate value. [Diagram 3] 4A to 4C are diagrams illustrating examples of waveforms when a switching element is turned off and turned on. [Figure 4] FIG. 2 is a diagram illustrating a configuration example of a first current detection circuit. [Diagram 5] 10A and 10B are diagrams illustrating examples of gate commands and output current waveforms for explaining specific examples of pulse conditions. [Figure 6] FIG. 13 is a table summarizing the pulse conditions and current detection timings of each phase. [Figure 7A] 6 is an enlarged view of a portion of a section including a period corresponding to pulse condition U-(I) in the waveform example of FIG. 5. [Figure 7B] 6 is an enlarged view of a portion of a section including a period corresponding to pulse condition U-(II) in the waveform example of FIG. 5. [Figure 7C] 6 is an enlarged view of a portion of a section including a period corresponding to pulse condition U-(III) in the waveform example of FIG. 5. [Figure 7D] 6 is an enlarged view of a portion of a section including a period corresponding to pulse condition U-(IV) in the waveform example of FIG. 5. [Figure 8] FIG. 11 is an explanatory diagram of the effect of applying the present invention. [Figure 9] 11 is a diagram showing how the magnitude of the relative error of the estimated current with respect to the true output current changes when the resistance value of the parasitic resistance is changed. FIG. [Figure 10] FIG. 6 is a diagram illustrating an example of the configuration of a power conversion device according to a second embodiment of the present invention. [Figure 11A] FIG. 11 is a diagram showing an example of a flowchart illustrating a process flow when an abnormality detection circuit according to a second embodiment of the present invention performs abnormality determination. [Figure 11B] FIG. 11 is a diagram showing an example of a flowchart illustrating a process flow when an abnormality detection circuit according to a second embodiment of the present invention performs abnormality determination. [Figure 12] FIG. 11 is a diagram illustrating an example of the configuration of a power conversion device according to a third embodiment of the present invention. [Figure 13] FIG. 11 is a diagram illustrating an example of the configuration of a power conversion device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (First embodiment) In the first embodiment of the present invention described below, an example of a power conversion device is described in which, instead of using conventional current sensors, an output current is calculated based on the integral value of the voltage of the inductance component and parasitic resistance at the main terminals of each switching element, and the calculation result is used to control a motor.

[0011] FIG. 1 is a diagram showing an example of the configuration of a power conversion device according to a first embodiment of the present invention. The power conversion device 1 shown in FIG. 1 is connected between a storage battery 2 and a motor 3, and converts DC power supplied from the storage battery 2 into AC power to power a stator winding (U-phase winding L u , V phase winding L V , W phase winding L W ) to rotate and drive a motor 3. The power conversion device 1, the storage battery 2, and the motor 3 are mounted on an electric vehicle such as an electric car, and the electric vehicle is driven using the driving force generated by the motor 3. The power conversion device 1 is configured with an inverter circuit 10, a smoothing capacitor 11, and a control device 20.

[0012] The inverter circuit 10 has a plurality of power modules 100 (U-phase upper arm power module 100UU, U-phase lower arm power module 100UL, V-phase upper arm power module 100VU, V-phase lower arm power module 100VL, W-phase upper arm power module 100WU, and W-phase lower arm power module 100WL) respectively provided for the upper and lower arms of each phase of the three-phase AC current output from the power conversion device 1 to the motor 3. Each power module 100 has a switching element 101, a freewheeling diode 102, an inductance component 103, and a parasitic resistance 104, and is connected to a gate driver 105 and an integrating circuit 106.

[0013] The DC power supplied from the storage battery 2 is input to the inverter circuit 10 via a smoothing capacitor 11. The inverter circuit 10 receives a gate command V G (U-phase upper arm gate command V G_UU , U-phase lower arm gate command V G_UL , V-phase upper arm gate command V G_VU , V-phase lower arm gate command V G_VL , W-phase upper arm gate command V G_WU , W-phase lower arm gate command V G_WL ) the switching elements 101 of the power modules 100 are switched in response to the input voltage Vout, thereby converting the DC power into three-phase AC power. The smoothing capacitor 11 suppresses fluctuations in the DC voltage caused by the switching of the switching elements 101.

[0014] The switching element 101 has a pair of main electrodes and a gate electrode, and is a power semiconductor element that performs switching drive to connect or disconnect the pair of main electrodes in response to a gate signal input from a gate driver 105 to the gate electrode. The switching element 101 is configured using, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). When the switching element 101 is a MOSFET, the main electrodes are a source electrode and a drain electrode, and when the switching element 101 is an IGBT, the main electrodes are an emitter electrode and a collector electrode. An example in which the switching element 101 is a MOSFET will be described below, but the same applies to the case of an IGBT.

[0015] The freewheel diode 102 is connected in anti-parallel to the switching element 101, and protects the switching element 101 from a current flowing in the reverse direction in the power module 100. When the switching element 101 is a MOSFET, the body diode of the MOSFET may be used as the freewheel diode 102.

[0016] An inductance component 103 and a parasitic resistance 104 connected in series with the source electrode of the switching element 101 represent, for example, an inductance component and a resistance component inside the switching element 101 and in the wiring of the power module 100 and the inverter circuit 10.

[0017] The gate driver 105 receives a gate command V G Based on this, a pulsed gate signal is output to the gate electrode of the switching element 101. The switching element 101 is alternately turned on and off in response to this gate signal, whereby the switching element 101 is switched and driven, and DC power is converted into AC power.

[0018] The integrating circuit 106 detects the voltage across the series connection of the inductance component 103 and the parasitic resistance 104, and outputs an output voltage V out The integration circuit 106 detects the voltage generated across the series connection of the inductance component 103 and the parasitic resistance 104 in the section before and after the switching element 101 is turned off and in the section before and after the switching element 101 is turned on, and outputs an output voltage V out The integrating circuit 106 is configured by an integrating circuit with a reset switch that uses, for example, an operational amplifier.

[0019] The control device 20 has a plurality of first current detection circuits 21 provided for each power module 100 of the inverter circuit 10, an output current estimation circuit 22, a control signal generation circuit 23, and a communication connector 24.

[0020] Each first current detection circuit 21 receives an output voltage V out Each first current detection circuit 21 detects the input output voltage V out Based on this, a calculation method called the di / dt integration method described later is used to calculate the magnitude of the current flowing through the main electrode (source electrode) of the switching element 101 in each arm of each phase, and the calculation result is referred to as the first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ) to the output current estimation circuit 22. The method of calculating the first current value by the first current detection circuit 21 will be described in detail later.

[0021] The output current estimation circuit 22 estimates the first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL, W-phase upper arm current I WU , W-phase lower arm current I WL ), the output current of each phase (U-phase output current I outU , V phase output current I outV , W-phase output current I outW ) is estimated. Then, the estimated results of the output current of each phase are output to the control signal generating circuit 23. The method of estimating the output current of each phase by the output current estimating circuit 22 will be described in detail later.

[0022] The control signal generating circuit 23 performs a known vector control based on the estimation result of the output current of each phase by the output current estimating circuit 22, and generates a gate command V for each arm of each phase in response to a torque command input from a higher-level control device (not shown) via a communication connector 24. G (U-phase upper arm gate command V G_UU , U-phase lower arm gate command V G_UL , V-phase upper arm gate command V G_VU , V-phase lower arm gate command V G_VL , W-phase upper arm gate command V G_WU , W-phase lower arm gate command V G_WL ) and outputs it to the inverter circuit 10.

[0023] Specifically, for example, the control signal generating circuit 23 determines a d-axis current command value Id* and a q-axis current command value Iq* based on the voltage and torque command of the storage battery 2, and determines a U-phase output current I outU , V phase output current I outV and W-phase output current I outWis converted to output currents on the dq axes (d-axis current value Id and q-axis current value Iq). Then, the d-axis voltage command value Vd* and the q-axis voltage command value Vq* are calculated from the difference between the d-axis current command value Id* and the d-axis current value Id, and the difference between the q-axis current command value Iq* and the q-axis current value Iq. These voltage command values ​​are then converted from two-phase to three-phase to calculate the voltage commands for each phase (U-phase voltage command value Vu*, V-phase voltage command value Vv*, and W-phase voltage command value Vw*). By performing PWM control based on the voltage commands for each phase calculated in this way, the gate commands V for each arm of each phase are calculated. G The above-described method for generating the gate command is merely an example, and the control signal generating circuit 23 can generate the gate command by any method as long as the gate command for each arm of each phase can be generated based on the estimation result of the output current of each phase by the output current estimating circuit 22.

[0024] Next, the details of the method of calculating the first current value by the first current detection circuit 21 (di / dt integration method) will be described below. In the following, the output voltage V out Based on this, an example will be described in which the magnitude of the current flowing through the source electrode of the switching element 101 in the W-phase upper arm power module 100WU is calculated as a first current value by the corresponding first current detection circuit 21, but the same applies to the other first current detection circuits 21.

[0025] The inductance value of the inductance component 103 in the W-phase upper arm power module 100WU is L Ss , the resistance value of the parasitic resistor 104 is R Ss Then, the voltage V Ss is expressed by the following (Equation 1). In (Equation 1), di S / dt represents the time rate of change of the source current flowing through the switching element 101 .

number

[0026] The output voltage V from the integrator circuit 106 out is the voltage V Ss Using the above, it is expressed by the following (Equation 2). In Equation (2), R i ,C i represent the values ​​of the resistance component and capacitance component of the integrating circuit 106, respectively.

number

[0027] In (Equation 2), t st , t read represent the start time of the integration operation and the read time in the integration circuit 106. That is, in the integration circuit 106, at time t st From read During the period up to Ss is integrated and the integral value is the output voltage V out and is read by the first current detection circuit 21.

[0028] From equation 2, the output voltage V out The source current estimate I S_est is expressed as follows (Equation 3).

number

[0029] According to (Equation 3), the error component due to the voltage drop of the parasitic resistance 104 (second term on the right side) is subtracted from the output of the integrator circuit 106 (first term on the right side) to obtain the time rate of change of the source current di S The source current estimate I S_est Here, the apparent source current estimate before subtracting the error due to the parasitic resistance 104 is I S_est ', this can be expressed as follows (Equation 4).

number

[0030] The apparent source current estimate I calculated using Equation 4 S_est 2, the following will explain the above-mentioned operation of the integrating circuit 106. In FIG. 2, (a) shows an example of the circuit configuration of the integrating circuit 106, and (b) shows an example of each waveform when the switching element 101 is turned off. In FIG. 2(b), the upper part shows the gate voltage V gs and the reset signal of the integrator circuit 106, and the actual source current I S and the estimated apparent source current I S_est ' shows an example of the current waveform obtained by calculation.

[0031] For example, when the integrator circuit 106 having the circuit configuration shown in FIG. 2A is used, the apparent source current estimate I S_est ' is the source current I before the actual turn-off S On the other hand, the resistance value R of the parasitic resistor 104 Ss In the current waveform example of FIG. 2(b), the resistance value R Ss The apparent source current estimates I S_est ' is displayed.

[0032] Resistance value R of parasitic resistor 104 Ss When is 0Ω, the apparent source current estimate I calculated by (Equation 4) is S_est ' is the source current before turn-off I S0 Therefore, in this case, the apparent source current estimate I S_est ' is the source current I S0 By calculating the resistance R of the parasitic resistor 104 as Ss If is not 0Ω, the apparent source current estimate I S_est ' is the resistance R of the parasitic resistor 104 Ss It includes an error according to the source current I S0 As shown in Figure 2(b), this error is due to the resistance R SsIt can be seen that even small resistance values ​​of around 50 to 200 μΩ cannot be ignored.

[0033] Here, the resistance value R of the parasitic resistor 104 Ss changes according to the temperature of the switching element 101. That is, when the switching element 101 is energized and the terminal temperature of the main electrode rises, the resistance value R Ss For example, when copper is used for the main electrode of the switching element 101, when the temperature of the main electrode increases from 20° C. to 150° C., the resistance value R Ss increases by about 1.5 times.

[0034] In the present invention, the resistance value R of the parasitic resistor 104 caused by the temperature change of the switching element 101 is Ss Regardless of the change in S In order to accurately obtain the first current, the first current detection circuit 21 estimates the current of each phase and each arm. This makes it possible to accurately calculate the first current value for each power module 100. A specific method for this will be described below.

[0035] 3 is a diagram showing examples of waveforms when the switching element 101 is turned off and turned on. In FIG. 3, (a) shows an example of the waveform when the switching element 101 is turned off, and (b) shows an example of the waveform when the switching element 101 is turned on. In FIGS. 3(a) and (b), as in FIG. 2(b), the gate voltage V gs 3(a) shows an example of the voltage waveform of the reset signal of the integrating circuit 106 and the actual source current and the estimated apparent source current. S(off) , the apparent source current estimate is I S(off)est In Fig. 3(b), the source current after turn-on is expressed as I S(on) , the apparent source current estimate is I S(on)est 3(a) and (b), the current estimation error due to the parasitic resistance 104 is represented as I RSs(off) , I RSs(on) are represented as follows, respectively.

[0036] As shown in Figure 3, the source current I S(off) , I S(on) is the estimated apparent source current I calculated from (Equation 4). S(off)est ', I S(on)est ' and the current estimation error I due to the parasitic resistance 104 RSs(off) , I RSs(on) Using these, these can be expressed by the following (Equation 5) and (Equation 6), respectively.

number

[0037] Here, if a specific pulse condition is selected under which the load current of the corresponding phase does not increase or decrease during the off period from after the switching element 101 of each phase is turned off until before it is turned on, the source current I S(off) and the source current after turn-on I S(on) are almost equal. In this case, taking the difference between the above (Equation 5) and (Equation 6), the following (Equation 7) is obtained.

number

[0038] From (Equation 7), the apparent source current estimate I before turn-off and after turn-on, calculated without considering the voltage drop of the parasitic resistance 104, is S(off)est ', I S(on)est From the difference between RSs(off) , I RSs(on) In the waveform example of FIG. 3, the integration range of the integrating circuit 106 is divided into a section before and after the turn-off and a section before and after the turn-on. The output voltage V output from the integrating circuit 106 is calculated according to the integral value in each of these integration ranges. out The apparent source current estimate I is calculated before turn-off and after turn-on based on S(off)est ', I S(on)estBy calculating the difference between these two, the calculation of (Equation 7) can be performed. However, the polarity of the integral value obtained is opposite between the integral in the period before and after turn-off and the integral in the period before and after turn-on. Therefore, the integration is continued from before turn-off to after turn-on, and the output voltage V output from the integration circuit 106 in this integration range is out Using Equation 4, we estimate the apparent source current I S_est Even if we calculate ', the same result as that of the calculation in (Equation 7) will be obtained.

[0039] Normally, in order to correct the current error due to the voltage integral of the parasitic resistance 104, the current value I S However, the source current we ultimately want to find is the same current value I S Therefore, the current value I S Therefore, in the power conversion device 1 of the present embodiment, the first current value calculated by the first current detection circuit 21 of each phase and each arm under the specific pulse condition as described above is selected, and the accurate source current value I of each phase and each arm can be obtained regardless of the current error due to the voltage integral of the parasitic resistance 104. S This is a main feature of the power conversion device 1 of the present embodiment.

[0040] Specifically, the current waveforms at turn-off and turn-on are approximated by square waves, and the current conduction period Δt cond(off) , Δt cond(on) The magnitude of the source current at a constant current value I S If we put (i s =I S ), the current estimation error I RSs(off) and the turn-on current estimation error I RSs(on) are calculated using the following (Equation 8) and (Equation 9), respectively.

number

[0041] From (Equation 7) to (Equation 9), the following (Equation 10) and (Equation 11) can be obtained.

number

[0042] From (Equation 8), (Equation 9), and (Equation 11), the following (Equation 12) and (Equation 13) can be obtained.

number

[0043] By substituting (Equation 12) and (Equation 13) into (Equation 5) and (Equation 6) above, respectively, the following (Equation 14) and (Equation 15) are obtained.

number

[0044] The prerequisite for (Equation 7) to hold is, as mentioned above, I S(off) ≒I S(on) ≒I S Therefore, whether (Equation 14) or (Equation 15) is used, the output voltage V output from the integrating circuit 106 in the period before and after the turn-off is out The apparent source current estimate I is calculated using (Equation 4) S(off)est ', and the output voltage V output from the integrating circuit 106 in the period before and after the turn-on. out The apparent source current estimate I is calculated using (Equation 4) S(on)est ' and the actual source current value I S Here, the source current value I S That is, in the power conversion device 1 of the present embodiment, the above-mentioned arithmetic processing is performed in each first current detection circuit 21, so that the output voltage V out The integral value (first integral value) represented by and the output voltage V output from the integrator circuit 106 of each phase and each arm in the period before and after the turn-onout A first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ) can be calculated.

[0045] Fig. 4 is a diagram showing a configuration example of the first current detection circuit 21. As shown in Fig. 4, the first current detection circuit 21 has, for example, functional blocks of a source current estimation unit 211, a turn-off / turn-on determination unit 212, a current conduction period estimation unit 213, and a parasitic resistance error correction unit 214. The first current detection circuit 21 can realize these functional blocks by, for example, a combination of a program executed by a microcomputer and a logic circuit. For the logic circuit, for example, an FPGA (Field Programmable Gate Array) or the like may be used.

[0046] The source current estimation unit 211 receives the output voltage V out The source current estimation unit 211 receives the output voltage V out Based on this, the apparent source current estimate I S_est ' is calculated.

[0047] The turn-off / turn-on discrimination unit 212 receives a gate command V G and the apparent source current estimation value I S_est The turn-off / turn-on discrimination unit 212 receives the apparent source current estimates I S_est ' and the gate command V GBased on this, the timing of turn-off and turn-on of the switching element 101 of the arm and the corresponding current detection timing are determined. The method of determining the current detection timing will be described later in detail. Then, the current detection timing obtained in the section before and after the turn-off is distinguished from the current detection timing obtained in the section before and after the turn-on, and the former is regarded as the apparent source current estimation value I before the turn-off. S(off)est ', the latter is the apparent source current estimate after turn-on I S(on)est ' respectively.

[0048] The current conduction period estimation unit 213 receives the apparent source current estimation value I S(off)est ', I S(on)est The first current detection circuit 21 receives inputs of a battery voltage representing the DC voltage of the storage battery 2, and an output signal from an on-chip temperature sensor (not shown) attached to the switching element 101 of the arm corresponding to the first current detection circuit 21. The current conduction period estimation unit 213 determines the switching conditions (current, voltage, temperature) of the switching element 101 based on these input parameters, and calculates the current conduction period Δt cond(off) , Δt cond(on) The current conduction period estimation unit 213 estimates the current conduction period Δt cond(off) , Δt cond(on) By referring to this table data, the current conduction period Δt corresponding to the switching condition represented by the input parameter is calculated. cond(off) , Δt cond(on) can be estimated.

[0049] In addition, the current conduction period estimation unit 213 estimates the current conduction period Δt cond(off) , Δt cond(on) When estimating, at least one of the above input parameters may be omitted. Alternatively, cond(off) , Δt cond(on) may be a preset fixed value. cond(off) , Δtcond(on) As long as these can be appropriately estimated, the current conduction period estimation unit 213 can estimate these by any method.

[0050] The parasitic resistance error correction unit 214 corrects the apparent source current estimate I S(off)est ', I S(on)est ' and the current conduction period Δt estimated by the current conduction period estimation unit 213. cond(off) , Δt cond(on) Based on this, the source current value I S Then, the obtained source current value I S The calculation result is used as the estimation result of the current flowing through the arm (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ) and outputs it to the output current estimation circuit 22.

[0051] Next, a method for determining the current detection timing in turn-off / turn-on determining section 212 will be described in detail below.

[0052] As described above, the turn-off / turn-on discrimination unit 212 in the first current detection circuit 21 of each phase and each arm detects the gate command V G At this time, the timing at which the PWM control state of the arm satisfies the condition of (Equation 7) described above, that is, the timing at which the load current does not increase or decrease during the off period from after the switching element 101 is turned off until before it is turned on, is determined.

[0053] A specific example of the above-mentioned specific pulse conditions will be described below using the example waveforms of gate commands and output currents shown in Fig. 5. In Fig. 5, (a) shows the gate commands V G_UU , VG_VU , V G_WU (b) shows the gate command V for the lower arms of the U, V, and W phases. G_UL , V G_VL , V G_WL 5(a) and (b) show waveform examples offset from each other in the vertical direction so that the waveforms of the gate commands can be seen. Also, (c) shows the output current I of each phase output from the power conversion device 1 in response to the gate commands of (a) and (b). outU , I outV , I outW (d) shows the waveform example of the current flowing through the U phase (U phase upper arm current I UU , U-phase lower arm current I UL ) is shown as an example waveform.

[0054] For example, in Figure 5, the U-phase output current I outU When attention is paid to the gate command V of the upper arm of the U phase with respect to the gate command of the other phases in each of the sections 51 to 56 shown in FIG. G_UU and lower arm gate command V G_UL The magnitude of the pulse width and the U-phase output current I outU The turn-off / turn-on determination unit 212 sets U-phase pulse conditions U-(I) to U-(V) in accordance with these combinations, and detects the current at different timings for each pulse condition.

[0055] In Figure 5, the U-phase output current I outU The sections 51 to 56 and the pulse conditions U-(I) to U-(V) for the V phase are shown in FIG. 1. Similarly, for the V phase, the gate command V for the upper arm of the V phase for the gate commands of the other phases is G_VU and lower arm gate command V G_VL The magnitude of the pulse width and the V phase output current I outV The V-phase pulse conditions V-(I) to V-(V) can be set according to the combination with the polarity of the V-phase. Similarly, for the W-phase, the upper arm gate command V for the W-phase relative to the gate commands of the other phases can be set according to the combination with the polarity of the V-phase. G_WU and lower arm gate command V G_WL The pulse width of and the W-phase output current IoutW The W-phase pulse conditions W-(I) to W-(V) can be set according to the combination with the polarity of the W-phase.

[0056] Fig. 6 is a table summarizing the pulse conditions and current detection timings of each phase. In Fig. 6, Table 61 shows the pulse conditions U-(I) to U-(V) of the U phase and their respective current detection timings, Table 62 shows the pulse conditions V-(I) to V-(V) of the V phase and their respective current detection timings, and Table 63 shows the pulse conditions W-(I) to W-(V) of the W phase and their respective current detection timings.

[0057] In the first current detection circuit 21 provided for each of the upper and lower arms of the U-phase, V-phase, and W-phase, a turn-off / turn-on discrimination unit 212 detects a gate command V G 6 is judged to be applicable based on the result of the pulse condition. Then, the integration period of the integration circuit 106 is set by changing the timing of reading the output of the integration circuit 106 in accordance with the current detection timing under the applicable pulse condition.

[0058] 6, when any one of the U, V, and W phases corresponds to the pulse condition U-(V), V-(V), or W-(V), the other two phases correspond to any one of U-(I) to U-(IV), V-(I) to V-(IV), or W-(I) to W-(IV). Therefore, for a phase that corresponds to the pulse condition U-(V), V-(V), or W-(V), the output current of that phase can be obtained by using the calculation results of the first current detection circuit 21 for the other two phases.

[0059] Next, the details of the U-phase pulse conditions U-(I) to U-(V) shown in Table 61 in FIG. 6 will be described below with reference to the enlarged views of each section of FIG. 5 shown in FIGS. 7A to 7D, respectively.

[0060] [Section 51: Pulse condition U-(I)] The pulse condition U-(I) is the gate command V G_UU , VG_VU , V G_WU Pulse width PW UU_OFF , P.W. VU_OFF , P.W. WU_OFF Among them, the pulse width PW of the U-phase upper arm (UU arm) UU_OFF is minimum and the U-phase output current I outU The polarity of the U-phase winding L u 7A is an enlarged view of a portion of section 51 in FIG. 5 including a period that corresponds to this pulse condition U-(I).

[0061] 7A, in section 51, the value of the current flowing through the UU arm does not change during the period from when switching element 101 of the UU arm is turned off until it is turned on again (the off period of the UU arm). The reason for this is as follows.

[0062] In order for the U-phase current not to change during the off-period of the UU arm, the U-phase winding L of the motor 3, which is the U-phase load, must be turned on during this period. u There must be no voltage applied across the U-phase output current I outU When the polarity of is positive, when the switching element 101 of the UU arm is turned off, the U-phase winding L u At this time, if either the V-phase upper arm (VU arm) or the W-phase upper arm (WU arm) is on, the V-phase or W-phase output voltage will be at a high potential, and the U-phase winding L u On the other hand, when the VU arm and WU arm are both off and the V-phase lower arm (VL arm) and W-phase lower arm (WL arm) are both on, the output voltages of both the V and W phases are at low potential. As a result, the U-phase winding L u No high voltage is applied to the U-phase output current I outU does not change.

[0063] In PWM control, when focusing on a certain carrier cycle, as shown in Figure 5, the gate command V for each arm (UU, VU, WU arms) on the high potential side is G_UU , V G_VU , V G_WU In the case of the UL, VL, and WL arms, the on-period timings overlap with each other, so the pulse widths are generated differently for each phase. G_UL , V G_VL , V G_WL In this case, each pulse on the high potential side is inverted, and a dead time is secured so that the upper and lower arms of the same phase are not turned on at the same time.

[0064] As shown in FIG. 7A, in section 51, the gate command V G_UU , V G_VU , V G_WU Of these, the gate command for the UU arm is V G_UU , and the pulse width PW UU_OFF At this time, the VU arm and the WU arm are in the OFF state, the VL arm and the WL arm are in the ON state, the switching element 101 of the UU arm is turned off, and then the pulse width PW UU_OFF That is, when the pulse condition U-(I) is satisfied, the gate command V G_UU During the off period of U-phase winding L u No high voltage is applied to the U phase output current I outU Therefore, the U-phase output current I outU can be considered to be the same, and the condition for formula (7) is satisfied.

[0065] From the above explanation, when the pulse condition U-(I) is satisfied, the first current detection circuit 21 provided for the UU arm detects the output voltage V out This output voltage V out Based on the U-phase upper arm current IUU At this time, the output current estimation circuit 22 can obtain the U-phase upper arm current I UU The value of U phase output current I outU can be output as an estimated result.

[0066] When the first current detection circuit 21 determines the pulse condition U-(I), the U-phase output current I outU The polarity of is, for example, the apparent source current estimation value I before correction calculated by the source current estimation unit 211 using (Equation 4). S_est This can be done in the same way when determining other pulse conditions.

[0067] [Section 56: Pulse condition U-(II)] Pulse condition U-(II) is the same as pulse condition U-(I) in terms of pulse width, and the U-phase output current I outU The polarity of the load U-phase winding L u This is a condition of pulse condition U-(II) (flowing from the current collector to the power converter 1). Fig. 7B is an enlarged view of a part of section 56 in Fig. 5 including a period corresponding to this pulse condition U-(II).

[0068] 7B, in section 56, during the off-period of the UU arm, the value of the current flowing through the UU arm does not change during the period from when switching element 101 in the UL arm is turned on until it is turned off again. The reason for this is as follows.

[0069] As shown in FIG. 7B, in section 56, the gate command V G_UL , V G_VL , V G_WL Of these, UL arm gate command V G_UL The pulse width PW UL_ONbecomes minimum. At this time, even after the switching element 101 of the UU arm is turned off, current flows in the UU arm via the freewheeling diode 102 of the UU arm, and the current in the UU arm is cut off in response to the turning on of the switching element 101 of the UL arm, not the switching element 101 of the UU arm. Thereafter, in response to the turning off of the switching element 101 of the UL arm, the current in the UU arm is conducted again. In other words, when the pulse condition U-(II) is satisfied, the gate command V of the UL arm G_UL During the on-period of U-phase winding L u No high voltage is applied to the U phase output current I outU Therefore, the U-phase output current I outU can be considered to be the same, and the condition for formula (7) is satisfied.

[0070] From the above description, when the pulse condition U-(II) is met, the first current detection circuit 21 provided for the UU arm detects the output voltage V out This output voltage V out Based on the U-phase upper arm current I UU At this time, in the output current estimation circuit 22, similarly to the case of the pulse condition U-(I), the U-phase upper arm current I UU The value of U phase output current I outU can be output as an estimated result.

[0071] [Section 53: Pulse condition U-(III)] Pulse condition U-(III) is the gate command V G_UL , V G_VL , V G_WL Pulse width PW UL_OFF , P.W. VL_OFF , P.W. WL_OFF Among them, the pulse width PW of the U-phase lower arm (UL arm) UL_OFFis minimum and the U-phase output current I outU The polarity of the pulse is positive. That is, compared with the above-mentioned pulse conditions U-(I) and U-(II), this pulse condition is different in that it targets the lower arm. Figure 7C is an enlarged view of a part of section 53 in Figure 5 including the period corresponding to this pulse condition U-(III).

[0072] 7C, in section 53, during the off-period of the UL arm, the value of the current flowing through the UL arm does not change during the period from when the switching element 101 of the UU arm is turned on until it is turned off again. The reason for this is as follows.

[0073] As shown in FIG. 7C, in section 53, the gate command V G_UU , V G_VU , V G_WU Of these, the gate command for the UU arm is V G_UU The pulse width PW UU_ON becomes minimum. At this time, even after the switching element 101 of the UL arm is turned off, a current flows in the UL arm via the freewheeling diode 102 of the UL arm, and the current in the UL arm is cut off in response to the turning on of the switching element 101 of the UU arm, not the switching element 101 of the UL arm. Thereafter, in response to the turning off of the switching element 101 of the UU arm, the current in the UL arm is conducted again. In other words, when the pulse condition U-(III) is satisfied, the gate command V of the UU arm G_UU During the on-period, the gate command V of the UL arm under pulse condition U-(II) G_UL As in the on-period of U-phase winding L u No high voltage is applied to the U phase output current I outU Therefore, the U-phase output current I outU can be considered to be the same, and the condition for formula (7) is satisfied.

[0074] From the above description, when the pulse condition U-(III) is met, the first current detection circuit 21 provided for the UL arm detects the output voltage V out This output voltage V out Based on the U-phase lower arm current I UL At this time, the output current estimation circuit 22 can obtain the U-phase lower arm current I UL Reversed polarity of -I UL The value of U phase output current I outU can be output as an estimated result.

[0075] [Section 54: Pulse condition U-(IV)] Pulse condition U-(IV) is the same as pulse condition U-(III) in terms of the pulse width, and the U-phase output current I outU This is a condition in which the polarity of the pulse is negative. Fig. 7D is an enlarged view of a portion of section 54 in Fig. 5 including a period that corresponds to this pulse condition U-(IV).

[0076] As shown in FIG. 7D, in section 54, the gate command V G_UL During the off period of the UL arm, the current value flowing through the UL arm does not change. In other words, when the pulse condition U-(IV) is satisfied, the gate command V G_UL During the off period of U-phase winding L u No high voltage is applied to the U phase output current I outU Therefore, the U-phase output current I outU can be considered to be the same, and the condition for formula (7) is satisfied.

[0077] From the above description, when the pulse condition U-(IV) is met, the first current detection circuit 21 provided for the UL arm detects the output voltage V out This output voltage V out Based on the U-phase lower arm current I UL At this time, the output current estimation circuit 22 can obtain the U-phase lower arm current I UL Reversed polarity of -I UL The value of U phase output current I outU can be output as an estimated result.

[0078] [Sections 52, 55: Pulse condition U-(V)] Pulse condition U-(V) is the pulse width PW of the UU arm and the UL arm. UU_OFF , P.W. UL_OFF In this case, the gate command V G_UU , V G_UL During the off period of U-phase winding L u A high voltage is applied to the U-phase output current I outU changes. Therefore, the condition of (Equation 7) does not hold for the U-phase current. On the other hand, for the remaining V-phase and W-phase, the pulse width during the on or off period is minimum in either the upper arm or lower arm, and either of the pulse conditions V-(I) to V-(IV) and W-(I) to W-(IV) shown in Tables 62 and 63 in FIG. 6 is satisfied, so that the condition of (Equation 7) is satisfied. Therefore, in this case, the V-phase output current I outV and the W-phase output current I obtained by the first current detection circuit 21 corresponding to the upper arm or lower arm of the W phase. outW Based on the value of and the fact that the sum of the output currents of each phase is zero, I outU =-(I outV +IoutW ) can be calculated.

[0079] In the above, the U-phase pulse conditions U-(I) to U-(V) and the U-phase output current I outU The method of estimating the V-phase output current I outV and W-phase output current I outW It is possible to make an estimate of the

[0080] Fig. 8 is an explanatory diagram of the application effect of the present invention. Fig. 8 shows an example of a case where the current waveform of each phase estimated using the current detection result in which the parasitic resistance error is corrected by the first current detection circuit 21 of this embodiment for the output current of each phase output from the power conversion device 1 and the current waveform of each phase estimated without correcting the parasitic resistance error are calculated. From each current waveform in Fig. 8, it can be confirmed that by applying the first current detection circuit 21 of this embodiment to estimate the output current of each phase, the deviation from the actual output current of the power conversion device 1 is smaller than when the parasitic resistance error is not corrected.

[0081] 9 is a diagram showing the change in magnitude of the relative error of the estimated current with respect to the true output current when the resistance value of the parasitic resistance 104 is changed. In a method of estimating the output current from the integral value obtained by the integrating circuit 106 without considering the error due to the parasitic resistance 104, as in the conventional technology, when the resistance value of the parasitic resistance 104 increases, the current estimation error also increases accordingly. On the other hand, in a method of estimating the output current by correcting the error due to the parasitic resistance 104, as in the first current detection circuit 21 of this embodiment, even if the resistance value of the parasitic resistance 104 increases, the current estimation error can be suppressed without increasing.

[0082] According to the first embodiment of the present invention described above, the following advantageous effects are achieved.

[0083] (1) The power conversion device 1 is a switching element 101, and an integral value of a voltage generated across an inductance component 103 and a parasitic resistor 104 connected in series to a source electrode, which is a main electrode of the switching element 101 (output voltage V out ), and the integral value (output voltage V out ) based on which the current I flows through the source electrode of the switching element 101 S The first current detection circuit 21 detects a first integral value (output voltage V out ), and a second integral value (output voltage V out ), and a first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ) is calculated. Since this is done, the current flowing through the switching element 101 provided in the power conversion device 1 can be estimated with high accuracy.

[0084] (2) The power conversion device 1 has a plurality of switching elements 101, and a first current detection circuit 21 is provided for each of the plurality of switching elements 101. The power conversion device 1 detects a first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ), the output current of the power conversion device 1 (U-phase output current I outU , V phase output current I outV , W-phase output current I outW) is provided. Since this is done, the output current of the power conversion device 1 can be estimated with high accuracy from the estimation result of the current flowing through each switching element 101.

[0085] (3) The switching element 101 controls the three-phase AC current (U-phase output current I outU , V phase output current I outV , W-phase output current I outW The output current estimation circuit 22 is provided for the upper and lower arms of each phase (U-phase, V-phase, W-phase). The output current estimation circuit 22 is provided for the gate commands (U-phase upper arm gate command V G_UU , U-phase lower arm gate command V G_UL , V-phase upper arm gate command V G_VU , V-phase lower arm gate command V G_VL , W-phase upper arm gate command V G_WU , W-phase lower arm gate command V G_WL 6 based on the combination of pulse widths of the U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ), the output current of each phase of the power conversion device 1 (U-phase output current I outU , V phase output current I outV , W-phase output current I outW ) is estimated. In this way, the arms that satisfy the condition of (Equation 7) can be selected in order and the current flowing through each phase and each arm can be accurately estimated regardless of the current error due to the voltage integral of the parasitic resistance 104. As a result, the output current of the power conversion device 1 can be estimated with high accuracy.

[0086] Second embodiment Fig. 10 is a diagram showing a configuration example of a power conversion device according to a second embodiment of the present invention. The power conversion device 1A shown in Fig. 10 further uses a Hall sensor 30 in addition to the power conversion device 1 described in the first embodiment, and performs motor control using a current value detected by the Hall sensor 30 while being able to detect an abnormality in the Hall sensor 30 when it occurs. The power conversion device 1A of this embodiment will be described below, focusing on the differences from the first embodiment.

[0087] The power conversion device 1A of this embodiment includes a Hall sensor 30 as a second current detection circuit that detects the output current of each phase. The Hall sensor 30 is used as a main current sensor used by the control signal generating circuit 23 of the control device 20 for motor control, and includes Hall elements 31U, 31V, and 31W provided in the U phase, V phase, and W phase, respectively, and a Hall IC 32 that outputs a second current value according to the current detection result of each phase based on the sensor signals output from these Hall elements 31U to 31W.

[0088] In the power conversion device 1A of the present embodiment, the control device 20 further includes an abnormality detection circuit 25 in addition to the configurations of the first current detection circuit 21, the output current estimation circuit 22, the control signal generation circuit 23, and the communication connector 24 described in the first embodiment. In the example of Fig. 10, only the configurations of the inverter circuit 10 and the control device 20 related to the W phase are shown, and the U phase and the V phase are not shown, but they are similar to those of the W phase.

[0089] In this embodiment, the first current detection circuit 21, which estimates the current value of each phase and each arm by the di / dt integration method, is used as a sub-current sensor. The output current value of each phase estimated by the output current estimation circuit 22 based on the current value of each phase and each arm calculated by the first current detection circuit 21, and the second current value indicating the output current of each phase detected by the second current detection circuit (Hall sensor 30) are each input to an abnormality detection circuit 25 in the control device 20. In the following, the output current value of each phase (U-phase output current I outU , V phase output current I outV, W-phase output current I outW ) to the first current value I out1 The output current value of each phase output from the Hall sensor 30 is set to a second current value I out2 and respectively.

[0090] The abnormality detection circuit 25 detects the first current value I out1 and the second current value I out2 Based on the comparison result, it is determined whether or not there is an abnormality in the Hall sensor 30. If it is determined that there is no abnormality, the second current value I out2 is used as a normal output current detection value, and is output to the control signal generating circuit 23 as a control current value. On the other hand, if it is determined that there is an abnormality in the Hall sensor 30, the first current value I out1 is adopted as a detection value of a normal output current, and is output as a control current value to the control signal generating circuit 23. At this time, an abnormality signal indicating the occurrence of an abnormality in the Hall sensor 30 may be further transmitted to a higher-level system via the communication connector 24. Based on this abnormality signal, the higher-level system controls the operation of the power conversion device 1A (continue operation, stop operation, ease conditions, etc.) or issues a warning to the user.

[0091] 11A and 11B are diagrams showing an example of a flowchart illustrating a process flow when the abnormality detection circuit 25 according to the second embodiment of the present invention performs an abnormality determination. In this embodiment, the abnormality detection circuit 25 performs the process shown in Figs. 11A and 11B at predetermined intervals, for example, to perform an abnormality determination of the Hall sensor 30.

[0092] 11A, it is determined whether or not there is an abnormality determination command from a higher-level system. If there is an abnormality determination command from the higher-level system, the process proceeds to step S102, and if there is no abnormality determination command, the process proceeds to step S111.

[0093] In step S102, the second current value I output from the Hall sensor 30 is out2 and the first current value I out1 The difference between them is calculated, and the absolute value of the difference is the difference value ΔI 21 Let us assume that.

[0094] In step S103, the difference value ΔI 21 It is judged whether the difference value ΔI is equal to or smaller than a preset allowable difference. 21 If the difference ΔI is equal to or smaller than the allowable difference, it is determined that there is no abnormality in either the first current detection circuit 21 or the Hall sensor 30, and the process proceeds to step S111. 21 If the difference is greater than the allowable difference, it is determined that there is an abnormality in at least one of the first current detection circuit 21 and the Hall sensor 30, and the process proceeds to step S104. The allowable difference used in the determination in step S103 is set according to the detection accuracy of the Hall sensor 30, and is, for example, a value obtained by multiplying the error defined in the specifications of the Hall sensor 30 by two.

[0095] In step S104, the first current value I out1 and the second current value I out2 For each of the U, V, and W phase currents, I sum1 ,I sum2 Calculate.

[0096] In step S105, the first current value I out1 Sum of I sum1 It is determined whether the first current value I out1 Sum of I sum1 If it is equal to or smaller than the allowable sum error, the process proceeds to step S106, and if it is larger than the allowable sum error, the first current detection circuit 21 is determined to be abnormal, and the process proceeds to step S112 in FIG. 11B.

[0097] In step S106, the second current value I out2 Sum of I sum2 It is determined whether the second current value I out2 Sum of I sum2 If the sum error is equal to or smaller than the allowable sum error, the process proceeds to step S107, and if the sum error is greater than the allowable sum error, the Hall sensor 30 is determined to be abnormal, and the process proceeds to step S110.

[0098] If both the first current detection circuit 21 and the Hall sensor 30 are normal, the first current value I out1 and the second current value I out2 Sum of I sum1 ,I sum2 Ideally, each of these will be 0, but in reality, an error occurs between these due to the displacement current passing through the wiring of the inverter circuit 10 and the parasitic capacitance of the motor 3. Therefore, in the processes of steps S105 and S106, the sum I sum1 ,I sum2 An allowable total error is set for each of these, and if this is not exceeded, it is determined that there is no abnormality in the first current detection circuit 21 and the Hall sensor 30. This allowable total error is set, for example, according to the error determined in the specifications of the Hall sensor 30, and is, for example, a value obtained by adding a displacement current component to three times the error. The magnitude of the displacement current component is about 1 to 2 A, assuming, for example, that the parasitic capacitance is 100 pF and the voltage change rate during switching in the switching element 101 is 10 to 20 kV / μs.

[0099] However, in steps S105 and S106, the first current value I out1 and the second current value I out2 Sum of I sum1 ,I sum2 are all determined to be equal to or smaller than the allowable sum error, it is not possible to determine at this point whether the first current detection circuit 21 or the Hall sensor 30 is abnormal. This situation may occur, for example, when the accuracy of the Hall elements 31U, 31V, and 31W provided in the U phase, V phase, and W phase, respectively, in the Hall sensor 30 deteriorates to the same extent. In such a case, the following processes in steps S107 and S108 are executed to determine whether the first current detection circuit 21 or the Hall sensor 30 is abnormal.

[0100] In step S107, the initial values ​​I of the first current value and the second current value at the beginning of operation of the power conversion device 1A are calculated. Ini1 ,I Ini2 and using these, the first current value I out1 and the first current initial value I Ini1 Absolute value of difference with |I out1 -IIni1 | and the second current value I out2 and the second current initial value I Ini2 Absolute value of difference with |I out2 -I Ini2 Calculate the initial value I Ini1 ,I Ini2 is acquired by referring to a preset lookup table, for example, for a current value at which the motor control conditions at the beginning of operation are equivalent to the control conditions at the time of abnormality determination. In the case of vector control, for example, the control conditions are a torque command or a current command, a current current detection value, a motor angular velocity and angle, and a voltage applied from the storage battery 2 to the inverter circuit 10. This lookup table can be realized by storing data of each control condition acquired in advance, for example, before shipment of the power conversion device 1A or during product operation, in a memory in the control device 20.

[0101] In step S108, the absolute difference value |I out1 -I Ini1 | and the absolute difference between the second current value |I out2 -I Ini2 | and determine which absolute difference is larger. As a result, the absolute difference |I out1 -I Ini1 If | is larger, it is determined that the first current detection circuit 21 is abnormal, and the process proceeds to step S109. out2 -I Ini2 If | is larger, it is determined that the Hall sensor 30 is abnormal, and the process proceeds to step S110.

[0102] In step S109, some abnormality has occurred in the first current detection circuit 21, and as a result, the first current value I out1 In this case, the abnormality detection circuit 25 determines that the second current value I out2 As a normal current detection result, the control signal generating circuit 23 selects the second current value I out2 The gate commands for each phase and each arm are generated using

[0103] In step S110, some abnormality has occurred in the Hall sensor 30. As a result, the second current value I out2 In this case, the abnormality detection circuit 25 determines that the first current value I out1 As a normal current detection result, the control signal generating circuit 23 selects the first current value I out1 The gate commands for each phase and each arm are generated using

[0104] In step S111, no abnormality is occurring in either the first current detection circuit 21 or the Hall sensor 30, and the first current value I out1 and the second current value I output from the Hall sensor 30. out2 In this case, the abnormality detection circuit 25 determines that both the second current value I out2 As a normal current detection result, the control signal generating circuit 23 selects the second current value I out2 The gate commands for each phase and each arm are generated using

[0105] Once any one of steps S109 to S111 has been executed, the processes in FIGS. 11A and 11B end.

[0106] In step S112 of FIG. 11B, similarly to step S106 of FIG. 11A, the second current value I out2 Sum of I sum2 It is determined whether the second current value I out2 Sum of I sum2 If the sum error is equal to or smaller than the allowable sum error, the process proceeds to step S117, and if the sum error is greater than the allowable sum error, the Hall sensor 30 is determined to be abnormal, and the process proceeds to step S113.

[0107] When the process proceeds to step S113, that is, when the first current value I out1 Sum of Isum1 and the second current value I out2 Sum of I sum2 If both of the first current detection circuit 21 and the Hall sensor 30 are larger than the allowable sum error, it is determined that both of them are abnormal. Even in such a case, it is necessary to output a current value from the abnormality detection circuit 25 to the control signal generation circuit 23 in preparation for the case where the operation of the power conversion device 1A cannot be stopped immediately, and the first current value I out1 and the second current value I out2 Therefore, in steps S113 and S114, the first current value I out1 and the second current value I out2 Among these, the initial value I Ini1 ,I Ini2 The control circuit 23 selects the control current value having the smallest difference from the control current value.

[0108] Specifically, in step S113, the first current value I out1 and the first current initial value I Ini1 Absolute value of difference with |I out1 -I Ini1 | and the second current value I out2 and the second current initial value I Ini2 Absolute value of difference with |I out2 -I Ini2 In the following step S114, the absolute difference |I out1 -I Ini1 | and the absolute difference between the second current value |I out2 -I Ini2 | and determine which absolute difference is larger. As a result, the absolute difference |I out1 -I Ini1 If | is larger, the process proceeds to step S115, and the absolute difference value |I out2 -I Ini2 If | is larger, the process proceeds to step S116.

[0109] In step S115, some abnormality has occurred in both the first current detection circuit 21 and the Hall sensor 30, but the first current value I out1 The second current value I out2 In this case, the abnormality detection circuit 25 determines that the error is larger than the second current value I out2 and outputs the second current value I out2 The gate commands for each phase and each arm are generated using

[0110] In step S116, some abnormality has occurred in both the first current detection circuit 21 and the Hall sensor 30, but the second current value I output from the Hall sensor 30 is out2 is the first current value I out1 In this case, the abnormality detection circuit 25 determines that the error is larger than the first current value I out1 and outputs the first current value I out1 The gate commands for each phase and each arm are generated using

[0111] In step S117, some abnormality has occurred in the first current detection circuit 21, and as a result, the first current value I out1 In this case, the abnormality detection circuit 25 determines that the second current value I out2 As a normal current detection result, the control signal generating circuit 23 selects the second current value I out2 The gate commands for each phase and each arm are generated using

[0112] Once any one of steps S115 to S117 has been executed, the processes in FIGS. 11A and 11B end.

[0113] In the second embodiment of the present invention described above, the Hall sensor 30, which is the second current detection circuit, is used as a main current sensor, and the first current detection circuit 21 is used as a sub current sensor. However, the main and sub current sensors may be reversed. Also, the second current detection circuit may be something other than the Hall sensor 30.

[0114] According to the second embodiment of the present invention described above, in addition to those described in the first embodiment, the following advantageous effects are further achieved.

[0115] (4) The power conversion device 1A includes a Hall sensor 30, which is a second current detection circuit that detects the output current of each phase of the power conversion device 1A, and an output current of each phase estimated by the output current estimation circuit 22 (first current value I out1 ) and the output current of each phase detected by the Hall sensor 30 (second current value I out2 ) and based on the comparison result, determine whether or not an abnormality has occurred in the Hall sensor 30. Since this is configured in this manner, while using the Hall sensor 30 as the main current sensor, if an abnormality has occurred in the Hall sensor 30, this can be detected.

[0116] (5) The second current detection circuit is, for example, a Hall sensor 30 that detects the three-phase AC current output by the power conversion device 1A. Since this is configured in this way, it is possible to accurately and reliably detect the three-phase AC current output by the power conversion device 1A.

[0117] (Third embodiment) 12 is a diagram showing a configuration example of a power conversion device according to a third embodiment of the present invention. The power conversion device 1B shown in FIG. 12 further includes a current sense element 107 and a temperature sensor 108, which are on-chip current sensors formed on the same chip as the switching elements 101 of each phase and each arm, in the power conversion device 1 described in the first embodiment, and a second current detection circuit 40 that detects the current flowing through the switching element 101 based on a signal from the on-chip current sensor and outputs a second current value according to the detection result. The second current detection circuit 40 includes a sense current detection circuit 109 that detects a sense current flowing through the current sense element 107, a temperature sensor temperature detection circuit 110 that detects the temperature sensor temperature, which is the temperature of the temperature sensor 108, and an on-chip sensor output current estimation circuit 41 that estimates the current of the switching element 101 with high accuracy from these detection values. In the example of Figure 12, the current sense element 107 and temperature sensor 108 of the W-phase upper arm power module 100WU, and the sense current detection circuit 109 and temperature sensor temperature detection circuit 110 connected thereto, respectively, are shown, and the other arms are not shown, but the configuration of each arm is similar to that of the W-phase upper arm.

[0118] In this embodiment, the second current detection circuit 40 estimates the source current value I of the switching element 101 based on the detection results of the sense current and the temperature sensor temperature by the sense current detection circuit 109 of each phase and each arm and the temperature sensor temperature detection circuit 110 in the on-chip sensor output current estimation circuit 41. S At this time, the deviation of the sense ratio of the current sense element 107 according to the temperature distribution in the chip caused by the self-heating of the switching element 101 is corrected based on the temperature detection value, and the source current value I is calculated from the sense current value using the corrected sense ratio. S For example, a lookup table showing the sense ratio value obtained in advance for each temperature is stored in the on-chip sensor output current estimation circuit 41, and the sense ratio corresponding to the temperature detection value is calculated using this lookup table. Using the sense ratio thus calculated, the source current value I S Calculate.

[0119] In the second current detection circuit 40 of the present embodiment, the characteristics (on-resistance, switching loss, thermal resistance, etc.) of the switching element 101 that change depending on the temperature are taken into consideration by the method described above, and the source current value I that flows through the source electrode, which is the main power of the switching element 101, is detected in a manner different from that of the first current detection circuit 21. S can be accurately detected.

[0120] Furthermore, the on-chip sensor output current estimation circuit 41 estimates the source current value I S For example, the source current value I S By calculating the difference between these values, the output current value of each phase can be obtained.

[0121] Furthermore, in the power conversion device 1B of the present embodiment, the control device 20 includes, as in the second embodiment, a first current detection circuit 21, an output current estimation circuit 22, a control signal generation circuit 23, and a communication connector 24, as well as an abnormality detection circuit 25. In the example of Fig. 12, only the configuration of the inverter circuit 10 and the control device 20 related to the W-phase upper arm is shown, and the W-phase lower arm and the upper and lower arms of the U and V phases are not shown, but these are similar to the W-phase upper arm.

[0122] In this embodiment, as in the second embodiment, the first current detection circuit 21, which estimates the current value of each phase and each arm by the di / dt integration method, is used as a sub-current sensor. The current value of each phase and each arm calculated by the first current detection circuit 21 is output to the control device 20 as the output current value of each phase estimated by the output current estimation circuit 22. In addition, a second current value representing the output current of each phase detected by the second current detection circuit 40 is also output to the control device 20. In the control device 20, the abnormality detection circuit 25 can determine the presence or absence of an abnormality in the second current detection circuit 40 or the current sense element 107 by comparing these input current values, as in the second embodiment.

[0123] Furthermore, in this embodiment, even if an abnormality occurs in the characteristics of the switching element 101, the abnormality can be detected. For example, when the switching element 101 approaches the power cycle life, the bonding material (solder, sintered material, etc.) between the switching element 101 and the terminal deteriorates and the thermal resistance increases. In such a case, the abnormality detection circuit 25 of this embodiment determines that the second current value is abnormal before the switching element 101 is destroyed by overheating due to the increase in thermal resistance. This makes it possible to detect the power cycle life and prompt the user to take measures such as replacing parts. In addition, when there is a change in the threshold value of the turn-on or turn-off of the switching element 101, the sense ratio changes, so that the abnormality detection circuit 25 of this embodiment similarly determines that the second current value is abnormal and can detect this. In addition, when the switching element 101 is made of SiC or the like, there is a possibility that the on-resistance increases due to bipolar deterioration. In this case, the abnormality detection circuit 25 of this embodiment similarly determines that the second current value is abnormal and can detect this.

[0124] According to the third embodiment of the present invention described above, in addition to those described in the first embodiment, the following advantageous effects are further achieved.

[0125] (6) The power conversion device 1B detects the current I flowing through the source electrode, which is the main electrode of the switching element 101, in a manner different from that of the first current detection circuit 21. S and an abnormality detection circuit 25 that compares the first current value calculated by the first current detection circuit 21 with the second current value output from the second current detection circuit 40 and determines whether or not an abnormality has occurred in the second current detection circuit 40 or the switching element 101 based on the comparison result. As a result of this, if an abnormality occurs in the second current detection circuit 40 or the switching element 101, it can be detected.

[0126] (7) The switching element 101 includes a current sense element 107 and a temperature sensing element 108. The second current detection circuit 40 includes a sense current detection circuit 109 that detects a sense current, which is the current of the current sense element 107, a temperature sensing element temperature detection circuit 110 that detects the temperature of the temperature sensing element 108, and an output current (second current value I out2 ) is provided. In this manner, the second current detection circuit 40 can reliably detect the output current of the power conversion device 1B using a method different from that of the first current detection circuit 21.

[0127] (Fourth embodiment) Fig. 13 is a diagram showing a configuration example of a power conversion device according to a fourth embodiment of the present invention. A power conversion device 1C shown in Fig. 13 is configured to estimate the terminal temperature of the source electrode, which is the main electrode of the switching element 101 of each phase and each arm, in the power conversion device 1 described in the first embodiment, and to detect overtemperature based on the estimation result. The power conversion device 1C of this embodiment will be described below, focusing on the differences from the first embodiment.

[0128] In the power conversion device 1C of the present embodiment, the control device 20 further includes a terminal temperature estimation circuit 26 and a terminal overtemperature detection circuit 27 in addition to the respective components of the first current detection circuit 21, the output current estimation circuit 22, the control signal generation circuit 23, and the communication connector 24 described in the first embodiment. In the example of Fig. 13, only the configuration of the inverter circuit 10 and the control device 20 related to the W phase is shown, and the illustration of the U phase and the V phase is omitted, but these are similar to those of the W phase.

[0129] In this embodiment, the first current detection circuit 21 detects the above-mentioned first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WLThe first current detection circuit 21 calculates the resistance value R of the parasitic resistance 104 by, for example, the following (Equation 16) which is a modification of the above-mentioned (Equation 11): Ss can be estimated.

number

[0130] In (Equation 16), the source current value I S For the above, the first current detection circuit 21 can use the value of the source current estimated by the calculation method described in the first embodiment using the above-mentioned (Equation 14) or (Equation 15). That is, the resistance value R of the parasitic resistor 104 can be calculated by the following (Equation 17) obtained by substituting (Equation 14) or (Equation 15) into (Equation 16). Ss can be estimated.

number

[0131] The first current detection circuit 21 provided for each phase and each arm calculates a parasitic resistance estimate value R representing the magnitude of the parasitic resistance 104 of the corresponding switching element 101 by (Equation 17). Ss The terminal temperature estimation circuit 26 calculates the parasitic resistance estimate value R Ss Based on this, the terminal temperature of the source electrode, which is the main electrode of the switching element 101 of each phase and each arm, is estimated, and the estimation result is output to the terminal overtemperature detection circuit 27. The terminal temperature estimation circuit 26 stores, for example, table data or an approximation formula based on the relationship between the parasitic resistance and the terminal temperature acquired in advance, and by referring to this table data or approximation formula, the parasitic resistance estimated value R Ss The terminal temperature of the source electrode can be estimated from

[0132] The terminal over-temperature detection circuit 27 detects an over-temperature of the source electrode, which is the main electrode of the switching element 101 of each phase and each arm, based on the terminal temperature estimated by the terminal temperature estimation circuit 26. For example, if the estimated value of the terminal temperature exceeds a predetermined allowable temperature, it determines that the source electrode of the switching element 101 is in an over-temperature state, and transmits an over-temperature abnormality signal to a higher-level system via the communication connector 24. If the higher-level system determines that a change in control is necessary in response to this over-temperature abnormality signal, an abnormality control command is transmitted from the higher-level system to the control signal generation circuit 23, and the control signal generation circuit 23 changes the control to eliminate the over-temperature, such as by stopping the operation of the power conversion device 1C or easing the operating conditions.

[0133] 13 shows a configuration in which control is changed via a higher-level system, a configuration in which an over-temperature abnormality signal is directly output from terminal over-temperature detection circuit 27 to control signal generation circuit 23, and control signal generation circuit 23 changes the control of power conversion device 1C in response to this over-temperature abnormality signal may also be used. In this way, by directly outputting a signal from terminal over-temperature detection circuit 27 to control signal generation circuit 23 without going through a higher-level system, control can be changed with low delay in cases where quick response is required, such as in an emergency stop.

[0134] According to the fourth embodiment of the present invention described above, in addition to those described in the first embodiment, the following advantageous effects are further achieved.

[0135] (8) The power conversion device 1C includes a terminal temperature estimation circuit 26 that estimates the terminal temperature of the source electrode, which is the main electrode of the switching element 101. The first current detection circuit 21 calculates a first integral value (output voltage V out ) and the second integral value (output voltage V out ) based on the estimated parasitic resistance R Ss The terminal temperature estimation circuit 26 outputs the parasitic resistance estimate R SsIn this way, the terminal temperature of the main electrode of the switching element 101 provided in the power conversion device 1C can be accurately estimated from the estimation result of the current flowing through the switching element 101.

[0136] (9) Power conversion device 1C includes terminal overtemperature detection circuit 27 that detects an overtemperature of the source electrode based on the terminal temperature estimated by terminal temperature estimation circuit 26. As a result, if an overtemperature abnormality occurs in switching element 101, this can be reliably detected.

[0137] The present invention is not limited to the various embodiments described above, and includes various modified examples. For example, the above-described embodiments have been specifically described in order to easily explain the present invention, and are not necessarily limited to those having all of the configurations described. Also, a part of the configuration of one embodiment can be replaced with a part of the configuration of another embodiment. Also, a configuration of another embodiment can be added to a configuration of one embodiment. Also, a part of the configuration of each embodiment can be deleted, a part of another configuration can be added, and a part of another configuration can be replaced with a part of another configuration.

[0138] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the present invention. [Explanation of symbols]

[0139] 1, 1A, 1B, 1C: power conversion device, 2: storage battery, 3: motor, 10: inverter circuit, 11: smoothing capacitor, 20: control device, 21: first current detection circuit, 22: output current estimation circuit, 23: control signal generation circuit, 24: communication connector, 25: abnormality detection circuit, 26: terminal temperature estimation circuit, 27: terminal overtemperature detection circuit, 30: Hall sensor, 40: second current detection circuit, 41: on-chip sensor output current estimation circuit, 100: power module, 101: switching element, 102: freewheel diode, 103: inductance, 104: parasitic resistor, 105: gate driver, 106: integration circuit, 107: current sense element, 108: temperature sensor, 109: sense current detection circuit, 110: temperature sensor temperature detection circuit

Claims

1. A switching element; an integrating circuit that outputs an integral value of a voltage generated in an inductance component and a parasitic resistance that are connected in series to a main electrode of the switching element; a first current detection circuit that determines a current flowing through the main electrode of the switching element based on the integral value output from the integration circuit, the first current detection circuit calculates a first current value representing a magnitude of a current flowing through the main electrode based on a first integral value output from the integrating circuit in a period before and after the turning-off of the switching element and a second integral value output from the integrating circuit in a period before and after the turning-on of the switching element; Power conversion equipment.

2. The power conversion device according to claim 1, The switching element is provided in a plurality of parts. the first current detection circuit is provided for each of the plurality of switching elements; an output current estimation circuit that estimates an output current of the power conversion device based on the first current value for each switching element calculated by the first current detection circuit; Power conversion equipment.

3. The power conversion device according to claim 2, the switching elements are provided for upper and lower arms of each phase of a three-phase AC current output from the power conversion device, the output current estimation circuit selects either the upper arm or the lower arm of any two phases based on a combination of pulse widths of gate commands input to the switching elements of the upper and lower arms of each phase, and estimates an output current of each phase of the power conversion device based on the first current value output from the first current detection circuit provided for the switching elements of each selected arm. Power conversion equipment.

4. The power conversion device according to claim 2 or 3, a second current detection circuit for detecting an output current of each phase of the power conversion device; an abnormality detection circuit that compares the output current of each phase estimated by the output current estimation circuit with the output current of each phase detected by the second current detection circuit, and determines whether or not an abnormality has occurred in the second current detection circuit based on a comparison result. Power conversion equipment.

5. The power conversion device according to claim 4, The second current detection circuit is a Hall sensor that detects a three-phase AC current output from the power conversion device. Power conversion equipment.

6. A power conversion device according to any one of claims 1 to 3, a second current detection circuit that detects a current flowing through the main electrode of the switching element by a method different from that of the first current detection circuit and outputs a second current value according to the detection result; an abnormality detection circuit that compares the first current value calculated by the first current detection circuit with the second current value output from the second current detection circuit and determines whether or not an abnormality has occurred in the second current detection circuit or the switching element based on a comparison result. Power conversion equipment.

7. 7. The power conversion device according to claim 6, The switching element includes a current sensing element and a temperature sensing element, the second current detection circuit includes a sense current detection circuit that detects a sense current that is a current of the current sense element, a temperature sensing element temperature detection circuit that detects a temperature sensing element temperature that is a temperature of the temperature sensing element, and an on-chip sensor output current estimation circuit that estimates an output current of the power conversion device based on the sense current and the temperature sensing element temperature. Power conversion equipment.

8. A power conversion device according to any one of claims 1 to 3, a terminal temperature estimation circuit for estimating a terminal temperature of the main electrode; the first current detection circuit outputs a parasitic resistance estimate value representing a magnitude of the parasitic resistance based on the first integral value and the second integral value; the terminal temperature estimation circuit estimates a terminal temperature of the main electrode based on the parasitic resistance estimate value. Power conversion equipment.

9. 9. The power conversion device according to claim 8, a terminal over-temperature detection circuit that detects an over-temperature of the main electrode based on the terminal temperature estimated by the terminal temperature estimation circuit; Power conversion equipment.

Images