Semiconductor device

Abstract

To suppress the decrease in power supply capability even when a free area is necessary in a power supply switch circuit.SOLUTION: A semiconductor device includes a first power supply line, a second power supply line, an end cap, and a first power supply switch circuit including a first transistor and a second transistor. The first transistor is connected to the first power supply line and the second power supply line. The second transistor is connected to the first power supply line and the second power supply line. The first transistor includes a first number of first fins extending in a first direction in a plan view and arranged in a second direction, which is different from the first direction, in the plan view. The second transistor includes a second number of second fins extending in the first direction in the plan view and arranged in the second direction in the plan view. The first number is greater than the second number. The second transistor is disposed between the first transistor and the end cap in the plan view.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In order to reduce leakage current in a semiconductor device, a method is known in which a power switch circuit that is turned on when a circuit block is in operation is provided between a power line and a virtual power line, which is the power line for each of a plurality of circuit blocks.

[0003] In order to increase the power supply capability of the power switch circuit, the size of the transistor used in the power switch circuit is designed to be larger than the size of the cell transistor used in the logic circuit. When transistors of different sizes are arranged adjacent to each other, the shape of the gate electrode of the small-sized transistor is likely to vary during the manufacturing of the semiconductor device. In order to suppress the variation in shape, the transistors of different sizes are arranged at an interval determined by the layout rule. For example, by providing an empty space at the end of the power switch circuit, the transistor of the power switch circuit and the transistor of the logic circuit or the like adjacent to the power switch circuit are arranged at an interval that satisfies the layout rule. For example, a dummy gate electrode or a dummy transistor is arranged in the empty space of the power switch circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 1,014,1336 [Patent Document 2] US Patent Application Publication No. 2019 / 0244900 [Patent Document 3] US Patent Application Publication No. 2019 / 0214377 [Patent Document 4] JP 2018-190760 A [Patent Document 5] International Publication No. 2017 / 208887 Summary of the Invention [Problem to be solved by the invention]

[0005] Recently, in order to achieve both high integration of semiconductor devices and suppression of leakage current, transistors mounted on semiconductor devices are being replaced with, for example, planar type FETs (Field Effect Transistors) to finFETs having a three-dimensional structure. As a result, the difference in size between transistors used in logic circuits and transistors used in power switch circuits tends to become larger. In order to suppress variations in the shape of gate electrodes and the like during manufacturing, a larger free area is provided at the edge of the power switch circuit.

[0006] The larger the free space, the larger the size of the power switch circuit, and the lower the power supply capability per unit size. In addition, typically, multiple power switch circuits are arranged in a semiconductor device. Therefore, as the size of the power switch circuit increases, the scale of the logic circuit that can be mounted on the semiconductor device decreases. If the scale of the logic circuit is maintained, the chip size of the semiconductor device increases.

[0007] The present invention has been made in view of the above-mentioned points, and has an object to suppress a decrease in power supply capability even when free space is required in a power switch circuit. [Means for solving the problem]

[0008] In one embodiment of the present invention, a semiconductor device has a first power supply line, a second power supply line, an end cap, and a first power supply switch circuit having a first transistor and a second transistor, the first transistor is connected to the first power supply line and the second power supply line, the second transistor is connected to the first power supply line and the second power supply line, the first transistor has a first number of first fins extending in a first direction in a planar view and arranged side by side in a second direction different from the first direction in a planar view, the second transistor has a second number of second fins extending in the first direction in a planar view and arranged side by side in the second direction in a planar view, the first number is greater than the second number, and the second transistor is arranged between the first transistor and the end cap in a planar view. Effect of the Invention

[0009] According to the disclosed technique, even when free space is required in the power switch circuit, a decrease in power supply capacity can be suppressed. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram illustrating an example of a layout of the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of power switch circuits SPSW and PPSW in FIG. [Diagram 3] 2 is a diagram showing an example of the layout of a power switch circuit provided in the peripheral region of FIG. 1; [Figure 4] 4 is a diagram showing an example of a layout of power supply wiring of the power switch circuit PPSW in FIG. 3. [Diagram 5] FIG. 5 is a diagram showing the layout of the fins, gate electrodes, and local interconnects in FIG. [Figure 6] FIG. 5 is a perspective view showing an example of the structure of the n2-fin×m1 transistor of FIGS. 3 and 4. [Figure 7] 5 is a cross-sectional view taken along line Y1-Y1' in FIG. 4. FIG. [Figure 8]5 is a cross-sectional view taken along line X1-X1' in FIG. 4. FIG. [Figure 9] 2 is a diagram showing an example of a layout of a power switch circuit provided in the standard cell region of FIG. 1; [Figure 10] FIG. 13 is a diagram showing an example (comparative example) of a circuit layout of another power switch circuit. [Figure 11] FIG. 13 is a diagram showing an example of a layout of a semiconductor device according to a second embodiment. [Figure 12] FIG. 13 is a diagram showing an example of a layout of a semiconductor device according to a third embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a layout of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 13 is a diagram showing an example of a layout of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 13 is a diagram showing an example of a layout of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the drawings. In the following, the power supply name and symbol are used for the power supply line through which power is supplied.

[0012] (First embodiment) Fig. 1 shows an example of a layout of a semiconductor device in the first embodiment. The semiconductor device 100 shown in Fig. 1 has, for example, at least one power domain PD1. In the power domain PD1, a standard cell area SCA in which a plurality of standard cells (not shown) are arranged, and a plurality of peripheral areas PA in which one or a plurality of RAMs (Random Access Memories) are arranged are provided. The standard cell area SCA is an example of a first area in which a logic circuit is arranged, and the peripheral area PA is an example of a second area in which a functional circuit different from the logic circuit is arranged.

[0013] 1 shows only one power domain PD1, the semiconductor device 100 may have multiple power domains. Note that the left side of the power domain PD1 in FIG. 1 may be the chip end of the semiconductor device 100. Although not limited thereto, the transistors mounted on the semiconductor device 100 are finFETs. The finFETs will be described with reference to FIG. 6.

[0014] In the standard cell area SCA, a plurality of power switch circuits SPSW are arranged at intervals. In addition, an end cap ECAP shown by a hatched pattern is arranged around the standard cell area SCA. The end cap ECAP has a dummy gate electrode or a dummy transistor. Note that only the standard cells may be arranged in the standard cell area SCA without arranging the power switch circuit SPSW.

[0015] In each peripheral area PA, one or more RAMs are arranged, and in some peripheral areas PA, multiple power switch circuits PPSW and end caps ECAP are arranged adjacent to the RAMs. The RAM is an example of a memory IP (Intellectual Property) that is a hard macro, and is an example of a functional circuit having a predetermined function. The power switch circuit PPSW is an example of a first power switch circuit. The power switch circuit SPSW is an example of a second power switch circuit.

[0016] FIG. 2 shows an example of the power switch circuits SPSW and PPSW of FIG. 1. The power switch circuit PPSW has a p-channel transistor PT1 and a power switch control circuit PCNT1. The power switch circuit SPSW has a p-channel transistor PT2 and a power switch control circuit PCNT2. Note that each of the p-channel transistors PT1 and PT2 actually includes a plurality of transistors connected in parallel. Note that the power switch circuits SPSW and PPSW may each have an n-channel transistor instead of the p-channel transistor PT1 and the p-channel transistor PT2. In this case, the source of the n-channel transistor is connected to the ground line VSS, and the drain is connected to each logic circuit of the standard cell and to a virtual ground line that supplies a ground potential.

[0017] The source of the p-channel transistor PT1 is connected to a power supply line VDD to which an external power supply VDD is supplied, and the drain of the p-channel transistor is connected to a virtual power supply line VVDD connected to a power supply terminal of the standard cell and the RAM. The power supply line VDD is an example of a first power supply line, and the virtual power supply line VVDD is an example of a second power supply line. The gate electrode of the p-channel transistor PT1 is connected to the output of the power switch control circuit PCNT1.

[0018] The source of the p-channel transistor PT2 is connected to the power supply line VDD, the drain of the p-channel transistor is connected to the virtual power supply line VVDD, and the gate electrode of the p-channel transistor PT2 is connected to the output of the power switch control circuit PCNT2.

[0019] Each of the power switch control circuits PCNT1 and PCNT2 is connected to a power line VDD and a ground line VSS in order to operate constantly, and operates based on the power control signal PCNT. When the power control signal PCNT indicates an active mode in which the circuits in the power domain PD1 are operated, the power switch control circuit PCNT1 supplies the ground voltage VSS to the gate electrode of the p-channel transistor PT1. This turns on the p-channel transistor PT1, and the power line VDD and the virtual power line VVDD are connected to each other.

[0020] When the power control signal PCNT indicates the active mode, the power switch control circuit PCNT2 supplies the ground voltage VSS to the gate electrode of the p-channel transistor PT2, which turns on the p-channel transistor PT2 and connects the power supply line VDD and the virtual power supply line VVDD to each other.

[0021] When the power control signal PCNT indicates the power down mode, the power switch control circuit PCNT1 supplies a power supply voltage VDD to the gate electrode of the p-channel transistor PT1, which turns off the p-channel transistor PT1 and cuts off the connection between the power supply line VDD and the virtual power supply line VVDD.

[0022] When the power control signal PCNT indicates the power down mode, the power switch control circuit PCNT2 supplies a power supply voltage VDD to the gate electrode of the p-channel transistor PT2. This turns off the p-channel transistor PT2, and the connection between the power supply line VDD and the virtual power supply line VVDD is cut off. In this way, the p-channel transistors PT1 and PT2 operate based on the common power control signal PCNT, and function as a power switch that connects the power supply line VDD to the virtual power supply line VVDD.

[0023] The power supply terminal of the RAM is connected to the virtual power supply line VVDD, and the ground terminal of the RAM is connected to the ground line VSS. Similarly, the power supply terminal of the standard cell is connected to the virtual power supply line VVDD, and the ground terminal of the standard cell is connected to the ground line VSS.

[0024] The p-channel transistors PT1 and PT2 turn on during active mode and connect the power supply line VDD to the virtual power supply line VVDD. As a result, the RAM and standard cells in the power domain PD1 receive the power supply voltage VDD via the virtual power supply line VVDD during active mode and operate. On the other hand, the p-channel transistors PT1 and PT2 turn off during power down mode and cut off the connection between the power supply line VDD and the virtual power supply line VVDD. As a result, the supply of the power supply voltage VDD to the RAM and standard cells in the power domain PD1 is stopped during power down mode and they stop operating.

[0025] The p-channel transistors PT1 may receive control signals at their gate electrodes from the power switch control circuit PCNT1 at different timings, and be sequentially turned on and off. Similarly, the p-channel transistors PT2 may receive control signals at their gate electrodes from the power switch control circuit PCNT2 at different timings, and be sequentially turned on and off.

[0026] By shifting the operation timing of the p-channel transistor PT1 (or PT2), it is possible to prevent a sudden flow of current from the power supply VDD to the virtual power line VVDD, thereby mitigating the power supply noise that occurs when the power switch circuits PPSW and SPSW start operating.

[0027] Fig. 3 shows an example of the layout of the power switch circuit PPSW provided in the peripheral area PA of Fig. 1. Fig. 3 shows an example in which the power switch circuit PPSW is a four-height cell that uses four areas provided between five power lines (VVDD, VSS) extending in the X direction. Note that the power switch circuit PPSW may be a double-height cell (two-height cell) or an eight-height cell. The X direction is an example of the first direction.

[0028] The power switch circuit PPSW includes a main transistor MTr, a sub-transistor STr, additional transistors ATr1 and ATr2, a well tap WLT, a main buffer unit MBUF, a sub-buffer unit SBUF, and two end caps ECAP. The main transistor MTr, the sub-transistor STr, and the additional transistors ATr1 and ATr2 each include a plurality of p-channel transistors corresponding to the p-channel transistor PT1 shown in FIG. 2. The main transistor MTr and the sub-transistor STr are an example of a first transistor. The additional transistor ATr1 is an example of a second transistor, and the additional transistor ATr2 is an example of a fifth transistor.

[0029] The main transistor MTr has a plurality of transistors each having n1 fins and m1 gate electrodes (hereinafter also referred to as n1-fin×m1 transistors). The main transistor MTr also has a plurality of transistors each having n2 fins and m1 gate electrodes (hereinafter also referred to as n2-fin×m1 transistors). The additional transistors ATr1 and ATr2 each have a plurality of transistors each having n2 fins and m2 gate electrodes (hereinafter also referred to as n2-fin×m2 transistors). Here, n1, n2, m1, and m2 are any natural numbers that satisfy the relationships n1>n2 and m1>m2.

[0030] The size of each transistor varies depending on the number of fins and the number of gate electrodes. For example, when n1=8, n2=3, m1=10, and m2=1, the sizes of the transistors are n1-fin×m1>n2-fin×m1>n2-fin×m2 in descending order. For example, the size of the n2-fin×m2 transistor is the same as the size of any one of the multiple types of transistors used in the logic circuit of the standard cell area SCA in FIG. 1.

[0031] The main buffer unit MBUF and the sub-buffer unit SBUF are included in the power switch control circuit PCNT1 shown in Fig. 2. The main buffer unit MBUF controls the operation of the main transistor MTr and the additional transistors ATr1 and ATr2, and the sub-buffer unit SBUF controls the operation of the sub-transistor STr. The additional transistors ATr1 and ATr2 may be controlled by the sub-buffer unit SBUF.

[0032] The well tap WLT supplies a power supply voltage VVDD to a well region in which a p-channel transistor is formed. The two end caps ECAP are arranged at both ends in the X direction, which is the horizontal direction in FIG.

[0033] In this embodiment, the edge of the n1-fin×m1 transistor in the X direction and the edge of the layout area of ​​the power switch circuit PPSW are spaced apart by a distance SP1 or more according to the layout rule of the semiconductor device 100. The rule of the distance SP1 is set in order to suppress variations in the shapes of the gate electrodes and the like of the n1-fin×m1 transistor caused by the influence of external factors such as other circuits adjacent to the power switch circuit PPSW during the manufacture of the semiconductor device 100, and to suppress variations in the electrical characteristics of the transistors.

[0034] For example, the width of the end cap ECAP in the X direction is smaller than the interval SP1, and an empty area is generated between the end cap ECAP and the n1-fin×m1 transistor. In this embodiment, an additional transistor ATr1 functioning as a power switch is arranged in this empty area. Also, an additional transistor ATr2 functioning as a power switch is arranged in another empty area of ​​the power switch circuit PPSW (in this example, between the main buffer unit MBUF and the sub-buffer unit SBUF).

[0035] In this way, the main transistor MTr, the sub-transistor STr, and the additional transistors ATr1 and ATr2 function as a power switch that connects the power line VDD to the virtual power line VVDD. Therefore, in the power switch circuit PPSW, the additional transistor ATr1 arranged in the free space generated by the constraints of the layout rule (space SP1) can improve the power supply capability of the power switch circuit PPSW.

[0036] In this case, the additional transistor ATr1 has the same structure as the n2-fin×m2 transistor used in the logic circuit arranged in the standard cell area SCA, which contributes to suppressing the variation in the shape of the gate electrode of the circuit adjacent to the power switch circuit PPSW.

[0037] In addition, the power supply capability of the power switch circuit PPSW can be improved by the additional transistor ATr2 that is placed in an empty area that occurs due to the circuit layout in the power switch circuit PPSW. As a result, the power supply capability of the power switch circuit PPSW can be improved without increasing the layout area of ​​the power switch circuit PPSW.

[0038] That is, by arranging the additional transistors ATr1 and ATr2 in the vacant region, it is possible to improve the power supply capability of the p-channel transistor PT1 while suppressing an increase in the layout area of ​​the power switch circuit PPSW.

[0039] FIG. 4 shows an example of the layout of the power wiring of the power switch circuit PPSW of FIG. 3. FIG. 4 shows the layout of the double-height cells on the right side of the main transistor MTr in the power switch circuit PPSW of FIG. 3. Hereinafter, the virtual power line VVDD and the ground line VSS that are wired from outside the power switch circuit PPSW are also referred to as power lines VVDD and VSS. The virtual power line VVDD and the power line VDD that are enclosed within the power switch circuit PPSW are also referred to as lines VVDD and VDD, respectively. In the example of FIG. 4, n1=8, n2=3, m1=10, and m2=1.

[0040] Two power supply lines VVDD and one power supply line VSS are formed using the M0 layer. The M0 layer is the metal wiring layer closest to the semiconductor substrate, and the wiring in the M0 layer extends in the X direction (horizontal direction in FIG. 4). Between each power supply line VVDD and the power supply line VSS, wiring VDD, VVDD and a signal line SIG are formed using the M0 layer. For example, the signal line SIG is the gate wiring of the p-channel transistor PT1 shown in FIG. 2.

[0041] The local wiring VDD extending in the Y direction is connected to the wiring VDD of the M0 layer through a via. The Y direction is an example of a second direction perpendicular to the X direction. The wiring VDD of the M0 layer is connected to a power supply line VDD formed using an upper metal wiring layer through a via (not shown). The local wiring VVDD extending in the Y direction is connected to the wiring VVDD of the M0 layer and the power supply line VVDD of the M0 layer through a via. The wiring VVDD and the power supply line VVDD of the M0 layer may be connected to the power supply line VVDD formed using an upper metal wiring layer. The local wirings VDD and VVDD are provided between the gate electrodes G extending in the Y direction.

[0042] The fins extend in the X direction and are arranged at intervals in the Y direction. For example, an n2-fin×m1 transistor has dummy gate electrodes DMYG on both sides in the X direction, and therefore has m1+2 gate electrodes. An n2-fin×m2 transistor has dummy gate electrodes DMYG on both sides in the X direction, and therefore has m2+2 gate electrodes. In the example shown in FIG. 4, the end cap ECAP has three dummy gate electrodes DMYG and dummy local wirings arranged between the dummy gate electrodes DMYG.

[0043] In the n2-fin×m1 transistor and the n2-fin×m2 transistor, a source region S or a drain region D is formed between two adjacent gate electrodes G. The source region S and the drain region D are formed alternately on either side of the gate electrode G, with a wiring VDD connected to the source region S and a wiring VVDD connected to the drain region D. Note that in a finFET, the source region S and the drain region D are each formed in a fin. For this reason, the local wiring VDD is connected to the fin that functions as the source region S, and the local wiring VVDD is connected to the fin that functions as the drain region D.

[0044] Fig. 5 shows a layout of the fins, gate electrode G, and local wiring in Fig. 4. The gate electrode G and local wiring are formed in the Y direction across the fins extending in the X direction.

[0045] Figure 6 shows an example of the structure of the n2-fin×m1 transistor of Figures 3 and 4. The fin transistor has a fin extending in the X direction provided on a semiconductor substrate, and a gate electrode G extending in the Y direction across the fin. A gate insulating film is formed on a portion of the fin facing the gate electrode G, and a channel of the transistor is formed in the surface portion of the fin covered with the gate insulating film.

[0046] A source region S and a drain region D are provided on both sides of the gate electrode G in the fin. Although not shown, each source region S and each drain region D are provided with a local wiring VDD and a local wiring VVDD along the extending direction of the gate electrode G. In the power switch circuit PPSW shown in FIG. 4, a p-channel transistor is formed, and the source region S is connected to the wiring VDD and the drain region D is connected to the wiring VVDD. In FIG. 6, the source region S and the drain region D may be interchanged.

[0047] FIG. 7 shows a cross section taken along line Y1-Y1' in FIG. 4. The fins are formed in an isolation insulating film such as STI (Shallow Trench Isolation) formed on a semiconductor substrate. The upper part of the fin protruding above the isolation insulating film is covered with a local wiring VVDD in the cross section shown in FIG. 7. In the cross section shown in FIG. 7, each local wiring VVDD is connected to a power supply line VVDD and wiring VVDD formed in the M0 layer through a via. Each local wiring VVDD, each via, and each wiring VVDD and VDD formed in the M0 layer are electrically isolated from each other by an interlayer insulating film.

[0048] Fig. 8 shows a cross section taken along line X1-X1' in Fig. 4. In the cross section shown in Fig. 8, local interconnects and gate electrodes are alternately formed on the fin. Among the local interconnects, the local interconnect connected to the drain region of a transistor (not shown) is connected to an interconnect VVDD formed in the M0 layer.

[0049] Fig. 9 shows an example of the layout of the power switch circuit SPSW provided in the standard cell area SCA of Fig. 1. The same elements as those in Fig. 3 are given the same reference numerals and detailed description is omitted. The power switch circuit SPSW provided in the standard cell area SCA does not have an end cap ECAP and does not require the space SP1 defined by the layout rule.

[0050] However, for example, when the power switch circuit SPSW is adjacent to an end cap ECAP arranged to surround the standard cell area SCA, it becomes necessary to provide a space SP1 between the power switch circuit SPSW and the end cap ECAP. In such a case, as shown in the example of Figure 9, an additional transistor ATr1 (n2-fin x m2 transistor) is arranged in the space SP1. Note that when the power switch circuit SPSW is arranged away from the end cap ECAP arranged to surround the standard cell area SCA, the space SP1 and the additional transistor ATr1 arranged in the space SP1 may be omitted.

[0051] Other configurations of the power switch circuit SPSW are similar to those of the power switch circuit PPSW in Fig. 3. An additional transistor ATr2 (n2-fin × m2 transistor) functioning as a power switch is arranged in another free area of ​​the power switch circuit SPSW (between the main buffer unit MBUF and the sub-buffer unit SBUF in this example).

[0052] The main transistor MTr and the sub-transistor STr provided in the power switch circuit SPSW are an example of a third transistor. The additional transistor ATr1 provided in the power switch circuit SPSW is an example of a fourth transistor, and the additional transistor ATr2 is an example of a fifth transistor.

[0053] 3, the main transistor MTr, sub-transistor STr, and additional transistors ATr1 and ATr2 of the power switch circuit SPSW function as a power switch that connects the power line VDD to the virtual power line VVDD. Therefore, in the power switch circuit SPSW, the additional transistor ATr1 arranged in the free space generated by the constraints of the layout rule (space SP1) can improve the power supply capability of the power switch circuit SPSW.

[0054] In this case, the additional transistor ATr1 has the same structure as the n2-fin×m2 transistor used in the logic circuit arranged in the standard cell area SCA. Therefore, the power switch circuit SPSW adjacent to the end cap ECAP can suppress variations in the shape of the gate electrode and the like caused by other circuits and other patterns arranged outside the standard cell area SCA.

[0055] In addition, the power supply capability of the power switch circuit SPSW can be improved by the additional transistor ATr2 that is placed in an empty area that occurs due to the circuit layout in the power switch circuit SPSW. As a result, the power supply capability of the power switch circuit SPSW can be improved without increasing the layout area of ​​the power switch circuit SPSW.

[0056] That is, by arranging the additional transistors ATr1 and ATr2 in the free area, it is possible to improve the power supply capability of the p-channel transistor PT2 while suppressing an increase in the layout area of ​​the power switch circuit SPSW.

[0057] 10 shows an example (comparative example) of the circuit layout of another power switch circuit PSW. The same elements as those in FIG. 3 are given the same reference numerals, and detailed description will be omitted. In the power switch circuit PSW shown in FIG. 10, no transistors are arranged in the arrangement areas of the additional transistors ATr1 and ATr2 of the power switch circuit PPSW in FIG. 3, leaving empty areas E1 and E2. In this case, the power supply capability of the power switch circuit PSW is lower than that of the power switch circuit PPSW in FIG. 3 and the power switch circuit SPSW in FIG. 9.

[0058] As described above, in this embodiment, in each of the power switch circuits PPSW and SPSW, the additional transistor ATr1 is placed in a free space generated due to the constraints of the layout rule (spacing SP1). This makes it possible to improve the power supply capability without increasing the layout area of ​​the power switch circuits PPSW and SPSW. In other words, even if free space is required in the power switch circuits PPSW and SPSW due to the constraints of the layout rule, it is possible to suppress a decrease in the power supply capability.

[0059] The additional transistor ATr1 has the same structure as the 3fin×1 transistor used in the logic circuit arranged in the standard cell area SCA, which contributes to suppressing the variation in the shape of the gate electrodes of the circuits adjacent to the power switch circuits PPSW and SPSW.

[0060] Furthermore, the power supply capability of the power switch circuits PPSW and SPSW can be improved by the additional transistor ATr2 that is placed in an empty area that occurs due to the circuit layout in the power switch circuits PPSW and SPSW, thereby improving the power supply capability of the power switch circuits PPSW and SPSW without increasing the layout area of ​​the power switch circuits PPSW and SPSW.

[0061] Second Embodiment Fig. 11 shows an example of the layout of the semiconductor device according to the second embodiment. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. The semiconductor device 102 shown in Fig. 10 has, for example, power domains PD2 and PD3 on the left side in the X direction of the power domain PD1 shown in Fig. 1.

[0062] The power domain PD2 has a circuit layout similar to that of the power domain PD1. The power domain PD3 has a circuit layout that operates constantly while power is being supplied to the semiconductor device 102, and therefore does not include the power switch circuits PPSW and SPSW.

[0063] As described above, in this embodiment, even when multiple power domains PD1, PD2, and PD3 are adjacent to each other, the power supply capability can be improved without increasing the layout area of ​​the power switch circuits PPSW and SPSW, as in the above-described embodiments.

[0064] (Third embodiment) Fig. 12 shows an example of the layout of the semiconductor device in the third embodiment. The same elements as those in Fig. 1 are given the same reference numerals and detailed description is omitted. In the semiconductor device 104 shown in Fig. 11, a RAM and an analog IP are arranged in the peripheral area PA.

[0065] In the semiconductor device 104, circuits other than the analog IP operate constantly while power is being supplied to the semiconductor device 104. For this reason, power switch circuits PPSW are arranged on both sides of the analog IP in the X direction, and the analog IP and the power switch circuit PPSW belong to the power domain PD4.

[0066] As described above, in this embodiment as well, similarly to the above-described embodiment, the power supply capability can be improved without increasing the layout area of ​​the power switch circuit PPSW.

[0067] (Fourth embodiment) 13 shows an example of the layout of a semiconductor device in the fourth embodiment. The same elements as those in FIG. 1 are given the same reference numerals, and detailed description thereof will be omitted. In a semiconductor device 106 shown in FIG. 13, two power switch circuit rows each including a plurality of power switch circuits PPSW arranged in the Y direction are provided in an area adjacent to the RAM. That is, the semiconductor device 106 has an increased number of power switch circuits PPSW compared to the semiconductor device 100 in FIG. 1. Other configurations of the semiconductor device 106 are similar to those of the semiconductor device 100 in FIG. 1.

[0068] As described above, in this embodiment, as in the above-mentioned embodiment, the power supply capability can be improved without increasing the layout area of ​​the power switch circuit PPSW. Furthermore, in this embodiment, if there is free space in the power domain PD1 of the semiconductor device 106, the free space can be utilized to add the power switch circuit PPSW, thereby further improving the power supply capability in the power domain PD1.

[0069] Fifth embodiment Fig. 14 shows an example of the layout of a semiconductor device in the fifth embodiment. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. A semiconductor device 108 shown in Fig. 14 has multiple types of power switch circuits PPSW (PPSWa, PPSWb, PPSWc) arranged in a power switch region provided around a standard cell area SCA. The power switch circuit SPSW shown in Fig. 1 is not arranged in the standard cell area SCA. Therefore, a power supply VVDD, which is an operating power supply for the circuits arranged in the standard cell area SCA, is supplied from the power switch circuit PPSW via an upper wiring layer not shown.

[0070] The power switch circuits PPSWa are arranged on both sides in the X direction in the standard cell area SCA. The power switch circuit PPSWa has an n2-fin×m1 transistor and an n1-fin×m1 transistor arranged in the center in the X direction. The power switch circuit PPSWa also has n2-fin×m2 transistors and end caps ECAP arranged on both sides in the X direction, which is the arrangement direction of the gate electrodes of the n2-fin×m1 transistor and the n1-fin×m1 transistor.

[0071] The n2-fin×m2 transistor is provided adjacent to the n2-fin×m1 transistor and the n1-fin×m1 transistor. The end cap ECAP is disposed on the opposite side of the n2-fin×m2 transistor to the n2-fin×m1 transistor and the n1-fin×m1 transistor. The end cap ECAP and the n2-fin×m2 transistor adjacent to the end cap ECAP ensure a space SP1 defined by the layout rule.

[0072] The power switch circuit PPSWb is arranged at the corners of the periphery of the standard cell area SCA. End caps ECAP are arranged around the power switch circuit PPSWb, except for the end on the power switch circuit PPSWc side. The power switch circuit PPSWb has n2-fin×m2 transistors adjacent to the end cap ECAP arranged at the end in the X direction, and n1-fin×m1 transistors and n2-fin×m1 transistors arranged adjacent to the row of n2-fin×m2 transistors. In the power switch circuit PPSWb, the end cap ECAP and the n2-fin×m2 transistors adjacent to the end cap ECAP ensure a space SP1.

[0073] The power switch circuits PPSWc are arranged on both sides in the Y direction in the standard cell area SCA. The power switch circuit PPSWc has a configuration obtained by removing the n2-fin×m2 transistor and the end cap ECAP adjacent to the n2-fin×m2 transistor in the X direction from the power switch circuit PPSWb.

[0074] Each of the power switch circuits PPSWa, PPSWb, and PPSWc may not have the main buffer unit MBUF and the sub-buffer unit SBUF. In this case, the power switch control circuit PCNT1 shown in FIG. 2 is provided outside each of the power switch circuits PPSWa, PPSWb, and PPSWc.

[0075] As described above, in this embodiment, as in the above-mentioned embodiment, the power supply capability can be improved without increasing the layout area of ​​the power switch circuit PPSW. Furthermore, in this embodiment, the power switch circuits PPSWa, PPSWb, and PPSWc are arranged around the standard cell area SCA, making it possible to eliminate the need for the power switch circuit SPSW in the standard cell area SCA. Therefore, the logic circuits in the standard cell area SCA can be connected without being affected by the power switch circuit SPSW, and the signal propagation delay time can be minimized. As a result, it is possible to contribute to improving the performance of the semiconductor device 108.

[0076] Sixth embodiment Fig. 15 shows an example of the layout of the semiconductor device in the sixth embodiment. The same elements as those in Figs. 1 and 14 are given the same reference numerals, and detailed description is omitted. The semiconductor device 110 shown in Fig. 15 has a plurality of types of power switch circuits PPSW (PPSWb, PPSWc, PPSWd, PPSWe) arranged in a power switch region provided adjacent to one side in the Y direction of the standard cell region SCA. As in Fig. 14, the power switch circuit SPSW shown in Fig. 1 is not arranged in the standard cell region SCA. Therefore, the power supply VVDD, which is the operating power supply of the circuits arranged in the standard cell region SCA, is supplied from the power switch circuit PPSW via an upper wiring layer not shown.

[0077] In this embodiment, the power switch circuit PPSWe is arranged inside the power switch circuits PPSWb, PPSWc, and PPSWd that are arranged in a ring shape. The power switch circuits PPSWb and PPSWc have the same configuration as the power switch circuits PPSWb and PPSWc in FIG.

[0078] The power switch circuit PPSWd has an n2-fin×m1 transistor and an n1-fin×m1 transistor arranged on the left side in the X direction. The power switch circuit PPSWd also has an n2-fin×m2 transistor and an end cap ECAP arranged in sequence on the opposite side of the power switch circuit PPSWe in the X direction.

[0079] The n2-fin×m2 transistors and the end cap ECAP adjacent to the n2-fin×m2 transistors ensure the space SP1. The power switch circuit PPSWd has a configuration in which one row of n2-fin×m2 transistors and one end cap ECAP are deleted from the power switch circuit PPSWa in Fig. 14. This is because one end of the power switch circuit PPSWd in the X direction is not adjacent to the standard cell area SCA.

[0080] Since the power switch circuit PPSWe is arranged inside the power switch circuits PPSWb, PPSWc, and PPSWd, the n2-fin×m2 transistor and the end cap ECAP for securing the interval SP1 are not arranged. Therefore, the power switch circuit PPSWe has only the n2-fin×m1 transistor and the n2-fin×m1 transistor.

[0081] As described above, in this embodiment as well, similarly to the above-described embodiment, the power supply capability can be improved without increasing the layout area of ​​the power switch circuit PPSW.

[0082] In the above-described embodiment, examples have been described in which the power switch circuits PSW1 and PSW2 have finFETs, but the present invention may also be applied to power switch circuits having planar transistors, nanowire transistors, nanosheet transistors, fork sheet transistors, CFETs (Complementary FETs), vertical nanowire transistors, etc.

[0083] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0084] 100, 102, 104, 106, 108, 110 Semiconductor device ATr1, ATr2 additional transistors D Drain region E1, E2 area ECAP end cap G gate electrode MBUF Main buffer section MTr Main Transistor PA Surrounding Area PCNT Power control signal PCNT1, PCNT2 Power switch control circuit PD, PD1, PD2, PD3, PD4 Power Domains PPSW, PPSWa, PPSWb Power switch circuit PPSWc, PPSWd, PPSWe Power switch circuit PT1, PT2 p-channel transistors S source region SBUF Sub-buffer section SCA Standard Cell Area SIG signal line SP1 interval SPSW Power switch circuit STr sub-transistor VDD power line VSS power wire (ground wire) VVDD Virtual power line WLT Well Tap

Claims

1. A first power supply line; A second power line; End caps and a first power switch circuit having a first transistor and a second transistor; having the first transistor is connected to the first power supply line and the second power supply line; the second transistor is connected to the first power supply line and the second power supply line; the first transistor extends in a first direction in a plan view and has a first number of first fins arranged side by side in a second direction different from the first direction in a plan view; the second transistor extends in the first direction in a plan view and has a second number of second fins arranged side by side in the second direction in a plan view; the first number is greater than the second number; The second transistor is disposed between the first transistor and the end cap in a plan view.

2. The semiconductor device of claim 1 , wherein the end cap has the second number of third fins.

3. the first power supply switch circuit has a third transistor connected to the first power supply line and the second power supply line; the third transistor extends in the first direction and has the second number of fourth fins arranged side by side in the second direction; The semiconductor device according to claim 1 , wherein the third transistor is adjacent to the first transistor and the second transistor.

4. A logic circuit; A functional circuit, The semiconductor device according to claim 1 , wherein the end cap is located between the logic circuit and the functional circuit in the first direction.

5. The semiconductor device according to claim 4 , wherein the logic circuit has the second number of fifth fins extending in the first direction and arranged side by side in the second direction.

6. the first power supply switch circuit has a fourth transistor connected to the first power supply line and the second power supply line; the fourth transistor extends in the first direction and has a second number of sixth fins arranged side by side in the second direction; The semiconductor device according to claim 4 , wherein the fourth transistor is located on an opposite side to the second transistor in the first direction.

7. a second power switch circuit having a fifth transistor and a sixth transistor; the fifth transistor is connected to the first power supply line and the second power supply line; the sixth transistor is connected to the first power supply line and the second power supply line; the fifth transistor has a third number of fourth fins extending in the first direction and arranged side by side in the second direction; the sixth transistor has a fourth number of fifth fins extending in the first direction and arranged side by side in the second direction; the third number is greater than the fourth number; The semiconductor device according to claim 4 , wherein the sixth transistor is disposed between the logic circuit and the fifth transistor in the first direction.

8. The semiconductor device according to claim 7 , wherein the logic circuit has the fourth number of ninth fins extending in the first direction and arranged side by side in the second direction.

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