Measuring method for DC bias aging properties of multilayer capacitor

Abstract

To measure the DC bias aging properties of a multilayer capacitor quickly and accurately, and accurately predict saturated electrostatic capacity by DC bias aging of a multilayer capacitor at different temperatures from one another.SOLUTION: A measuring method for the DC bias aging properties of a multilayer capacitor according to an embodiment may include: a step which applies a first polling voltage to a multilayer capacitor consisting of a body that includes a dielectric layer including a plurality of dielectric crystal particles and an internal electrode arranged alternately with the dielectric layer in a first direction, and an external electrode that is arranged on the body; a step which maintains the first polling voltage for a first time t1; a step which applies a DC bias voltage lower than the first polling voltage; a step which maintains the DC bias voltage for a second time t2; and a step which measures electrostatic capacitance saturated after the DC bias voltage is applied.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a method for measuring DC bias aging characteristics of a multilayer capacitor. [Background technology]

[0002] Stacked capacitors are widely used as components for electronic devices such as computers and mobile phones due to their small size, high capacitance, and ease of implementation. They are also widely used as components for electrical devices (including vehicles) due to their high reliability and strength.

[0003] As described above, due to the variety of electronic / electrical devices in which the multilayer capacitor is used, the multilayer capacitor can be evaluated with various guarantee indices such as capacitance characteristics, temperature characteristics, and operating voltage characteristics.

[0004] Among the many guarantee indicators, the DC bias aging characteristic may be a guarantee indicator of the minimum capacitance value when the stacked capacitor is used for a long period of time (e.g., 10 years or more). Therefore, the time required for measuring the DC bias aging characteristic may be relatively long compared to other guarantee indicators, and if the required time is forcibly reduced, the accuracy of the DC bias aging characteristic measurement may be reduced. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2000-340474 Summary of the Invention [Problem to be solved by the invention]

[0006] One objective of embodiments of the present invention is to quickly and accurately measure the DC bias aging characteristics of a stacked capacitor.

[0007] Another object of the present invention is to accurately predict the saturation capacitance of a multilayer capacitor due to DC bias aging at different temperatures. [Means for solving the problem]

[0008] According to one aspect of the present invention, a DC bias aging characteristic of a multilayer capacitor may be measured by applying a first poling voltage to a multilayer capacitor including a dielectric layer including a plurality of dielectric crystal grains, a body including internal electrodes alternately arranged with the dielectric layer in a first direction, and an external electrode arranged on the body, maintaining the first poling voltage for a first time t1, applying a DC bias voltage lower than the first poling voltage, maintaining the DC bias voltage for a second time t2, and measuring a saturated capacitance after applying the DC bias voltage.

[0009] According to another aspect of the present invention, a DC bias aging characteristic of a multilayer capacitor may be measured through the steps of: applying a first poling voltage to a multilayer capacitor including a body including a capacitive region in which at least one first internal electrode and at least one second internal electrode are alternately stacked in a first direction with at least one dielectric layer sandwiched therebetween; and first and second external electrodes disposed on the body at a distance from each other to be connected to the at least one first internal electrode and the at least one second internal electrode, respectively; measuring a first capacitance of the multilayer capacitor to which a DC bias voltage lower than the first poling voltage is applied after applying the first poling voltage; applying a second poling voltage different from the first poling voltage to the multilayer capacitor; measuring a second capacitance of the multilayer capacitor to which a DC bias voltage lower than the second poling voltage is applied after applying the second poling voltage; and measuring a DC bias aging characteristic of the multilayer capacitor based on the first and second poling voltages and the first and second capacitances. Effect of the Invention

[0010] A method for measuring DC bias aging characteristics of a multilayer capacitor according to an embodiment of the present invention can quickly and accurately measure the DC bias aging characteristics of a multilayer capacitor, and can quickly and accurately provide a minimum value guarantee index for the capacitance of the multilayer capacitor.

[0011] The method for measuring DC bias aging characteristics of a multilayer capacitor according to another embodiment of the present invention can accurately predict the saturated capacitance due to DC bias aging of a multilayer capacitor at different temperatures.

[0012] By using the measurement method according to an embodiment of the present invention, the measurement time, which currently requires at least 100 hours, can be reduced to less than one hour. This not only reduces the spatial and tangible costs required for expanding the measurement equipment, but also has the intangible effect of shortening product development time. [Brief description of the drawings]

[0013] [Figure 1] 1 is a diagram showing a system for performing a method for measuring DC bias aging characteristics of a multilayer capacitor according to an embodiment of the present invention. [Diagram 2] 4 is a flowchart illustrating a method for measuring DC bias aging characteristics of a multilayer capacitor according to an embodiment of the present invention. [Diagram 3] 1 is a perspective view showing a multilayer capacitor that is a measurement target of a method for measuring DC bias aging characteristics of a multilayer capacitor according to an embodiment of the present invention; [Figure 4] FIG. 2 is an exploded perspective view showing a laminated structure of an internal electrode. [Diagram 5] 4 is a cross-sectional view taken along line II' of FIG. 3 and a partially enlarged view. [Figure 6] 1 is a diagram illustrating a change in a domain wall due to aging of a multilayer capacitor. [Figure 7] 1 is a graph showing the temperature-dependent voltage-current characteristics of a multilayer capacitor; [Figure 8a] 1 is a graph showing a change in capacitance due to aging when no DC bias voltage is applied to a multilayer capacitor. [Figure 8b] 1 is a graph showing a change in capacitance due to aging when a DC bias voltage is applied to a multilayer capacitor. [Figure 9a] 1 is a TEM photograph showing the fine structure of a domain wall of a multilayer capacitor depending on temperature. [Figure 9b] 1 is a TEM photograph showing the fine structure of a domain wall of a multilayer capacitor depending on temperature. [Figure 9c] 1 is a TEM photograph showing the fine structure of a domain wall depending on the temperature of a multilayer capacitor. [Figure 9d] 1 is a TEM photograph showing the fine structure of a domain wall depending on the temperature of a multilayer capacitor. [Figure 9e] 1 is a TEM photograph showing the fine structure of a domain wall depending on the temperature of a multilayer capacitor. [Figure 10] 1 is a graph showing the change in capacitance due to aging at different temperatures when a DC bias voltage is applied to a multilayer capacitor. [Figure 11] 1 is a graph showing the capacitance when a poling voltage of 30 V to 70 V is applied to a multilayer capacitor at 25° C., and the capacitance when a DC bias voltage of 3.3 V is applied. [Figure 12] 1 is a graph showing a change in saturated capacitance of a multilayer capacitor due to poling voltage, the change being fitted with an exponential decay function. [Figure 13a] 1 is a graph showing the capacitance when a poling voltage of 30 V to 70 V is applied to a multilayer capacitor under various temperature conditions and the capacitance when a DC bias voltage of 3.3 V is applied. [Figure 13b] 1 is a graph showing the capacitance when a poling voltage of 30 V to 70 V is applied to a multilayer capacitor under various temperature conditions and the capacitance when a DC bias voltage of 3.3 V is applied. [Figure 13c]1 is a graph showing the capacitance when a poling voltage of 30 V to 70 V is applied to a multilayer capacitor under various temperature conditions and the capacitance when a DC bias voltage of 3.3 V is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those having average knowledge in the art. Therefore, the shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0015] In addition, in the drawings, in order to clearly explain the present invention, parts that are not relevant to the explanation are omitted, thicknesses are enlarged to clearly express multiple layers and regions, and components that have the same function within the same concept may be described using the same reference symbols.

[0016] Throughout the specification, when a part "comprises" an element, it means that it can further include other elements, not excluding other elements, unless specifically stated to the contrary.

[0017] In order to clearly explain the embodiments of the present invention, the directions of the hexahedron are defined as follows: the first to third directions shown in the drawings indicate the thickness direction, the length direction, and the width direction, respectively. Here, the thickness direction can be used in the same concept as the stacking direction (or the first direction) in which the dielectric layers are stacked.

[0018] Hereinafter, a multilayer capacitor according to an embodiment of the present invention will be described, particularly, as a multilayer ceramic capacitor (MLCC), but the present invention is not limited thereto.

[0019] Measurement method for DC bias aging characteristics of multilayer capacitors In this specification, the DC bias aging characteristic of the multilayer capacitor is one of the reliability assurance indexes of the multilayer capacitor 100, and means the minimum capacitance value after the multilayer capacitor 100 is used for a long period of time (e.g., 10 years or more) under operating conditions in which a specific DC bias voltage is applied at various temperatures.

[0020] Conventionally, in order to measure the DC bias aging characteristics of the above-mentioned multilayer capacitor, a DC bias voltage was applied to the multilayer capacitor for a considerable period of time (e.g., 100 hours to 3000 hours) and the capacitance that finally saturated was measured. However, in the present embodiment, the DC bias aging characteristics of the above-mentioned multilayer capacitor can be measured in a short period of time with high accuracy close to that of existing measurements.

[0021] Hereinafter, a system used in the method for measuring the DC bias aging characteristics of the multilayer capacitor according to this embodiment and the measurement method will be specifically described.

[0022] FIG. 1 is a diagram showing a system for performing a method for measuring DC bias aging characteristics of a multilayer capacitor according to an embodiment of the present invention.

[0023] Referring to FIG. 1, a system for performing a method for measuring DC bias aging characteristics of a multilayer capacitor according to the present embodiment includes a temperature control unit 10 that houses a multilayer capacitor 100 to be measured, a power supply unit 20 that provides power to the system, a measurement unit 30 that measures the capacitance of the multilayer capacitor 100, and at least a portion of a bias tee 40 that applies a DC voltage to the multilayer capacitor 100 based on the power provided by the power supply unit 20 but is isolated in circuit to prevent interference with the measurement by the measurement unit 30.

[0024] The temperature control unit 10 may be configured to control the temperature of the internal space in which the multilayer capacitor 100 is accommodated so that the temperature is always within a predetermined temperature range. The temperature may be equal to or lower than the Curie temperature of the dielectric layer of the multilayer capacitor 100.

[0025] The power supply unit 20 may include a DC power supply. Alternatively, the power supply unit 20 may include a converter for converting an AC voltage to a DC voltage or changing the DC voltage. For example, the DC voltage applied to the stacked capacitor 100 may be changed by the power supply unit 20.

[0026] The bias T 40 can control the applied DC voltage so that the DC voltage applied between the first and second external electrodes of the multilayer capacitor 100 is maintained at the same level as a target DC voltage.

[0027] For example, the measuring unit 30 may apply an AC signal to the stacked capacitor 100 for capacitance measurement, and the bias Tee 40 may be configured to prevent interference between the AC signal and the DC voltage, so that the DC voltage application and the capacitance measurement may be performed simultaneously. For example, a DC blocking capacitor may be connected in series between the bias Tee 40 and the measuring unit 30, and the bias Tee 40 may include a low-pass filter, a high-pass filter, or a switch.

[0028] The control unit 50 can control each of the temperature control unit 10, the power supply unit 20, and the measurement unit 30, and can record the measured data. In addition, the control unit 50 can calculate a predicted value for the saturated capacitance of the multilayer capacitor 100 based on the recorded data, but is not limited thereto.

[0029] FIG. 2 is a flowchart showing a method for measuring DC bias aging characteristics of a multilayer capacitor according to an embodiment of the present invention.

[0030] Referring to FIG. 2, first, the stacked capacitor 100 to be measured according to this embodiment is placed in a temperature control unit 10 (S110), and the inside of the temperature control unit 10 can be maintained at a specific temperature (S120).

[0031] Here, the temperature of the temperature control unit 10 may be a temperature equal to or lower than the Curie temperature Tc of the dielectric layer 111 of the multilayer capacitor 100 to be measured. For example, the temperature of the temperature control unit 10 in this embodiment may be lower than 180° C., and may be a specific temperature preferably within a range of 25° C. to 125° C., but is not limited thereto.

[0032] Next, a poling voltage may be applied to the multilayer capacitor 100 using the power supply unit 20 and the bias Tee 40 (S210).

[0033] Here, the poling voltage is a voltage that can polarize the dielectric of the multilayer capacitor 100, and can correspond to a voltage of a magnitude that can align the domains in one direction and expand the domain walls DW.

[0034] Meanwhile, the poling voltage may be a voltage lower than the breakdown voltage. For example, the poling voltage may be a voltage equal to or lower than 70% of the breakdown voltage of the multilayer capacitor 100 to be measured, and may be 30V or more and 70V or less, but is not limited thereto.

[0035] Next, the poling voltage applied to the stacked capacitor 100 may be maintained for a first time t1 (S220).

[0036] The first time t1 may correspond to a time sufficient for polarization to occur in the dielectric layer 111 of the multilayer capacitor 100, and may correspond to a time of 1 minute or more. However, a longer first time t1 may be advantageous in terms of accuracy of measuring the DC bias aging characteristics of the multilayer capacitor, and the first time t1 may be preferably 20 minutes, but is not limited thereto.

[0037] Next, a DC bias voltage can be applied to the multilayer capacitor 100 using the power supply unit 20 and the bias Tee 40 (S230).

[0038] The DC bias voltage applied to the stacked capacitor 100 is a voltage of a level similar to the DC bias voltage applied when the stacked capacitor 100 is surface-mounted on a PCB board for actual use, and may be a voltage lower than the first poling voltage.

[0039] By way of example, and not limitation, the DC bias voltage can be 1.8V or 3.3V.

[0040] Next, the DC bias voltage applied to the stacked capacitor 100 may be maintained for a second time t2 (S240).

[0041] The second time t2 may correspond to a time sufficient for depoling to occur in the dielectric layer 111 of the multilayer capacitor 100, and may correspond to a time of 1 minute or more. However, a longer second time t2 may be advantageous in terms of accuracy of measuring the DC bias aging characteristics of the multilayer capacitor, and the second time t2 may be preferably 20 minutes, but is not limited thereto.

[0042] Next, the saturated capacitance of the multilayer capacitor 100 to be measured can be measured using the measuring unit 30 and the control unit 50 (S250).

[0043] In the method for measuring the DC bias aging characteristics of a multilayer capacitor according to the present embodiment, since the step of applying a poling voltage precedes the step of applying a poling voltage, it is possible to measure the saturated capacitance in a much faster time than when the capacitance is measured by immediately applying a DC bias voltage.

[0044] Next, the changed poling voltage can be applied to the multilayer capacitor 100 using the control unit 50, the power supply unit 20, and the bias Tee 40 (S310).

[0045] For example, when the poling voltage initially applied to the stacked capacitor 100 is the first poling voltage, and the poling voltage applied again after step S310 is the second poling voltage, the first poling voltage and the second poling voltage may have a voltage difference of 10V.

[0046] Also, the first poling voltage and the second poling voltage may be selected from the range of 30V to 70V, but are not limited thereto.

[0047] The above steps can be repeated to obtain multiple saturation capacitance measurements for different poling voltages.

[0048] Next, the saturated capacitance of the stacked capacitor after DC bias aging can be predicted using a comparative analysis of multiple saturated capacitance measurements for various poling voltages and an exponential decay function (S410).

[0049] Detailed experimental data and error results will be described later.

[0050] The multilayer capacitor to be measured in this embodiment FIG. 3 is a schematic perspective view of a multilayer capacitor that is a measurement target of a method for measuring DC bias aging characteristics of a multilayer capacitor according to an embodiment of the present invention, FIG. 4 is an exploded perspective view showing a laminated structure of an internal electrode, and FIG. 5 is a cross-sectional view taken along line II' in FIG. 3 and a partially enlarged view.

[0051] 3 to 5, the multilayer capacitor 100 to be measured in this embodiment includes a body 110 including a dielectric layer 111 including a plurality of dielectric crystal grains G and internal electrodes 131, 132 arranged alternately with the dielectric layer 111 in a first direction, and external electrodes 131, 132 arranged on the body 110.

[0052] The body 110 has dielectric layers 111 and internal electrodes 121 and 122 laminated alternately.

[0053] The body 110 may include a capacitance forming portion that is disposed inside the body 110 and includes first internal electrodes 121 and second internal electrodes 122 that are alternately arranged to face each other with the dielectric layer 111 in between, forming a capacitance.

[0054] The multiple dielectric layers 111 forming the body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to see without using a scanning electron microscope (SEM).

[0055] Meanwhile, referring to the enlarged view of FIG. 5, the dielectric layer 111 may include dielectric crystal grains G therein, and polarizations in different directions are formed within the dielectric crystal grains G, and domain walls DW, which are the boundaries between the dielectric crystal grains, may be observed.

[0056] The method for measuring the DC bias aging characteristics of the multilayer capacitor according to this embodiment utilizes the change in polarization and domain walls caused by application of a poling voltage.

[0057] Specifically, the domain wall DW in the dielectric layer 111 can be expanded through a step of applying a poling voltage to the multilayer capacitor 100 of the present embodiment. Thereafter, the domain wall DW in the dielectric layer 111 can be contracted to the previous size through a step of applying a DC bias voltage lower than the poling voltage to the multilayer capacitor 100 of the present embodiment.

[0058] The raw material for forming the dielectric layer 111 is not limited as long as sufficient capacitance can be obtained. Generally, perovskite (ABO3)-based materials can be used. In the chemical formula ABO3, A can include any one of barium (Ba), strontium (Sr), and calcium (Ca), and B can include any one of titanium (Ti) and zirconium (Zr), but is not limited thereto.

[0059] As an example, as the material for forming the dielectric layer 111, a barium titanate-based material, a lead composite perovskite-based material, a strontium titanate-based material, or the like can be used. The barium titanate-based material can include BaTiO3-based ceramic powder. Examples of the ceramic powder include BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), or Ba(Ti 1-y Zr y )O3 (0 < y < 1), and the like.

[0060] In addition, various ceramic additives, organic solvents, binders, dispersants, etc. can be added to the powder such as barium titanate (BaTiO3) according to the purpose of the present invention as the raw material for forming the dielectric layer 111.

[0061] 2 and 3, the internal electrodes 121 and 122 may be laminated alternately with the dielectric layers 111.

[0062] The internal electrodes 121, 122 may include a first internal electrode 121 and a second internal electrode 122, and the first and second internal electrodes 121, 122 are alternately arranged to face each other across the dielectric layer 111 constituting the body 110, and may be exposed to the third and fourth surfaces 3, 4 of the body 110, respectively.

[0063] The first internal electrode 121 may be connected to the first external electrode 131 without being connected to the second external electrode 132, and the second internal electrode 122 may be connected to the second external electrode 132 without being connected to the first external electrode 131. In this case, the first and second internal electrodes 121 and 122 may be electrically isolated from each other by a dielectric layer 111 disposed therebetween.

[0064] Meanwhile, the body 110 may be formed by alternately stacking ceramic green sheets on which the first internal electrodes 121 are printed and ceramic green sheets on which the second internal electrodes 122 are printed, and then firing the stacked ceramic green sheets.

[0065] There are no particular limitations on the material forming the internal electrodes 121 and 122, and any material having excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0066] On the other hand, the capacitance of the multilayer capacitor 100 is proportional to the overlap area in the stacking direction (first direction) between the first and second internal electrodes 121, 122, proportional to the total number of stacks of the first and second internal electrodes 121, 122, and inversely proportional to the distance between the first and second internal electrodes 121, 122.

[0067] The multilayer capacitor 100 may have a larger capacitance relative to the thickness as the distance between the first and second internal electrodes 121, 122 is shorter. Meanwhile, the withstand voltage of the multilayer capacitor 100 may be higher as the distance between the first and second internal electrodes 121, 122 is longer. Therefore, the internal electrode distance may be adjusted according to the required specifications of the multilayer capacitor 100 (e.g., a capacitor for electronic devices may require small size and / or high capacity, or a capacitor for electric devices may require high withstand voltage characteristics and / or high strength, etc.).

[0068] The body 110 may include cover portions 112, 113 disposed on both end-surfaces in a first direction of the capacitance forming portion.

[0069] More specifically, it may include an upper cover part 112 disposed at an upper part in the first direction of the capacitance forming part and a lower cover part 113 disposed at a lower part in the first direction of the capacitance forming part.

[0070] The upper cover part 112 and the lower cover part 113 may be formed by stacking a single dielectric layer 111 or two or more dielectric layers 111 in a first direction on the upper and lower surfaces of the capacitance forming part, respectively, and may basically serve to prevent damage to the internal electrodes 121, 122 due to physical or chemical stress.

[0071] The upper cover part 112 and the lower cover part 113 do not include the internal electrodes 121, 122 and may include the same material as the dielectric layer 111. That is, the upper cover part 112 and the lower cover part 113 may include a ceramic material, for example, a barium titanate (BaTiO3)-based ceramic material.

[0072] The outer electrodes 131 and 132 may be disposed on the body 110 and connected to the inner electrodes 121 and 122 .

[0073] More specifically, the external electrodes 131, 132 may include first and second external electrodes 131, 132 disposed on the third and fourth surfaces 3, 4 of the body 110, respectively, and connected to the first and second internal electrodes 121, 122, respectively. That is, the first external electrode 131 may be disposed on the third surface 3 of the body and connected to the first internal electrode 121, and the second external electrode 132 may be disposed on the fourth surface 4 of the body and connected to the second internal electrode 122.

[0074] The external electrodes 131, 132 may be formed using any material that has electrical conductivity, such as a metal, and the specific material may be determined taking into consideration electrical characteristics, structural stability, etc., and may further have a multi-layer structure.

[0075] For example, the external electrodes 131, 132 may include electrode layers 131a, 132a disposed on the body 110 and plating layers 131b, 132b disposed on the electrode layers 131a, 132a.

[0076] As a more specific example of the electrode layers 131a and 132a, the electrode layers 131a and 132a may be fired electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0077] Also, the electrode layers 131a and 132a may be in a form in which a fired electrode and a resin-based electrode are sequentially formed on the body 110.

[0078] In addition, the electrode layers 131a and 132a may be formed by transferring a sheet containing a conductive metal onto the body 110, or may be formed by transferring a sheet containing a conductive metal onto a fired electrode.

[0079] The conductive metal used for the electrode layers 131a and 132a is not particularly limited as long as it can be electrically connected to the internal electrodes 121 and 122 to form capacitance, and may include, for example, at least one selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. The electrode layers 131a and 132a may be formed by applying a conductive paste prepared by adding glass frit to the conductive metal powder, and then firing the paste.

[0080] Measurement principle and experimental results of DC bias aging characteristics of multilayer capacitors FIG. 6 is a diagram showing a schematic diagram of a change in a domain wall due to aging of a multilayer capacitor.

[0081] Referring to FIG. 6, the dielectric crystal grains G of the multilayer capacitor 100 form domain walls DW due to spontaneous polarization. After a long time at a temperature below the Curie temperature Tc of the dielectric layer 111, the 180° domain walls DW are rearranged into a more stable 90° domain wall DW′, and the capacitance of the multilayer capacitor 100 may decrease due to a decrease in the dielectric constant.

[0082] In this embodiment, the purpose is to accurately predict the saturation capacitance of the multilayer capacitor 100, which decreases after long-term aging, and to utilize it as a guarantee index. The principle is utilized in that a poling voltage higher than the DC bias voltage in the actual usage environment of the multilayer capacitor 100 is applied for a certain period of time in advance to expand the domain wall DW, and then when the DC bias voltage is applied again, the domain wall DW contracts and the saturation capacitance can be reached quickly.

[0083] FIG. 7 is a graph showing the temperature-dependent voltage-current characteristics of the multilayer capacitor.

[0084] Referring to FIG. 7, when a DC voltage is applied to a multilayer capacitor at a specific temperature, in addition to the aging characteristics, variables such as mechanical defects, IR degradation, and oxygen void generation occur under high voltage or high temperature. Therefore, in the method for measuring the DC bias aging characteristics of the multilayer capacitor according to the present embodiment, the poling voltage and temperature range are appropriately controlled to focus on the aging characteristics.

[0085] As an example, the poling voltage applied to the multilayer capacitor 100 was set to a DC voltage of less than 100V, and the temperature was controlled to less than 180°C.

[0086] FIG. 8a is a graph showing the change in capacitance due to aging when no DC bias voltage is applied to the multilayer capacitor.

[0087] Referring to FIG. 8a, when no DC bias voltage is applied to the stacked capacitor, the capacitance can be described as an exponential decay function having the following equation:

number

[0088] Here, when measuring the aging rate k, the capacitance value at a specific time, typically 1000 to 2000 hours or less, can be used.

[0089] FIG. 8b is a graph showing the change in capacitance due to aging when a DC bias voltage is applied to the multilayer capacitor.

[0090] Comparing FIG. 8b with FIG. 8a, as a DC bias voltage of 3.3V is applied to stacked capacitor 100, the capacitance deviates from the exponential decay and at some point becomes saturated.

[0091] This is presumably because the domain walls DW in the dielectric crystal grains G of the multilayer capacitor 100 continue to bond with each other due to the application of a DC electric field or high temperature.

[0092] However, even if the time to capacitance saturation is shortened by applying a DC bias voltage or high temperature, it may still take more than 1000 hours. Therefore, in order to predict the saturated capacitance within a short period of time, it is necessary to observe the changes in the aging characteristics related to the DC bias voltage and temperature.

[0093] 9a to 9e are TEM photographs showing the microstructure of the domain wall depending on the temperature of the multilayer capacitor.

[0094] 9a to 9e, the domain walls have shapes similar to those indicated by the arrows in FIGS. 9a to 9c, but at temperatures above 100° C., the number of domain walls is reduced.

[0095] The above phenomenon is related to a phase transition of the barium titanate (BaTiO3) crystal structure contained in the dielectric layer from a tetrahedral to a cubic structure. In the case of the BaTiO3-based perovskite oxide, which is the material contained in the dielectric layer 111 of the stacked capacitor 100 of this embodiment, some domain walls were observed even at 180°C.

[0096] FIG. 10 is a graph showing the change in capacitance due to aging at different temperatures when a DC bias voltage is applied to a multilayer capacitor.

[0097] Referring to FIG. 10, the DC bias aging characteristics of the multilayer capacitor were measured under various temperature conditions from 25° C. to 180° C.

[0098] The time until the capacitance was saturated was measured for each temperature. Since the capacitance saturation characteristic at 180° C. was different from that at other temperatures lower than 180° C., the DC bias aging characteristics of the multilayer capacitor according to the present embodiment were measured at temperatures lower than 180° C., except for 180° C.

[0099] FIG. 11 is a graph showing the capacitance when a poling voltage of 30 V to 70 V is applied to a multilayer capacitor at 25° C., and the capacitance when a DC bias voltage of 3.3 V is applied.

[0100] Referring to FIG. 11, when a poling voltage was applied to the multilayer capacitor 100, the capacitance had a small value of less than 1 μF, and it could be observed that when the poling voltage was maintained for 20 minutes and then a DC bias voltage of 3.3 V was immediately applied, the capacitance was rapidly saturated.

[0101] The experiment was carried out at 25° C., and the capacitance of the multilayer capacitor 100 to be measured when a poling voltage of 30 V to 70 V was applied was rapidly aged within a short period of time without IR degradation.

[0102] Thereafter, the voltage was reduced and a 3.3 V DC bias voltage was applied to measure the capacitance after depolarization, and it was observed that the capacitance rapidly reached a saturated state within about 1000 seconds.

[0103] FIG. 12 is a graph showing the change in saturated capacitance of a multilayer capacitor due to poling voltage, fitted with an exponential decay function.

[0104] Referring to Fig. 12, Fig. 12 shows the saturated capacitance measured value according to the poling voltage at 25°C, which is obtained by fitting the measured values ​​in Fig. 11 with an exponential decay function. It can be seen from the graph that the saturated capacitance decreases as the poling voltage increases, and the DC bias aging characteristics of the multilayer capacitor can be measured by predicting the saturated capacitance by exponential decay function fitting.

[0105] For example, immediately after applying a DC bias voltage of 3.3 V to a stacked capacitor having a capacitance of 9.19 μF, the capacitance was 5.66 μF, and after applying a DC bias voltage of 3.3 V for 100 hours, the capacitance was 3.58 μF.

[0106] In comparison, after applying a poling voltage of 40 V for 20 minutes using the method for measuring the DC bias aging characteristics of the multilayer capacitor according to this embodiment, the capacitance saturated at 3.50 μF within 1000 seconds when a DC bias voltage of 3.3 V was applied, which corresponds to an error rate of 2.23% compared to the comparative example.

[0107] Therefore, compared to the capacitance measured after applying a DC bias voltage for 100 hours as in the above comparative example, it is possible to measure the saturated capacitance with high accuracy within a short time of less than one hour.

[0108] 13a to 13c are graphs showing the capacitance when a poling voltage of 30V to 70V is applied to a multilayer capacitor under various temperature conditions and the capacitance when a DC bias voltage of 3.3V is applied.

[0109] 13a to 13c, it was observed that the capacitance of the multilayer capacitor was saturated more quickly as the temperature increased from 25° C. to 75° C. to 125° C. This can be explained as a phenomenon in which depolarization caused by application of a DC bias voltage progresses more rapidly as the temperature increases.

[0110] Although one embodiment of the present invention has been described above, a person having ordinary knowledge in the art may modify and change the present invention in various ways by adding, changing or deleting components, without departing from the concept of the present invention described in the claims, and this also falls within the scope of the present invention. [Explanation of symbols]

[0111] 10 Temperature control section 20 Power supply section 30 Measuring part 40 Bias Tee 50 Control section 100 Stacked Capacitor 110 Main unit 111 Dielectric layer G Dielectric grains DW, DW' domain wall 112, 113 Cover part 121, 122 Internal electrode 131, 132 External electrode

Claims

1. applying a first poling voltage to a multilayer capacitor including a body including a dielectric layer including a plurality of dielectric crystal grains, internal electrodes alternately arranged with the dielectric layer in a first direction, and external electrodes arranged on the body; maintaining the first poling voltage for a first time t1; applying a DC bias voltage lower than the first poling voltage to the stacked capacitor; maintaining the DC bias voltage for a second time t2; measuring a saturated capacitance of the multilayer capacitor.

2. applying a second poling voltage different from the first poling voltage to the stacked capacitor; maintaining the second poling voltage for the first time t1; applying the DC bias voltage to the stacked capacitor, the DC bias voltage being lower than the second poling voltage; maintaining the DC bias voltage for the second time t2; The method of claim 1 , further comprising: measuring a saturated capacitance of the multilayer capacitor.

3. 3. The method of claim 2, further comprising: predicting a saturated capacitance of the multilayer capacitor after DC bias aging using the measured capacitance and an exponential decay function.

4. 3. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 2, wherein the first poling voltage and the second poling voltage are each 30V or more and 70V or less.

5. 3. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 2, wherein the first poling voltage and the second poling voltage have a voltage difference of 10V.

6. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 1 , wherein the first poling voltage is lower than a dielectric breakdown voltage of the multilayer capacitor.

7. 7. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 6, wherein the first poling voltage is 70% or less of a dielectric breakdown voltage of the multilayer capacitor.

8. 2. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 1, wherein the DC bias voltage is 1.8V or 3.3V.

9. 2. The method of claim 1, wherein the first time t1 and the second time t2 are each 1 minute or longer.

10. 10. The method of claim 9, wherein the first time t1 is 20 minutes.

11. Before applying a first poling voltage to the stacked capacitor, preparing a temperature control unit; placing the stacked capacitor in the temperature control unit; 2. The method of claim 1, further comprising: maintaining an internal temperature of the temperature control unit at a specific temperature.

12. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 11, wherein the specific temperature is equal to or lower than a Curie temperature of the dielectric layer.

13. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 11, wherein the specific temperature is less than 180°C.

14. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 13, wherein the specific temperature is 25° C. or more and 125° C. or less.

15. 2. The method of claim 1, further comprising the step of applying a first poling voltage to the multilayer capacitor to expand domain walls in the dielectric layer.

16. 16. The method of measuring DC bias aging characteristics of a multilayer capacitor according to claim 15, further comprising the step of applying a DC bias voltage lower than the first poling voltage to shrink domain walls in the dielectric layer.

17. The dielectric layer has the chemical formula ABO ３ The method for measuring DC bias aging characteristics of the multilayer capacitor according to claim 1, comprising:

18. The chemical formula ABO ３ 18. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 17, wherein A includes any one of barium (Ba), strontium (Sr), and calcium (Ca).

19. The chemical formula ABO ３ 18. The method for measuring DC bias aging characteristics of a multilayer capacitor according to claim 17, wherein B includes one of titanium (Ti) and zirconium (Zr).

20. applying a first poling voltage to a multilayer capacitor including a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately stacked in a first direction with at least one dielectric layer sandwiched therebetween, and first and second external electrodes disposed on the body and spaced apart from each other so as to be connected to the at least one first internal electrode and the at least one second internal electrode, respectively; measuring a first capacitance of the stacked capacitor to which a DC bias voltage lower than the first poling voltage is applied after applying the first poling voltage; applying a second poling voltage different from the first poling voltage to the stacked capacitor; measuring a second capacitance of the stacked capacitor to which a DC bias voltage smaller than the second poling voltage is applied after applying the second poling voltage; measuring a DC bias aging characteristic of the multilayer capacitor based on the first and second poling voltages and the first and second capacitances.

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