Semiconductor device

Abstract

To provide a semiconductor device capable of increasing speed of switching between on and off of a high frequency switch.SOLUTION: A semiconductor device of an embodiment includes: transistors M1 and M2 for respectively supplying a voltage Vp and a voltage Vn to a first end; transistors M3 and M4 for respectively supplying a power supply voltage and a ground voltage to the first end; a level shifter LS1 for converting a signal EP and outputting a signal RGP; and a second level shifter LS2 for converting a signal EN and outputting a signal RGN. When outputting the voltage Vp from the first end, the semiconductor device supplies the power supply voltage from the transistor M3 to the first end according to the signal RGN, and then supplies the voltage Vp from the transistor M1 to the first end according to the signal RGP. When outputting the voltage Vn from the first end, the semiconductor device supplies the ground voltage from the transistor M4 to the first end according to the signal RGP, and then supplies the voltage Vn from the transistor M2 to the first end according to the signal RGN.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices including high frequency switches are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-46584 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of speeding up on-off switching of a high-frequency switch is provided. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a first transistor that is supplied with a first voltage higher than a power supply voltage and supplies the first voltage to a first end, a second transistor that is supplied with a second voltage lower than a ground voltage and supplies the second voltage to the first end, a third transistor that is supplied with the power supply voltage and supplies the power supply voltage to the first end, a fourth transistor that is supplied with the ground voltage and supplies the ground voltage to the first end, a first level shifter that converts the power supply voltage to the first voltage and outputs a second signal when a first signal is the power supply voltage, and a second level shifter that converts the ground voltage to the second voltage and outputs a fourth signal when a third signal is the ground voltage. When the first voltage is output from the first end, the power supply voltage is supplied to the first end from the third transistor in response to the fourth signal, and then the first voltage is supplied to the first end from the first transistor in response to the second signal; when the second voltage is output from the first end, the ground voltage is supplied to the first end from the fourth transistor in response to the second signal, and then the second voltage is supplied to the first end from the second transistor in response to the fourth signal. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing a configuration of a wireless device including a switch circuit according to a first embodiment; [Diagram 2] FIG. 2 is a circuit diagram showing a configuration of a switch circuit according to the first embodiment. [Diagram 3] 4 is a timing chart showing the operation of a switch control circuit in the switch circuit of the first embodiment. [Figure 4] 6 is a timing chart showing the operation of a switch control circuit in a switch circuit of a comparative example. [Diagram 5] FIG. 11 is a circuit diagram showing a configuration of a switch circuit according to a second embodiment. [Figure 6] FIG. 11 is a circuit diagram showing a configuration of a switch circuit according to a modified example of the second embodiment. [Figure 7] FIG. 13 is a circuit diagram showing a configuration of a switch circuit according to another modified example of the second embodiment. [Figure 8]FIG. 11 is a circuit diagram showing a configuration of a switch circuit according to a third embodiment. [Figure 9] FIG. 13 is a circuit diagram showing a configuration of a switch circuit according to a fourth embodiment. [Figure 10] FIG. 13 is a circuit diagram showing a configuration of a delay circuit included in a plurality of switch circuits according to a fifth embodiment. [Figure 11] FIG. 13 is a circuit diagram showing a configuration of a delay circuit included in a plurality of switch circuits according to a sixth embodiment. [Figure 12] 13 is a timing chart showing the operation of a switch control circuit in the switch circuit of the sixth embodiment. [Figure 13] FIG. 23 is a circuit diagram showing a configuration of a delay circuit included in a switch circuit according to a modified example of the sixth embodiment. [Figure 14] FIG. 23 is a circuit diagram showing a configuration of a switch element in a delay circuit according to a modified example of the sixth embodiment. [Figure 15] FIG. 13 is a circuit diagram showing a configuration of a switch circuit according to a seventh embodiment. [Figure 16] FIG. 13 is a circuit diagram showing a part of the operation of an on / off switching circuit in a switch circuit according to a seventh embodiment. [Figure 17] FIG. 13 is a circuit diagram showing a configuration of a switch circuit according to an eighth embodiment. [Figure 18] FIG. 13 is a circuit diagram showing a part of the operation of an on / off switching circuit in a switch circuit according to an eighth embodiment. [Figure 19] FIG. 13 is a circuit diagram showing a configuration of a switch circuit according to a ninth embodiment. [Figure 20] FIG. 13 is a circuit diagram showing a part of the operation of an on / off switching circuit in a switch circuit according to a ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same functions and configurations are given the same reference numerals. Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas of the embodiments, and do not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0008] The functional blocks can be realized as either hardware or computer software, or a combination of both. It is not essential that the functional blocks are differentiated as in the following example. For example, some functions may be performed by a functional block other than the illustrated functional block. Furthermore, the illustrated functional blocks may be further divided into smaller functional subblocks.

[0009] 1. First embodiment The following describes a semiconductor device according to a first embodiment. The semiconductor device includes a switch circuit 1.

[0010] 1.1 Configuration of the first embodiment 1.1.1 Radio equipment 1 is a block diagram showing the configuration of a wireless device WD including a switch circuit 1 according to the first embodiment. The wireless device WD is, for example, a smartphone, a feature phone, a mobile terminal (for example, a tablet terminal), a personal computer, a game device, a router, a base station, etc. The wireless device WD transmits and receives signals using communication standards such as LTE (registered trademark) (Long Term Evolution) and / or Wifi.

[0011] The wireless device WD includes, for example, an antenna ANT, switch circuits 1, 2, 3, and 4, signal processing circuits 5 and 6, a control circuit 7, and a power supply circuit 8. In the wireless device WD, for example, the switch circuits 1, 2, 3, and 4 and the power supply circuit 8 are mounted on one semiconductor substrate to configure a semiconductor device (or a semiconductor package, an IC chip). Note that, although Fig. 1 shows an example in which the power supply circuit 8 is provided outside the switch circuits 1, 2, 3, and 4, the power supply circuit 8 may be provided inside the switch circuits.

[0012] The antenna ANT receives high-frequency signals from other devices (eg, base stations or other wireless devices) and is also capable of transmitting high-frequency signals from the wireless device WD to other devices.

[0013] The control circuit 7 transmits control signals CNT (including CNT1, CNT2, CNT3, and CNT4) to, for example, the switch circuits 1, 2, 3, and 4 and to the signal processing circuits 5 and 6. Whether each of the switch circuits 1, 2, 3, and 4 is in an on state or an off state is controlled by the control signal CNT transmitted from the control circuit 7. While a certain switch circuit is in an on state, the switch circuit is capable of transmitting a signal between the first terminal and the second terminal of the switch circuit. On the other hand, while a certain switch circuit is in an off state, the switch circuit does not transmit a signal between the first terminal and the second terminal of the switch circuit. Each of the signal processing circuits 5 and 6 processes a signal based on the control signal CNT received from the control circuit 7.

[0014] A first terminal of the switch circuit 1 is connected to the antenna ANT, and a second terminal of the switch circuit 1 is connected to the signal processing circuit 5. The switch circuit 1 receives a control signal CNT1 from the control circuit 7. While the switch circuit 1 is set to an on state based on the control signal CNT1, the switch circuit 1 transmits, for example, a high-frequency signal received via the antenna ANT to the signal processing circuit 5.

[0015] A first terminal of the switch circuit 2 is connected to a signal path between the switch circuit 1 and the signal processing circuit 5. A second terminal of the switch circuit 2 is connected to, for example, a node to which a ground voltage GND is supplied (hereinafter, a ground voltage GND node). That is, the second terminal of the switch circuit 2 is grounded.

[0016] The switch circuit 2 receives a control signal CNT2 from the control circuit 7. For example, while the switch circuit 1 is set to an off state, the switch circuit 2 is set to an on state based on the control signal CNT2. While set to an on state, the switch circuit 2 sets the potential of the signal path between the switch circuit 1 and the signal processing circuit 5 to the ground voltage.

[0017] The signal processing circuit 5 receives the high-frequency signal transmitted via the switch circuit 1, and executes various processes on the high-frequency signal based on a control signal CNT3 received from the control circuit .

[0018] A first end of the switch circuit 3 is connected to the antenna ANT, and a second end of the switch circuit 3 is connected to the signal processing circuit 6. The switch circuit 3 receives, for example, a control signal CNT2 from the control circuit 7. While the switch circuit 3 is set to an on state based on the control signal CNT2, the switch circuit 3 transmits, for example, a high-frequency signal received via the antenna ANT to the signal processing circuit 6. The frequency band of the high-frequency signal transmitted by the switch circuit 3 is different from, for example, the frequency band of the high-frequency signal transmitted by the switch circuit 1. The switch circuit 1 and the switch circuit 3 are selectively set to an on state under the control of, for example, the control circuit 7.

[0019] A first end of the switch circuit 4 is connected to a signal path between the switch circuit 3 and the signal processing circuit 6. A second end of the switch circuit 4 is, for example, grounded. The switch circuit 4 receives, for example, a control signal CNT1 from the control circuit 7. For example, the switch circuit 4 is in an on state based on the control signal CNT1 while the switch circuit 3 is in an off state. While in the on state, the switch circuit 4 sets the potential of the signal path between the switch circuit 3 and the signal processing circuit 6 to the ground potential.

[0020] The signal processing circuit 6 receives the high-frequency signal transmitted via the switch circuit 3, and executes various processes on the high-frequency signal based on a control signal CNT4 received from the control circuit .

[0021] The power supply circuit 8 is provided in a semiconductor device including the switch circuit 1, and generates a high voltage Vp and a low voltage Vn using a power supply voltage VDD and a ground voltage GND supplied from outside the semiconductor device. As described above, the power supply circuit 8 may be provided inside the switch circuit 1 or outside the switch circuit 1. The power supply circuit 8 includes, for example, a charge pump. The high voltage Vp is, for example, about 3V to 5V, and is assumed to be 3.5V here. The low voltage Vn is, for example, -4V to -2V, and is assumed to be -3.5V here.

[0022] In the above description, the switch circuits 1 and 3 each transmit a high-frequency signal that the wireless device WD receives from another device. The switch circuits 1 and 3 are not limited to this. Either of the switch circuits 1 and 3 may transmit a high-frequency signal that the wireless device WD transmits to another device.

[0023] 1.1.2 Switch circuits Next, a description will be given of the switch circuit 1 of the first embodiment. Fig. 2 is a circuit diagram showing the configuration of the switch circuit of the first embodiment.

[0024] The switch circuit 1 includes a switch control circuit 10 and a high-frequency switch 20. The switch control circuit 10 controls the high-frequency switch 20 to switch from an on state to an off state or from an off state to an on state. Switching from an on state to an off state and from an off state to an on state is also referred to as on / off switching.

[0025] The high-frequency switch 20 is, for example, a switch that switches the path of a high-frequency signal. The on state of the high-frequency switch 20 is a state in which all switch transistors connected between the first end and the second end are on, and the first end and the second end are electrically connected. The off state of the high-frequency switch 20 is a state in which any of the switch transistors is off, and the first end and the second end are electrically disconnected. Details of the high-frequency switch 20 will be described later.

[0026] The following describes the switch control circuit 10. The switch control circuit 10 includes an on / off switching circuit 11 and a delay circuit 12.

[0027] The on / off switching circuit 11 outputs a switch signal SWG from a terminal TSW for setting the high frequency switch 20 to an on state or an off state. The on / off switching circuit 11 receives a control signal CNT from the control circuit 7. The on / off switching circuit 11 outputs a voltage Vp or a voltage Vn as the switch signal SWG based on the control signal CNT. When the voltage Vp is output as the switch signal SWG, the high frequency switch 20 is set to an on state. On the other hand, when the voltage Vn is output as the switch signal SWG, the high frequency switch 20 is set to an off state.

[0028] The delay circuit 12 generates signals EN and EP from the control signal CNT. The signal EN is a signal whose rising edge from "L" level to "H" level occurs at the same time as the control signal CNT, and whose falling edge from "H" level to "L" level is delayed. The signal EP is a signal whose rising edge from "L" level to "H" level is delayed as compared to the control signal CNT, and whose falling edge from "H" level to "L" level occurs at the same time.

[0029] The circuit configuration and connections of the circuit elements in the switch control circuit 10 will be described below.

[0030] The on / off switching circuit 11 includes p-channel MOS field effect transistors (hereinafter referred to as pMOS transistors) M1, M4, M5, M7, M9, M11, M13, and M15, n-channel MOS field effect transistors (hereinafter referred to as nMOS transistors) M2, M3, M6, M8, M10, M12, M14, and M16, buffers B1, B2, B3, and B4, and diodes D1 and D2.

[0031] A signal EP is input to the input terminal of a buffer B1. The output terminal of the buffer B1 is connected to the input terminal of a buffer B2. The output terminal of the buffer B2 is connected to the gates of a pMOS transistor M5 and an nMOS transistor M6.

[0032] A first power supply end of the buffer B1 is connected to a node to which a power supply voltage VDD is supplied (hereinafter referred to as a power supply voltage VDD node). The power supply voltage VDD node is supplied with a power supply voltage VDD from outside the semiconductor device. A second power supply end of the buffer B1 is connected to a ground voltage GND node. The ground voltage GND node is supplied with a ground voltage GND from outside the semiconductor device. When the signal EP is at an "H" level, the buffer B1 outputs the power supply voltage VDD as an "H" level, and when the signal EP is at an "L" level, the buffer B1 outputs the ground voltage GND as an "L" level.

[0033] A first power supply terminal of buffer B2 is connected to a node to which voltage Vp is supplied (hereinafter referred to as voltage Vp node). Voltage Vp is supplied to the voltage Vp node from a power supply circuit 8. A second power supply terminal of buffer B2 is connected to a ground voltage GND node. When the output of buffer B1 is the power supply voltage VDD, buffer B2 outputs voltage Vp as an "H" level, and when the output of buffer B1 is the ground voltage GND, buffer B2 outputs the ground voltage GND as an "L" level. Buffers B1 and B2 constitute a level shifter LS1.

[0034] The drains of the pMOS transistor M5 and the nMOS transistor M6 are connected to the gates of the pMOS transistor M7 and the nMOS transistor M8. The drains of the pMOS transistor M7 and the nMOS transistor M8 are connected to the source of the pMOS transistor M1 and the gate of the pMOS transistor M4. A signal RGP corresponding to the signal EP is output from the drains of the pMOS transistor M7 and the nMOS transistor M8.

[0035] The sources of the pMOS transistors M5 and M7 are connected to the voltage Vp node, and the sources of the nMOS transistors M6 and M8 are connected to the ground voltage GND node.

[0036] The drain of the pMOS transistor M1 is connected to the drain of the nMOS transistor M2 and the terminal TSW The gates of the pMOS transistors M1 and M2 are connected to the ground voltage GND node.

[0037] The drain of the nMOS transistor M3 is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the power supply voltage VDD node. The drain of the pMOS transistor M4 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to the ground voltage GND node. The sources of the nMOS transistor M3 and the pMOS transistor M4 are connected to the terminal TSW. A switch signal SWG is output from the terminal TSW.

[0038] A signal EN is input to the input terminal of a buffer B3. The output terminal of the buffer B3 is connected to the input terminal of a buffer B4. The output terminal of the buffer B4 is connected to the gates of a pMOS transistor M9 and an nMOS transistor M10.

[0039] A first power supply terminal of the buffer B3 is connected to a power supply voltage VDD node. A second power supply terminal of the buffer B3 is connected to a ground voltage GND node. When the signal EN is at a high level, the buffer B3 outputs the power supply voltage VDD as a high level, and when the signal EN is at a low level, the buffer B3 outputs the ground voltage GND as a low level.

[0040] A first power supply terminal of buffer B4 is connected to a power supply voltage VDD node. A second power supply terminal of buffer B4 is connected to a node to which a voltage Vn is supplied (hereinafter referred to as a voltage Vn node). A voltage Vn is supplied to the voltage Vn node from a power supply circuit 8. When the output of buffer B3 is the power supply voltage VDD, buffer B4 outputs the power supply voltage VDD as an "H" level, and when the output of buffer B3 is the ground voltage GND, buffer B4 outputs voltage Vn as an "L" level. Buffers B3 and B4 constitute a level shifter LS2.

[0041] The drains of the pMOS transistor M9 and the nMOS transistor M10 are connected to the gates of the pMOS transistor M11 and the nMOS transistor M12. The drains of the pMOS transistor M11 and the nMOS transistor M12 are connected to the source of the nMOS transistor M2. The sources of the pMOS transistors M9 and M11 are connected to the ground voltage GND node. The sources of the nMOS transistors M10 and M12 are connected to the voltage Vn node.

[0042] The output terminal of the buffer B4 is also connected to the gates of the pMOS transistor M13 and the nMOS transistor M14. The drains of the pMOS transistor M13 and the nMOS transistor M14 are connected to the gates of the pMOS transistor M15 and the nMOS transistor M16. The drains of the pMOS transistor M15 and the nMOS transistor M16 are connected to the gate of the nMOS transistor M3. A signal RGN corresponding to the signal EN is output from the drains of the pMOS transistor M15 and the nMOS transistor M16.

[0043] The sources of the pMOS transistors M13 and M15 are connected to the power supply voltage VDD node, and the sources of the nMOS transistors M14 and M16 are connected to the voltage Vn node.

[0044] The delay circuit 12 includes buffers B5 and B6, a resistive element R, a capacitive element C, a logical AND circuit AD1, and a logical OR circuit OR1.

[0045] A control signal CNT is input to the input terminal of buffer B5. The output terminal of buffer B5 is connected to a first input terminal of AND circuit AD1, a first input terminal of OR circuit OR1, and an input terminal of buffer B6. A first power supply terminal of buffer B5 is connected to a power supply voltage VDD node. A second power supply terminal of buffer B5 is connected to a ground voltage GND node. Similarly, a first power supply terminal of buffer B6 is connected to a power supply voltage VDD node. A second power supply terminal of buffer B6 is connected to a ground voltage GND node.

[0046] An output terminal of the buffer B6 is connected to one terminal of a resistive element R. The other terminal of the resistive element R is connected to a first electrode of a capacitive element C, a second input terminal of the AND circuit AD1, and a second input terminal of the OR circuit OR1. A second electrode of the capacitive element C is connected to a ground voltage GND node. A signal EP is output from the output terminal of the AND circuit AD1, and a signal EN is output from the output terminal of the OR circuit OR1.

[0047] Next, the circuit configuration and connections of circuit elements in the high-frequency switch 20 will be described with reference to Fig. 2. In Fig. 2, a first end and a second end of the high-frequency switch 20 are shown as terminals T1 and T2, respectively.

[0048] The high-frequency switch 20 has nMOS transistors N1_1, N1_2, N1_3, ..., N1_(n-1), N1_n, and resistive elements R1_1, R1_2, R1_3, ..., R1_(n-1), R1_n, where n is an integer equal to or greater than 1. The high-frequency switch 20 has any number of transistors and resistive elements, and may be one or more.

[0049] In addition, in the circuit symbol of each transistor, one end of the transistor is shown as a drain and the other end as a source, but the drain and source can be interchanged depending on the relationship of the potentials of the one end and the other end. The resistance values ​​of the resistance elements R1_1 to R1_n are, for example, substantially the same. Below, a case where the resistance values ​​of these resistance elements R1_1 to R1_n are substantially the same will be described.

[0050] Between the terminal T1 and the terminal T2, the current paths of the nMOS transistors N1_1, N1_2, N1_3, ..., N1_n are connected in series. Specifically, it is as follows. The drain of the nMOS transistor N1_1 is connected to the terminal T1, and the drain of the nMOS transistor N1_2 is connected to the source of the nMOS transistor N1_1. The drain of the nMOS transistor N1_3 is connected to the source of the nMOS transistor N1_2, and the drain of the nMOS transistor N1_4 is connected to the source of the nMOS transistor N1_3. The same applies to the connection relationship of the nMOS transistors N1_4, N1_5, ..., N1_n, and the terminal T2 is connected to the source of the nMOS transistor N1_n.

[0051] A resistive element R1_1 is connected between the gate (or control end) of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. A resistive element R1_2 is connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. A resistive element R1_3 is connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. The same is true for the resistive elements R1_4, R1_5, ..., R1_n. Furthermore, one end of the resistive element R1_n is connected to the gate of the nMOS transistor N1_n, and the other end of the resistive element R1_n is connected to the terminal TSW.

[0052] 1.2 Operation of the First Embodiment Next, the operation of the switch circuit 1 of the first embodiment will be described.

[0053] FIG. 3 is a timing chart showing the operation of the switch control circuit 10 in the switch circuit 1 of the first embodiment.

[0054] When the high-frequency switch 20 is switched from the OFF state to the ON state, the switch signal SWG output from the terminal TSW of the switch control circuit 10 is set from voltage Vn to voltage Vp. Also, when the high-frequency switch 20 is switched from the ON state to the OFF state, the switch signal SWG output from the terminal TSW of the switch control circuit 10 is set from voltage Vp to voltage Vn.

[0055] In this embodiment, when the high frequency switch 20 is switched from the off state to the on state, a power supply voltage VDD (for example, 1.2 V) is supplied to the terminal TSW before a voltage Vp (for example, 3.5 V) is supplied to the terminal TSW. Then, when the voltage of the terminal TSW rises to about the power supply voltage VDD, the voltage Vp is supplied to the terminal TSW. In this way, when the switch signal SWG is raised from the voltage Vn to the voltage Vp, the power supply voltage VDD is first supplied to the terminal TSW to raise the switch signal SWG from the voltage Vn to the power supply voltage VDD, and then the voltage Vp is supplied to the terminal TSW to raise the switch signal SWG from the power supply voltage VDD to the voltage Vp. As a result, even if the driving force of the power supply circuit 8 that supplies the voltage Vp is insufficient, the switch signal SWG can be raised from the voltage Vn to the voltage Vp without lowering the voltage Vp when the voltage Vp is supplied. This prevents the transition of the switch signal SWG from the voltage Vn to the voltage Vp from being delayed due to a drop in the voltage Vp that occurs when the driving force of the power supply circuit 8 is insufficient. This shortens the time it takes for the switch signal SWG to transition from the voltage Vn to the voltage Vp.

[0056] Furthermore, when switching the high frequency switch 20 from an on state to an off state, a ground voltage GND (for example, 0V) is supplied to the terminal TSW before a voltage Vn (for example, -3.5V) is supplied to the terminal TSW. Then, when the voltage of the terminal TSW drops to about the ground voltage GND, the voltage Vn is supplied to the terminal TSW. In this way, when the switch signal SWG is lowered from the voltage Vp to the voltage Vn, the ground voltage GND is first supplied to the terminal TSW to lower the switch signal SWG from the voltage Vp to the ground voltage GND, and then the voltage Vn is supplied to the terminal TSW to lower the switch signal SWG from the ground voltage GND to the voltage Vn. As a result, even if the driving force of the power supply circuit 8 that supplies the voltage Vn is insufficient, the switch signal SWG can be lowered from the voltage Vp to the voltage Vn without increasing the voltage Vn when the voltage Vn is supplied. This prevents the transition of the switch signal SWG from the voltage Vp to the voltage Vn from being delayed due to an increase in the voltage Vn that occurs when the driving force of the power supply circuit 8 is insufficient. This shortens the time it takes for the switch signal SWG to transition from the voltage Vp to the voltage Vn.

[0057] The operations of the high-frequency switch 20 (1) when it is switched from the OFF state to the ON state, and (2) when it is switched from the ON state to the OFF state will be described in detail below.

[0058] (1) When switching from the off state to the on state First, at time t0, a voltage Vn (e.g., −3.5V) is output as a signal SWG from the terminal TSW of the switch control circuit 10. This sets the high-frequency switch 20 to an OFF state. At this time, the control signal CNT input to the delay circuit 12 in the switch control circuit 10 is “L” (e.g., 0V), and the signals EP and EN are also “L”. This sets the transistor M2 to an ON state, and the transistors M1, M3, and M4 to an OFF state.

[0059] Next, at time t1, the control signal CNT rises from "L" to "H" (for example, power supply voltage VDD). Then, the signal EN rises from "L" to "H", and the signal EP is maintained at "L". Therefore, the transistor M3 is set to an ON state, and the transistors M1, M2, and M4 are set to an OFF state. As a result, charge flows from the power supply voltage VDD node through the diode D1 and the transistor M3 to the terminal TSW, and the terminal TSW is charged. As a result, as shown in FIG. 3, the voltage of the signal SWG rises, and at time t2a, when it reaches a first voltage (for example, 0.7 V), the high-frequency switch 20 switches from an OFF state to an ON state.

[0060] Next, at time t2, the signal EP rises from "L" to "H", and the signal EN remains at "H". As a result, the transistor M1 is set to the ON state, and the transistors M2, M3, and M4 are set to the OFF state. As a result, charge flows from the voltage Vp node through the transistor M1 to the terminal TSW, and the terminal TSW is further charged. As a result, as shown in FIG. 3, the voltage of the signal SWG further rises to the voltage Vp, and the high-frequency switch 20 is stably maintained in the ON state.

[0061] (2) When switching from the on state to the off state After that, at time t3, the control signal CNT falls from "H" to "L". Then, the signal EP falls from "H" to "L", and the signal EN is maintained at "H". Therefore, the transistor M4 is set to the ON state, and the transistors M1, M2, and M3 are set to the OFF state. As a result, the charge of the terminal TSW is released to the ground voltage GND node via the transistor M4 and the diode D2, and the terminal TSW is discharged. As a result, as shown in FIG. 3, the voltage of the signal SWG decreases, and when it reaches a certain second voltage at time t4a, the high-frequency switch 20 is switched from the ON state to the OFF state.

[0062] Next, at time t4, the signal EN falls from "H" to "L", and the signal EP remains at "L". As a result, the transistor M2 is set to the ON state, and the transistors M1, M3, and M4 are set to the OFF state. This causes the charge of the terminal TSW to be released to the voltage Vn node via the transistor M2, and the terminal TSW is further discharged. As a result, as shown in FIG. 3, the voltage of the signal SWG further decreases to the voltage Vn, and the high-frequency switch 20 is stably maintained in the OFF state.

[0063] As described above, when the high-frequency switch 20 is set to the on state, the transistor M1 is set to on and the transistor M2 is set to off, and the voltage Vp is output to the high-frequency switch 20 from the terminal TSW of the switch control circuit 10 as the switch signal SWG.

[0064] When the high-frequency switch 20 is switched from an off state to an on state, before the transistor M1 is set to on and the transistor M2 is set to off, the transistors M1 and M2 are set to off and the transistor M3 is set to on. During this period, the power supply voltage VDD is supplied from the power supply voltage VDD node to the terminal TSW. After that, the transistor M1 is set to on and the transistors M2, M3, and M4 are set to off. During this period, the voltage Vp is supplied from the voltage Vp node to the terminal TSW. This causes the signal SWG to transition from the voltage Vn to the voltage Vp at high speed. This allows the high-frequency switch 20 to be switched from the off state to the on state at high speed.

[0065] Furthermore, when the high-frequency switch 20 is set to the off state, the transistor M2 is set to the on state, the transistor M1 is set to the off state, and the voltage Vn is output from the terminal TSW of the switch control circuit 10 to the high-frequency switch 20 as the switch signal SWG.

[0066] When the high-frequency switch 20 is switched from the on state to the off state, the transistors M1 and M2 are set off and the transistor M4 is set on before the transistor M2 is set on and the transistor M1 is set off. During this period, a current is drawn from the terminal TSW to the ground voltage GND node. After that, the transistor M2 is set on and the transistors M1, M3, and M4 are set off. During this period, a current is drawn from the terminal TSW to the voltage Vn node. This causes the signal SWG to transition from the voltage Vp to the voltage Vn at high speed. This causes the high-frequency switch 20 to be switched from the on state to the off state at high speed.

[0067] In addition, a diode D1 is provided between the drain of the nMOS transistor M3 and the power supply voltage VDD node. When the high-frequency switch 20 is set to the on state, that is, when the signal SWG is at the voltage Vp, the diode D1 prevents a reverse current from flowing from the terminal TSW to the power supply voltage VDD node via the parasitic diode of the nMOS transistor M3.

[0068] Similarly, a diode D2 is provided between the drain of the pMOS transistor M4 and the ground voltage GND node. The diode D2 prevents a reverse current from flowing from the ground voltage GND node to the terminal TSW via the parasitic diode of the pMOS transistor M4 when the high-frequency switch 20 is set to the off state, that is, when the signal SWG is at the voltage Vn.

[0069] 1.3 Effects of the First Embodiment According to the first embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0070] A switch circuit of a comparative example will be described below with reference to FIG. 4, followed by a description of the effects of the first embodiment.

[0071] FIG. 4 is a timing chart showing the operation of the switch control circuit in the switch circuit of the comparative example.

[0072] In the comparative example, when the high frequency switch is switched from the off state to the on state, at time t11, the power supply circuit 8 supplies the voltage Vp to the terminal TSW. However, if the driving force of the power supply circuit 8 is insufficient, as shown in FIG. 4, the voltage Vp supplied from the power supply circuit 8 drops significantly. This slows down the rise of the signal SWG from the signal Vn to the signal Vp, and for example, at time t12, when the signal SWG rises to the first voltage, the high frequency switch switches from the off state to the on state. This slows down the switching of the high frequency switch from the off state to the on state.

[0073] Furthermore, when the high frequency switch is switched from the on state to the off state, at time t13, the power supply circuit 8 supplies the voltage Vn to the terminal TSW. That is, a current flows from the terminal TSW to the voltage Vn node. However, if the driving force of the power supply circuit 8 is insufficient, as shown in FIG. 4, the voltage Vn supplied from the power supply circuit 8 rises significantly. Therefore, the decrease in the signal SWG from the signal Vp to the signal Vn becomes slower, and for example, at time t14, when the signal SWG decreases to the second voltage, the high frequency switch switches from the on state to the off state. Therefore, the switching of the high frequency switch from the on state to the off state becomes slower.

[0074] In contrast to this, in the first embodiment, when the high-frequency switch is switched from the off state to the on state or from the on state to the off state, it operates as follows.

[0075] When switching the high frequency switch 20 from an off state to an on state, first, the power supply voltage VDD supplied from outside the semiconductor device is supplied to the terminal TSW. Then, the voltage Vp output from the power supply circuit 8 in the semiconductor device is supplied to the terminal TSW. In this way, by switching between the power supply voltage VDD and the voltage Vp in two stages and supplying them to the terminal TSW, even if the driving force of the power supply circuit 8 that supplies the voltage Vp is insufficient, the switch signal SWG can be increased from the voltage Vn to the voltage Vp without lowering the voltage Vp when the voltage Vp is supplied. This makes it possible to speed up the switching of the high frequency switch 20 from an off state to an on state. In other words, the switching time of the high frequency switch 20 from an off state to an on state can be shortened.

[0076] Furthermore, when switching the high frequency switch 20 from an on state to an off state, first, a ground voltage GND supplied from outside the semiconductor device is supplied to the terminal TSW. Then, a voltage Vn output from the power supply circuit 8 in the semiconductor device is supplied to the terminal TSW. In this way, by switching between the ground voltage GND and the voltage Vn in two stages and supplying them to the terminal TSW, even if the driving force of the power supply circuit 8 that supplies the voltage Vn is insufficient, the switch signal SWG can be reduced from the voltage Vp to the voltage Vn without increasing the voltage Vn when the voltage Vn is supplied. This allows the high frequency switch 20 to be switched from an on state to an off state at high speed. In other words, the time required for the high frequency switch 20 to be switched from an on state to an off state can be shortened.

[0077] 2. Second embodiment Next, a semiconductor device according to a second embodiment will be described. In the second embodiment, a circuit including an nMOS transistor and a resistive element is added to the high frequency switch 20 in the first embodiment. Furthermore, signals to be supplied to these nMOS transistors and resistive elements are prepared. In the second embodiment, descriptions of the configuration, operation, and effects similar to those of the switch circuit 1 in the first embodiment will be omitted, and differences will be mainly described.

[0078] 2.1 Configuration of the second embodiment FIG. 5 is a circuit diagram showing a configuration of a switch circuit according to the second embodiment.

[0079] The switch circuit 1 of the second embodiment differs from the first embodiment in the configuration of an on / off switching circuit 11a and a high-frequency switch 20a included in a switch control circuit 10. Specifically, this is as follows.

[0080] The on / off switching circuit 11a includes a terminal TRN connected to the drains of the pMOS transistor M15 and the nMOS transistor M16. The terminal TRN outputs a signal RGN in response to the signal EN.

[0081] 2, the high-frequency switch 20a further includes, for example, nMOS transistors N2_1, N2_2, N2_3, . . . , N2_(n-1), N2_n and resistive elements R2_1, R2_2, R2_3, .

[0082] The high-frequency switch 20a is provided with an nMOS transistor N2_1 capable of shorting both ends of a resistive element R1_1. An nMOS transistor N2_2 capable of shorting both ends of a resistive element R1_2 is provided. An nMOS transistor N2_3 capable of shorting both ends of a resistive element R1_3 is provided. The same is true for the nMOS transistors N2_4, N2_5, ..., N2_(n-1), and N2_n. Furthermore, resistive elements R2_1, R2_2, R2_3, ..., R2_(n-1), and R2_n are provided at the gates of the nMOS transistors N2_1, N2_2, N2_3, ..., N2_(n-1), and N2_n, respectively.

[0083] The connections of the circuit elements in the high-frequency switch 20a will be described below.

[0084] The drain and source of the nMOS transistor N2_1 are connected between the gate of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. That is, the drain of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_1, and the source of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_2. The drain and source of the nMOS transistor N2_2 are connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. That is, the drain of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_2, and the source of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_3. The drain and source of the nMOS transistor N2_3 are connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. That is, the drain of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_3, and the source of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_4. The same is true for the nMOS transistors N2_4, N2_5, ..., N2_(n-1). Furthermore, the drain of the nMOS transistor N2_n is connected to the gate of the nMOS transistor N1_n, and the terminal TSW is connected to the source of the nMOS transistor N2_n.

[0085] A resistive element R2_1 is connected between the gate of the nMOS transistor N2_1 and the gate of the nMOS transistor N2_2. A resistive element R2_2 is connected between the gate of the nMOS transistor N2_2 and the gate of the nMOS transistor N2_3. A resistive element R2_3 is connected between the gate of the nMOS transistor N2_3 and the gate of the nMOS transistor N2_4. The same is true for the resistive elements R2_4, R2_5, ..., R2_(n-1). Furthermore, one end of the resistive element R2_n is connected to the gate of the nMOS transistor N2_n, and the other end of the resistive element R2_n is connected to the terminal TRG.

[0086] 2.2 Operation of the Second Embodiment When the high-frequency switch 20a is switched from the OFF state to the ON state, in the switch circuit 1 shown in FIG. 5, the signals SWG and RGN output from the ON / OFF switching circuit 11a are input to the terminals TSW and TRN of the high-frequency switch 20a, respectively.

[0087] In the high frequency switch 20a, the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are sequentially turned on by the signal SWG input to the terminal TSW. In addition, the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., N2_1 are sequentially turned on by the signal RGN input to the terminal TRN. As a result, the resistive elements R1_n, R1_(n-1), R1_(n-2), ..., R1_1 are shorted by the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., N2_1, respectively, and the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are accelerated in transition from off to on. As a result, the high frequency switch 20a is accelerated in switching from off to on.

[0088] 2.3 Effects of the second embodiment According to the second embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0089] Furthermore, in the second embodiment, in addition to the configuration of the first embodiment, nMOS transistors N2_1 to N2_n for shorting both ends of each of the resistive elements R1_1 to R1_n in the high frequency switch 20a and a signal RGN for controlling the on and off of these nMOS transistors N2_1 to N2_n are provided. This makes it possible to reduce the time until all of the nMOS transistors N1_1 to N1_n in the high frequency switch 20a are turned on. As a result, it is possible to speed up the switching of the high frequency switch 20a from the off state to the on state.

[0090] 2.4 Modification of the second embodiment Next, a description will be given of a switch circuit 1 according to a modification of the second embodiment. Fig. 6 is a circuit diagram showing the configuration of a switch circuit according to a modification of the second embodiment.

[0091] In the switch circuit 1 of the modified example, the high-frequency switch 20b has a different configuration from that of the second embodiment described above.

[0092] The high-frequency switch 20b has a configuration in which the source and drain of each of the nMOS transistors N2_1, N2_2, N2_3, . . . , N2_(n-1), and N2_n included in the high-frequency switch 20a shown in FIG. 5 are interchanged.

[0093] The source of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_1, and the drain of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_2. The source of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_2, and the drain of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_3. The source of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_3, and the drain of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_4. The same applies to the nMOS transistors N2_4, N2_5, ..., N2_(n-1). Furthermore, the source of the nMOS transistor N2_n is connected to the gate of the nMOS transistor N1_n, and the drain of the nMOS transistor N2_n is connected to the terminal TSW.

[0094] As described above, in the high-frequency switch 20b in which the sources and drains of the nMOS transistors N2_1, N2_2, N2_3, ..., N2_(n-1), and N2_n are interchanged with each other in the high-frequency switch 20a, the operation of the high-frequency switch 20b is similar to that of the high-frequency switch 20a in the second embodiment.

[0095] 2.5 Other Modifications of the Second Embodiment Next, a description will be given of the switch circuit 1 according to another modified example of the second embodiment. Fig. 7 is a circuit diagram showing the configuration of a switch circuit according to another modified example of the second embodiment.

[0096] In the switch circuit 1 of this modification, the high-frequency switch 20c has a different configuration from that of the second embodiment described above.

[0097] The high-frequency switch 20c includes, in addition to the configuration of the high-frequency switch 20 shown in FIG. 2, for example, nMOS transistors N2_1, N2_2, N2_3, ..., N2_(n-1), N2_n, N2_(n+1) and resistive elements R2_1, R2_2, R2_3, ..., R2_(n-1), R2_n, R2_(n+1), R2_(n+2).

[0098] The source of the nMOS transistor N2_(n+1) and one end of the resistor element R2_(n+1) are connected to the terminal TSW. The drain of the nMOS transistor N2_(n+1) is connected to the other end of the resistor element R2_(n+1).

[0099] Between a first node, to which the drain of the nMOS transistor N2_(n+1) and the other end of the resistor element R2_(n+1) are connected, and the gate of the nMOS transistor N1_1, the nMOS transistor N2_1 and the resistor element R1_1 are connected in parallel. Between the first node and the gate of the nMOS transistor N1_2, the nMOS transistor N2_2 and the resistor element R1_2 are connected in parallel. Between the first node and the gate of the nMOS transistor N1_3, the nMOS transistor N2_3 and the resistor element R1_3 are connected in parallel. The same is true for the nMOS transistor N2_4 and the resistor element R1_4, ..., the nMOS transistor N2_(n-1) and the resistor element R1_(n-1), and the nMOS transistor N2_n and the resistor element R1_n.

[0100] The gate of the nMOS transistor N2_1 is connected to the terminal TRN via the resistor elements R2_1 and R2_(n+2). The gate of the nMOS transistor N2_2 is connected to the terminal TRN via the resistor elements R2_2 and R2_(n+2). The gate of the nMOS transistor N2_3 is connected to the terminal TRN via the resistor elements R2_3 and R2_(n+2). Similarly, the gate of the nMOS transistor N2_4 is connected to the terminal TRN via the resistor elements R2_4 and R2_(n+2), the gate of the nMOS transistor N2_(n-1) is connected to the terminal TRN via the resistor elements R2_(n-1) and R2_(n+2), and the gate of the nMOS transistor N2_n is connected to the terminal TRN via the resistor elements R2_n and R2_(n+2). Furthermore, the gate of the nMOS transistor N2_(n+1) is connected to the terminal TRN via the resistor element R2_(n+2).

[0101] As described above, even if an nMOS transistor and a resistive element are connected in parallel to each gate of the nMOS transistors N1_1, N1_2, N1_3, ..., N1_(n-1), and N1_n, the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., and N2_1 are turned on by the signal RGN input to the terminal TRN. As a result, the resistive elements R1_n, R1_(n-1), R1_(n-2), ..., and R1_1 are shorted by the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., and N2_1, respectively, and the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., and N1_1 are accelerated in transition from off to on. As a result, the high-frequency switch 20c is accelerated in switching from off to on.

[0102] 3. Third embodiment Next, a semiconductor device according to a third embodiment will be described. In the third embodiment, a circuit including a pMOS transistor and a resistive element is added to the high frequency switch 20 in the first embodiment. Furthermore, signals to be supplied to these pMOS transistors and resistive elements are prepared. In the third embodiment, descriptions of the configuration, operation, and effects similar to those of the switch circuit 1 in the first embodiment will be omitted, and differences will be mainly described.

[0103] 3.1 Configuration of the third embodiment FIG. 8 is a circuit diagram showing a configuration of a switch circuit according to the third embodiment.

[0104] The switch circuit 1 of the third embodiment differs from the first embodiment in the configuration of an on / off switching circuit 11b and a high-frequency switch 20d included in a switch control circuit 10. Specifically, this is as follows.

[0105] The on / off switching circuit 11b includes a terminal TRP connected to the drains of the pMOS transistor M7 and the nMOS transistor M8. The terminal TRP outputs a signal RGP that corresponds to the signal EP.

[0106] 2, the high-frequency switch 20d further includes, for example, pMOS transistors P1_1, P1_2, P1_3, . . . , P1_(n-1), P1_n and resistive elements R2_1, R2_2, R2_3, .

[0107] The high-frequency switch 20d is provided with a pMOS transistor P1_1 capable of shorting both ends of a resistive element R1_1. A pMOS transistor P1_2 capable of shorting both ends of a resistive element R1_2 is provided. A pMOS transistor P1_3 capable of shorting both ends of a resistive element R1_3 is provided. The same is true for the pMOS transistors P1_4, P1_5, ..., P1_(n-1), and P1_n. Furthermore, resistive elements R2_1, R2_2, R2_3, ..., R2_(n-1), and R2_n are provided at the gates of the pMOS transistors P1_1, P1_2, P1_3, ..., P1_(n-1), and P1_n, respectively.

[0108] The connections of the circuit elements in the high-frequency switch 20d will be described below.

[0109] The source and drain of the pMOS transistor P1_1 are connected between the gate of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. That is, the source of the pMOS transistor P1_1 is connected to the gate of the nMOS transistor N1_1, and the drain of the pMOS transistor P1_1 is connected to the gate of the nMOS transistor N1_2. The source and drain of the pMOS transistor P1_2 are connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. That is, the source of the pMOS transistor P1_2 is connected to the gate of the nMOS transistor N1_2, and the drain of the pMOS transistor P1_2P2 is connected to the gate of the nMOS transistor N1_3. The source and drain of the pMOS transistor P1_3P3 are connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. That is, the source of the pMOS transistor P1_3 is connected to the gate of the nMOS transistor N1_3, and the drain of the pMOS transistor P1_3 is connected to the gate of the nMOS transistor N1_4. The same is true for the pMOS transistors P1_4, P1_5, ..., P1_(n-1). Furthermore, the source of the pMOS transistor P1_n is connected to the gate of the nMOS transistor N1_n, and the drain of the pMOS transistor P1_n is connected to the terminal TSW.

[0110] A resistive element R2_1 is connected between the gate of the pMOS transistor P1_1 and the gate of the pMOS transistor P1_2. A resistive element R2_2 is connected between the gate of the pMOS transistor P1_2 and the gate of the pMOS transistor P1_3. A resistive element R2_3 is connected between the gate of the pMOS transistor P1_3 and the gate of the pMOS transistor P1_4. The same is true for the resistive elements R2_4, R2_5, ..., R2_(n-1). Furthermore, one end of the resistive element R2_n is connected to the gate of the pMOS transistor P1_n, and the other end of the resistive element R2_n is connected to the terminal TRP.

[0111] 3.2 Operation of the Third Embodiment When the high frequency switch 20d is switched from the on state to the off state, in the switch circuit 1 shown in FIG. 7, the signals SWG and RGP output from the on / off switching circuit 11b are input to the terminals TSW and TRP of the high frequency switch 20d.

[0112] In the high-frequency switch 20d, the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are sequentially turned off by the signal SWG input to the terminal TSW. In addition, the pMOS transistors P1_n, P1_(n-1), P1_(n-2), ..., P1_1 are sequentially turned off by the signal RGP input to the terminal TRP. This speeds up the transition from on to off of the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1. As a result, the high-frequency switch 20d is switched from the on state to the off state at high speed.

[0113] 3.3 Effects of the third embodiment According to the third embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0114] Furthermore, in the third embodiment, in addition to the configuration of the first embodiment, pMOS transistors P1_1 to P1_n for electrically cutting off both ends of each of the resistive elements R1_1 to R1_n in the high frequency switch 20d and a signal RGP for controlling the on and off of these pMOS transistors P1_1 to P1_n are provided. This makes it possible to reduce the time it takes for the pMOS transistors P1_1 to P1_n in the high frequency switch 20d to turn off. As a result, it is possible to speed up the switching of the high frequency switch 20d from the on state to the off state.

[0115] 4. Fourth embodiment Next, a semiconductor device according to a fourth embodiment will be described. In the fourth embodiment, a circuit including an nMOS transistor and a resistive element, and a circuit including a pMOS transistor and a resistive element are added to the high frequency switch 20 in the first embodiment. Furthermore, signals are provided to be supplied to the circuit including the nMOS transistor and the resistive element, and the circuit including the pMOS transistor and the resistive element. In the fourth embodiment, a description of the configuration, operation, and effects similar to those of the switch circuit 1 in the first embodiment will be omitted, and the differences will be mainly described.

[0116] 4.1 Configuration of the fourth embodiment FIG. 9 is a circuit diagram showing a configuration of a switch circuit according to the fourth embodiment.

[0117] The switch circuit 1 of the fourth embodiment differs from the first embodiment in the configuration of an on / off switching circuit 11c and a high-frequency switch 20e included in a switch control circuit 10. Specifically, this is as follows.

[0118] The on / off switching circuit 11c has a terminal TRN connected to the drains of the pMOS transistor M15 and the nMOS transistor M16. The terminal TRN outputs a signal RGN in response to the signal EN. The on / off switching circuit 11c also has a terminal TRP connected to the drains of the pMOS transistor M7 and the nMOS transistor M8. The terminal TRP outputs a signal RGP in response to the signal EP.

[0119] 2, the high-frequency switch 20e further includes, for example, nMOS transistors N2_1, N2_2, N2_3, . . . , N2_(n-1), N2_n and resistive elements R2_1, R2_2, R2_3, .

[0120] The drain and source of the nMOS transistor N2_1 are connected between the gate of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. That is, the drain of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_1, and the source of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_2. The drain and source of the nMOS transistor N2_2 are connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. That is, the drain of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_2, and the source of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_3. The drain and source of the nMOS transistor N2_3 are connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. That is, the drain of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_3, and the source of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_4. The same applies to the nMOS transistors N2_4, N2_5, ..., N2_(n-1). Furthermore, the drain of the nMOS transistor N2_n is connected to the gate of the nMOS transistor N1_n, and the terminal TSW is connected to the source of the nMOS transistor N2_n.

[0121] A resistive element R2_1 is connected between the gate of the nMOS transistor N2_1 and the gate of the nMOS transistor N2_2. A resistive element R2_2 is connected between the gate of the nMOS transistor N2_2 and the gate of the nMOS transistor N2_3. A resistive element R2_3 is connected between the gate of the nMOS transistor N2_3 and the gate of the nMOS transistor N2_4. The resistive elements R2_4, R2_5, ..., R2_(n-1) are connected in the same manner. Furthermore, one end of the resistive element R2_n is connected to the gate of the nMOS transistor N2_n, and the other end of the resistive element R2_n is connected to the terminal TRN.

[0122] The high-frequency switch 20e further includes, for example, pMOS transistors P1_1, P1_2, P1_3, . . . , P1_(n-1), P1_n and resistive elements R3_1, R3_2, R3_3, . . . , R3_(n-1), R3_n.

[0123] The source and drain of the pMOS transistor P1_1 are connected between the gate of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. That is, the source of the pMOS transistor P1_1 is connected to the gate of the nMOS transistor N1_1, and the drain of the pMOS transistor P1_1 is connected to the gate of the nMOS transistor N1_2. The source and drain of the pMOS transistor P1_2 are connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. That is, the source of the pMOS transistor P1_2 is connected to the gate of the nMOS transistor N1_2, and the drain of the pMOS transistor P1_2 is connected to the gate of the nMOS transistor N1_3. The source and drain of the pMOS transistor P1_3 are connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. That is, the source of the pMOS transistor P1_3 is connected to the gate of the nMOS transistor N1_3, and the drain of the pMOS transistor P1_3 is connected to the gate of the nMOS transistor N1_4. The same applies to the pMOS transistors P1_4, P1_5, ..., P1_(n-1). Furthermore, the source of the pMOS transistor P1_n is connected to the gate of the nMOS transistor N1_n, and the drain of the pMOS transistor P1_n is connected to the terminal TSW.

[0124] A resistive element R3_1 is connected between the gate of the pMOS transistor P1_1 and the gate of the pMOS transistor P1_2. A resistive element R3_2 is connected between the gate of the pMOS transistor P1_2 and the gate of the pMOS transistor P1_3. A resistive element R3_3 is connected between the gate of the pMOS transistor P1_3 and the gate of the pMOS transistor P1_4. The resistive elements R3_4, R3_5, ..., R3_(n-1) are similarly connected. Furthermore, one end of the resistive element R3_n is connected to the gate of the pMOS transistor P1_n, and the other end of the resistive element R3_n is connected to the terminal TRP.

[0125] 4.2 Operation of the Fourth Embodiment When the high-frequency switch 20e is switched from the OFF state to the ON state, in the switch circuit 1 shown in FIG. 9, the signals SWG and RGN output from the ON / OFF switching circuit 11c are input to the terminals TSW and TRN of the high-frequency switch 20e, respectively.

[0126] In the high frequency switch 20e, the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are sequentially turned on by the signal SWG input to the terminal TSW. In addition, the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., N2_1 are sequentially turned on by the signal RGN input to the terminal TRN. As a result, the resistive elements R1_n, R1_(n-1), R1_(n-2), ..., R1_1 are shorted by the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., N2_1, respectively, and the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are accelerated in transition from off to on. As a result, the high frequency switch 20e is accelerated in switching from off to on.

[0127] On the other hand, when the high frequency switch 20e is switched from the on state to the off state, in the switch circuit 1 shown in FIG. 9, the signals SWG and RGP output from the on / off switching circuit 11c are input to the terminals TSW and TRP of the high frequency switch 20e, respectively.

[0128] In the high-frequency switch 20e, the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are sequentially turned off by the signal SWG input to the terminal TSW. In addition, the pMOS transistors P1_n, P1_(n-1), P1_(n-2), ..., P1_1 are sequentially turned off by the signal RGP input to the terminal TRP. This speeds up the transition from on to off of the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1. As a result, the high-frequency switch 20d is switched from the on state to the off state at high speed.

[0129] 4.3 Effects of the fourth embodiment According to the fourth embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0130] Furthermore, in the fourth embodiment, in addition to the configuration of the first embodiment, nMOS transistors N2_1 to N2_n for shorting both ends of each of the resistive elements R1_1 to R1_n in the high frequency switch 20e and a signal RGN for controlling the on and off of these nMOS transistors N2_1 to N2_n are provided. This makes it possible to reduce the time until all of the nMOS transistors N1_1 to N1_n in the high frequency switch 20e are turned on. As a result, it is possible to speed up the switching of the high frequency switch 20e from the off state to the on state.

[0131] Furthermore, in the fourth embodiment, in addition to the configuration of the first embodiment, pMOS transistors P1_1 to P1_n for electrically cutting off both ends of each of the resistive elements R1_1 to R1_n in the high frequency switch 20e and a signal RGP for controlling the on and off of these pMOS transistors P1_1 to P1_n are provided. This makes it possible to shorten the time it takes for the pMOS transistors P1_1 to P1_n in the high frequency switch 20e to turn off. As a result, it is possible to speed up the switching of the high frequency switch 20e from the on state to the off state.

[0132] 5. Fifth embodiment Next, a semiconductor device according to a fifth embodiment will be described. For example, in the wireless device WD shown in FIG. 1, when four switch circuits 1, 2, 3, and 4 are controlled by control signals CNT1, 2, 3, and 4, four delay circuits 12 are required. However, since the delay circuit 12 includes a resistive element R and a capacitive element C, the area occupied by the delay circuit may become large. Therefore, by using the delay circuit proposed in the fifth embodiment, the RC circuit is reduced to one, thereby reducing the area occupied by the delay circuit. In the fifth embodiment, the description of the configuration, operation, and effect similar to those of the switch circuit 1 in the first embodiment will be omitted, and the description will focus on the differences.

[0133] 5.1 Configuration of the fifth embodiment FIG. 10 is a circuit diagram showing a configuration of a delay circuit included in a plurality of switch circuits according to the fifth embodiment.

[0134] The plurality of switch circuits of the fifth embodiment differ from the first embodiment in the configuration of delay circuits 12a included in the plurality of switch control circuits 10. Specifically, this is as follows.

[0135] The delay circuit 12a includes a plurality of buffers B11, B12, B13, and B14, exclusive OR circuits XO1, XO2, XO3, XO4, and XO5, D flip-flops DF1, DF2, DF3, DF4, and DF5, AND circuits AD1, AD2, AD3, and AD4, OR circuits OR1, OR2, OR3, OR4, and OR5, inverters IV1, IV2, and IV3, a resistive element R, and a capacitive element C.

[0136] The connections of the circuit elements in the delay circuit 12a will be described below.

[0137] Each of the control signals CNT1, 2, 3, and 4 is input to a first input terminal of an exclusive OR circuit XO1, XO2, XO3, and XO4, respectively. Each of the control signals CNT1, 2, 3, and 4 is also input to a D input terminal of a D flip-flop DF1, DF2, DF3, and DF4, respectively. Furthermore, each of the control signals CNT1, 2, 3, and 4 is also input to a first input terminal of an AND circuit AD1, AD2, AD3, and AD4, respectively, and is also input to a first input terminal of an OR circuit OR1, OR2, OR3, and OR4, respectively.

[0138] The control signals CNT1, 2, 3, and 4 are input to the input terminals of buffers B11, B12, B13, and B14, respectively. The output terminals of buffers B11, B12, B13, and B14 are connected to second input terminals of exclusive OR circuits XO1, XO2, XO3, and XO4, respectively.

[0139] The output terminals of the exclusive OR circuits XO1, XO2, XO3, and XO4 are connected to the four input terminals of the OR circuit OR5. The output terminal of the OR circuit OR5 is connected to the clock input terminal of the D flip-flop DF5. The Q inverted output terminal of the D flip-flop DF5 is connected to the D input terminal.

[0140] The Q output terminal of the D flip-flop DF5 is connected to a first input terminal of the exclusive OR circuit XO5 via an inverter IV1, a resistor R, and an inverter IV2. A first electrode of a capacitor C is connected to a node between the resistor R and the inverter IV2, and a second electrode of the capacitor C is connected to the ground voltage GND node. The Q output terminal of the D flip-flop DF5 is also connected to a second input terminal of the exclusive OR circuit XO5.

[0141] The output terminal of the exclusive OR circuit XO5 is connected to the clock input terminals of the D flip-flops DF1, DF2, DF3, and DF4 via the inverter IV3. The Q output terminals of the D flip-flops DF1, DF2, DF3, and DF4 are connected to the second input terminals of the AND circuits AD1, AD2, AD3, and AD4, respectively, and are also connected to the second input terminals of the OR circuits OR1, OR2, OR3, and OR4, respectively.

[0142] Then, signals EP1 and EN1 are output from the output terminals of AND circuit AD1 and OR circuit OR1, respectively. Signals EP2 and EN2 are output from the output terminals of AND circuit AD2 and OR circuit OR2, respectively. Signals EP3 and EN3 are output from the output terminals of AND circuit AD3 and OR circuit OR3, respectively. Furthermore, signals EP4 and EN4 are output from the output terminals of AND circuit AD4 and OR circuit OR4, respectively.

[0143] 5.2 Operation of the Fifth Embodiment The operation of the delay circuit 12a in the fifth embodiment will be described with reference to FIG.

[0144] The delay circuit 12a receives control signals CNT1, CNT2, CNT3, and CNT4 for controlling the switch circuits 1, 2, 3, and 4, respectively. For example, the signal waveforms shown in (1a), (2a), (3a), and (4a) in FIG. 10 are input to the buffers B11, B12, B13, and B14, respectively, as the control signals CNT1 to CNT4. Then, the signal waveforms shown in (1b), (2b), (3b), and (4b) are output as signals EP1 and EN1, EP2 and EN2, EP3 and EN3, and EP4 and EN4 from the circuits AD1 and OR1, AD2 and OR2, AD3 and OR3, and AD4 and OR4, respectively, via the logic circuits and one RC circuit provided at the output stages of the buffers B11 to B14.

[0145] Thereafter, the signals EP1 and EN1, EP2 and EN2, EP3 and EN3, and EP4 and EN4 output from the delay circuit 12a are input to the ON / OFF switching circuits 11 in the switch circuits 1, 2, 3, and 4, respectively, and the signal SWG is generated.

[0146] Here, an example is shown in which each of the buffers B11 to B14 includes a three-stage buffer, but each of the buffers B11 to B14 may be a one-stage or two-stage buffer, or may be a four-stage or more buffer, as long as the signal delay required for the circuit operation at the subsequent stage can be generated. Furthermore, here, a delay circuit that generates a signal delay using an RC circuit including a resistive element R and a capacitive element C is shown, but if the delay required for the signals EP1 to 4 and the signals EN1 to 4 can be generated only by a multi-stage buffer, the delay circuit may be configured only by a multi-stage buffer without using an RC circuit. The same applies to the delay circuits described below.

[0147] 5.3 Effects of the fifth embodiment According to the fifth embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0148] Furthermore, in the fifth embodiment, a plurality of delay circuits for controlling a plurality of switch circuits are configured with one RC circuit. This makes it possible to prevent an increase in the occupied area that occurs when a plurality of delay circuits are provided, and to reduce the occupied area by the delay circuits. Note that, although an example in which four delay circuits are configured with one RC circuit has been shown here, this is not limiting. It is also possible to configure delay circuits other than four with one RC delay circuit.

[0149] 6. Sixth embodiment Next, a semiconductor device according to a sixth embodiment will be described. There may be a plurality of switch circuits to which a power supply circuit (e.g., a charge pump) 8 supplies voltages Vp and Vn, and there may be a plurality of switch circuits that are switched simultaneously. The greater the number of switch circuits that are turned on or off simultaneously, the greater the fluctuations in voltages Vp and Vn, and the longer the time it takes to switch on and off. In the sixth embodiment, the delay time in the delay circuit is optimized according to the number of switch circuits that are switched, and the switching speed is increased for each number of switch circuits that are switched.

[0150] 6.1 Configuration of the sixth embodiment FIG. 11 is a circuit diagram showing a configuration of a delay circuit included in a plurality of switch circuits according to the sixth embodiment.

[0151] The switch circuits of the sixth embodiment differ from the first embodiment in the configuration of the delay circuits 12b included in the switch control circuits 10. Specifically, this is as follows.

[0152] The delay circuit 12b includes a plurality of buffers B11, B12, B13, B14, B15, and B16, exclusive OR circuits XO1, XO2, XO3, XO4, and XO5, D flip-flops DF1, DF2, DF3, DF4, DF5, DF6, DF7, DF8, and DF9, AND circuits AD1, AD2, AD3, and AD4, OR circuits OR1, OR2, OR3, OR4, and OR5, inverters IV1, IV2, and IV3, a variable resistance element VR, a capacitance element C, and a count circuit CO.

[0153] The connections of the circuit elements in the delay circuit 12b will be described below.

[0154] Each of the control signals CNT1, 2, 3, and 4 is input to a first input terminal of an exclusive OR circuit XO1, XO2, XO3, and XO4, respectively. Each of the control signals CNT1, 2, 3, and 4 is also input to a D input terminal of a D flip-flop DF1, DF2, DF3, and DF4, respectively. Furthermore, each of the control signals CNT1, 2, 3, and 4 is also input to a first input terminal of an AND circuit AD1, AD2, AD3, and AD4, respectively, and is also input to a first input terminal of an OR circuit OR1, OR2, OR3, and OR4, respectively.

[0155] The control signals CNT1, 2, 3, and 4 are input to the input terminals of buffers B11, B12, B13, and B14, respectively. The output terminals of buffers B11, B12, B13, and B14 are connected to second input terminals of exclusive OR circuits XO1, XO2, XO3, and XO4, respectively.

[0156] The output terminals of the exclusive OR circuits XO1, XO2, XO3, and XO4 are connected to the four input terminals of the OR circuit OR5. The output terminals of the exclusive OR circuits XO1, XO2, XO3, and XO4 are also connected to the D input terminals of the D flip-flops DF5, DF6, DF7, and DF8. The Q output terminals of the D flip-flops DF5, DF6, DF7, and DF8 are connected to the input terminals of the count circuit CO. The output terminal of the count circuit CO is input to the control terminal of the variable resistance element VR. The count circuit CO counts the number of rising and falling edges of the signals CNT1, CNT2, CNT3, and CNT4 using the signals output from the Q output terminals of the D flip-flops DF5 to DF8, and outputs a signal according to the count number to the control terminal. The variable resistance element VR changes its resistance value according to the signal input to the control terminal. The number of rising edges and falling edges corresponds to the number of switching operations of the high frequency switch.

[0157] The output terminal of the OR circuit OR5 is connected to the clock input terminal of the D flip-flop DF9 via buffers B15 and B16. The Q inverted output terminal of the D flip-flop DF5 is connected to the D input terminal. The node between the buffers B15 and B16 is connected to the clock input terminals of the D flip-flops DF5, DF6, DF7, and DF8, respectively.

[0158] The Q output terminal of the D flip-flop DF9 is connected to a first input terminal of the exclusive OR circuit XO5 via an inverter IV1, a variable resistance element VR, and an inverter IV2. A first electrode of a capacitance element C is connected to a node between the variable resistance element VR and the inverter IV2, and a second electrode of the capacitance element C is connected to the ground voltage GND node. The Q output terminal of the D flip-flop DF9 is connected to a second input terminal of the exclusive OR circuit XO5.

[0159] The output terminal of the exclusive OR circuit XO5 is input to the clock input terminals of the D flip-flops DF1, DF2, DF3, and DF4 via the inverter IV3. The Q output terminals of the D flip-flops DF1, DF2, DF3, and DF4 are connected to the second input terminals of the AND circuits AD1, AD2, AD3, and AD4, respectively, and are also connected to the second input terminals of the OR circuits OR1, OR2, OR3, and OR4, respectively.

[0160] Then, signals EP1 and EN1 are output from the output terminals of AND circuit AD1 and OR circuit OR1, respectively. Signals EP2 and EN2 are output from the output terminals of AND circuit AD2 and OR circuit OR2, respectively. Signals EP3 and EN3 are output from the output terminals of AND circuit AD3 and OR circuit OR3, respectively. Furthermore, signals EP4 and EN4 are output from the output terminals of AND circuit AD4 and OR circuit OR4, respectively.

[0161] 6.2 Operation of the Sixth Embodiment The operation of the delay circuit 12b in the sixth embodiment will be described with reference to Figures 11 and 12. Figure 12 is a timing chart showing the operation of the switch control circuit 10 in the switch circuit of the sixth embodiment.

[0162] The delay circuit 12b receives control signals CNT1, CNT2, CNT3, and CNT4 for controlling the switch circuits 1, 2, 3, and 4, respectively. For example, the signal waveforms shown in (1c), (2c), (3c), and (4c) in FIG. 11 are input to the buffers B11, B12, B13, and B14, respectively, as the control signals CNT1 to CNT4. Then, the signal waveforms shown in (1d), (2d), (3d), and (4d) are output as signals EP1 and EN1, EP2 and EN2, EP3 and EN3, and EP4 and EN4 from the circuits AD1 and OR1, AD2 and OR2, AD3 and OR3, and AD4 and OR4, respectively, via the logic circuit, count circuit CO, and RC circuit including the variable resistance element VR provided at the output stage of the buffers B11 to B14.

[0163] Thereafter, the signals EP1 and EN1, EP2 and EN2, EP3 and EN3, and EP4 and EN4 output from the delay circuit 12b are input to the ON / OFF switching circuits 11 in the switch circuits 1, 2, 3, and 4, respectively, and the signal SWG is generated.

[0164] Here, as shown in FIG. 12, for example, when the control signal CNT1 rises from "L" to "H" at time t1, the signal EN1 rises from "L" to "H" at the same time t1. After that, the signal EP1 rises from "L" to "H" at time t2b. Also, for example, at time t1, the control signal CNT2 is maintained at "L", CNT3 falls from "H" to "L", and CNT4 is maintained at "H". This time t1-t2b period (i.e., the transition period from the OFF state to the ON state) changes according to the total number of rising edges and falling edges of the signals CNT1, CNT2, CNT3, and CNT4. The total number of rising edges and falling edges corresponds to the number of switching of the high-frequency switch. The number of rising edges is also called the number of transitions from "L" to "H", and the number of falling edges is also called the number of transitions from "H" to "L".

[0165] Note that here, the period from time t1 to t2b (i.e., the transition period from the off state to the on state) is changed according to the combined number of rising edges and falling edges. However, it is also possible to change the transition period from the off state to the on state according to the number of rising edges, and to change the transition period from the on state to the off state according to the number of falling edges.

[0166] In the delay circuit 12b, if the number of rising and falling edges is large, i.e., if the number of switching of the high frequency switch is large, the resistance value of the variable resistance element VR becomes large and the period from time t1 to t2b is set long. On the other hand, if the number of rising and falling edges is small, i.e., if the number of switching of the high frequency switch is small, the resistance value of the variable resistance element VR becomes small and the period from time t1 to t2b is set short. This makes it possible to make the switching time of the high frequency switch appropriate, i.e., the shortest.

[0167] 6.3 Effects of the Sixth Embodiment According to the sixth embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0168] Furthermore, in the sixth embodiment, when multiple switch circuits are controlled, the delay time in the delay circuit can be minimized according to the number of high frequency switches in the multiple switch circuits that are switched on and off, thereby speeding up the switching on and off of the high frequency switches in the switch circuits.

[0169] 6.4 Modification of the sixth embodiment Next, a description will be given of a switch circuit according to a modification of the sixth embodiment. Fig. 13 is a circuit diagram showing the configuration of a delay circuit included in the switch circuit according to the modification of the sixth embodiment.

[0170] The multiple switch circuits of the modified example differ from the sixth embodiment in the configuration of the delay circuits 12c included in the multiple switch control circuits 10. Specifically, this is as follows.

[0171] The delay circuit 12c includes a plurality of buffers B11, B12, B13, B14, B15, and B16, exclusive OR circuits XO1, XO2, XO3, XO4, and XO5, D flip-flops DF1, DF2, DF3, DF4, DF5, DF6, DF7, DF8, and DF9, AND circuits AD1, AD2, AD3, and AD4, OR circuits OR1, OR2, OR3, OR4, and OR5, inverters IV1, IV2, and IV3, resistive elements R1, R2, R3, and R4, switching elements S1, S2, S3, and S4, and a capacitive element C.

[0172] The connections of the circuit elements in the delay circuit 12c will be described below.

[0173] The Q inverting output terminals of the D flip-flops DF5, DF6, DF7, and DF8 are connected to the control ends of the switch elements S1, S2, S3, and S4, respectively.

[0174] The output terminal of the inverter IV1 is connected to the input terminal of the inverter IV2 via four resistor elements R1, R2, R3, and R4 connected in series. One end of the switch element S1 is connected to one end of the resistor element R1, and the other end of the switch element S1 is connected to the other end of the resistor element R1. One end of the switch element S2 is connected to one end of the resistor element R2, and the other end of the switch element S2 is connected to the other end of the resistor element R2. One end of the switch element S3 is connected to one end of the resistor element R3, and the other end of the switch element S3 is connected to the other end of the resistor element R3. One end of the switch element S4 is connected to one end of the resistor element R4, and the other end of the switch element S4 is connected to the other end of the resistor element R4.

[0175] A first electrode of the capacitance element C is connected to a node between the resistance element R4 and the inverter IV2, and a second electrode of the capacitance element C is connected to the ground voltage GND node. The other connections are the same as those in the sixth embodiment.

[0176] 14 shows a detailed circuit diagram of each of the switch elements S1, S2, S3, and S4. Each of the switch elements S1, S2, S3, and S4 has an nMOS transistor N31, a pMOS transistor P31, and an inverter IV11. The signal output from the Q inverting output terminal of each of the D flip-flops DF5, DF6, DF7, and DF8 is input to the gate of the nMOS transistor N31 and the input terminal of the inverter IV11 of the switch elements S1, S2, S3, and S4, respectively. The output terminal of the inverter IV11 is connected to the gate of the pMOS transistor P31. Each of the switch elements S1, S2, S3, and S4 sets the switch element to either a connected state or a cut-off state according to the signal input to the control terminal, i.e., the gate of the nMOS transistor N31 and the inverter IV11.

[0177] In the delay circuit 12c, the period from time t1 to time t2b shown in FIG. 12 changes according to the number of rising edges and falling edges of the signals CNT1, CNT2, CNT3, and CNT4.

[0178] If the number of rising and falling edges of the signals CNT1, CNT2, CNT3, and CNT4 is large, that is, if the number of switching of the high frequency switch is large, the number of switching elements S1 to S4 that are set to the cut-off state increases. Therefore, the resistance value of the circuit including the switching elements S1 to S4 and the resistance elements R1 to R4 increases. As a result, the period from time t1 to t2b is set long.

[0179] Furthermore, if the number of rising and falling edges of the signals CNT1, CNT2, CNT3, and CNT4 is small, that is, if the number of switching of the high frequency switches is small, the number of switching elements S1 to S4 that are set to the connected state will increase. Therefore, the resistance value of the circuit including the switching elements S1 to S4 and the resistance elements R1 to R4 will be small. As a result, the period t1-t2b is set short. Through these controls, the switching time of the high frequency switches can be made appropriate, that is, the shortest possible.

[0180] 7. Seventh embodiment Next, a semiconductor device according to a seventh embodiment will be described. In the seventh embodiment, the pMOS transistor M4 and the diode D2 are deleted from the switch control circuit 10 of the first embodiment. In the seventh embodiment, the description of the configuration, operation, and effects similar to those of the switch circuit 1 of the first embodiment will be omitted, and the description will focus on the differences.

[0181] 7.1 Configuration of the Seventh Embodiment FIG. 15 is a circuit diagram showing a configuration of a switch circuit according to the seventh embodiment.

[0182] The switch circuit 1 of the seventh embodiment differs from that of the first embodiment in the configuration of an on / off switching circuit 11d included in a switch control circuit 10. Specifically, this is as follows.

[0183] The on / off switching circuit 11d has the same configuration as the on / off switching circuit 11 shown in FIG. 2 except that the pMOS transistor M4 and the diode D2 are omitted.

[0184] 7.2 Operation of the Seventh Embodiment FIG. 16 is a circuit diagram showing a part of the operation of the on / off switching circuit 11d in the switch circuit of the seventh embodiment.

[0185] In the seventh embodiment, when the high-frequency switch 20 is switched from the on state to the off state or from the off state to the on state, signals EP and EN similar to those shown in FIG. 3 are supplied.

[0186] In the on / off switching circuit 11 of the first embodiment shown in FIG. 2, when the high-frequency switch 20 is switched from the on state to the off state, as shown in FIG. 16(b), the charge of the voltage Vp (e.g., 3.5 V) in the signal SWG flows through the pMOS transistor M4 and the diode D2 to the ground voltage GND node (e.g., 0 V).

[0187] In the on / off switching circuit 11d of the seventh embodiment, when the high frequency switch 20 is switched from the on state to the off state, during the period from time t3 to t4, as shown in FIG. 16(a), the charge of the voltage Vp (e.g., 3.5 V) in the signal SWG flows through the parasitic diode PD1 present in the pMOS transistor M1 to the node to which the source of the pMOS transistor M1 is connected. At this time, the node to which the source of the pMOS transistor M1 is connected is set to the ground voltage GND (e.g., 0 V). As a result, the signal SWG drops from the voltage Vp to the ground voltage GND. Note that during the period from time t3 to t4, the signal EP is at "L" and the signal EN is at "H."

[0188] Moreover, the operation when the high-frequency switch 20 is switched from the OFF state to the ON state is the same as in the first embodiment.

[0189] 7.3 Effects of the Seventh Embodiment According to the seventh embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0190] Furthermore, in the seventh embodiment, when the high-frequency switch 20 is switched from the on state to the off state, i.e., when the signal SWG is switched from the voltage Vp to the voltage Vn, by setting a period (the period from time t3 to t4) during which the signal EP is at “L” and the signal EN is at “H”, the charge of the voltage Vp in the signal SWG can be discharged to the ground voltage GND via the parasitic diode PD1 present in the pMOS transistor M1 during this period.

[0191] Therefore, in the configuration of the first embodiment shown in FIG. 2, the pMOS transistor M4 and the diode D2 can be deleted to obtain the configuration of the seventh embodiment.

[0192] 8. Eighth embodiment Next, a semiconductor device according to an eighth embodiment will be described. In the eighth embodiment, the nMOS transistor M3, the diode D1, the pMOS transistor M4, and the diode D2 are deleted from the switch control circuit 10 according to the first embodiment. In the eighth embodiment, the description of the configuration, operation, and effects similar to those of the switch circuit 1 according to the first embodiment will be omitted, and the description will focus on the differences.

[0193] 8.1 Configuration of the eighth embodiment FIG. 17 is a circuit diagram showing a configuration of a switch circuit according to the eighth embodiment.

[0194] The switch circuit 1 of the eighth embodiment differs from that of the first embodiment in the configuration of an on / off switching circuit 11e included in a switch control circuit 10. Specifically, this is as follows.

[0195] The on / off switching circuit 11e has the same configuration as the on / off switching circuit 11 shown in FIG. 2 except that the nMOS transistor M3, the diode D1, the pMOS transistor M4, the diode D2, the pMOS transistor M13, the nMOS transistor M14, the pMOS transistor M15, and the nMOS transistor M16 are omitted.

[0196] 8.2 Operation of the Eighth Embodiment FIG. 18 is a circuit diagram showing a part of the operation of the on / off switching circuit 11e in the switch circuit of the eighth embodiment.

[0197] In the eighth embodiment, when the high-frequency switch 20 is switched from the on state to the off state or from the off state to the on state, signals EP and EN similar to those shown in FIG. 3 are supplied.

[0198] In the on / off switching circuit 11 of the first embodiment shown in FIG. 2, when the high-frequency switch 20 is switched from the off state to the on state, as shown in FIG. 18(b), a current flows from the power supply voltage VDD node through the diode D1 and the nMOS transistor M3 to the terminal TSW, causing the signal SWG to rise from a voltage Vn (e.g., −3.5 V) to a power supply voltage VDD (e.g., 1.2 V).

[0199] In the on / off switching circuit 11e of the eighth embodiment, when the high-frequency switch 20 is switched from the off state to the on state, during the period from time t1 to t2, as shown in FIG. 18(a), a current flows from the node to which the source of the nMOS transistor M2 is connected to the terminal TSW through the parasitic diode PD2 present in the nMOS transistor M2. At this time, the node to which the source of the nMOS transistor M2 is connected is set to the ground voltage GND. As a result, the signal SWG rises from the voltage Vn (e.g., −3.5 V) to the ground voltage GND (e.g., 0 V). Note that during the period from time t1 to t2, the signal EP is at “L” and the signal EN is at “H”.

[0200] Moreover, the operation when the high-frequency switch 20 is switched from the on state to the off state is similar to that in the seventh embodiment.

[0201] 8.3 Effects of the Eighth Embodiment According to the eighth embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0202] Furthermore, in the eighth embodiment, when the high-frequency switch 20 is switched from the OFF state to the ON state, i.e., when the signal SWG is switched from the voltage Vn to the voltage Vp, a period (the period from time t1 to t2) during which the signal EP is "L" and the signal EN is "H" is set, so that a current flows from the node to which the source of the nMOS transistor M2 is connected to the terminal TSW via the parasitic diode PD2 present in the nMOS transistor M2 during this period. This makes it possible to raise the signal SWG from the voltage Vn to the ground voltage GND.

[0203] Furthermore, when switching the high-frequency switch 20 from the on state to the off state, as in the seventh embodiment, by setting a period during which the signal EP is at “L” and the signal EN is at “H” (the period from time t3 to t4), the charge of the voltage Vp in the signal SWG can be discharged to the ground voltage GND via the parasitic diode PD1 present in the pMOS transistor M1.

[0204] As described above, in the configuration of the first embodiment shown in FIG. 2, the nMOS transistor M3, the diode D1, the pMOS transistor M4, the diode D2, the pMOS transistor M13, the nMOS transistor M14, the pMOS transistor M15, and the nMOS transistor M16 can be deleted to obtain the configuration of the eighth embodiment.

[0205] 9. Ninth embodiment Next, a semiconductor device according to a ninth embodiment will be described. In the second embodiment, the signal RGN input to the gate of the nMOS transistor M3 in the switch control circuit 10 is a signal corresponding to the signal EN, but in the ninth embodiment, the signal RGN input to the gate of the nMOS transistor M3 is set to a signal corresponding to the signal EP. In the ninth embodiment, a description of the configuration, operation, and effects similar to those of the switch circuit 1 of the second embodiment will be omitted, and the differences will be mainly described.

[0206] 9.1 Configuration of the ninth embodiment FIG. 19 is a circuit diagram showing a configuration of a switch circuit according to the ninth embodiment.

[0207] The switch circuit 1 of the ninth embodiment differs from that of the second embodiment in the configuration of an on / off switching circuit 11f included in a switch control circuit 10. Specifically, this is as follows.

[0208] The on / off switching circuit 11f has the same configuration as the on / off switching circuit 11a shown in FIG. 5 except that the wiring connecting the output terminal of the buffer B4 to the gates of the pMOS transistor M13 and the nMOS transistor M14, the pMOS transistor M4, and the diode D2 are removed and a level shifter LS3 is added.

[0209] A signal EP is input to an input terminal of the level shifter LS3. An output terminal of the level shifter LS3 is connected to the gates of a pMOS transistor M13 and an nMOS transistor M14. The level shifter LS3 converts the signal EP to a voltage level using a power supply voltage VDD and a voltage Vn as power supplies.

[0210] 9.2 Operation of the ninth embodiment FIG. 20 is a circuit diagram showing a part of the operation of the on / off switching circuit 11f in the switch circuit of the ninth embodiment.

[0211] In the ninth embodiment, when the high-frequency switch 20a is switched from the on state to the off state or from the off state to the on state, signals EP and EN similar to those shown in FIG. 3 are supplied.

[0212] In the on / off switching circuit 11a of the second embodiment shown in Fig. 5, when the high frequency switch 20a is switched from the on state to the off state, as shown in Fig. 20(b), a leakage current flows from the power supply voltage node VDD through the diode D1, the nMOS transistor M3, and the parasitic diode PD1 of the pMOS transistor M1 to the node to which the source of the pMOS transistor M1 is connected. This leakage current prevents the voltage of the signal SWG from decreasing when the high frequency switch 20a is switched from the on state to the off state. This causes a delay in switching the high frequency switch 20a from the on state to the off state.

[0213] In the on / off switching circuit 11f of the ninth embodiment, when the high frequency switch 20a is switched from the on state to the off state, the switching of the signal RGN between “H” (for example, VDD) and “L” (for example, Vn) is controlled according to the timing of the signal EP. That is, the switching of the signal RGN from “H” to “L” is matched with the switching timing of the signal EP. This speeds up the time when the signal RGN switches from “H” to “L”, and as shown in FIG. 20(a), the nMOS transistor M3 is turned off to stop the inflow of current from the power supply voltage VDD node to the terminal TSW, and the charge at the terminal TSW is discharged to the node to which the source of the pMOS transistor M1 is connected via the parasitic diode PD1 of the pMOS transistor M1. This eliminates the operation of preventing the voltage of the signal SWG from decreasing, and speeds up the switching speed of the signal SWG from the voltage Vp to the voltage Vn.

[0214] Moreover, the operation when the high-frequency switch 20a is switched from the OFF state to the ON state is the same as in the seventh embodiment.

[0215] 9.3 Effects of the ninth embodiment According to the ninth embodiment, it is possible to provide a semiconductor device that can increase the speed of switching on and off a high-frequency switch.

[0216] Furthermore, in the ninth embodiment, when the high frequency switch 20a is switched from the on state to the off state, i.e., when the signal SWG is switched from the voltage Vp to the voltage Vn, the switching of the signal RGN from "H" to "L" is synchronized with the switching timing of the signal EP. This stops the current flowing from the power supply voltage VDD node to the terminal TSW via the nMOS transistor M3, and speeds up the switching of the signal SWG from the voltage Vp to the voltage Vn. As a result, the high frequency switch 20a can be switched from the on state to the off state at high speed.

[0217] 10.Other The semiconductor device according to the above-described embodiment may take the following forms.

[0218] 1. A first transistor (M1) that is supplied with a first voltage (Vp) higher than a power supply voltage (VDD) and supplies the first voltage to a first terminal (TSW); a second transistor (M2) that is supplied with a second voltage (Vn) lower than a ground voltage (GND) and supplies the second voltage to the first terminal; a third transistor (M3) that is supplied with the power supply voltage and supplies the power supply voltage to the first terminal; a fourth transistor (M4) that is supplied with the ground voltage and supplies the ground voltage to the first terminal; a first level shifter (LS1) that converts the power supply voltage to the first voltage (Vp) and outputs a second signal (RGP) when the first signal (EP) is the power supply voltage; a second level shifter (LS2) that converts the ground voltage to the second voltage (Vn) and outputs a fourth signal (RGN) when the third signal (EN) is the ground voltage; Equipped with When the first voltage is output from the first terminal, supplying the power supply voltage from the third transistor to the first terminal in response to the fourth signal, and thereafter supplying the first voltage from the first transistor to the first terminal in response to the second signal; When the second voltage is output from the first terminal, The semiconductor device supplies the ground voltage to the first terminal from the fourth transistor in response to the second signal, and thereafter supplies the second voltage to the first terminal from the second transistor in response to the fourth signal.

[0219] 2. Further comprising a high frequency switch (20); The high frequency switch includes: A second end (T1) and a third end (T2), a first plurality of transistors connected in series between the second end and the third end; a first plurality of resistance elements connected in series between a gate of a fifth transistor connected to the second end among the first plurality of transistors and the first end, and each resistance element is connected between each gate of the first plurality of transistors; 2. The semiconductor device according to claim 1, comprising:

[0220] 3. Further comprising a fourth terminal (TRN) for outputting the fourth signal; The high frequency switch includes: a second plurality of transistors connected in series between the gate of the fifth transistor and the first terminal; a second plurality of resistive elements connected in series between a gate of a sixth transistor connected to a gate of the fifth transistor among the second plurality of transistors and the fourth terminal, and each resistive element is connected between each gate of the second plurality of transistors; 3. The semiconductor device according to claim 2, further comprising:

[0221] 4. Further comprising a fifth terminal (TRP) for outputting the second signal; The high frequency switch includes: a third plurality of transistors connected in series between the gate of the fifth transistor and the first terminal; a third plurality of resistive elements connected in series between a gate of a seventh transistor connected to a gate of the fifth transistor among the third plurality of transistors and the fifth terminal, and each of the third plurality of resistive elements is connected between each of the gates of the third plurality of transistors; 3. The semiconductor device according to claim 2, further comprising:

[0222] 5. A high frequency switch having a second end and a third end; a fourth terminal (TRN) for outputting the fourth signal; Further equipped with The high frequency switch includes: a first plurality of transistors connected in series between the second end and the third end; a second plurality of transistors and a first plurality of resistive elements respectively connected in parallel between each gate of the first plurality of transistors and the first terminal; a second plurality of resistive elements respectively connected between the gates of the second plurality of transistors and a fourth terminal; 2. The semiconductor device according to claim 1, comprising:

[0223] 6. The semiconductor device according to any one of 1 to 5 above, further comprising a power supply circuit (8) that generates the first voltage and the second voltage.

[0224] 7. The semiconductor device according to claim 6, wherein the power supply circuit includes a charge pump.

[0225] 8. a first diode (D1) connected between a node to which the power supply voltage is supplied and the third transistor; a second diode (D2) connected between the node to which the ground voltage is supplied and the fourth transistor; The semiconductor device according to claim 1 , further comprising:

[0226] 9. The semiconductor device according to claim 1, further comprising a delay circuit (12) that delays a control signal (CNT) and outputs the first signal and the third signal.

[0227] 10. A plurality of switch circuits (1); a delay circuit (12a) for delaying a plurality of control signals corresponding to the plurality of switch circuits; Equipped with Each of the plurality of switch circuits a first transistor to which a first voltage higher than a power supply voltage is supplied and which supplies the first voltage to a first terminal; a second transistor to which a second voltage lower than a ground voltage is supplied and which supplies the second voltage to the first terminal; a third transistor that is supplied with the power supply voltage and supplies the power supply voltage to the first terminal; a fourth transistor to which the ground voltage is supplied and which supplies the ground voltage to the first terminal; a first level shifter that converts the power supply voltage to the first voltage and outputs a second signal when the first signal is the power supply voltage; a second level shifter that converts the ground voltage to the second voltage and outputs a fourth signal when the third signal is the ground voltage; having When the first voltage is output from the first terminal, supplying the power supply voltage from the third transistor to the first terminal in response to the fourth signal, and thereafter supplying the first voltage from the first transistor to the first terminal in response to the second signal; When the second voltage is output from the first terminal, supplying the ground voltage to the first terminal from the fourth transistor in response to the second signal, and thereafter supplying the second voltage to the first terminal from the second transistor in response to the fourth signal; The delay circuit includes: a first circuit that generates a delay signal from the plurality of control signals; and a plurality of logic circuits that generate the first signal and the third signal using each of the plurality of control signals and the delay signal; each of the plurality of logic circuits outputs each of the plurality of control signals as either the first signal or the third signal; Each of the plurality of logic circuits delays each of the plurality of control signals using the delay signal, and outputs each of the delayed control signals as the other of the first signal or the third signal.

[0228] 11. The semiconductor device according to claim 10, wherein the first circuit has a pair of a resistive element and a capacitive element.

[0229] 12. The plurality of control signals are held at a voltage level of either a low level or a high level; The first circuit is a counting circuit that counts the number of transitions of the plurality of control signals from a low level to a high level and from a high level to a low level; a variable resistance element whose resistance value varies depending on the number of transitions counted by the count circuit, 11. The semiconductor device according to claim 10.

[0230] 13. The plurality of control signals are held at a voltage level of either a low level or a high level; the first circuit includes a plurality of flip-flops provided corresponding to the plurality of control signals, a plurality of switch elements and a plurality of resistance elements provided corresponding to the plurality of flip-flops, and a capacitance element; the plurality of resistance elements are connected in series, one end and the other end of each of the plurality of switch elements are connected to one end and the other end of each of the plurality of resistance elements, each of the plurality of flip-flops outputs a fifth signal when each of the plurality of control signals transitions from a low level to a high level or from a high level to a low level; 11. The semiconductor device according to claim 10, wherein each of the plurality of switch elements is set to either a connected state or a cut-off state in response to the fifth signal.

[0231] 14. The semiconductor device according to any one of claims 10 to 13, further comprising a power supply circuit that generates the first voltage and the second voltage.

[0232] The semiconductor device according to the above-described embodiment can be applied to antenna tuning switches for mobile terminals such as mobile phones or smartphones, switches for base stations, phase shift switches, and the like.

[0233] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0234] 1...switch circuit, 2...switch circuit, 3...switch circuit, 4...switch circuit, 5...signal processing circuit, 6...signal processing circuit, 7...control circuit, 8...power supply circuit, 10...switch control circuit, 11...on / off switching circuit, 11a...on / off switching circuit, 11b...on / off switching circuit, 11c...on / off switching circuit, 11d...on / off switching circuit, 11e...on / off switching circuit, 11f...on / off switching circuit, 12...delay circuit, 12a...delay circuit, 12b...delay circuit, 12c...delay circuit, 20...high frequency switch, 20a...high frequency switch, 20b...high frequency switch, 20c...high frequency switch, 20d...high frequency switch, 20e...high frequency switch, B1...buffer, B2...buffer, B3...buffer, B4...buffer, B5...buffer, B6...buffer, D1...diode, D2...diode, LS1...level shifter, LS2...level shifter, LS3...level shifter, M1...p-channel MOS field effect transistor, M2...n-channel MOS field effect transistor, M3...n-channel MOS field effect transistor, M4...p-channel MOS field effect transistor.

Claims

1. a first transistor to which a first voltage higher than a power supply voltage is supplied and which supplies the first voltage to a first terminal; a second transistor to which a second voltage lower than a ground voltage is supplied and which supplies the second voltage to the first terminal; a third transistor that is supplied with the power supply voltage and supplies the power supply voltage to the first terminal; a fourth transistor to which the ground voltage is supplied and which supplies the ground voltage to the first terminal; a first level shifter that converts the power supply voltage to the first voltage and outputs a second signal when a first signal is the power supply voltage; a second level shifter that converts the ground voltage to the second voltage and outputs a fourth signal when the third signal is the ground voltage; Equipped with When the first voltage is output from the first terminal, supplying the power supply voltage from the third transistor to the first terminal in response to the fourth signal, and thereafter supplying the first voltage from the first transistor to the first terminal in response to the second signal; When the second voltage is output from the first terminal, The semiconductor device supplies the ground voltage to the first terminal from the fourth transistor in response to the second signal, and thereafter supplies the second voltage to the first terminal from the second transistor in response to the fourth signal.

2. Further comprising a high frequency switch; The high frequency switch includes: A second end and a third end; a first plurality of transistors connected in series between the second end and the third end; a first plurality of resistance elements connected in series between a gate of a fifth transistor of the first plurality of transistors connected to the second end and the first end, and each resistance element is connected between each gate of the first plurality of transistors; The semiconductor device according to claim 1 .

3. a fourth terminal for outputting the fourth signal; The high frequency switch includes: a second plurality of transistors connected in series between the gate of the fifth transistor and the first terminal; a second plurality of resistive elements connected in series between a gate of a sixth transistor connected to a gate of the fifth transistor among the second plurality of transistors and the fourth end, and each resistive element being connected between each gate of the second plurality of transistors; The semiconductor device according to claim 2 , further comprising:

4. a fifth terminal for outputting the second signal; The high frequency switch includes: a third plurality of transistors connected in series between the gate of the fifth transistor and the first terminal; a third plurality of resistive elements connected in series between a gate of a seventh transistor connected to a gate of the fifth transistor among the third plurality of transistors and the fifth end, and each of the third plurality of resistive elements being connected between the gates of the third plurality of transistors; The semiconductor device according to claim 2 , further comprising:

5. a radio frequency switch having a second end and a third end; a fourth terminal for outputting the fourth signal; Further equipped with The high frequency switch includes: a first plurality of transistors connected in series between the second end and the third end; a second plurality of transistors and a first plurality of resistive elements respectively connected in parallel between each gate of the first plurality of transistors and the first terminal; a second plurality of resistive elements respectively connected between the gates of the second plurality of transistors and a fourth terminal; The semiconductor device according to claim 1 .

6. 6. The semiconductor device according to claim 1, further comprising a power supply circuit that generates the first voltage and the second voltage.

7. 7. The semiconductor device according to claim 6, wherein the power supply circuit includes a charge pump.

8. a first diode connected between a node to which the power supply voltage is supplied and the third transistor; a second diode connected between the node to which the ground voltage is supplied and the fourth transistor; The semiconductor device according to claim 1 , further comprising:

9. The semiconductor device according to claim 1 , further comprising a delay circuit that delays a control signal and outputs the first signal and the third signal.

10. A plurality of switch circuits; a delay circuit for delaying a plurality of control signals corresponding to the plurality of switch circuits; Equipped with Each of the plurality of switch circuits a first transistor to which a first voltage higher than a power supply voltage is supplied and which supplies the first voltage to a first terminal; a second transistor to which a second voltage lower than a ground voltage is supplied and which supplies the second voltage to the first terminal; a third transistor that is supplied with the power supply voltage and supplies the power supply voltage to the first terminal; a fourth transistor to which the ground voltage is supplied and which supplies the ground voltage to the first terminal; a first level shifter that converts the power supply voltage to the first voltage and outputs a second signal when a first signal is the power supply voltage; a second level shifter that converts the ground voltage to the second voltage and outputs a fourth signal when the third signal is the ground voltage; having When the first voltage is output from the first terminal, supplying the power supply voltage from the third transistor to the first terminal in response to the fourth signal, and thereafter supplying the first voltage from the first transistor to the first terminal in response to the second signal; When the second voltage is output from the first terminal, supplying the ground voltage to the first terminal from the fourth transistor in response to the second signal, and thereafter supplying the second voltage to the first terminal from the second transistor in response to the fourth signal; The delay circuit includes: a first circuit that generates a delay signal from the plurality of control signals; and a plurality of logic circuits that generate the first signal and the third signal using each of the plurality of control signals and the delay signal; each of the plurality of logic circuits outputs each of the plurality of control signals as either the first signal or the third signal; Each of the plurality of logic circuits delays each of the plurality of control signals using the delay signal, and outputs each of the delayed control signals as the other of the first signal or the third signal.

11. The semiconductor device according to claim 10 , wherein the first circuit includes a pair of a resistive element and a capacitive element.

12. The plurality of control signals are held at a voltage level of either a low level or a high level, The first circuit is a counting circuit that counts the number of transitions of the plurality of control signals from a low level to a high level and from a high level to a low level; a variable resistance element whose resistance value varies depending on the number of transitions counted by the count circuit, The semiconductor device according to claim 10.

13. The plurality of control signals are held at a voltage level of either a low level or a high level, the first circuit includes a plurality of flip-flops provided corresponding to the plurality of control signals, a plurality of switch elements and a plurality of resistance elements provided corresponding to the plurality of flip-flops, and a capacitance element; the plurality of resistance elements are connected in series, one end and the other end of each of the plurality of switch elements are connected to one end and the other end of each of the plurality of resistance elements, each of the plurality of flip-flops outputs a fifth signal when each of the plurality of control signals transitions from a low level to a high level or from a high level to a low level; The semiconductor device according to claim 10 , wherein each of the plurality of switch elements is set to either a connected state or a cut-off state in response to the fifth signal.

14. 14. The semiconductor device according to claim 10, further comprising a power supply circuit that generates the first voltage and the second voltage.

Images