Printed circuit board

Abstract

To provide a printed circuit board capable of ensuring reliability by improving the adhesion between an electronic component built into a board and an insulating layer.SOLUTION: A printed circuit board according to the present invention includes a plurality of insulating layers 111 having a through portion H1, a plurality of wiring layers 121 respectively arranged on or within the plurality of insulating layers 111, a plurality of via layers 131 each penetrating at least a portion of at least one of the plurality of insulating layers 111 and each connected to at least one of the plurality of wiring layers 121, an electronic component 140 having at least a portion arranged within the through portion H1 and embedded in at least one of the plurality of insulating layers 111, and an insulating film 151 arranged within the plurality of insulating layers 111 and covering at least a portion of a side surface of the electronic component 140 and at least a portion of a wall surface of the through portion H1.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] Due to the trend towards higher circuit density and smaller, thinner electronic products, there has been active research into technologies for embedding electronic components such as semiconductor chips and passive elements into printed circuit boards, and much research is being conducted into related board structures and manufacturing methods.

[0003] On the other hand, when manufacturing a substrate, surface treatment is usually performed to ensure adhesion between the metal layer and the insulating layer, but since the electronic components to be built in are provided separately, it is not easy to modify the surface at the substrate manufacturing stage, which may result in insufficient adhesion between the electronic components and the insulating layer, resulting in reliability problems. Summary of the Invention [Problem to be solved by the invention]

[0004] One of several objects of the present invention is to provide a printed circuit board capable of ensuring reliability by improving the adhesion between electronic components built into the board and an insulating layer. [Means for solving the problem]

[0005] One of the various solutions proposed in the present invention is to form an insulating film that covers at least a part of electronic components, etc., embedded in a substrate during the substrate manufacturing process by using a thin film deposition method such as ALD (Atomic Layer Deposition) or MVD (Molecular Vapor Deposition).

[0006] For example, one example of a printed circuit board may include a plurality of insulating layers having a through portion, a plurality of wiring layers each arranged on or within the plurality of insulating layers, a plurality of via layers each penetrating at least a portion of at least one of the plurality of insulating layers and each connected to at least one of the plurality of wiring layers, an electronic component at least a portion of which is arranged within the through portion and embedded in at least one of the plurality of insulating layers, and an insulating film arranged within the plurality of insulating layers and covering at least a portion of a side surface of the electronic component and at least a portion of a wall surface of the through portion.

[0007] For example, a printed circuit board according to one example may include a plurality of insulating layers, a plurality of wiring layers respectively disposed on or within the plurality of insulating layers, a plurality of via layers each penetrating at least a portion of at least one of the plurality of insulating layers and each connected to at least one of the plurality of wiring layers, an electronic component disposed within the plurality of insulating layers, and an insulating film disposed on the plurality of insulating layers and covering at least a portion of at least one of the plurality of wiring layers and at least a portion of the electronic component. Effect of the Invention

[0008] One of the various effects of the present invention is that it is possible to provide a printed circuit board capable of ensuring reliability by improving the adhesion between the insulating layer and electronic components built into the board. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a printed circuit board. [Figure 4a] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4b]4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4c] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4d] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4e] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4f] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4g] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4h] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4i] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Figure 4j] 4A to 4C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3. [Diagram 5] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 6a] 6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 6b] 6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 6c] 6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 6d] 6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 6e] 6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 6f] 6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 6g]6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 6h] 6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 6i] 6A to 6C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 5. [Figure 7] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 8a] 8A to 8C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 7. [Figure 8b] 8A to 8C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 7. [Figure 8c] 8A to 8C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 7. [Figure 8d] 8A to 8C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 7. [Figure 8e] 8A to 8C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 7. [Figure 8f] 8A to 8C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 7. [Figure 8g] 8A to 8C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0011] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0012] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0013] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0014] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0015] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0016] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0017] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0018] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0019] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0020] Printed Circuit Board FIG. 3 is a cross-sectional view that illustrates an example of a printed circuit board.

[0021] Referring to the drawings, a printed circuit board 100A according to an example includes a plurality of insulating layers 111, 112, 113, 114, 115, a plurality of wiring layers 121, 122, 123, 124 disposed on or within the plurality of insulating layers 111, 112, 113, 114, 115, and a plurality of insulating layers 111, 112, 113, 114, 115, each of which has a plurality of wiring layers 121, 122, 123, 124 that penetrate at least a portion of at least one of the insulating layers 111, 112, 113, 114, 115 and a small number of the wiring layers 121, 122, 123, 124. The insulating layers 111, 112, 113, 114, 115 may include a plurality of via layers 131, 132, 133 each connected to at least one of the via layers 131, 132, 133, an electronic component 140 disposed in the plurality of insulating layers 111, 112, 113, 114, 115, and insulating films 151, 152 disposed in the plurality of insulating layers 111, 112, 113, 114, 115 and covering at least one of the plurality of insulating layers 111, 112, 113, 114, 115, at least one of the plurality of wiring layers 121, 122, 123, 124, and at least a portion of the electronic component 140. The plurality of insulating layers 111, 112, 113, 114, 115 may have a through portion H1, and the electronic component 140 may be at least partially disposed in the through portion H1 and embedded in at least one of the plurality of insulating layers 111, 112, 113, 114, 115. The insulating films 151 and 152 can cover at least a portion of each of the side surface of the electronic component 140 and the wall surface of the through hole H1.

[0022] The multiple insulating layers 111, 112, 113, 114, 115 may include a first insulating layer 111 having a through portion H1, a second insulating layer 112 covering at least a portion of each of the first insulating layer 111 and the electronic component 140 and filling at least a portion of the through portion H1, and a third insulating layer 113 arranged on the lower surface of the second insulating layer 112. The through portion H1 may include a through cavity H1 penetrating the first insulating layer 111. The multiple wiring layers 121, 122, 123, 124 may include a first wiring layer and a second wiring layer 121, 122 arranged on the upper surface and the lower surface of the first insulating layer 111, respectively, a third wiring layer 123 arranged on the upper surface of the second insulating layer 112, and a fourth wiring layer 124 arranged on the lower surface of the third insulating layer 113. The multiple via layers 131, 132, 133 may include a first via layer 131 penetrating at least a portion of the first insulating layer 111, a second via layer 132 penetrating at least a portion of the second insulating layer 112, and a third via layer 133 penetrating at least a portion of the third insulating layer 113.

[0023] The electronic component 140 may have a back surface opposite to the front surface on which the pads P are disposed, and the electronic component 140 may be disposed such that the front surface faces downward. The insulating films 151 and 152 may include a first insulating film and a second insulating film 151 and 152. The first insulating film and the second insulating film 151 and 152 may be connected to each other. The first and second insulating films 151 and 152 may be coating layers formed using a thin film deposition method, for example, an ALD (Atomic Layer Deposition) method, an MVD (Molecular Vapor Deposition) method, or the like. For example, the first insulating film and the second insulating film 151 and 152 may each include a thin film having a thickness of less than 100 nm, for example, a thickness of about 1 nm to 10 nm, and the thin film may be an alumina film, for example, an oxide film containing Al2O3, but is not limited thereto, and may be an oxide film containing TiO2, ZnO, SiO2, or the like. The first insulating film 151 can cover at least a portion of each of the upper and lower surfaces of the first insulating layer 111, the wall surface of the through cavity H1, the upper surface and side surface of the first wiring layer 121, the side surface of the second wiring layer 122, and the front surface, back surface, and side surface of the electronic component 140 with a substantially constant thickness. The second insulating film 152 can cover at least a portion of each of the lower surface of the second insulating layer 112 and the lower surface of the second wiring layer 122 with a substantially constant thickness. The second insulating layer 112 can cover at least a portion of the first insulating film 151, and the third insulating layer 113 can cover at least a portion of the second insulating film 152.

[0024] In this way, in the printed circuit board 100A according to an example, the first insulating film 151 and the second insulating film 152 can cover at least a part of the electronic component 140, the first insulating layer 111, the wall surface of the through cavity H1, and the first wiring layer 121 and the second wiring layer 122, and can be disposed at least partially between them and the second insulating layer 112 and the third insulating layer 113. In this case, the first insulating film 151 and the second insulating film 152 can be used as an adhesive auxiliary layer because they have excellent adhesion to the second insulating layer 112 and the third insulating layer 113. As a result, the adhesion between the electronic component 140, the first insulating layer 111, the wall surface of the through cavity H1, the first wiring layer 121 and the second wiring layer 122, etc., and the second insulating layer 112 and the third insulating layer 113 can be improved, and reliability can be ensured.

[0025] The components of the example printed circuit board 100A are described in more detail below with reference to the drawings.

[0026] Each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as CCL (Copper Clad Laminate), ABF (Ajinomoto Build-up Film), or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). As a non-limiting example, the first insulating layer 111 may include CCL, and each of the second insulating layer 112 and the third insulating layer 113 may include ABF or PPG, but is not limited thereto. The first insulating layer 111 may be a core layer, and the second insulating layer 112 and the third insulating layer 113 may be build-up layers. The first insulating layer 111 and the second insulating layer 112 may be separated from each other by a second insulating film 152.

[0027] The fourth insulating layer and the fifth insulating layer 114, 115 may each include, but are not limited to, a liquid or film type solder resist, and may also include other types of insulating materials such as ABF. The fourth insulating layer and the fifth insulating layer 114, 115 may have openings that expose at least a part of the third wiring layer and the fourth wiring layer 123, 124, respectively, and a surface treatment layer may be formed on the exposed patterns as necessary.

[0028] Each of the first to fourth wiring layers 121, 122, 123, and 124 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first to fourth wiring layers 121, 122, 123, and 124 may perform various functions according to the design. For example, the first to fourth wiring layers 121, 122, 123, and 124 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the first to fourth wiring layers 121, 122, 123, and 124 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, the first to fourth wiring layers 121, 122, 123, and 124 may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). It may include a sputtering layer instead of the electroless plating layer (or chemical copper), or it may include both.

[0029] Each of the first to third via layers 131, 132, and 133 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. The first via layer 131 may include a through via. The second and third via layers 132 and 133 may include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along the wall surface of a via hole. The microvia may be arranged in a stacked type and / or staggered type. The vias of the first to third via layers 131, 132, and 133 may perform various functions depending on the design of the layer. For example, the via layers may include ground vias, power vias, signal vias, etc. The first to third via layers 131, 132, 133 may each include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The first via layer 131 may have a cylindrical or hourglass shape, and the second and third via layers 132, 133 may have tapered shapes in opposite directions, but are not limited to this.

[0030] The electronic component 140 may be a chip-type component, and may be an active component or a passive component. For example, the electronic component 140 may be an active component such as a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory; an application processor chip such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller; or a logic chip such as an analog-to-digital converter or an application-specific IC (ASIC). Alternatively, the electronic component 140 may be a passive component such as a high-frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-firing ceramics (LTCC), an electro-magnetic interference (EMI) filter, or a multi-layer ceramic capacitor (MLCC). In the case of an active component, the front surface on which the pad P is disposed may be an active surface, and the opposite back surface may be an inactive surface. In the case of a passive component, an external electrode may be disposed instead of the pad P, and the external electrode may include a first electrode and a second electrode disposed at both ends in the length direction, but is not limited thereto, and the external electrode may be formed in various forms.

[0031] As described above, the first insulating film and the second insulating film 151, 152 may each include a thin film having a thickness of less than 100 nm, for example, a thickness of about 1 nm to 10 nm. The thin film may be an alumina film, for example, an oxide film containing Al2O3, as described above, but is not limited thereto, and may be an oxide film containing TiO2, ZnO, SiO2, etc. The first insulating film and the second insulating film 151, 152 may substantially include the same material as each other. The first insulating film and the second insulating film 151, 152 may be a first adhesive auxiliary layer and a second adhesive auxiliary layer, respectively. If necessary, an insulating film may be further formed on the upper surface of the second insulating layer 112 and on the lower surfaces of the third insulating layers 112, 113, and these insulating films may be at least partially disposed between the second insulating layer and the third insulating layer 112, 113 and the third wiring layer and the fourth wiring layer 123, 124, respectively, and may be used as an adhesive auxiliary layer.

[0032] 4a to 4j are cross-sectional views illustrating steps of a manufacturing process for the printed circuit board of FIG.

[0033] 4a, a first insulating layer 111 is prepared using CCL or the like, and a through cavity H1, a first wiring layer and a second wiring layer 121, 122, and a first via layer 131 are formed in the first insulating layer 111. The through cavity H1 can be formed using mechanical drilling, laser processing, blasting, or the like. A via hole for the first via layer 131 can also be formed using mechanical drilling, laser processing, or the like. The first wiring layer and the second wiring layer 121, 122, and the first via layer 131 can be formed by a circuit formation process such as AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), TT (Tenting), or the like.

[0034] 4b, a tape 210 is attached to the underside of the first insulating layer 111. The tape 210 may be attached to the underside of the second wiring layer 122. The tape 210 may close the lower portion of the through cavity H1.

[0035] 4c, the electronic component 140 is placed in the through cavity H1. If the electronic component 140 is an active component, the electronic component 140 may be placed face-down so that the front surface on which the pads P are arranged is attached to the tape 210.

[0036] 4d, a first insulating film 151 is formed. The first insulating film 151 may be formed on the tape 210 to cover the first insulating layer 111, the first wiring layer 121, the second wiring layer 122, and at least a portion of the electronic component 140. The first insulating film 151 may be formed using a thin film deposition method such as ALD or MVD as described above.

[0037] 4e, a first insulating layer 111, a first wiring layer 121 and a second wiring layer 122, and a second insulating layer 112 in which an electronic component 140 is embedded are formed on a tape 210. The second insulating layer 112 may be formed by a lamination process in a state where it is attached to a first film 220 including PET (PolyEthylene Terephthalate) or the like.

[0038] Referring to FIG. 4f, the tape 210 is removed.

[0039] Referring to FIG. 4g, the second insulating film 152 is formed. The second insulating film 152 may be formed in the area where the tape 210 has been removed. The second insulating film 152 may be formed to cover at least a portion of each of the second insulating layer 112 and the second wiring layer 122. If necessary, the second insulating film 152 may be formed to further cover at least a portion of the pad P. When forming the second insulating film 152, an insulating film may also be formed on the upper surface of the first film 220. The second insulating film 152 may also be formed using a thin film deposition method such as ALD or MVD as described above.

[0040] 4h, a third insulating layer 113 is formed on the second insulating layer 152 to cover the second insulating layer 152. The third insulating layer 113 may also be formed by a lamination process in a state where it is attached to a second film 230 including PET or the like.

[0041] Referring to FIG. 4i, the first and second films 220, 230 are removed.

[0042] Referring to FIG. 4j, the third wiring layer 123, 124 and the second via layer 132, 133 are formed on the second insulating layer 112, 113. The fourth insulating layer 114, 115 are formed using solder resist or ABF as the outermost layer, and openings are formed in the fourth insulating layer 114, 115, respectively, as necessary. The via holes for the second via layer 132, 133 can be formed using a mechanical drill, laser processing, etc. The via holes for the second via layer 132, 133 can penetrate a part of the first insulating layer 151, 152, respectively, so that a part of the first wiring layer 121, 122 can be exposed from the first insulating layer 151, 152, respectively. In addition, the via hole for the second via layer 133 can penetrate another part of the pad P to expose the pad P from the second insulating film 152. The third and fourth wiring layers 123 and 124 and the second and third via layers 132 and 133 can be formed by the circuit formation process such as the above-mentioned AP, SAP, MSAP, and TT.

[0043] The printed circuit board 100A according to the above-mentioned embodiment can be manufactured through a series of processes, and the other repeated explanations will be omitted.

[0044] FIG. 5 is a cross-sectional view that illustrates a schematic diagram of another example of a printed circuit board.

[0045] Referring to the drawings, the printed circuit board 100B according to another example may be arranged such that, when the electronic component 140 is an active component, the front surface on which the pads P are arranged faces upward, as compared with the printed circuit board 100A according to the above example. Therefore, the first insulating film 151 may cover at least a portion of each of the upper and lower surfaces of the first insulating layer 111, the wall surface of the through cavity H1, the upper and side surfaces of the first wiring layer 121, the side surfaces of the second wiring layer 122, and the front and side surfaces of the electronic component 140. Also, the second insulating layer 112 may cover at least a portion of the first insulating film 151. Meanwhile, the second insulating film 152 may be omitted as necessary. In this way, even when the electronic component 140 is arranged in a face-up form, the application of the first insulating film 151 can improve adhesion, and as a result, reliability can be improved. Since other contents are substantially the same as those described above, repeated explanations will be omitted.

[0046] 6a to 6i are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG.

[0047] Referring to FIG. 6a, as described above, a first insulating layer 111 is prepared using CCL or the like, and a through cavity H1, a first wiring layer and a second wiring layer 121, 122, and a first via layer 131 are formed in the first insulating layer 111.

[0048] Referring to FIG. 6b, tape 210 is applied to the underside of the first insulating layer 111 as described above.

[0049] 6c, the electronic component 140 is placed in the through cavity H1. At this time, if the electronic component 140 is an active component, the electronic component 140 may be placed in a face-up form so that the back surface of the electronic component 140 is attached to the tape 210.

[0050] 6d, a first insulating film 151 is formed. The first insulating film 151 may be formed to cover at least a portion of each of the first insulating layer 111, the first and second wiring layers 121 and 122, the front and side surfaces of the electronic component 140, and the wall surfaces of the through cavity H1. If necessary, the first insulating film 151 may be formed to further cover at least a portion of the pad P. The first insulating film 151 may be formed using a thin film deposition method such as ALD or MVD as described above.

[0051] 6e, the second insulating layer 112 is formed. The second insulating layer 112 may be formed to cover at least a portion of each of the first insulating layer 111, the first wiring layer 121 and the second wiring layer 122, the electronic component 140, and the first insulating film 151. The second insulating layer 112 may be formed by a lamination process in a state where it is attached to the first film 220 including PET or the like as described above.

[0052] Referring to FIG. 6f, the tape 210 is removed.

[0053] 6g, a third insulating layer 113 is formed in the area where the tape 210 has been removed. The third insulating layer 113 may be formed to cover at least a portion of the lower surface of each of the second insulating layer 112 and the second wiring layer 122. The third insulating layer 113 may also be formed by a lamination process in a state where it is attached to the second film 230 including PET or the like.

[0054] Referring to FIG. 6h, the first and second films 220, 230 are removed.

[0055] Referring to FIG. 6i, as described above, the third wiring layer 123 and the fourth wiring layer 124 and the second via layer 132 and the third via layer 133 are formed in the second insulating layer 112 and the third insulating layer 113. In addition, the fourth insulating layer 114 and the fifth insulating layer 115 are formed using solder resist or ABF as the outermost layer, and openings are formed in the fourth insulating layer 114 and the fifth insulating layer 115, respectively, as necessary. The via holes for the second via layer 132 and the third via layer 133 can be formed using a mechanical drill, laser processing, or the like. The via hole for the second via layer 132 can penetrate a part of the first insulating layer 151, so that each part of the first wiring layer 121 and the pad P can be exposed from the first insulating layer 151. The third wiring layer 123 and the fourth wiring layer 124 and the second via layer 132 and the third via layer 133 can be formed by the above-mentioned circuit formation process, or the like.

[0056] Through a series of processes, the printed circuit board 100B according to the above-mentioned embodiment can be manufactured, and the other repeated explanations will be omitted.

[0057] FIG. 7 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0058] Referring to the drawings, a printed circuit board 100C according to yet another example differs from the printed circuit board 100A according to the above-mentioned example and the printed circuit board 100B according to another example in that the through portion H2 penetrates not the first insulating layer 111 but at least one of the multiple second insulating layers 112a, 112b, 112c, for example the 2-1 insulating layer and the 2-2 insulating layer 112a, 112b, and includes a blind cavity H2 having a stopper layer M disposed on the bottom surface. The multiple insulating layers 111, 112a, 112b, 112c, 113a, 113b, 113c, 114, 115 may include a first insulating layer 111, multiple second insulating layers 112a, 112b, 112c arranged on the upper surface of the first insulating layer 111 and having a through portion H2, multiple third insulating layers 113a, 113b, 113c arranged on the lower surface of the first insulating layer 111, and a fourth insulating layer and a fifth insulating layer 114, 115 arranged on the uppermost and lowermost sides, respectively. The multiple wiring layers 121, 122, 123a, 123b, 123c, 124a, 124b, 124c may include a first wiring layer and a second wiring layer 121, 122 respectively arranged on the upper and lower surfaces of the first insulating layer 111, a multiple number of third wiring layers 123a, 123b, 123c respectively arranged on the multiple second insulating layers 112a, 112b, 112c, and a multiple number of fourth wiring layers 124a, 124b, 124c respectively arranged on the multiple third insulating layers 113a, 113b, 113c. The via layers 131, 132a, 132b, 132c, 133a, 133b, 133c may include a first via layer 131 penetrating at least a portion of the first insulating layer 111, a plurality of second via layers 132a, 132b, 132c penetrating at least a portion of each of the plurality of second insulating layers 112a, 112b, 112c, and a plurality of third via layers 133a, 133b, 133c penetrating at least a portion of the plurality of third insulating layers 113a, 113b, 113c. The blind cavity H2 may penetrate at least one of the plurality of second insulating layers 112a, 112b, 112c, for example, the 2-1 insulating layer and the 2-2 insulating layer 112a, 112b. The 2-3 insulating layer 112c may fill at least a portion of the blind cavity H2. The first wiring layer 121 may include a stopper layer M that provides the bottom surface of the blind cavity H2.When the electronic component 140 is an active component, the electronic component 140 may be disposed such that the front surface on which the pads P are disposed faces upward. For example, the electronic component 14 may have a back surface attached to the stopper layer M using an adhesive such as DAF (Die Attach Film). The insulating films 151 and 153 may include a first insulating film and a third insulating film 151 and 153 disposed apart from each other. The first insulating film 151 may cover at least one of the plurality of second insulating layers 112a, 112b, and 112c, for example, an upper surface of the 2-2 insulating layer 112b, a wall surface of the blind cavity H2, an upper surface of the stopper layer M, at least one of the third wiring layers 123a, 123b, and 123c, for example, an upper surface and a side surface of the 3-2 wiring layer 123b, and at least a portion of each of the front surface and side surface of the electronic component 140. The third insulating film 153 can cover at least one of the plurality of third insulating layers 113a, 113b, 113c, for example, the lower surface of the 3-2 insulating layer 113b, and at least one of the plurality of fourth wiring layers 124a, 124b, 124c, for example, at least a part of the lower surface and side surface of the 4-2 wiring layer 124b. At least another of the plurality of second insulating layers 112a, 112b, 112c, for example, the 2-3 insulating layer 112c, can cover at least a part of the first insulating film 151. At least another of the plurality of third insulating layers 113a, 113b, 113c, for example, the 3-3 insulating layer 113c, can cover at least a part of the third insulating film 153. Other contents are substantially the same as those described above, so repeated explanations will be omitted.

[0059] 8a to 8g are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG.

[0060] 8a, a first insulating layer 111 is prepared using CCL or the like, and a first wiring layer and a second wiring layer 121, 122 and a first via layer 131 are formed in the first insulating layer 111. A via hole for the first via layer 131 can be formed using a mechanical drill, laser processing, or the like. The first wiring layer and the second wiring layer 121, 122 and the first via layer 131 can be formed by a circuit formation process such as AP, SAP, MSAP, TT, or the like. The first wiring layer 121 can include a stopper layer M. The stopper layer M can be formed together by a circuit formation process.

[0061] Referring to FIG. 8b, in the build-up process, the 2-1 and 2-2 insulating layers 112a, 112b, the 3-1 and 3-2 insulating layers 113a, 113b, the 3-1 and 3-2 wiring layers 123a, 123b, the 4-1 and 4-2 wiring layers 124a, 124b, and the 2-1 and 2-2 via layers 132a, 132b, and the 3-1 and 3-2 via layers 133a, 133b are formed on both sides of the first insulating layer 111, respectively. The 2-1 and 2-2 insulating layers 112a and 112b can be formed by a lamination process, and the 3-1 and 3-2 wiring layers 123a and 123b, the 4-1 and 4-2 wiring layers 124a and 124b, the 2-1 and 2-2 via layers 132a and 132b, and the 3-1 and 3-2 via layers 133a and 133b can be formed by the circuit formation process described above. The via holes can be formed by mechanical drilling or laser processing.

[0062] Referring to Fig. 8c, a blind cavity H2 is formed. The blind cavity H2 can be formed by using a stopper layer M. For example, the blind cavity H2 can be formed by blasting. However, the method is not limited to this, and it goes without saying that the blind cavity H2 can be formed by mechanical drilling, laser processing, etching, or the like.

[0063] 8d, the electronic component 140 is placed in the blind cavity H2. If the electronic component 140 is an active component, the electronic component 140 may be placed face-up such that the pads P face upward. For example, the back surface of the electronic component 140 may be attached to the upper surface of the stopper layer M using an adhesive or the like.

[0064] Referring to FIG. 8e, a first insulating film and a third insulating film 151, 153 are formed. The first insulating film 151 may be formed to cover at least a portion of each of the 2-2 insulating layer 112b, the 3-2 wiring layer 123b, the electronic component 140, the pad P, the wall surface of the blind cavity H2, and the stopper layer M. The third insulating film 153 may cover at least a portion of each of the 3-2 insulating layer 113b and the 4-2 wiring layer 124b. The first insulating film and the third insulating film 151, 153 may be formed by using a thin film deposition method such as ALD or MVD as described above.

[0065] 8f, a second-third insulating layer 112c and a third-third insulating layer 113c are formed on the first insulating layer 151 and the third insulating layer 153, respectively. The second-third insulating layer 112c and the third-third insulating layer 113c may be formed by a lamination process.

[0066] 8g, the 3-3 wiring layer and the 4-3 wiring layer 123c, 124c and the 2-3 via layer and the 3-3 via layer 132c, 133c are formed in the 2-3 insulating layer 112c and the 3-3 insulating layer 113c. In addition, the 4th insulating layer and the 5th insulating layer 114, 115 are formed using solder resist or ABF as the outermost layer, and openings are formed in the 4th insulating layer and the 5th insulating layer 114, 115, respectively, as necessary. The via holes for the 2-3 via layer and the 3-3 via layer 132c, 133c can be formed using a mechanical drill, laser processing, or the like. The via holes for the 2-3 via layer and the 3-3 via layers 132c and 133c can penetrate a part of the first insulating film and the third insulating film 151 and 153, respectively, and can expose a part of the 3-2 wiring layer and the 4-2 wiring layer 123b and 124b from the first insulating film and the third insulating film 151 and 153. The via hole for the 3-3 via layer 133c can penetrate another part of the third insulating film 153 and can expose a part of the pad P from the third insulating film 153. The 3-3 wiring layer and the 4-3 wiring layer 123c and 124c and the 2-3 via layer and the 3-3 via layer 132c and 133c can be formed by the circuit formation process such as the above-mentioned AP, SAP, MSAP, and TT.

[0067] The printed circuit board 100C according to the above-mentioned embodiment can be manufactured through a series of processes, and the other repeated explanations will be omitted.

[0068] In the present invention, "substantially" can be determined by taking into account process errors, positional deviations, measurement errors, etc. that occur in the manufacturing process. For example, "line width, interval, thickness, height, etc., substantially have a specific value" can include not only the case where the line width, interval, thickness, height, etc. have the specific value, but also the case where the line width, interval, thickness, height, etc. have a similar value. Furthermore, "substantially coplanar" can include not only the case where the line width, interval, thickness, height, etc. are on the same plane, but also the case where the line width, interval, thickness, height, etc. are on the same plane.

[0069] In the present invention, the meaning of "on a cross section" can mean the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is viewed from a side, and the meaning of "on a plane" can mean the planar shape when an object is cut horizontally, or the planar shape when an object is viewed from a top view or a bottom view.

[0070] In the present invention, for convenience, terms such as "lower side, lower part, bottom surface" are used to mean a downward direction based on a cross section of a drawing, and terms such as "upper side, upper part, top surface" are used to mean the opposite direction. Also, terms such as "side, lateral surface" are used to mean a direction perpendicular to the top surface and bottom surface. However, these are definitions of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of such directions, and the concepts of up / down can be changed at any time.

[0071] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0072] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0073] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0074] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060:Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140: Speaker 100A, 100B, 100C: Printed circuit boards 111, 112, 113, 114, 115, 112a, 112b, 112c, 113a, 113b, 113c: insulating layer 121, 122, 123, 124, 123a, 123b, 123c, 124a, 124b, 124c: Wiring layer 131, 132, 133, 132a, 132b, 132c, 133a, 133b, 133c: via layers 140: Electronic parts P: Pad 150, 151, 152, 153: insulating film 210: Tape 220, 230: Film H1: Penetration (penetration cavity) H2: Penetration (blind cavity) M: Stopper layer

Claims

1. A plurality of insulating layers having through-holes; A plurality of wiring layers disposed on or within the plurality of insulating layers, respectively; a plurality of via layers each penetrating at least a portion of at least one of the plurality of insulating layers and each connected to at least one of the plurality of wiring layers; an electronic component at least a portion of which is disposed within the through-hole and embedded in at least one of the insulating layers; an insulating film disposed within the plurality of insulating layers and covering at least a portion of a side surface of the electronic component and at least a portion of a wall surface of the through portion.

2. The printed circuit board according to claim 1 , wherein the insulating film covers at least a part of the side surface of the electronic component and at least a part of the wall surface of the through portion with a substantially constant thickness.

3. The insulating film includes an oxide film having a thickness of less than 100 nm, The oxide film is Al ２ O ３ , TiO ２ , ZnO, and SiO ２ The printed circuit board of claim 2 , comprising at least one of:

4. the electronic component has a front surface on which pads are arranged and a back surface opposite the front surface; The printed circuit board of claim 1 , wherein the insulating film further covers at least a portion of a front surface of the electronic component.

5. The printed circuit board according to claim 4 , wherein the insulating film further covers at least a portion of at least one of a plurality of wiring layers.

6. The printed circuit board of claim 5 , wherein the insulating film contacts at least a portion of at least one of the plurality of via layers.

7. the plurality of insulating layers include a first insulating layer having the through portion, a second insulating layer covering at least a portion of the first insulating layer and the electronic component and filling at least a portion of the through portion, and a third insulating layer disposed on a lower surface of the second insulating layer; the plurality of wiring layers include a first wiring layer and a second wiring layer respectively disposed on an upper surface and a lower surface of the first insulating layer, a third wiring layer disposed on the upper surface of the second insulating layer, and a fourth wiring layer disposed on the lower surface of the third insulating layer; the plurality of via layers include a first via layer penetrating at least a portion of the first insulating layer, a second via layer penetrating at least a portion of the second insulating layer, and a third via layer penetrating at least a portion of the third insulating layer; The printed circuit board of claim 4 , wherein the penetration comprises a penetration cavity that penetrates the first insulating layer.

8. The electronic components are arranged so that the front surface faces downward, The insulating layer includes a first insulating layer and a second insulating layer connected to each other, the first insulating film covers at least a portion of each of an upper surface and a lower surface of the first insulating layer, a wall surface of the through cavity, an upper surface and a side surface of the first wiring layer, a side surface of the second wiring layer, and a front surface, a back surface, and a side surface of the electronic component; the second insulating film covers at least a part of a lower surface of the second insulating layer and a part of a lower surface of the second wiring layer; the second insulating layer covers at least a portion of the first insulating film; The printed circuit board according to claim 7 , wherein the third insulating layer covers at least a portion of the second insulating layer.

9. The electronic component is arranged so that the front surface faces upward, the insulating film covers at least a portion of each of an upper surface and a lower surface of the first insulating layer, a wall surface of the through cavity, an upper surface and a side surface of the first wiring layer, a side surface of the second wiring layer, and a front surface and a side surface of the electronic component; The printed circuit board of claim 7 , wherein the second insulating layer covers at least a portion of the insulating film.

10. the plurality of insulating layers include a first insulating layer, a plurality of second insulating layers disposed on an upper surface of the first insulating layer and having the through portion, and a plurality of third insulating layers disposed on a lower surface of the first insulating layer; the plurality of wiring layers include a first wiring layer and a second wiring layer respectively disposed on an upper surface and a lower surface of the first insulating layer, a plurality of third wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of fourth wiring layers respectively disposed on the plurality of third insulating layers; the plurality of via layers include a first via layer penetrating at least a portion of the first insulating layer, a plurality of second via layers penetrating at least a portion of each of the plurality of second insulating layers, and a plurality of third via layers penetrating at least a portion of each of the plurality of third insulating layers; The printed circuit board of claim 4 , wherein the penetration portion comprises a blind cavity penetrating at least one of the second insulating layers.

11. The electronic components are arranged so that the front surface faces upward, the insulating layer includes a first insulating layer and a third insulating layer spaced apart from each other; the first insulating film covers an upper surface of at least one of the second insulating layers, a wall surface of the blind cavity, an upper surface and a side surface of at least one of the third wiring layers, and at least a part of a front surface and a side surface of the electronic component; the third insulating film covers at least a part of a lower surface of at least one of the plurality of third insulating layers and at least a part of a lower surface and a side surface of at least one of the plurality of fourth wiring layers; At least one other of the plurality of second insulating layers covers at least a portion of the first insulating film, The printed circuit board according to claim 10 , wherein at least one other of the plurality of third insulating layers covers at least a portion of the third insulating film.

12. the first wiring layer includes a stopper layer; the blind cavity includes the stopper layer as a bottom surface; the back surface of the electronic component is attached to the stopper layer; The printed circuit board according to claim 11 , wherein the first insulating film further covers at least a portion of an upper surface of the stopper layer.

13. A plurality of insulating layers; A plurality of wiring layers disposed on or within the plurality of insulating layers, respectively; a plurality of via layers each penetrating at least a portion of at least one of the plurality of insulating layers and each connected to at least one of the plurality of wiring layers; an electronic component disposed within the plurality of insulating layers; an insulating film disposed within the plurality of insulating layers and covering at least a portion of at least one of the plurality of wiring layers and at least a portion of the electronic component.

14. 14. The printed circuit board according to claim 13, wherein the insulating film is disposed with a substantially constant thickness between at least one of the plurality of insulating layers and at least one of the plurality of wiring layers, and between at least one of the plurality of insulating layers and the electronic component.

15. 15. The printed circuit board of claim 14, wherein the insulating film comprises an alumina film having a thickness of less than 100 nm.

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