Diode wafer and method for manufacturing processed wafer

Abstract

To provide high-quality diode wafers and a method for manufacturing processed wafer.SOLUTION: A method determines whether a plurality of raw wafers meet a manufacturing specification. If it is determined that the raw wafer meets the manufacturing specification, the raw wafer is determined as a high-level raw wafer. If it is determined that the raw wafer does not meet the manufacturing specification, the raw wafer is determined as a low-level raw wafer. Next, the method, calculates a ratio of the quantity of low-level raw wafers having problems related to crystal orientation pits to the quantity of all low-level raw wafers, and determines whether this ratio is greater than a predetermined value. If it is determined that the ratio is not greater than the predetermined value, the method removes a partial structure of each of the low-level raw wafers, and smooths the surface of each of the low-level raw wafers. Finally, the method forms a diode structure on the smoothed low-level raw wafer to obtain a diode wafer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a wafer, and more particularly to a method for manufacturing a diode wafer and a processed wafer. [Background technology]

[0002] In the semiconductor process, wafers are manufactured from ingots. First, an appropriate material is selected to manufacture an ingot. Common materials include silicon, gallium arsenide, etc. The selected material is put into a high-temperature melting furnace to melt. The temperature and gas conditions of the melting furnace must be properly controlled so that the material is melted uniformly and reaches the desired purity. A crystal called a "seed crystal" (usually single crystal silicon) is gently put into the molten material and slowly raised. During the rising process, the crystal grabs the seed crystal from the molten material and forms one long ingot. During the process of pulling out the ingot, it is gradually cooled to form a single crystal structure. The cooling speed and temperature control during the process are important for the quality of the ingot, ensuring the purity and integrity of the ingot. After cooling the ingot, it is cut to form wafers of the desired diameter. Cutting is usually performed using a diamond cutter or other cutting tools. After dicing, the wafers are chemically or mechanically treated to remove surface residues, contamination, and defects, making the surface flat and clean. The wafers are then given a mirror finish to further improve the surface flatness and optical quality. Finally, the produced wafers are cleaned to remove any residues and contamination. The wafers are then inspected and tested to meet certain quality standards. Summary of the Invention [Problem to be solved by the invention]

[0003] In the semiconductor manufacturing industry, A-grade wafers and B-grade wafers are definitions of quality and specifications for wafers. These definitions are usually achieved through consultations between semiconductor manufacturers, the International Organization for Standardization, and customers. In general, A-grade wafers usually have high quality standards in terms of surface flatness, uniformity of wafer thickness, perfection of crystal lattice structure, etc. The quality standards of B-grade wafers are relatively low, and they are usually used for general applications and do not require very high performance and reliability. A-grade wafers have low defect density, that is, there are few defects on the surface or in the volume of the wafer. B-grade wafers have high defect density, which means there may be many defects on the surface or in the volume of the wafer. A-grade wafers have strict specification control in terms of size, wafer thickness, wafer flatness, crystal lattice orientation, etc., to ensure process consistency and repeatability. B-grade wafers have relatively loose specification control in terms of size, flatness, crystal lattice orientation, etc., which is not as strict as A-grade wafers. Generally, processed wafers include low-level wafers, medium-level wafers, and high-level wafers. However, the market price of high-level wafers has not fallen easily. For example, diode wafers include low-level diode wafers, mid-level diode wafers, and high-level diode wafers. Due to the selling price of the wafers, many low-level diode wafers use low-quality A-grade wafers, which are of poor quality. In addition, many mid-level diode wafers use high-quality A-grade wafers, but due to the difference in substrate cost, they cannot compete with mid / low-level diode wafers.

[0004] Therefore, the present inventors believed that the above-mentioned drawbacks could be improved, and as a result of extensive research, they came to propose the manufacturing method of the diode wafer and processed wafer of the present invention, which effectively improves the above-mentioned problems through rational design.

[0005] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a manufacturing method for a diode wafer and a processed wafer that can produce high-quality diode wafers and processed wafers at low cost. [Means for solving the problem]

[0006] According to one aspect of the present invention, a method for manufacturing a diode wafer includes processing a plurality of raw wafers obtained by slicing an ingot, the method for manufacturing a diode wafer includes the steps of: determining whether the plurality of raw wafers meet a manufacturing specification; if it is determined that the raw wafers meet a manufacturing specification, the raw wafers are classified as high-level raw wafers; if it is determined that the raw wafers do not meet a manufacturing specification, the raw wafers are classified as low-level raw wafers, and the number of the low-level raw wafers is multiple; calculating a ratio of the number of the low-level raw wafers having problems related to crystal oriented pits (COP) to the number of all the low-level raw wafers, and determining whether the ratio is greater than a predetermined value; if it is determined that the ratio is greater, terminating; if it is determined that the ratio is not greater, removing a partial structure of each of the low-level raw wafers, the partial structure having a fixed thickness; smoothing a surface of each of the low-level raw wafers from which the structure has been removed; and forming a plurality of diode structures on each of the smoothed low-level raw wafers to obtain a diode wafer.

[0007] In addition, in the manufacturing method of the diode wafer according to the present invention, the manufacturing specification items include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth mode, wafer size, wafer surface, metal particle residual concentration, total thickness deviation, total indicator reading, wafer warpage, partial total indicator reading, and dust count.

[0008] In addition, in the method for manufacturing a diode wafer according to the present invention, the defects include chipping, cracks, excessive laser engraving, scratches, stains, and tears in the crystal lattice.

[0009] In addition, in the manufacturing method of a diode wafer according to the present invention, in the step of removing each partial structure of a low-level raw wafer, a low-level raw wafer having a thickness greater than a predetermined value is selected, and each partial structure of the selected low-level raw wafer is removed.

[0010] In addition, in the method for manufacturing a diode wafer according to the present invention, an etching process and a mirror finishing process are sequentially performed on each surface of the lower-level raw wafer from which the structures have been removed, to smooth the surface of each of the lower-level raw wafers from which the structures have been removed.

[0011] In addition, in the method for manufacturing a diode wafer according to the present invention, a grinding process and a mirror finishing process are sequentially performed on each surface of the lower-level raw wafer from which the structures have been removed, to smooth the surface of each of the lower-level raw wafers from which the structures have been removed.

[0012] In addition, in the method for manufacturing a diode wafer according to the present invention, the method for manufacturing a diode wafer further includes a step of roughening a surface of each of the planarized low-level raw wafers, and in the step of forming a plurality of diode structures on each of the planarized low-level raw wafers to obtain a diode wafer, a plurality of diode structures are formed on each of the roughened low-level raw wafers to obtain a diode wafer.

[0013] In the method for manufacturing a diode wafer according to the present invention, each surface of the smoothed low-level raw wafer is roughened by bench etching or spin etching.

[0014] In addition, in the method for manufacturing a diode wafer according to the present invention, the method for manufacturing a diode wafer further includes a step of forming a metal conductive layer on the surface of the diode wafer.

[0015] Also, in the method of manufacturing a diode wafer according to the present invention, the diode structure includes a doping well region, a first heavily doped region, and a second heavily doped region. The doping well region and the first heavily doped region have a first conductivity type, and the doping well region is located in the smoothed lower level raw wafer. The first heavily doped region is located in the doping well region. The second heavily doped region has a second conductivity type opposite the first conductivity type, and the second heavily doped region is located in the doping well region.

[0016] In addition, a method for manufacturing a processed wafer, which is another aspect of the present invention, processes a plurality of raw wafers obtained by slicing an ingot. The method for manufacturing the processed wafer includes the steps of: determining whether the plurality of raw wafers meet a manufacturing specification; if it is determined that they meet the manufacturing specification, the raw wafers are classified as high-level raw wafers; if it is determined that they do not meet the manufacturing specification, the raw wafers are classified as low-level raw wafers, and the number of the low-level raw wafers is multiple; calculating the ratio of the number of the low-level raw wafers having problems related to crystal oriented pits (COP) to the number of all the low-level raw wafers, and determining whether this ratio is greater than a predetermined value; if it is determined that it is greater, terminating; if it is determined that it is not greater, removing partial structures of each of the low-level raw wafers, the partial structures having a fixed thickness; and smoothing the surface of each of the low-level raw wafers from which the structures have been removed, to obtain a processed wafer.

[0017] In addition, in the manufacturing method of the processed wafer according to the present invention, the manufacturing specification items include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth mode, wafer size, wafer surface, metal particle residual concentration, total thickness deviation, total indicator reading, wafer warp, partial total indicator reading, and dust count.

[0018] In addition, in the manufacturing method of the processed wafer according to the present invention, the defects include chipping, cracks, excessive laser engraving, scratches, stains, and tears in the crystal lattice.

[0019] In addition, in the manufacturing method of the processed wafer according to the present invention, in the step of removing each partial structure of a low-level raw wafer, a low-level raw wafer having a thickness greater than a predetermined value is selected, and each partial structure of the selected low-level raw wafer is removed.

[0020] In addition, in the method for manufacturing a processed wafer according to the present invention, an etching process and a mirror finishing process are sequentially performed on the surface of each of the lower-level raw wafers from which the structures have been removed, thereby smoothing the surface of each of the lower-level raw wafers from which the structures have been removed.

[0021] In addition, in the method for manufacturing a processed wafer according to the present invention, a grinding process and a mirror finishing process are sequentially performed on each surface of the lower-level raw wafer from which the structures have been removed, thereby smoothing the surface of each of the lower-level raw wafers from which the structures have been removed.

[0022] In addition, in the method for manufacturing a processed wafer according to the present invention, the method for manufacturing a processed wafer further includes a step of roughening the surface of each of the planarized low-level raw wafers.

[0023] In the method for manufacturing a processed wafer according to the present invention, the surface of each of the planarized low-level raw wafers is roughened by bench etching or spin etching. Effect of the Invention

[0024] As described above, the manufacturing method of diode wafers and processed wafers produces high quality diode wafers and processed wafers at low cost by selecting suitable quality low-level raw wafers based on the presence of crystal oriented pits (COPs).

[0025] At least the following points will become apparent from the following specification and drawings. [Brief description of the drawings]

[0026] [Figure 1] 1 is a flowchart showing a method for manufacturing a diode wafer according to an embodiment of the present invention. [Diagram 2] 1 is a cross-sectional view showing a configuration of a diode wafer according to an embodiment of the present invention. [Diagram 3] 1 is a flowchart showing a method for manufacturing a processed wafer according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, the embodiments of the present invention will be described with reference to the drawings. In the drawings and the specification, the same reference numerals indicate the same or similar components. In the drawings, shapes and thicknesses may be enlarged for simplification or convenience of illustration. It should be noted that elements not shown in the drawings or described in the specification are obvious to those skilled in the art. Those skilled in the art can make various modifications and improvements based on the contents of the present invention. Unless otherwise specified, conditional statements or words such as "can" or "may" are often intended to express features, components, or steps that are present in this embodiment but may also be interpreted as not being required. In other embodiments, these features, components, or steps may not be required. In this specification, the phrases "one embodiment" or "embodiment" refer to a particular element, structure, or feature that relates to at least one embodiment. Thus, the phrases "one embodiment" or "embodiment" in this specification do not necessarily refer to the same embodiment. It is to be noted that particular elements, structures, and features described in multiple embodiments can be combined as appropriate. In the present specification and the scope of the patent application, certain terms are used to refer to certain components. However, a person having ordinary skill in the art (a person skilled in the art) should understand that the same components may be referred to by different terms. The scope of the specification and the patent application does not distinguish components by differences in name, but rather by differences in function. The term "including" in the present specification and the scope of the patent application is an open-ended term and should be interpreted as "including, but not limited to." Furthermore, "coupled" or "connected" in this specification includes all direct and indirect coupling means. Thus, when a first element is described as being connected to a second element in this specification, it means that the first element may be directly connected to the second element by an electrical or signal connection, such as wireless transmission, optical transmission, etc., or may be indirectly electrically or signally connected to the second element by some other element or connection means. It will be understood by those skilled in the art that the following contents are merely examples, that various modifications are possible, and that such modifications are also within the scope of the present invention. The scope of the present invention is indicated by the appended claims. In the specification and claims, "a" and "the" refer to "one or at least one" element or component, unless otherwise specified. In addition, singular articles also include the meaning of a plurality of elements or components, unless otherwise specified, that is clearly understood from the surrounding text. In addition, "in" also includes the meaning of "in" and "on". Terms in the specification and claims have the same meaning as those understood by those skilled in the art, unless otherwise specified. In addition, some specific terms will be clearly defined and explained below. The terms in the specification are merely examples, and do not limit the scope of the present invention. In addition, the present invention is not limited to the following examples. The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0028] In addition, in the specification and claims, when it is described that a first member is located on a second member, it means that the first member is connected, joined, or joined to the second member above the second member, or is connected to the second member, and the first member is directly located on the second member and directly connected, joined, or joined to the second member, and there may be other members between the first member and the second member. In contrast, when it is described that a first member is directly located on a second member, it means that the first member is directly connected, joined, directly joined, or directly connected to the second member, and there is no other member between the first member and the second member.

[0029] In the following description, a method for manufacturing diode wafers and processed wafers is provided, which produces high quality diode wafers and processed wafers at low cost by selecting high quality low level raw wafers based on problems related to crystal oriented pits (COPs).

[0030] FIG. 1 is a flow chart showing a method for manufacturing a diode wafer according to an embodiment of the present invention. Next, an example of a specific embodiment of the method for manufacturing a diode wafer according to the present invention will be described with reference to FIG. 1. A plurality of raw wafers obtained by slicing an ingot are processed. The surfaces of these wafers are smoothed through grinding, etching, and mirror finishing processes. The raw wafers are exemplified as silicon wafers, but the present invention is not limited thereto. First, as shown in step S10, it is determined whether the plurality of raw wafers conform to the manufacturing specifications. If it is determined that the raw wafers conform to the manufacturing specifications, the raw wafers are classified as high-grade raw wafers as shown in step S12. If it is determined that the raw wafers do not conform to the manufacturing specifications, the raw wafers are classified as low-grade raw wafers as shown in step S14. For example, the manufacturing specification items include, but are not limited to, electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth type, wafer size, wafer surface, metal particle residual concentration, total thickness deviation, total indicator reading, wafer warpage, partial total indicator reading, and dust count. The defects include, but are not limited to, chipping, cracks, excess laser engraving, scratches, stains, and crystal lattice tears. The total thickness deviation is defined as the difference between the maximum and minimum distances from the thickness of the reference plane when the wafer is clamped. It is generally expressed in micrometers (μm), and a common expression is, for example, ≦15 μm. The total indicator reading is defined as the difference between the maximum and minimum distances between the wafer surface and the reference plane, with the smallest plane formed by the sum of the intercepts of all points within the area of ​​the correct mass on the wafer surface being clamped. Wafer bow is defined as the difference between the minimum and maximum distances between the wafer surface being measured and the reference plane, with the back surface of the wafer usually being used as the reference plane, with the wafer not being clamped. Wafer bow includes both concave and convex situations, with the concave curvature being a negative value and the convex curvature being a positive value.It is generally expressed in micrometers, and a common form of expression is, for example, ≦30 μm. The partial total indicator reading is defined as the difference between the maximum and minimum distances between the surface of the wafer and the reference plane, with the smallest plane formed by the sum of the intercepts of all points within a portion of the surface of the wafer when the wafer is clamped. Table 1 provides the manufacturing specifications. If it is determined that the raw wafer does not meet one of the conditions of the manufacturing specifications, it is considered to be a low-level raw wafer. If it is determined that the raw wafer meets all the conditions of the manufacturing specifications, it is considered to be a high-level raw wafer. In addition, if the raw wafer is observed to have defects, black film, or color film, it is considered to be a low-level raw wafer. If the raw wafer is not observed to have defects, black film, or color film, it is considered to be a high-level raw wafer.

[0031] [Table 1]

[0032] Generally, the quantity of low-level raw wafers obtained by cutting from an ingot is more than one. Step S18 is performed after step S14. In step S18, the ratio of the quantity of low-level raw wafers having problems related to crystal orientation pits (COP) to the quantity of all low-level raw wafers is calculated, and it is determined whether this ratio is greater than a predetermined value. The crystal orientation pits cannot be easily removed by etching, grinding, or mirror finishing processes, and the crystal orientation pits are observed using tools such as an optical microscope or an electron microscope. The problem related to crystal orientation pits is defined as the corresponding low-level raw wafer not passing the COP specification test set in the inspection equipment. For example, if the quantity of crystal orientation pits of one low-level raw wafer is more than a set value, the low-level raw wafer cannot pass the COP specification test set in the inspection equipment. If the quantity of the selected low-level raw wafers having problems related to crystal orientation pits is 64, the quantity of all selected low-level raw wafers is 100, and the ratio is 0.64. The appearance of crystal orientation pits indicates that holes that should not be present have appeared during the manufacture of diodes and wafer etching. When manufacturing diodes, silicon wafers need to be processed. In the process, processes such as ion implantation or diffusion are performed using silicon wafers as substrates. Where holes are present, silicon wafers do not exist. As a result, the diodes cannot withstand the required processes, and the electrical properties of the diodes themselves drift, causing defects, which reduces yields. In addition, when manufacturing diodes, drilling and filling with the required material may be required. If the COP is poor, there is a high possibility that there will be too much dust after drilling, which will cause problems in the subsequent processes, and then the electrical properties of the diodes themselves will drift, leading to defects, which reduces yields. Thus, a suitable silicon wafer substrate will aid the diodes and will not reduce the overall process yield due to material problems.In other words, if the ratio of the quantity of the selected low-level raw wafers having the problem related to the crystal orientation pits to the quantity of the total selected low-level raw wafers is greater than a predetermined value, it indicates that the yield of the diode wafers manufactured from the low-level raw wafers of this lot is significantly decreased, and proceed to step S20 and end all the flowcharts. If the ratio of the quantity of the selected low-level raw wafers having the problem related to the crystal orientation pits to the quantity of the total selected low-level raw wafers is not greater than a predetermined value, it indicates that the yield of the diode wafers manufactured from the low-level raw wafers of this lot is significantly increased, and the low-level raw wafers have a low price and are very valuable in the market. That is, if the judgment result of step S18 is negative, proceed to step S22. In step S22, select the low-level raw wafers having a thickness greater than a predetermined value and remove each partial structure of the selected low-level raw wafers. Since this partial structure has a fixed thickness, the observed crystal orientation pits are removed. This fixed thickness is determined by how deep the observed crystal orientation pits are located. As an example, if an observed crystal orientation pit is located at a depth of 7 micrometers from the surface, this indicates a fixed thickness of 7 micrometers.

[0033] Step S22 is followed by step S24. In step S24, the surface of each of the lower-level raw wafers from which the structures have been removed is smoothed to remove surface stains, chemical films, or scratches, and to obtain a desired level of flatness and particle count for the surface of the lower-level raw wafer. In some embodiments of the present invention, an etching process and a polishing process are sequentially performed on the surface of each of the lower-level raw wafers from which the structures have been removed, to smooth the surface of each of the lower-level raw wafers from which the structures have been removed. Alternatively, a grinding process and a mirror finishing process are sequentially performed on the surface of each of the lower-level raw wafers from which the structures have been removed, to smooth the surface of each of the lower-level raw wafers from which the structures have been removed.

[0034] After step S24, step S26 is performed. In step S26, the surface of each of the planarized low-level raw wafers is roughened to improve the stability of bonding the metal layer. The surface of each of the planarized low-level raw wafers is roughened by bench etching or spin etching. Then, in step S28, a plurality of diode structures are formed on each of the roughened low-level raw wafers to obtain a diode wafer. Finally, as shown in step S30, a metal conductive layer is formed on the surface of the diode wafer, and the metal conductive layer is the electrode of the diode. After step S30, proceed to step S20. These steps do not necessarily have to be performed in the order shown in FIG. 1 if substantially the same results are to be obtained.

[0035] FIG. 2 is a cross-sectional view showing the structure of a diode wafer according to an embodiment of the present invention. As shown in the figure, each of the diode structures 10 includes a doping well region 100, a first highly doped region 102, and a second highly doped region 104. The doping well region 100 and the first highly doped region 102 have a first conductivity type, and the second highly doped region 104 has a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is n-type, the second conductivity type is p-type. When the first conductivity type is p-type, the second conductivity type is n-type. The doping well region 100 is located in the roughened low-level raw wafer 11. The first highly doped region 102 is located in the doping well region 100, and the second highly doped region 104 is located in the doping well region 100. The metal conductive layer 12 is located on the surface of the roughened low-level raw wafer 11.

[0036] In the example of FIG. 1, the step of selecting a low-level raw wafer having a thickness greater than a predetermined value may be omitted, and in step S22, each partial structure of the low-level raw wafer is removed. Also, step S26 may be omitted. If step S26 is omitted, in step S28, a plurality of diode structures are formed on each of the smoothed low-level raw wafers to obtain a diode wafer. Step S30 may be performed or omitted as required. If step S30 is omitted, step S20 is performed directly after step S28 is completed.

[0037] FIG. 3 is a flow chart showing a method for manufacturing a processed wafer according to an embodiment of the present invention. Next, an example of a specific embodiment of the method for manufacturing a processed wafer according to the present invention will be described with reference to FIG. 3. A plurality of raw wafers obtained by slicing an ingot are processed. The surfaces of these wafers are smoothed through grinding, etching, and mirror finishing processes. The raw wafers are exemplified as silicon wafers, but the present invention is not limited thereto. Steps S32, S34, S36, S40, S42, and S44 in FIG. 3 are the same as steps S10, S12, S14, S18, S20, and S22 in FIG. 1, respectively, and similar points will not be described. After step S44 is completed, step S46 is performed. In step S46, the surfaces of the lower-level raw wafers from which the structures have been removed are smoothed to obtain processed wafers. Any semiconductor components such as diodes and microelectromechanical system (MEMS) elements can be formed on the processed wafers. In step S46, an etching process and a mirror finish process are sequentially performed on the surface of each of the lower-level raw wafers from which the structures have been removed, to smooth the surface of each of the lower-level raw wafers from which the structures have been removed. Alternatively, a grinding process and a mirror finish process are sequentially performed on the surface of each of the lower-level raw wafers from which the structures have been removed, to smooth the surface of each of the lower-level raw wafers from which the structures have been removed. Next, step S48 is performed to roughen the surface of each of the smoothed lower-level raw wafers to improve the stability of bonding the metal layer. The surface of each of the smoothed lower-level raw wafers is roughened by bench etching or spin etching. After the completion of step S48, step S42 is performed.

[0038] In the example of Fig. 3, the step of selecting a low-level raw wafer having a thickness greater than a predetermined value may be omitted, and each partial structure of the low-level raw wafer is removed in step S44. Also, step S48 may be performed or omitted as necessary. When step S48 is omitted, step S42 is directly performed after step S46 is completed.

[0039] According to the above-described embodiments, the manufacturing method of diode wafers and processed wafers produces high quality diode wafers and processed wafers at low cost by selecting high quality low level raw wafers based on problems related to crystal orientation pits.

[0040] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0041] 1 Diode wafer 10 Diode Structure 100 Doping Well Area 102 First highly doped region 104 Second highly doped region 11 Low-grade raw wafers 12 Metal conductive layer

Claims

1. A method for manufacturing a diode wafer, comprising processing a plurality of raw wafers obtained by slicing an ingot, determining whether the plurality of raw wafers conforms to manufacturing specifications, If it is determined that the raw wafer is compliant, the raw wafer is designated as a high grade raw wafer. if it is determined that the raw wafer is not in conformity, the raw wafer is a low grade raw wafer, and the quantity of the low grade raw wafer is a plurality of low grade raw wafers; calculating a ratio of the quantity of the low-level raw wafers having crystal oriented pits (COP) related problems to a total quantity of the low-level raw wafers, and determining whether the ratio is greater than a predetermined value; if so, terminating; if it is determined that the thickness is not large, removing each partial structure of the lower level raw wafer, the partial structure having a fixed thickness; smoothing the surface of each of the lower level raw wafers from which structures have been removed; forming a plurality of diode structures on each of the planarized low-level raw wafers to obtain a diode wafer.

2. 2. The method for manufacturing a diode wafer according to claim 1, wherein the manufacturing specification items include: electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth mode, wafer size, wafer surface, metal particle residual concentration, total thickness deviation, total indicator reading, wafer warpage, partial total indicator reading, and dust count.

3. 3. The method of claim 2, wherein the defects include chipping, cracks, excess laser engraving, scratches, stains, and crystal lattice tears.

4. 2. The method for manufacturing a diode wafer according to claim 1, wherein in the step of removing the partial structure of each of the low-level raw wafers, the low-level raw wafers having a thickness greater than a predetermined value are selected, and the partial structure of each of the selected low-level raw wafers is removed.

5. 2. The method for manufacturing a diode wafer according to claim 1, wherein in the step of smoothing the surface of each of the lower-level raw wafers from which structures have been removed, an etching process and a mirror finishing process are sequentially performed on the surface of each of the lower-level raw wafers from which structures have been removed, thereby smoothing the surface of each of the lower-level raw wafers from which structures have been removed.

6. 2. The method for manufacturing a diode wafer according to claim 1, wherein in the step of smoothing the surface of each of the lower-level raw wafers from which structures have been removed, a grinding process and a mirror finishing process are sequentially performed on the surface of each of the lower-level raw wafers from which structures have been removed, thereby smoothing the surface of each of the lower-level raw wafers from which structures have been removed.

7. 2. The method for manufacturing a diode wafer as described in claim 1, further comprising the step of roughening the surface of each of the smoothed low-level raw wafers, and forming a plurality of the diode structures on each of the smoothed low-level raw wafers to obtain the diode wafer, wherein the step of forming a plurality of the diode structures on each of the roughened low-level raw wafers to obtain the diode wafer comprises the step of forming a plurality of the diode structures on each of the roughened low-level raw wafers to obtain the diode wafer.

8. 8. The method of claim 7, wherein the surface of each of the planarized low-level raw wafers is roughened by bench etching or spin etching.

9. 8. The method of claim 7, further comprising forming a metal conductive layer on a surface of the diode wafer.

10. The diode structure comprises: a doping well region having a first conductivity type, said doping well region being located in the planarized lower level raw wafer; a first highly doped region having the first conductivity type, the first highly doped region being located in the doping well region; 2. The method of claim 1 further comprising: a second highly doped region having a second conductivity type opposite the first conductivity type, the second highly doped region being located in the doping well region.

11. A method for manufacturing a processed wafer, which processes a plurality of raw wafers obtained by slicing an ingot, comprising the steps of: determining whether the plurality of raw wafers conforms to manufacturing specifications, If it is determined that the raw wafer is suitable, the raw wafer is classified as a high-grade raw wafer. if it is determined that the raw wafers are not suitable, the raw wafers are low-level raw wafers, and the number of the low-level raw wafers is more than one; calculating a ratio of the quantity of the low-level raw wafers having crystal oriented pits (COP) related problems to a total quantity of the low-level raw wafers, and determining whether the ratio is greater than a predetermined value; if so, terminating; if it is determined that the thickness is not large, removing each partial structure of the lower level raw wafer, the partial structure having a fixed thickness; and smoothing a surface of each of the lower-level raw wafers from which structures have been removed to obtain a processed wafer.

12. The method for manufacturing a processed wafer as described in claim 11, characterized in that the manufacturing specification items include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth mode, wafer size, wafer surface, metal particle residual concentration, total thickness deviation, total indicator reading, wafer warp, partial total indicator reading, and dust count.

13. 13. The method for manufacturing a processed wafer according to claim 12, wherein the defects include chipping, cracks, excess laser engraving, scratches, stains, and tears in the crystal lattice.

14. 12. The method for manufacturing a processed wafer according to claim 11, wherein in the step of removing the partial structure of each of the low-level raw wafers, the low-level raw wafers having a thickness greater than a predetermined value are selected, and the partial structure of each of the selected low-level raw wafers is removed.

15. 12. The method for manufacturing a processed wafer according to claim 11, wherein in the step of smoothing the surface of each of the lower-level raw wafers from which structures have been removed, an etching process and a mirror finishing process are sequentially performed on the surface of each of the lower-level raw wafers from which structures have been removed, thereby smoothing the surface of each of the lower-level raw wafers from which structures have been removed.

16. 12. The method for manufacturing a processed wafer according to claim 11, wherein in the step of smoothing the surface of each of the lower-level raw wafers from which structures have been removed, a grinding process and a mirror finishing process are sequentially performed on the surface of each of the lower-level raw wafers from which structures have been removed, thereby smoothing the surface of each of the lower-level raw wafers from which structures have been removed.

17. The method of claim 11 further comprising the step of roughening the surface of each of the planarized low-level raw wafers.

18. 20. The method of claim 17, wherein the surface of each of the planarized low-level raw wafers is roughened by bench etching or spin etching.

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