LATERAL SiC-JFET DEVICE AND MANUFACTURING METHOD FOR THE SAME

Abstract

To provide a lateral SiC-JFET device and a manufacturing method for the same, that easily achieve the design of breakdown voltage from several tens of volts to several hundreds of volts without being restricted by a channel region.SOLUTION: A lateral SiC-JFET device includes a substrate 101, a source electrode 107 and a drift region 104 existing on the substrate and arranged in order, a first source contact region 108, a second source contact region 111, and a channel region 109 existing on the source electrode and arranged in order, and a gate electrode 110 existing on the channel region. Here, the channel region and the drift region are a channel region and a drift region with independent structures, respectively.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This application relates to the technical field of semiconductor devices, and in particular to lateral SiC-JFET devices and methods for fabricating same. [Background technology]

[0002] As a third-generation semiconductor material, SiC has many advantages over traditional Si materials. First, SiC is a wide bandgap material, with a bandgap width of 3.2 eV, much wider than Si (bandgap width 1.1 eV). Therefore, devices manufactured using SiC have a much smaller volume than Si-based devices at the same breakdown voltage, and can usually be reduced in size by more than 10 times. Second, the carrier mobility of SiC is close to that of Si, and the saturation drift velocity of its electrons is twice that of Si. Therefore, at the same breakdown voltage, the device size is small, so it is easy to use SiC to manufacture small-sized, high-breakdown-voltage, low-on-resistance power devices, and thus SiC devices are very widely used in power applications. At the same time, SiC materials have excellent thermal conductivity, and for power applications, the excellent thermal conductivity ability can meet high-power applications.

[0003] Typically, SiC power devices include SiC-based VDMOS, vertical JFET (V-JFET), LDMOS, lateral JFET (L-JFET), etc. In most radio frequency applications, the source electrode generally needs to be provided on the back side of the wafer to meet the requirements of heat dissipation and grounding, so all mainstream radio frequency power devices are lateral structures. Meanwhile, SiC LDMOS has channel mobility and reliability problems. The electron mobility of SiC materials is comparable to that of Si, but the mobility here generally refers to the bulk mobility of the material. For LDMOS devices, when conducting, the carriers mainly move near the SiC-SiO2 interface that exists in the channel, but here the channel mobility is affected by the SiC-SiO2 interface defects, so currently, the channel mobility of SiC LDMOS is low and the impedance corresponding to the channel part is large. To increase the channel mobility, the general method is to increase the gate voltage to form a thicker inversion layer under the channel, which can further reduce the impact of interface defects on the conducting part in the channel, but excessive gate voltage will bring about reliability problems of the corresponding gate oxide film.

[0004] SiC lateral JFET devices can completely avoid the channel mobility issue and take full advantage of the superior performance of SiC material since its conducting parts are entirely within the SiC body. Summary of the Invention [Problem to be solved by the invention]

[0005] Fig. 1 is a schematic diagram showing an existing L-JFET structure. As shown in Fig. 1, the starting substrate 1, the p-type first epitaxial layer 2, the p-epitaxial layer 3, the n-type epitaxial layer 4, the p-gate region 5, the n-source region 6, the n-drain region 7, the p+ impurity region 8, the p-type second epitaxial layer 9, the ohmic contact electrodes 11a, 11b, 11c, 11d, the gate electrode 12a, the source electrode 12b, the drain electrode 12c, the control electrode 12d, and the oxide layer 13 are included. The channel region of this structure is located below the gate electrode 12a region, and the n-drain region 7 withstands a voltage due to the reverse bias of the reverse PN junction formed by the portion of the n-type epitaxial layer 4 between the gate electrode 12a and the n-drain region 7 and the p-epitaxial layer 3. In this way, the adjustment of the size of the portion between the gate electrode 12a and the n-drain region 7 in the n-type epitaxial layer 4 (i.e., the junction depth of the PN junction) is limited by the channel region. Therefore, it is expected that flexible adjustment of the breakdown voltage will be difficult in this device. Therefore, tuning the breakdown voltage of conventional lateral SiC-JFET devices is limited by the size of the channel region, which is a technical problem that must be urgently solved by those skilled in the art.

[0006] The above information disclosed in the Background section is intended only to facilitate understanding of the background of the present application, and may therefore contain information that does not constitute prior art known to those skilled in the art. [Means for solving the problem]

[0007] The embodiments of the present application provide a lateral SiC-JFET device and a manufacturing method thereof to solve a technical problem existing in conventional lateral SiC-JFET devices that the adjustment of the breakdown voltage is limited by the size of the channel region.

[0008] In a first aspect according to an embodiment of the present application, there is provided a lateral SiC-JFET device, the lateral SiC-JFET device comprising: A substrate; a source electrode and a drift region disposed over the substrate, the source electrode and the drift region being arranged in sequence; a first source contact region, a second source contact region, and a channel region arranged in sequence on the source electrode; a gate electrode located over the channel region, Here, the channel region and the drift region are respectively independent in structure.

[0009] In a second aspect according to an embodiment of the present application, there is provided a method for manufacturing a lateral SiC-JFET device, the method comprising the steps of: Step S1 of forming a substrate; Step S2 of forming a source electrode and a first source contact region on the substrate; and step S3 of forming a second source contact region, a channel region, a gate electrode, and a drift region by implantation; Here, the channel region and the drift region are formed by independent implantation processes, and are independent structures, i.e., the channel region (109) and the drift region (104), and the channel region can be independently adjusted to adjust the on / off characteristics of the lateral SiC JFET device, and the drift region can be independently adjusted to adjust the breakdown voltage of the lateral SiC JFET device. Effect of the Invention

[0010] By adopting the above technical solutions, the embodiments of the present application have the following technical effects:

[0011] The channel region 109 and the drift region 104 are independent structures, and therefore the channel region 109 and the drift region 104 can be adjusted independently. The on / off of the lateral SiC-JFET device is realized by pinching off or opening the channel region by changing the voltage between the source electrode 107 and the gate electrode 110. The on / off characteristics of the device can be optimized by individually and independently adjusting the implantation dose of the channel region. The breakdown voltage of the lateral SiC-JFET device is realized by the reverse bias PN junction formed by the drift region 104 and the epitaxial layer, and the breakdown voltage of the reverse bias PN junction formed by the drift region 104 and the epitaxial layer correlates with the size and concentration of the drift region 104 and the epitaxial layer. Therefore, by individually adjusting parameters such as the size and implantation concentration of the drift region 104, the breakdown voltage of the device can be flexibly adjusted, and it is easy to design a breakdown voltage ranging from tens of volts to hundreds of volts without being limited by the channel region. [Brief description of the drawings]

[0012] The accompanying drawings illustrated herein are used for further understanding of the present application and constitute a part of the present application, and the exemplary embodiments and the description thereof are used to explain the present application and are not to be construed as unduly limiting the present application. [Figure 1] FIG. 1 is a schematic diagram showing a conventional L-JFET structure. [Diagram 2] FIG. 1 is a schematic diagram showing a lateral SiC-JFET device according to an embodiment of the present application. [Diagram 3] FIG. 2 is a schematic diagram showing step S1 of a method for manufacturing a lateral SiC-JFET device according to an embodiment of the present application. [Figure 4] FIG. 2 is a schematic diagram showing the completion of step S2 in a method for manufacturing a lateral SiC-JFET device according to an embodiment of the present application. [Diagram 5]FIG. 2 is a schematic diagram showing the completion of step S3 in a method for manufacturing a lateral SiC-JFET device according to an embodiment of the present application. [Figure 6] FIG. 2 is a schematic diagram showing step S4 of a method for manufacturing a lateral SiC-JFET device according to an embodiment of the present application. [Figure 7] FIG. 2 is a schematic diagram showing the completion of step S5 in the method for manufacturing a lateral SiC-JFET device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In order to make the technical solutions and advantages of the embodiments of the present application clearer, the exemplary embodiments of the present application are described in more detail below with reference to the drawings, but it is obvious that the described embodiments are only some of the embodiments of the present application and are not exhaustive of all the embodiments. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without contradiction.

[0014] <Example 1> As shown in FIG. 2, a lateral SiC-JFET device according to an embodiment of the present application has A starting substrate 101, which is an N+ starting substrate; a p+ epitaxial layer 102 overlying a starting substrate 101; a p- epitaxial layer 103 located on the p+ epitaxial layer 102; a source electrode 107 and a drift region 104 disposed in the p-epitaxial layer and arranged in sequence; a first source contact region 108, a second source contact region 111, and a channel region 109 arranged in this order on the source electrode; a gate electrode 110 located above the channel region; Here, the channel region 109 and the drift region 104 are formed by independent processes and have independent structures, and the channel region 109 can be independently adjusted to adjust the on / off characteristics of the lateral SiC-JFET device, and the drift region 104 can be independently adjusted to adjust the breakdown voltage of the lateral SiC-JFET device.

[0015] In the lateral SiC-JFET device according to the embodiment of the present application, the channel region 109 and the drift region 104 are formed by independent processes, and thus the channel region 109 and the drift region 104 can be adjusted independently. The on / off of the lateral SiC-JFET device is realized by pinching off or opening the channel region by changing the voltage between the source electrode 107 and the gate electrode 110. The on / off characteristics of the device can be optimized by individually and independently adjusting the implantation dose of the channel region. The breakdown voltage of the lateral SiC-JFET device is realized by the reverse bias PN junction formed by the drift region 104 and the p-epitaxial layer 103, and the breakdown voltage of the reverse bias PN junction formed by the drift region 104 and the p-epitaxial layer 103 is correlated only with the size and concentration of the drift region 104 and the p-epitaxial layer 103. Therefore, by individually adjusting parameters such as the size and implantation concentration of the drift region 104, the breakdown voltage of the device can be flexibly adjusted, and a breakdown voltage design ranging from tens of volts to hundreds of volts can be easily realized without being restricted by the channel region.

[0016] Specifically, the channel region 109 and the drift region 104 are independent of each other, and being independent of each other includes the following.

[0017] 1. The channel region 109 is formed in an independent process, and the drift region 104 is formed in an independent process, that is, the channel region 109 and the drift region 104 are not formed in the same process.

[0018] 2. The channel region 109 has a structure independent of the drift region 104, and the drift region 104 has a structure independent of the channel region 109, and the two structures do not affect each other.

[0019] 3. The parameters of the channel region 109 can be independently controlled at the time of formation according to the needs of the lateral SiC JFET device, and the parameters of the drift region 104 can also be independently controlled at the time of formation according to the needs of the lateral SiC JFET device, including but not limited to size, concentration, etc.

[0020] In FIG. 2, the substrate for the lateral SiC JFET device includes an N+ starting substrate 101, a p+ epitaxial layer 102 and a p- epitaxial layer 103.

[0021] The N+ starting substrate is currently a mature product that is already in mass production, with high precision and low cost, and is suitable for the development of lateral SiC-JFET device products.

[0022] As another alternative embodiment, the substrate of the lateral SiC-JFET device may be a high resistivity SiC starting substrate and a p+ epitaxial layer 102 and a p- epitaxial layer 103. For a lateral SiC-JFET device in which the substrate is a high resistivity SiC starting substrate and a P+ epitaxial layer 102 and a p- epitaxial layer 103, the other structures are identical to those of a lateral SiC-JFET device in which the substrate is an N+ starting substrate and a p+ epitaxial layer 102 and a p- epitaxial layer 103.

[0023] Although the mass production rate of high-resistance SiC starting substrates is not very high at present, the cost is somewhat high, but the performance of lateral SiC-JFET devices on high-resistance SiC starting substrates is excellent, which is an important direction for the development of lateral SiC-JFET device products. As the cost of high-resistance SiC starting substrates decreases, the number of lateral SiC-JFET devices on high-resistance SiC starting substrates will increase more and more.

[0024] 2, there is a first gap between the source electrode 107 and the drift region 104. There is a second gap between the gate electrode 110 and the second source contact region 111 and between the gate electrode 110 and the drift region 104, and the PN junction formed by the drift region 104 and the p-epitaxial layer 103, the PN junction formed by the drift region 104 and the source electrode 107, and the PN junction formed by the drift region 104 and the gate electrode 110 are broken down in the order of arrangement.

[0025] A PN junction is formed between the drift region 104 and the p-epitaxial layer 103, a PN junction is formed between the drift region 104 and the source electrode 107, and a PN junction is formed between the drift region 104 and the gate electrode 110, i.e., three PN junctions are formed. The size of the first and second gaps affects the breakdown voltage of the lateral SiC JFET device.

[0026] If the PN junction formed by the drift region 104 and the gate electrode 110 breaks down, the gate electrode will be burned away, so it is necessary to avoid the breakdown as much as possible. That is, among the three PN junctions, the PN junction formed by the drift region 104 and the gate electrode 110 breaks down last.

[0027] After the drift region 104 of the PN junction formed by the drift region 104 and the p-epitaxial layer 103 and the PN junction formed by the drift region 104 and the source electrode 107 breaks down, the avalanche current generated flows away from the drain end due to the electric field, and the drain end is grounded directly via the starting substrate, so that gate electrode burn and drain electrode burn are avoided, and the current is led out by the drain end, thereby improving the reliability and robustness of the device.

[0028] As an example, when the breakdown voltage of the lateral SiC-JFET device according to the embodiment of the present application is 150 V, the PN junction formed by the drift region 104 and the p-epitaxial layer 103, the PN junction formed by the drift region 104 and the source electrode 107, and the PN junction formed by the drift region 104 and the gate electrode 110 have breakdown voltages of 150 to 200 V, 50 to 100 V, and 20 to 30 V, respectively, according to the results obtained from the simulations so far. By adjusting the widths of the first and second gaps, the breakdown of the latter two PN junctions can be effectively postponed, and the first PN junction can be preferentially broken down.

[0029] Greater industrial demand can be achieved by tailoring the breakdown voltage of the lateral SiC JFET device according to the embodiments of the present application, particularly by tailoring the size of the drift region, including but not limited to 200V, 500V, or 1000V.

[0030] In an embodiment, as shown in FIG. 2, the lateral SiC-JFET device further comprises: an oxide layer 206; a source contact metal compound 201-1 located within the oxide layer and overlying the first source contact region 108 and the second source contact region 111; a source contact via 203-1 located within the oxide layer and above the source contact metallurgy 201-1; a source metal layer 204-1 located within the oxide layer and overlying the source contact via 203-1; a ground backhole 205 connected to the source metal layer 204-1 and penetrating from top to bottom to the bottom of the starting substrate; Here, the bottom of the starting substrate is grounded and connected to a heat dissipation structure.

[0031] The source end includes a source electrode 107, a first source contact region 108, and a second source contact region 111. This realizes grounding of the source end through the source contact metal compound 201-1, the source contact via 203-1, the source metal layer 204-1, and the ground back hole 205, and realizes connection between the source end and the heat dissipation structure. Since heat generated at the source end can be quickly dissipated, the lateral SiC-JFET device according to the embodiment of the present application can be applied to radio frequencies.

[0032] In an embodiment, as shown in FIG. 2, the lateral SiC-JFET device further comprises: a drain electrode 106 located in the drift region 104 and spaced apart from the gate electrode 110; a drain implant region 105 located below the drain electrode 106; a drain contact metal compound 201-3 located within the oxide layer and overlying the drain electrode 106; a drain contact via 203-3 located within the oxide layer and overlying the drain contact metallurgy 201-3; a drain metal layer 204-3 located within the oxide layer and overlying the drain contact via 203-3.

[0033] The drain end includes a drain implant region 105 and a drain electrode 106. The drain end connection is realized by a drain contact metallization 201-3 and a drain metal layer 204-3.

[0034] In an embodiment, the lateral SiC JFET device further comprises: a gate contact metal compound 201-2 located within the oxide layer and overlying the gate electrode 110; a gate contact via 203-2 located within the oxide layer and above the gate contact metallurgy 201-2.

[0035] The gate end includes the gate electrode 110 and the gate contact metallization 201-2. The gate end connection is realized through the gate contact metallization 201-2 and the gate contact via 203-2.

[0036] In an embodiment, as shown in FIG. 2, the lateral SiC-JFET device further comprises: a gate shielding plate (202) located within the oxide layer and between the gate electrode (110) and the drain electrode (106); a gate shield plate contact via (not shown) located in an oxide layer and above the gate shield plate, the gate shield plate contact via being connected to the source metal layer 204-1.

[0037] This realizes the connection between the gate shield and the source electrode 107. The presence of the gate shield can effectively isolate the drain electrode and the gate electrode, significantly reduce the reverse insulation capacitance of the device, significantly reduce the parasitic capacitance between the drain electrode 106 and the gate electrode 110, and improve the performance of the lateral SiC-JFET device.

[0038] In an embodiment, as shown in FIG. 2, the gate shielding plates 202 include an L-shaped gate shielding plate and a Z-shaped gate shielding plate spaced apart from the gate electrode 110 towards the drain electrode 106 .

[0039] Since the shape and position of the gate shielding plate affect the breakdown voltage, parasitic capacitance, and reliability of the device, the specific shape and position must be adjusted based on the design parameter index of the device.

[0040] Here, the starting N+ substrate has a high doping concentration and low resistivity. First, the cost of the starting N+ substrate is low; second, the low resistivity of the starting N+ substrate reduces the resistance of the source-ground path of the device, so that the device can have a relatively good performance.

[0041] Specifically, the drain implant region 105 is a step-type drain implant region.

[0042] Specifically, the first source contact region 108 is a P-type first source contact region 108, and the second source contact region 111 is an N-type second source contact region 111.

[0043] Specifically, in the lateral SiC-JFET device according to the embodiment of the present application, the overall device structure is realized by independently forming each functional region in the p-epitaxial layer 103, and the functional regions include a source electrode 107, a first source contact region 108, a drain electrode 106, a second source contact region 111, a channel region 109, a drift region 104, a drain injection region 105, and a gate electrode 110.

[0044] Each region of the lateral SiC-JFET device is completed by implantation, avoiding complex processes such as trenches, making the process easier to implement and lower cost.

[0045] According to design simulations already performed, the lateral SiC-JFET device according to the embodiments of the present application can easily achieve a breakdown voltage of several tens to several hundreds of volts, and the on-resistance for the same breakdown voltage is several times lower than that of a silicon substrate device. At the same time, the simulation data shows that the reverse insulation capacitance of the device can be reduced by 10 times or more, acting as a gate shield.

[0046] <Example 2> The method for manufacturing a lateral SiC-JFET device according to this embodiment is used to manufacture the lateral SiC-JFET device of Example 1. The method for manufacturing a lateral SiC-JFET device includes the following steps:

[0047] As shown in FIG. 3, in step S1, a p+ epitaxial layer 102 and a p- epitaxial layer 103 are formed on a starting substrate 101 in this order from bottom to top.

[0048] As shown in FIG. 4, in step S2, a source electrode 107 and a first source contact region 108 are formed in the P-epitaxial layer.

[0049] As shown in FIG. 5, in step S3, the second source contact region 111, the channel region 109, the gate electrode 110, and the drift region 104 are formed by implantation.

[0050] Here, the channel region 109 and the drift region 104 are formed by independent implantation processes, and have independent structures, such that the channel region 109 can be independently adjusted to adjust the on / off characteristics of the lateral SiC JFET device, and the drift region 104 can be independently adjusted to adjust the breakdown voltage of the lateral SiC JFET device.

[0051] In an embodiment, there is a first gap between the source electrode 107 and the drift region 104, There is a second gap between the gate electrode 110 and a second source contact region 111 and between the gate electrode 110 and the drift region 104 .

[0052] In an embodiment, as shown in FIG. 6, the method for manufacturing a lateral SiC-JFET device further includes step S4, which includes: forming a source contact metal compound 201-1 on the first source contact region 108, the second source contact region 111, a drain contact metal compound 201-3 on the drain electrode 106, and a gate contact metal compound 201-2 on the gate electrode 110; growing a first oxide layer, forming a gate shield, and then growing a second oxide layer to cover the shield; and drilling holes to form source contact via 203-1, gate contact via 203-2, drain contact via 203-3, and gate shield plate contact via.

[0053] In an embodiment, as shown in FIG. 7, the method for manufacturing a lateral SiC-JFET device further includes step S5, which includes: forming a source metal layer 204-1 and a drain metal layer 204-3; and forming a ground backhaul 205.

[0054] The following takes the fabrication of a lateral SiC-JFET device on an N+ starting substrate as an example to describe the fabrication method in detail, including the following steps:

[0055] As shown in FIG. 3, in step 1, a p+ epitaxial layer 102 is grown on an N+ starting substrate 101, and then a p- epitaxial layer 103 is grown thereon.

[0056] Here, the N+ starting substrate 101 has a high doping concentration and a low resistivity. First, the cost of the N+ starting substrate is low, and second, the low resistivity of the N+ starting substrate reduces the resistance of the source electrode ground path of the device, so that the device can have a relatively good performance.

[0057] As shown in FIG. 4, in step 2, a photoresist is applied on the p-epitaxial layer 103, exposed, developed, a photolithography pattern is formed, a source electrode 107 is implanted, specifically, the source electrode 107 is formed as a source buried layer, and finally the photoresist is removed.

[0058] The first source contact region 108 is formed using a similar method, where the first source contact region 108 is a very heavily doped P-type region to ensure good electrode contact, and the source buried layer is also a P-type region, but with a lower implantation concentration than the first source contact region. By adjusting the implantation dose, a connection between the first source contact region and the source buried layer is achieved.

[0059] As shown in FIG. 5, in step 3, a drain electrode 106, a second source contact region 111, a channel region 109, an n drift region 104, a drain electrode 105 (specifically, a drain step implantation), and a gate electrode 110 (specifically, a gate electrode P region) are formed on the p-epitaxial layer 103 by the above-mentioned photolithography and implantation methods.

[0060] Here, the drain implantation region and the second source contact region 111 have different names, but share one photomask and are completed by the same implantation. A certain gap (i.e., a second gap) is left between the gate electrode 110 and the second source contact region 111, and between the gate electrode 110 and the n drift region 104, and adjustments to this gap correspond to adjusting the breakdown voltage of the device. Also, a certain gap (i.e., a first gap) is left between the source electrode 107 and the n drift region 104, and adjustments to the size of this gap can correspond to adjusting the breakdown voltage of the device.

[0061] As shown in FIG. 6, in step 4, a source contact metal compound 201-1, a gate contact metal compound 201-2, and a drain contact metal compound 201-3 are formed above the second source contact region 111, the gate electrode 110, and the drain electrode 106, respectively; Then, a first oxide layer 206 is grown, then the gate shield 202 is fabricated, then a second oxide layer having a certain thickness is grown to close the structure, then the oxide layer is planarized, Thereafter, holes are drilled to form a source contact via 203-1, a gate contact via 203-2, a drain contact via 203-3, and a gate shielding plate contact via, and the three terminals of the device are led out.

[0062] Here, the source contact metal compound 201-1 functions as a 1-pole contact, the gate contact metal compound 201-2 functions as a 1-pole contact, and the drain contact metal compound 201-3 functions as a 1-pole contact. The source contact metal compound 201-1 and the gate shielding plate are connected, that is, the gate shielding plate 202 is connected to the source electrode.

[0063] Since the gate shielding plate 202 is located between the gate electrode and the drain electrode, the parasitic capacitance between the drain electrode and the gate electrode can be significantly reduced, thereby improving the device performance.

[0064] As shown in FIG. 7, in step 5, a metal layer is formed on the planarized oxide layer 206, and each pole is further extended to form a source metal layer 204-1 and a drain metal layer 204-3; Then, a ground backhole 205 is fabricated to connect the source electrode of the device to the backside of the wafer.

[0065] Here, taking into consideration the convenience of pattern design or other device designs, the device may have a multi-layer oxide-contact via-metal layer structure, and correspondingly, the ground backhole may also be connected to any metal layer to ground the source electrode in terms of the difficulty of process implementation, etc.

[0066] <Example 3> The lateral SiC-JFET device according to this embodiment differs from the lateral SiC-JFET device of Example 1 in the following respects.

[0067] The substrate of the lateral SiC-JFET device according to this embodiment is a high-resistance SiC starting substrate. Correspondingly, the PN junction formed by the drift region and the source electrode, and the PN junction formed by the drift region and the gate electrode are broken down in the order of arrangement. At this time, although only two PN junctions are formed, the PN junction formed by the drift region and the gate electrode is still broken down last.

[0068] In the description of this application and its embodiments, it is to be understood that the orientations or positional relationships indicated by the terms "top", "bottom", "height", etc. are based on the orientations or positional relationships shown in the drawings, and are merely for the purpose of facilitating and simplifying the description of this application, and are not intended to indicate or imply that the devices or elements referred to have a particular orientation or must be constructed or operated in a particular orientation, and therefore cannot be understood as limiting this application.

[0069] In the present application and its embodiments, unless otherwise clearly specified and limited, the terms "provide", "attach", "couple", "connect", "fixed", etc. should be understood in a broad sense, for example, may be fixed connection, detachable connection, or integral, may be mechanical connection, electrical connection, communication, and may be either direct connection, indirect connection through an intermediate medium, internal communication of two elements, or interactive relationship of two elements. For those skilled in the art, the specific meaning of the above terms in the present specification may be understood according to the specific situation.

[0070] In the present application and its embodiments, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean either that the first and second features are in direct contact or that the first and second features are in indirect contact via an intermediate medium. Furthermore, a first feature being "above," "above," and "on the upper surface" of a second feature may mean that the first feature is directly above or diagonally above the second feature, or simply that the horizontal height of the first feature is higher than that of the second feature. A first feature being "below," "below," and "on the lower surface" of a second feature may mean that the first feature is directly below or diagonally below the second feature, or simply that the horizontal height of the first feature is lower than that of the second feature.

[0071] The above disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, specific example components and configurations are described above. Of course, these are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numbers and / or reference characters in different examples for the purpose of brevity and clarity, and as such does not indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, although the present application describes examples of various specific processes and materials, those skilled in the art may envision the application of other processes and / or the use of other materials.

[0072] Although the preferred embodiments of the present application have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they have learned the basic creative concept. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiments and all changes and modifications that should fall within the scope of the present application.

[0073] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application are within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations. [Explanation of symbols]

[0074] (Background technology) 1. Starting substrate 2 p-type first epitaxial layer 3 p-epitaxial layer 4 n-type epitaxial layer 5p gate region 6 n source region 7 n-drain region 8 p+ impurity region 9 p-type second epitaxial layer 11a, 11b, 11c, 11d ohmic contact electrode 12a Gate electrode 12b Source electrode 12c Drain electrode 12d Control electrode 13 Oxide layer (Present Application) 101 Starting Substrate 102 p+ epitaxial layer 103 p-epitaxial layer 104 Drift Region 105 Drain implantation region 106 Drain electrode 107 Source electrode 108 first source contact region 109 Channel Region 110 Gate electrode 111 second source contact region 206 Oxide layer 201-1 Source Contact Metal Compounds 201-2 Gate Contact Metal Compounds 201-3 Drain contact metal compound 202 Gate shield plate 203-1 Source Contact Via 203-2 Gate Contact Via 203-3 Drain Contact Via 204-1 Source metal layer 204-3 Drain metal layer 205 Ground Backhaul

Claims

1. A substrate; a source electrode (107) and a drift region (104) arranged in sequence on the substrate; a first source contact region (108), a second source contact region (111) and a channel region (109) arranged in sequence on the source electrode; a gate electrode (110) located over the channel region; Here, the channel region (109) and the drift region (104) are independent structures of the channel region (109) and the drift region (104), respectively. A lateral SiC-JFET device.

2. The substrate is A starting substrate (101) which is an N+ starting substrate or a high resistivity SiC starting substrate; a p+ epitaxial layer (102) and a p- epitaxial layer (103) provided on a starting substrate from bottom to top; 2. The lateral SiC-JFET device of claim 1 .

3. A first gap is provided between the source electrode (107) and the drift region (104), and a second gap is provided between the gate electrode (110) and a second source contact region (111) and between the gate electrode (110) and the drift region (104), and a PN junction formed by the drift region (104) and the p-epitaxial layer, a PN junction formed by the drift region (104) and the source electrode (107), and a PN junction formed by the drift region (104) and the gate electrode (110) are broken down in the order of arrangement. A lateral SiC-JFET device according to claim 2.

4. the substrate is a high resistivity SiC starting substrate, There is a first gap between the source electrode (107) and the drift region (104), and a second gap between the gate electrode (110) and a second source contact region (111) and between the gate electrode (110) and the drift region (104), and a PN junction formed by the drift region (104) and the source electrode (107) and a PN junction formed by the drift region (104) and the gate electrode (110) are broken down in an array order.

2. The lateral SiC-JFET device of claim 1 .

5. The lateral SiC-JFET device is an oxide layer (206); a source contact metal compound (201-1) located within the oxide layer and overlying the first source contact region (108) and the second source contact region (111); a source contact via (203-1) located within the oxide layer and overlying the source contact metallization (201-1); a source metal layer (204-1) located within the oxide layer and overlying the source contact via (203-1); a ground backhole (205) connected to the source metal layer (204-1) and penetrating from top to bottom to the bottom of the starting substrate; A lateral SiC-JFET device according to claim 3.

6. The lateral SiC-JFET device is a drain electrode (106) located in the drift region (104) and spaced apart from the gate electrode (110); a drain implant region (105) located below the drain electrode (106); a drain contact metal compound (201-3) located within the oxide layer and overlying the drain electrode (106); a drain contact via (203-3) located within the oxide layer and overlying the drain contact metallization (201-3); a drain metal layer (204-3) located within the oxide layer and overlying the drain contact via (203-3); A lateral SiC-JFET device according to claim 5.

7. The lateral SiC-JFET device is a gate contact metal compound (201-2) located within the oxide layer and overlying the gate electrode (110); a gate contact via (203-2) located within the oxide layer and above the gate contact metal compound (201-2). A lateral SiC-JFET device according to claim 6.

8. The lateral SiC-JFET device a gate shield (202) located within the oxide layer and between the gate electrode (110) and the drain electrode (106); a gate shield plate contact via located in an oxide layer and above the gate shield plate, the gate shield plate contact via being connected to the source metal layer (204-1); The gate shielding plate includes an L-shaped gate shielding plate and a Z-shaped gate shielding plate spaced apart from each other from the gate electrode (110) toward the drain electrode (106). A lateral SiC-JFET device according to claim 7.

9. The lateral SiC-JFET device is an oxide layer (206); a source contact metal compound (201-1) located within the oxide layer and overlying the first source contact region (108) and the second source contact region (111); a source contact via (203-1) located within the oxide layer and overlying the source contact metallization (201-1); a source metal layer (204-1) located within the oxide layer and overlying the source contact via (203-1); a ground backhole (205) connected to the source metal layer (204-1) and penetrating from top to bottom to the bottom of the starting substrate; A lateral SiC-JFET device according to claim 4.

10. The lateral SiC-JFET device is a drain electrode (106) located in the drift region (104) and spaced apart from the gate electrode (110); a drain implant region (105) located below the drain electrode (106); a drain contact metal compound (201-3) located within the oxide layer and overlying the drain electrode (106); a drain contact via (203-3) located within the oxide layer and overlying the drain contact metallization (201-3); a drain metal layer (204-3) located within the oxide layer and overlying the drain contact via (203-3); A lateral SiC-JFET device according to claim 9.

11. The lateral SiC-JFET device is a gate contact metal compound (201-2) located within the oxide layer and overlying the gate electrode (110); a gate contact via (203-2) located within the oxide layer and above the gate contact metal compound (201-2). A lateral SiC-JFET device according to claim 10.

12. The lateral SiC-JFET device a gate shield (202) located within the oxide layer and between the gate electrode (110) and the drain electrode (106); a gate shield plate contact via located in an oxide layer and above the gate shield plate, the gate shield plate contact via being connected to the source metal layer (204-1); The gate shielding plate includes an L-shaped gate shielding plate and a Z-shaped gate shielding plate spaced apart from each other from the gate electrode (110) toward the drain electrode (106). A lateral SiC-JFET device according to claim 11.

13. A method for manufacturing a lateral SiC-JFET device according to any one of claims 1 to 12, comprising the steps of: Step S1 of forming a substrate; Step S2 of forming a source electrode (107) and a first source contact region (108) on the substrate; and step S3 of forming by implantation a second source contact region (111), a channel region (109), a gate electrode (110) and a drift region (104), wherein the channel region (109) and the drift region (104) are formed by independent implantation processes, and are independent structures of the channel region (109) and the drift region (104), and the channel region (109) can be independently adjusted to adjust the on / off characteristics of the lateral SiC-JFET device, and the drift region (104) can be independently adjusted to adjust the breakdown voltage of the lateral SiC-JFET device. A method for fabricating a lateral SiC-JFET device.

14. There is a first gap between the source electrode (107) and the drift region (104); a second gap between the gate electrode (110) and a second source contact region (111) and between the gate electrode (110) and the drift region (104); A method for manufacturing a lateral SiC-JFET device according to claim 13.

15. The method for manufacturing the lateral SiC-JFET device includes the steps of: forming a source contact metal compound (201-1) on the first source contact region (108) and the second source contact region (111), a drain contact metal compound (201-3) on the drain electrode (106), and a gate contact metal compound (201-2) on the gate electrode (110); growing a first oxide layer to form a gate shield, and then growing a second oxide layer to cover the shield; Step 4 further includes drilling holes to form a source contact via (203-1), a gate contact via (203-2), a drain contact via (203-3), and a gate shield plate contact via. A method for manufacturing a lateral SiC-JFET device according to claim 14.

16. The method for manufacturing the lateral SiC-JFET device includes the steps of: forming a source metal layer (204-1) and a drain metal layer (204-3); Step 5 further includes forming a ground backhaul (205). A method for manufacturing a lateral SiC-JFET device according to claim 15.

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